Re: [coreboot] memtest86 reading 0k memory
On Thu, Apr 09, 2015 at 11:03:43AM -0600, Martin Roth wrote: In regards to other approaches, instead of removing coreboot's memory tables, would it be better if SeaBIOS updated the tables with what it had changed instead of deleting the tables? It's technically possible, but I don't think it's a good idea. It would be complex to do and it could lead to confusion when troubleshooting. As far as I know, only memtest86 has this problem. Is it possible to get your patch into its upstream repo? -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On 04/08/2015 08:45 PM, Kevin O'Connor wrote:
On Wed, Apr 08, 2015 at 10:55:18PM +0200, Stefan Tauner wrote:
On Thu, 19 Feb 2015 10:43:44 -0500
Kevin O'Connor ke...@koconnor.net wrote:
On Wed, Feb 18, 2015 at 10:26:21PM +0100, Stefan Reinauer wrote:
* Timothy Pearson tpear...@raptorengineeringinc.com [150205 19:23]:
e820: BIOS-provided physical RAM map:
BIOS-e820: [mem 0x-0x0009fbff] usable
BIOS-e820: [mem 0x0009fc00-0x0009] reserved
BIOS-e820: [mem 0x000f-0x000f] reserved
BIOS-e820: [mem 0x0010-0x3ffacfff] usable
BIOS-e820: [mem 0x3ffad000-0x3fff] reserved
BIOS-e820: [mem 0xe000-0xefff] reserved
One of the issues seems to be that the coreboot table space is not
marked as reserved (i.e. the lower 4k should be marked as reserved, and
whatever is used at the top of memory)
coreboot tends to reserve the first 4K, but this breaks lots of
bootloaders. So, SeaBIOS always overrides coreboot and unreserves the
first 4K. My experience is that the first one megabyte of the e820 is
just magical and should always read as listed above.
Separately, it is possible for SeaBIOS to remove the coreboot table
forwarder, and thus force memtest86 to not use the coreboot tables.
I'm not sure if this would affect other programs though.
I ran into the problem today when trying to verify that the ASRock
IMB-A180-H works correctly with coreboot. Is there any consensus on
what to do? IMHO this is a bug in SeaBIOS... it creates the discrepancy
between the tables and that leads to problems downstream... but that's
arguable. What is not arguable: some action is required. :)
I don't agree the above is a defect in SeaBIOS. SeaBIOS properly
reads the memory tables from coreboot, and it properly provides
updated memory tables to clients.
SeaBIOS could try to force memtest86 to not use the coreboot memory
table (by deleting the coreboot forwarding table), but I suspect that
will interfere with other users of the coreboot tables. (For example,
it's unclear to me if cbmem will continue to work from linux if
SeaBIOS removes the forwarding table.)
I'd guess it would be better to change memtest86 to not use the
coreboot table if it is started via a BIOS.
-Kevin
To fix this for myself, I've updated memsize.c file with the following:
void mem_size(void)
{
int i, flag=0;
v-test_pages = 0;
unsigned long intvect = *(unsigned long *)(0x15 * sizeof (void *));
/* Get the memory size from the BIOS */
/* Determine the memory map */
if (intvect query_pcbios()) {
flag = 2;
}
else if (query_linuxbios()) {
flag = 1;
}
...
This tells it to use SeaBIOS's int15 tables first if they exist. This
way anything that SeaBIOS has reserved gets picked up. If the Int 15h
vector isn't there, such as when memtest is being run directly from
coreboot as a payload, it uses the coreboot memory tables instead.
Unfortunately, this doesn't solve the problem for all the other copies
of memtest86+ that could be run.
In regards to other approaches, instead of removing coreboot's memory
tables, would it be better if SeaBIOS updated the tables with what it
had changed instead of deleting the tables?
Martin
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On Wed, Apr 08, 2015 at 10:55:18PM +0200, Stefan Tauner wrote: On Thu, 19 Feb 2015 10:43:44 -0500 Kevin O'Connor ke...@koconnor.net wrote: On Wed, Feb 18, 2015 at 10:26:21PM +0100, Stefan Reinauer wrote: * Timothy Pearson tpear...@raptorengineeringinc.com [150205 19:23]: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x-0x0009fbff] usable BIOS-e820: [mem 0x0009fc00-0x0009] reserved BIOS-e820: [mem 0x000f-0x000f] reserved BIOS-e820: [mem 0x0010-0x3ffacfff] usable BIOS-e820: [mem 0x3ffad000-0x3fff] reserved BIOS-e820: [mem 0xe000-0xefff] reserved One of the issues seems to be that the coreboot table space is not marked as reserved (i.e. the lower 4k should be marked as reserved, and whatever is used at the top of memory) coreboot tends to reserve the first 4K, but this breaks lots of bootloaders. So, SeaBIOS always overrides coreboot and unreserves the first 4K. My experience is that the first one megabyte of the e820 is just magical and should always read as listed above. Separately, it is possible for SeaBIOS to remove the coreboot table forwarder, and thus force memtest86 to not use the coreboot tables. I'm not sure if this would affect other programs though. I ran into the problem today when trying to verify that the ASRock IMB-A180-H works correctly with coreboot. Is there any consensus on what to do? IMHO this is a bug in SeaBIOS... it creates the discrepancy between the tables and that leads to problems downstream... but that's arguable. What is not arguable: some action is required. :) I don't agree the above is a defect in SeaBIOS. SeaBIOS properly reads the memory tables from coreboot, and it properly provides updated memory tables to clients. SeaBIOS could try to force memtest86 to not use the coreboot memory table (by deleting the coreboot forwarding table), but I suspect that will interfere with other users of the coreboot tables. (For example, it's unclear to me if cbmem will continue to work from linux if SeaBIOS removes the forwarding table.) I'd guess it would be better to change memtest86 to not use the coreboot table if it is started via a BIOS. -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On Thu, 19 Feb 2015 10:43:44 -0500 Kevin O'Connor ke...@koconnor.net wrote: On Wed, Feb 18, 2015 at 10:26:21PM +0100, Stefan Reinauer wrote: * Timothy Pearson tpear...@raptorengineeringinc.com [150205 19:23]: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x-0x0009fbff] usable BIOS-e820: [mem 0x0009fc00-0x0009] reserved BIOS-e820: [mem 0x000f-0x000f] reserved BIOS-e820: [mem 0x0010-0x3ffacfff] usable BIOS-e820: [mem 0x3ffad000-0x3fff] reserved BIOS-e820: [mem 0xe000-0xefff] reserved One of the issues seems to be that the coreboot table space is not marked as reserved (i.e. the lower 4k should be marked as reserved, and whatever is used at the top of memory) coreboot tends to reserve the first 4K, but this breaks lots of bootloaders. So, SeaBIOS always overrides coreboot and unreserves the first 4K. My experience is that the first one megabyte of the e820 is just magical and should always read as listed above. Separately, it is possible for SeaBIOS to remove the coreboot table forwarder, and thus force memtest86 to not use the coreboot tables. I'm not sure if this would affect other programs though. I ran into the problem today when trying to verify that the ASRock IMB-A180-H works correctly with coreboot. Is there any consensus on what to do? IMHO this is a bug in SeaBIOS... it creates the discrepancy between the tables and that leads to problems downstream... but that's arguable. What is not arguable: some action is required. :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On 08.04.2015 22:55, Stefan Tauner wrote: On Thu, 19 Feb 2015 10:43:44 -0500 Kevin O'Connor ke...@koconnor.net wrote: On Wed, Feb 18, 2015 at 10:26:21PM +0100, Stefan Reinauer wrote: * Timothy Pearson tpear...@raptorengineeringinc.com [150205 19:23]: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x-0x0009fbff] usable BIOS-e820: [mem 0x0009fc00-0x0009] reserved BIOS-e820: [mem 0x000f-0x000f] reserved BIOS-e820: [mem 0x0010-0x3ffacfff] usable BIOS-e820: [mem 0x3ffad000-0x3fff] reserved BIOS-e820: [mem 0xe000-0xefff] reserved One of the issues seems to be that the coreboot table space is not marked as reserved (i.e. the lower 4k should be marked as reserved, and whatever is used at the top of memory) coreboot tends to reserve the first 4K, but this breaks lots of bootloaders. So, SeaBIOS always overrides coreboot and unreserves the first 4K. My experience is that the first one megabyte of the e820 is just magical and should always read as listed above. Separately, it is possible for SeaBIOS to remove the coreboot table forwarder, and thus force memtest86 to not use the coreboot tables. I'm not sure if this would affect other programs though. I ran into the problem today when trying to verify that the ASRock IMB-A180-H works correctly with coreboot. Is there any consensus on what to do? IMHO this is a bug in SeaBIOS... it creates the discrepancy between the tables and that leads to problems downstream... but that's arguable. What is not arguable: some action is required. :) The Linux kernel expects coreboot+SeaBIOS to lie and marks the first 4K as reserved again. Excerpt from my dmesg on a T60 running coreboot+SeaBIOS: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x-0x0009fbff] usable BIOS-e820: [mem 0x0009fc00-0x0009] reserved BIOS-e820: [mem 0x000f-0x000f] reserved BIOS-e820: [mem 0x0010-0xcfec9fff] usable BIOS-e820: [mem 0xcfeca000-0xcfff] reserved BIOS-e820: [mem 0xf000-0xf3ff] reserved SMBIOS 2.7 present. DMI: LENOVO 2007VVT/2007VVT, BIOS CBET4000 4.0-7070-g2fc0a1d 10/18/2014 e820: update [mem 0x-0x0fff] usable == reserved e820: remove [mem 0x000a-0x000f] usable Regards, Carl-Daniel -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On Wed, Feb 18, 2015 at 10:26:21PM +0100, Stefan Reinauer wrote: * Timothy Pearson tpear...@raptorengineeringinc.com [150205 19:23]: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x-0x0009fbff] usable BIOS-e820: [mem 0x0009fc00-0x0009] reserved BIOS-e820: [mem 0x000f-0x000f] reserved BIOS-e820: [mem 0x0010-0x3ffacfff] usable BIOS-e820: [mem 0x3ffad000-0x3fff] reserved BIOS-e820: [mem 0xe000-0xefff] reserved One of the issues seems to be that the coreboot table space is not marked as reserved (i.e. the lower 4k should be marked as reserved, and whatever is used at the top of memory) coreboot tends to reserve the first 4K, but this breaks lots of bootloaders. So, SeaBIOS always overrides coreboot and unreserves the first 4K. My experience is that the first one megabyte of the e820 is just magical and should always read as listed above. Separately, it is possible for SeaBIOS to remove the coreboot table forwarder, and thus force memtest86 to not use the coreboot tables. I'm not sure if this would affect other programs though. -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
* Timothy Pearson tpear...@raptorengineeringinc.com [150205 19:23]: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x-0x0009fbff] usable BIOS-e820: [mem 0x0009fc00-0x0009] reserved BIOS-e820: [mem 0x000f-0x000f] reserved BIOS-e820: [mem 0x0010-0x3ffacfff] usable BIOS-e820: [mem 0x3ffad000-0x3fff] reserved BIOS-e820: [mem 0xe000-0xefff] reserved One of the issues seems to be that the coreboot table space is not marked as reserved (i.e. the lower 4k should be marked as reserved, and whatever is used at the top of memory) Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On 02/05/2015 09:45 PM, Timothy Pearson wrote: On 02/05/2015 09:13 PM, Scott Duplichan wrote: Timothy Pearson [mailto:tpear...@raptorengineeringinc.com] wrote: ]Sent: Thursday, February 05, 2015 06:49 PM ]To: Coreboot ]Subject: Re: [coreboot] memtest86 reading 0k memory ] ]On 02/05/2015 06:42 PM, Timothy Pearson wrote: ] On 02/05/2015 02:06 PM, Timothy Pearson wrote: ] On 02/05/2015 01:51 PM, Aaron Durbin wrote: ] Do you have the coreboot console log? Looking at memtest86 it ] constructs its own e820 when using linuxbios. Additionally, it also ] has some concept of a window to test as well as plim_lower and ] plim_upper variables that seem to add to the mix. ] ] What's super frightening is that find_chunks(int tst) is called in the ] code as find_chunks() while the find_chunks() function actually ] references tst as an array index. That's all from config.c. But I ] think that's only if you hit c on the keyboard. I wouldn't do that... ] ] I can't make heads or tails of that code at the moment. for selecting ] the window to test. ] ] Please see text log attached. It looks like the failing accesses start ] at 0xa, which (judging by memtest's effects on the screen) appears ] to be mapped to the VGA text buffer. That region is *not* reserved under ] the proprietary BIOS's e820 map. ] ] Thanks! ] ] ] I was able to resolve the lower MMIO region failures (coreboot driver ] patch in for review), but memtest86 is stubbornly insisting on testing ] reserved memory, causing a single failure at 3ffade80. The e820 map says ] that address is out of bounds but the coreboot tables do not: ] ] e820 map has 6 items: ] 0: - 0009fc00 = 1 RAM ] 1: 0009fc00 - 000a = 2 RESERVED ] 2: 000f - 0010 = 2 RESERVED ] 3: 0010 - 3ffad000 = 1 RAM ] 4: 3ffad000 - 4000 = 2 RESERVED ] 5: e000 - f000 = 2 RESERVED ] ] coreboot table: 460 bytes. ] CBMEM ROOT 0. 3000 1000 ] CONSOLE 1. 3ffdf000 0002 ] TIME STAMP 2. 3ffde000 1000 ] GDT 3. 3ffdd000 1000 ] SMP TABLE 4. 3ffdc000 1000 ] ACPI 5. 3ffb8000 00024000 ] SMBIOS 6. 3ffb7000 1000 ] COREBOOT 7. 3ffaf000 8000 ] ] Why the discrepancy? Am I correct in assuming this is a bug in coreboot ] that needs to be fixed? ] ] ]Sorry, wrong coreboot table above: ] ]Writing coreboot table at 0x3ffaf000 ]rom_table_end = 0x3ffaf000 ]... aligned to 0x3ffb ] 0. -0fff: CONFIGURATION TABLES ] 1. 1000-0009: RAM ] 2. 000a-000a: RESERVED ] 3. 000b-000b7fff: RAM ] 4. 000b8000-000b: RESERVED ] 5. 000c-3ffaefff: RAM ] 6. 3ffaf000-3fff: CONFIGURATION TABLES ] 7. e000-efff: RESERVED ] ]I assume something is placing itself at 3ffad000 (coreboot? SeaBIOS?) ]and that overwriting it is a Bad Thing, but whatever it is does not ]update the coreboot tables and memtest86 promptly stomps on it. I imagine SeaBIOS is taking memory from the end of free RAM below 4GB for USB structures. There is probably an incrementing frame counter at 3ffade80. It looks like SeaBIOS builds the E820 table to properly account for the memory it uses. If memtest86 uses the coreboot tables even when an E820 handler is installed, that seems wrong. Unless SeaBIOS is supposed to adjust the coreboot tables to reflect its memory usage, which I don't think is the case. I suspect you're right about the USB structures; my USB keyboard quit working when memtest started. Looks like I'll be building memtest86 with coreboot support disabled; judging by the numerous problems reported by other coreboot users memtest badly needs an update to disable coreboot support by default. Recompiling memtest with the coreboot table detection bypassed resolved the problem. Thanks for the help! -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On 02/05/2015 09:13 PM, Scott Duplichan wrote: Timothy Pearson [mailto:tpear...@raptorengineeringinc.com] wrote: ]Sent: Thursday, February 05, 2015 06:49 PM ]To: Coreboot ]Subject: Re: [coreboot] memtest86 reading 0k memory ] ]On 02/05/2015 06:42 PM, Timothy Pearson wrote: ] On 02/05/2015 02:06 PM, Timothy Pearson wrote: ] On 02/05/2015 01:51 PM, Aaron Durbin wrote: ] Do you have the coreboot console log? Looking at memtest86 it ] constructs its own e820 when using linuxbios. Additionally, it also ] has some concept of a window to test as well as plim_lower and ] plim_upper variables that seem to add to the mix. ] ] What's super frightening is that find_chunks(int tst) is called in the ] code as find_chunks() while the find_chunks() function actually ] references tst as an array index. That's all from config.c. But I ] think that's only if you hit c on the keyboard. I wouldn't do that... ] ] I can't make heads or tails of that code at the moment. for selecting ] the window to test. ] ] Please see text log attached. It looks like the failing accesses start ] at 0xa, which (judging by memtest's effects on the screen) appears ] to be mapped to the VGA text buffer. That region is *not* reserved under ] the proprietary BIOS's e820 map. ] ] Thanks! ] ] ] I was able to resolve the lower MMIO region failures (coreboot driver ] patch in for review), but memtest86 is stubbornly insisting on testing ] reserved memory, causing a single failure at 3ffade80. The e820 map says ] that address is out of bounds but the coreboot tables do not: ] ] e820 map has 6 items: ] 0: - 0009fc00 = 1 RAM ] 1: 0009fc00 - 000a = 2 RESERVED ] 2: 000f - 0010 = 2 RESERVED ] 3: 0010 - 3ffad000 = 1 RAM ] 4: 3ffad000 - 4000 = 2 RESERVED ] 5: e000 - f000 = 2 RESERVED ] ] coreboot table: 460 bytes. ] CBMEM ROOT 0. 3000 1000 ] CONSOLE 1. 3ffdf000 0002 ] TIME STAMP 2. 3ffde000 1000 ] GDT 3. 3ffdd000 1000 ] SMP TABLE 4. 3ffdc000 1000 ] ACPI 5. 3ffb8000 00024000 ] SMBIOS 6. 3ffb7000 1000 ] COREBOOT 7. 3ffaf000 8000 ] ] Why the discrepancy? Am I correct in assuming this is a bug in coreboot ] that needs to be fixed? ] ] ]Sorry, wrong coreboot table above: ] ]Writing coreboot table at 0x3ffaf000 ]rom_table_end = 0x3ffaf000 ]... aligned to 0x3ffb ] 0. -0fff: CONFIGURATION TABLES ] 1. 1000-0009: RAM ] 2. 000a-000a: RESERVED ] 3. 000b-000b7fff: RAM ] 4. 000b8000-000b: RESERVED ] 5. 000c-3ffaefff: RAM ] 6. 3ffaf000-3fff: CONFIGURATION TABLES ] 7. e000-efff: RESERVED ] ]I assume something is placing itself at 3ffad000 (coreboot? SeaBIOS?) ]and that overwriting it is a Bad Thing, but whatever it is does not ]update the coreboot tables and memtest86 promptly stomps on it. I imagine SeaBIOS is taking memory from the end of free RAM below 4GB for USB structures. There is probably an incrementing frame counter at 3ffade80. It looks like SeaBIOS builds the E820 table to properly account for the memory it uses. If memtest86 uses the coreboot tables even when an E820 handler is installed, that seems wrong. Unless SeaBIOS is supposed to adjust the coreboot tables to reflect its memory usage, which I don't think is the case. I suspect you're right about the USB structures; my USB keyboard quit working when memtest started. Looks like I'll be building memtest86 with coreboot support disabled; judging by the numerous problems reported by other coreboot users memtest badly needs an update to disable coreboot support by default. -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On Thu, Feb 5, 2015 at 12:48 PM, Timothy Pearson tpear...@raptorengineeringinc.com wrote: On 02/05/2015 12:38 PM, Jonathan A. Kollasch wrote: That's a pretty old memtest86+. Also, memtest86+ prefers linuxbios/coreboot memory map to e820. This becomes a problem when SeaBIOS sets up a USB controller to DMA to e820-reserved memory that wasn't reserved by coreboot. Try a modern memtest86+ with the coreboot table probe patched out. Jonathan Kollasch Yep, that was it. Didn't catch the obsolete version number. I'm trying to figure out the point of memtest86 reading the coreboot tables. It doesn't help that the coreboot tables / e820 map are apparently wrong; memtest86+ almost immediately started stepping on the lower MMIO regions (e.g. 0xb800) rendering the display mostly useless. Interestingly Linux doesn't seem to have any problems; I'll need to investigate further. Your e820 looks fine to me. memtest86 should just be testing the usable regions. Since b800 isn't in there, the only issue that could arise is it using that physical address as a mmio bar. However, that'd be an OS level thing, and I wouldn't expect the memtest86 doing any such things. It sounds more like it does a merge of some sort with e820 and its notion of valid memory instead relying on e820 proper. -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On 02/05/2015 12:59 PM, Aaron Durbin wrote: On Thu, Feb 5, 2015 at 12:48 PM, Timothy Pearson tpear...@raptorengineeringinc.com wrote: On 02/05/2015 12:38 PM, Jonathan A. Kollasch wrote: That's a pretty old memtest86+. Also, memtest86+ prefers linuxbios/coreboot memory map to e820. This becomes a problem when SeaBIOS sets up a USB controller to DMA to e820-reserved memory that wasn't reserved by coreboot. Try a modern memtest86+ with the coreboot table probe patched out. Jonathan Kollasch Yep, that was it. Didn't catch the obsolete version number. I'm trying to figure out the point of memtest86 reading the coreboot tables. It doesn't help that the coreboot tables / e820 map are apparently wrong; memtest86+ almost immediately started stepping on the lower MMIO regions (e.g. 0xb800) rendering the display mostly useless. Interestingly Linux doesn't seem to have any problems; I'll need to investigate further. Your e820 looks fine to me. memtest86 should just be testing the usable regions. Since b800 isn't in there, the only issue that could arise is it using that physical address as a mmio bar. However, that'd be an OS level thing, and I wouldn't expect the memtest86 doing any such things. It sounds more like it does a merge of some sort with e820 and its notion of valid memory instead relying on e820 proper. Thanks for the information. The e820 map is comparable to the one generated from the proprietary BIOS so I agree it is likely correct. That leaves the coreboot tables themselves and/or memtest86's interpretation of them. BTW it looks I am not the only one to have run into this: http://www.coreboot.org/pipermail/coreboot/2010-December/062245.html At this point I'm not sure if the bug is in coreboot, SeaBIOS, or memtest86. -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On 02/05/2015 02:06 PM, Timothy Pearson wrote: On 02/05/2015 01:51 PM, Aaron Durbin wrote: Do you have the coreboot console log? Looking at memtest86 it constructs its own e820 when using linuxbios. Additionally, it also has some concept of a window to test as well as plim_lower and plim_upper variables that seem to add to the mix. What's super frightening is that find_chunks(int tst) is called in the code as find_chunks() while the find_chunks() function actually references tst as an array index. That's all from config.c. But I think that's only if you hit c on the keyboard. I wouldn't do that... I can't make heads or tails of that code at the moment. for selecting the window to test. Please see text log attached. It looks like the failing accesses start at 0xa, which (judging by memtest's effects on the screen) appears to be mapped to the VGA text buffer. That region is *not* reserved under the proprietary BIOS's e820 map. Thanks! I was able to resolve the lower MMIO region failures (coreboot driver patch in for review), but memtest86 is stubbornly insisting on testing reserved memory, causing a single failure at 3ffade80. The e820 map says that address is out of bounds but the coreboot tables do not: e820 map has 6 items: 0: - 0009fc00 = 1 RAM 1: 0009fc00 - 000a = 2 RESERVED 2: 000f - 0010 = 2 RESERVED 3: 0010 - 3ffad000 = 1 RAM 4: 3ffad000 - 4000 = 2 RESERVED 5: e000 - f000 = 2 RESERVED coreboot table: 460 bytes. CBMEM ROOT 0. 3000 1000 CONSOLE 1. 3ffdf000 0002 TIME STAMP 2. 3ffde000 1000 GDT 3. 3ffdd000 1000 SMP TABLE 4. 3ffdc000 1000 ACPI5. 3ffb8000 00024000 SMBIOS 6. 3ffb7000 1000 COREBOOT7. 3ffaf000 8000 Why the discrepancy? Am I correct in assuming this is a bug in coreboot that needs to be fixed? -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On 02/05/2015 06:42 PM, Timothy Pearson wrote: On 02/05/2015 02:06 PM, Timothy Pearson wrote: On 02/05/2015 01:51 PM, Aaron Durbin wrote: Do you have the coreboot console log? Looking at memtest86 it constructs its own e820 when using linuxbios. Additionally, it also has some concept of a window to test as well as plim_lower and plim_upper variables that seem to add to the mix. What's super frightening is that find_chunks(int tst) is called in the code as find_chunks() while the find_chunks() function actually references tst as an array index. That's all from config.c. But I think that's only if you hit c on the keyboard. I wouldn't do that... I can't make heads or tails of that code at the moment. for selecting the window to test. Please see text log attached. It looks like the failing accesses start at 0xa, which (judging by memtest's effects on the screen) appears to be mapped to the VGA text buffer. That region is *not* reserved under the proprietary BIOS's e820 map. Thanks! I was able to resolve the lower MMIO region failures (coreboot driver patch in for review), but memtest86 is stubbornly insisting on testing reserved memory, causing a single failure at 3ffade80. The e820 map says that address is out of bounds but the coreboot tables do not: e820 map has 6 items: 0: - 0009fc00 = 1 RAM 1: 0009fc00 - 000a = 2 RESERVED 2: 000f - 0010 = 2 RESERVED 3: 0010 - 3ffad000 = 1 RAM 4: 3ffad000 - 4000 = 2 RESERVED 5: e000 - f000 = 2 RESERVED coreboot table: 460 bytes. CBMEM ROOT 0. 3000 1000 CONSOLE 1. 3ffdf000 0002 TIME STAMP 2. 3ffde000 1000 GDT 3. 3ffdd000 1000 SMP TABLE 4. 3ffdc000 1000 ACPI 5. 3ffb8000 00024000 SMBIOS 6. 3ffb7000 1000 COREBOOT 7. 3ffaf000 8000 Why the discrepancy? Am I correct in assuming this is a bug in coreboot that needs to be fixed? Sorry, wrong coreboot table above: Writing coreboot table at 0x3ffaf000 rom_table_end = 0x3ffaf000 ... aligned to 0x3ffb 0. -0fff: CONFIGURATION TABLES 1. 1000-0009: RAM 2. 000a-000a: RESERVED 3. 000b-000b7fff: RAM 4. 000b8000-000b: RESERVED 5. 000c-3ffaefff: RAM 6. 3ffaf000-3fff: CONFIGURATION TABLES 7. e000-efff: RESERVED I assume something is placing itself at 3ffad000 (coreboot? SeaBIOS?) and that overwriting it is a Bad Thing, but whatever it is does not update the coreboot tables and memtest86 promptly stomps on it. -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
Timothy Pearson [mailto:tpear...@raptorengineeringinc.com] wrote: ]Sent: Thursday, February 05, 2015 06:49 PM ]To: Coreboot ]Subject: Re: [coreboot] memtest86 reading 0k memory ] ]On 02/05/2015 06:42 PM, Timothy Pearson wrote: ] On 02/05/2015 02:06 PM, Timothy Pearson wrote: ] On 02/05/2015 01:51 PM, Aaron Durbin wrote: ] Do you have the coreboot console log? Looking at memtest86 it ] constructs its own e820 when using linuxbios. Additionally, it also ] has some concept of a window to test as well as plim_lower and ] plim_upper variables that seem to add to the mix. ] ] What's super frightening is that find_chunks(int tst) is called in the ] code as find_chunks() while the find_chunks() function actually ] references tst as an array index. That's all from config.c. But I ] think that's only if you hit c on the keyboard. I wouldn't do that... ] ] I can't make heads or tails of that code at the moment. for selecting ] the window to test. ] ] Please see text log attached. It looks like the failing accesses start ] at 0xa, which (judging by memtest's effects on the screen) appears ] to be mapped to the VGA text buffer. That region is *not* reserved under ] the proprietary BIOS's e820 map. ] ] Thanks! ] ] ] I was able to resolve the lower MMIO region failures (coreboot driver ] patch in for review), but memtest86 is stubbornly insisting on testing ] reserved memory, causing a single failure at 3ffade80. The e820 map says ] that address is out of bounds but the coreboot tables do not: ] ] e820 map has 6 items: ] 0: - 0009fc00 = 1 RAM ] 1: 0009fc00 - 000a = 2 RESERVED ] 2: 000f - 0010 = 2 RESERVED ] 3: 0010 - 3ffad000 = 1 RAM ] 4: 3ffad000 - 4000 = 2 RESERVED ] 5: e000 - f000 = 2 RESERVED ] ] coreboot table: 460 bytes. ] CBMEM ROOT 0. 3000 1000 ] CONSOLE 1. 3ffdf000 0002 ] TIME STAMP 2. 3ffde000 1000 ] GDT 3. 3ffdd000 1000 ] SMP TABLE 4. 3ffdc000 1000 ] ACPI 5. 3ffb8000 00024000 ] SMBIOS 6. 3ffb7000 1000 ] COREBOOT 7. 3ffaf000 8000 ] ] Why the discrepancy? Am I correct in assuming this is a bug in coreboot ] that needs to be fixed? ] ] ]Sorry, wrong coreboot table above: ] ]Writing coreboot table at 0x3ffaf000 ]rom_table_end = 0x3ffaf000 ]... aligned to 0x3ffb ] 0. -0fff: CONFIGURATION TABLES ] 1. 1000-0009: RAM ] 2. 000a-000a: RESERVED ] 3. 000b-000b7fff: RAM ] 4. 000b8000-000b: RESERVED ] 5. 000c-3ffaefff: RAM ] 6. 3ffaf000-3fff: CONFIGURATION TABLES ] 7. e000-efff: RESERVED ] ]I assume something is placing itself at 3ffad000 (coreboot? SeaBIOS?) ]and that overwriting it is a Bad Thing, but whatever it is does not ]update the coreboot tables and memtest86 promptly stomps on it. I imagine SeaBIOS is taking memory from the end of free RAM below 4GB for USB structures. There is probably an incrementing frame counter at 3ffade80. It looks like SeaBIOS builds the E820 table to properly account for the memory it uses. If memtest86 uses the coreboot tables even when an E820 handler is installed, that seems wrong. Unless SeaBIOS is supposed to adjust the coreboot tables to reflect its memory usage, which I don't think is the case. ]-- ]Timothy Pearson ]Raptor Engineering ]+1 (415) 727-8645 ]http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On Thu, Feb 05, 2015 at 12:23:40PM -0600, Timothy Pearson wrote: All, I have a board here that loads memtest86 but won't actually test memory. This is the output: Memtest86+ v2.11 AMD K10 CPU @ 2312 MHz L1 Cache: 64K 35028 MB/s L2 Cache: 512K 6963 MB/s L3 Cache: 2048K 6052 MB/s Memory :0K |- Chipset : 0K LinuxBIOS I'm guessing memtest86 doesn't understand coreboot's memory tables/structure, but I have no idea why that would be. The e820 map is valid: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x-0x0009fbff] usable BIOS-e820: [mem 0x0009fc00-0x0009] reserved BIOS-e820: [mem 0x000f-0x000f] reserved BIOS-e820: [mem 0x0010-0x3ffacfff] usable BIOS-e820: [mem 0x3ffad000-0x3fff] reserved BIOS-e820: [mem 0xe000-0xefff] reserved Any ideas? Other than this one irritating glitch coreboot is working perfectly on this board. That's a pretty old memtest86+. Also, memtest86+ prefers linuxbios/coreboot memory map to e820. This becomes a problem when SeaBIOS sets up a USB controller to DMA to e820-reserved memory that wasn't reserved by coreboot. Try a modern memtest86+ with the coreboot table probe patched out. Jonathan Kollasch -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On 02/05/2015 12:38 PM, Jonathan A. Kollasch wrote: That's a pretty old memtest86+. Also, memtest86+ prefers linuxbios/coreboot memory map to e820. This becomes a problem when SeaBIOS sets up a USB controller to DMA to e820-reserved memory that wasn't reserved by coreboot. Try a modern memtest86+ with the coreboot table probe patched out. Jonathan Kollasch Yep, that was it. Didn't catch the obsolete version number. I'm trying to figure out the point of memtest86 reading the coreboot tables. It doesn't help that the coreboot tables / e820 map are apparently wrong; memtest86+ almost immediately started stepping on the lower MMIO regions (e.g. 0xb800) rendering the display mostly useless. Interestingly Linux doesn't seem to have any problems; I'll need to investigate further. -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] memtest86 reading 0k memory
All, I have a board here that loads memtest86 but won't actually test memory. This is the output: Memtest86+ v2.11 AMD K10 CPU @ 2312 MHz L1 Cache: 64K 35028 MB/s L2 Cache: 512K 6963 MB/s L3 Cache: 2048K 6052 MB/s Memory :0K |- Chipset : 0K LinuxBIOS I'm guessing memtest86 doesn't understand coreboot's memory tables/structure, but I have no idea why that would be. The e820 map is valid: e820: BIOS-provided physical RAM map: BIOS-e820: [mem 0x-0x0009fbff] usable BIOS-e820: [mem 0x0009fc00-0x0009] reserved BIOS-e820: [mem 0x000f-0x000f] reserved BIOS-e820: [mem 0x0010-0x3ffacfff] usable BIOS-e820: [mem 0x3ffad000-0x3fff] reserved BIOS-e820: [mem 0xe000-0xefff] reserved Any ideas? Other than this one irritating glitch coreboot is working perfectly on this board. Thanks! -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] memtest86 reading 0k memory
On Thu, Feb 5, 2015 at 1:15 PM, Timothy Pearson tpear...@raptorengineeringinc.com wrote: On 02/05/2015 12:59 PM, Aaron Durbin wrote: On Thu, Feb 5, 2015 at 12:48 PM, Timothy Pearson tpear...@raptorengineeringinc.com wrote: On 02/05/2015 12:38 PM, Jonathan A. Kollasch wrote: That's a pretty old memtest86+. Also, memtest86+ prefers linuxbios/coreboot memory map to e820. This becomes a problem when SeaBIOS sets up a USB controller to DMA to e820-reserved memory that wasn't reserved by coreboot. Try a modern memtest86+ with the coreboot table probe patched out. Jonathan Kollasch Yep, that was it. Didn't catch the obsolete version number. I'm trying to figure out the point of memtest86 reading the coreboot tables. It doesn't help that the coreboot tables / e820 map are apparently wrong; memtest86+ almost immediately started stepping on the lower MMIO regions (e.g. 0xb800) rendering the display mostly useless. Interestingly Linux doesn't seem to have any problems; I'll need to investigate further. Your e820 looks fine to me. memtest86 should just be testing the usable regions. Since b800 isn't in there, the only issue that could arise is it using that physical address as a mmio bar. However, that'd be an OS level thing, and I wouldn't expect the memtest86 doing any such things. It sounds more like it does a merge of some sort with e820 and its notion of valid memory instead relying on e820 proper. Thanks for the information. The e820 map is comparable to the one generated from the proprietary BIOS so I agree it is likely correct. That leaves the coreboot tables themselves and/or memtest86's interpretation of them. BTW it looks I am not the only one to have run into this: http://www.coreboot.org/pipermail/coreboot/2010-December/062245.html At this point I'm not sure if the bug is in coreboot, SeaBIOS, or memtest86. Do you have the coreboot console log? Looking at memtest86 it constructs its own e820 when using linuxbios. Additionally, it also has some concept of a window to test as well as plim_lower and plim_upper variables that seem to add to the mix. What's super frightening is that find_chunks(int tst) is called in the code as find_chunks() while the find_chunks() function actually references tst as an array index. That's all from config.c. But I think that's only if you hit c on the keyboard. I wouldn't do that... I can't make heads or tails of that code at the moment. for selecting the window to test. -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
