Re: [coreboot] riscv: how to running coreboot on HiFive Unleashed?
Hi again, On Tue, Nov 27, 2018 at 12:20:53PM +0800, 王翔 wrote: > > coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 bootblock > > starting... > > Boot mode: 15 > > Couldn't load romstage. I just tried the same version (coreboot-4.8-2282-gc88828daeb), and it worked, both with a 1 MiB coreboot image and a 32 MiB coreboot image: coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 bootblock starting... Boot mode: 15 CBFS: 'Master Header Locator' located CBFS at [20100:200) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 2dca CBMEM:ot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 romstage starting... IMD: root @ 00027000 254 entries. IMD: root @ 00027fffec00 62 entries. CBFS: 'Master Header Locator' located CBFS at [20100:200) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 2ec0 size 532f coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 ramstage starting... BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 1 BS: BS_DEV_INIT_CHIPS times (us): entry 1 run 0 exit 0 Enumerating buses... CPU_CLUSTER: 0 enabled scan_bus: scanning of bus Root Device took 2050 usecs done BS: BS_DEV_ENUMERATE times (us): entry 1 run 9289 exit 1 Allocating resources... Reading resources... CPU_CLUSTER: 0 missing read_resources Done reading resources. Setting resources... Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 16149 exit 0 Enabling resources... done. BS: BS_DEV_ENABLE times (us): entry 0 run 2605 exit 0 Initializing devices... Root Device init ... Root Device init finished in 1910 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 0 run 9464 exit 0 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 3473 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0 Writing coreboot table at 0x27ffdc000 0. 8000-80011fff: RAMSTAGE 1. 80012000-8003: RAM 2. 8004-80044fff: RAMSTAGE 3. 80045000-00027ffdbfff: RAM 4. 00027ffdc000-00027fff: CONFIGURATION TABLES Exception: Store address misaligned Previous mode: machine Bad instruction pc: 8de2 Bad address:00027ffdc0f4 Stored ra: 8d36 Stored sp: 80040ec8 CBFS: 'Master Header Locator' located CBFS at [20100:200) Exception: Store address misaligned Previous mode: machine Bad instruction pc: 8d6a Bad address:00027ffdc10c Stored ra: 8d66 Stored sp: 80040ec8 Exception: Store address misaligned Previous mode: machine Bad instruction pc: 8d6e Bad address:00027ffdc114 Stored ra: 8d66 Stored sp: 80040ec8 Exception: Store address misaligned Previous mode: machine Bad instruction pc: 8d74 Bad address:00027ffdc11c Stored ra: 8d66 Stored sp: 80040ec8 Exception: Store address misaligned Previous mode: machine Bad instruction pc: 8d7e Bad address:00027ffdc0fc Stored ra: 8d66 Stored sp: 80040ec8 Exception: Store address misaligned Previous mode: machine Bad instruction pc: 8d82 Bad address:00027ffdc104 Stored ra: 8d66 Stored sp: 80040ec8 FMAP: Found "FLASH" version 1.1 at 2. FMAP: base = 0 size = 200 #areas = 4 Exception: Store address misaligned Previous mode: machine Bad instruction pc: 8d8e Bad address:00027ffdc104 Stored ra: 8d8a Stored sp: 80040ec8 Exception: Store address misaligned Previous mode: machine Bad instruction pc: 80001c68 Bad address:00027ffdc124 Stored ra: 80001c66 Stored sp: 80040e58 Exception: Store address misaligned Previous mode: machine Bad instruction pc: 80001c72 Bad address:00027ffdc12c Stored ra: 80001c72 Stored sp: 80040e58 Exception: Store address misaligned Previous mode: machine Bad instruction pc: 80001c68 Bad address:00027ffdc13c Stored ra: 80001c66 Stored sp: 80040e58 Exception: Store address misaligned Previous mode:
Re: [coreboot] riscv: how to running coreboot on HiFive Unleashed?
On Tue, Nov 27, 2018 at 12:20:53PM +0800, 王翔 wrote: > I tried it again. Press reset key can see the serial output. Maybe the > power is turned on too fast. The computer does not capture the serial > port data. Unfortunately, the FTDI chip is also behind the power button, so when you release the power button, the FTDI chip starts up, and minicom has to reconnect, and at the same time the SoC already starts running and printing things on the UART. Something like this helps sometimes: - Power the board off via the power button - Press and hold the reset button - Power the board on - Wait until minicom has reconnected - Release the reset button > Below is my serial output > [...] > > coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 bootblock > > starting... > > Boot mode: 15 > > Couldn't load romstage. Hmm, this looks like a bug. Jonathan Neuschäfer signature.asc Description: PGP signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] riscv: how to running coreboot on HiFive Unleashed?
I tried it again. Press reset key can see the serial output. Maybe the power is turned on too fast. The computer does not capture the serial port data. Below is my serial output > Welcome to minicom 2.7 > > OPTIONS: I18n > Compiled on Apr 22 2017, 09:14:19. > Port /dev/ttyUSB1, 12:14:37 > > Press CTRL-A Z for help on special keys > > > > coreboot-4.8-2282-gc88828daeb Mon Nov 26 09:56:26 UTC 2018 bootblock > starting... > Boot mode: 15 > Couldn't load romstage. Thank you for your help. 在2018年11月27 10时56分, "王翔"写道: I am sure my uart configuration is 115200 8N1 on /dev/ttyUSB1. I have a power cycle after the burn is complete. 在2018年11月26 18时03分, "Jonathan Neuschäfer"写道: Hi! On Mon, Nov 26, 2018 at 02:54:46PM +0800, 王翔 wrote: > I try to running coreboot on HiFive Unleashed, but nothing come from uart. > > > I tested by the following steps: > > > 1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card. > 2. Change MSEL to 11 and boot linux > 3. Copy coreboot.rom via scp > 4. Write coreboot.rom to /dev/mtd0 by flashcp. > 5. Change MSEL to 15 and boot coreboot. No response on uart. > > > > Do you have any suggestions? How did you listen to the UART? Note that the FTDI Chip on the H5U will show up as two serial ports on the computer that it is connected to (usually /dev/ttyUSB0 and /dev/ttyUSB1). The first one is for JTAG and the second one is for UART. Also make sure that you configure the right baud rate (115200 usually) on /dev/ttyUSB1. You might also have to power-cycle the board and/or press the reset button. Sometimes that helps. If you continue to see no output, perhaps there is a bug in coreboot that prevents the output. Whenever I tested coreboot on the H5U, I could always see output, but I haven't tested it recently. Jonathan Neuschäfer -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] riscv: how to running coreboot on HiFive Unleashed?
I am sure my uart configuration is 115200 8N1 on /dev/ttyUSB1. I have a power cycle after the burn is complete. 在2018年11月26 18时03分, "Jonathan Neuschäfer"写道: Hi! On Mon, Nov 26, 2018 at 02:54:46PM +0800, 王翔 wrote: > I try to running coreboot on HiFive Unleashed, but nothing come from uart. > > > I tested by the following steps: > > > 1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card. > 2. Change MSEL to 11 and boot linux > 3. Copy coreboot.rom via scp > 4. Write coreboot.rom to /dev/mtd0 by flashcp. > 5. Change MSEL to 15 and boot coreboot. No response on uart. > > > > Do you have any suggestions? How did you listen to the UART? Note that the FTDI Chip on the H5U will show up as two serial ports on the computer that it is connected to (usually /dev/ttyUSB0 and /dev/ttyUSB1). The first one is for JTAG and the second one is for UART. Also make sure that you configure the right baud rate (115200 usually) on /dev/ttyUSB1. You might also have to power-cycle the board and/or press the reset button. Sometimes that helps. If you continue to see no output, perhaps there is a bug in coreboot that prevents the output. Whenever I tested coreboot on the H5U, I could always see output, but I haven't tested it recently. Jonathan Neuschäfer -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] riscv: how to running coreboot on HiFive Unleashed?
I try to running coreboot on HiFive Unleashed, but nothing come from uart. I tested by the following steps: 1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card. 2. Change MSEL to 11 and boot linux 3. Copy coreboot.rom via scp 4. Write coreboot.rom to /dev/mtd0 by flashcp. 5. Change MSEL to 15 and boot coreboot. No response on uart. Do you have any suggestions? -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] riscv: how to running coreboot on HiFive Unleashed?
Hi! On Mon, Nov 26, 2018 at 02:54:46PM +0800, 王翔 wrote: > I try to running coreboot on HiFive Unleashed, but nothing come from uart. > > > I tested by the following steps: > > > 1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card. > 2. Change MSEL to 11 and boot linux > 3. Copy coreboot.rom via scp > 4. Write coreboot.rom to /dev/mtd0 by flashcp. > 5. Change MSEL to 15 and boot coreboot. No response on uart. > > > > Do you have any suggestions? How did you listen to the UART? Note that the FTDI Chip on the H5U will show up as two serial ports on the computer that it is connected to (usually /dev/ttyUSB0 and /dev/ttyUSB1). The first one is for JTAG and the second one is for UART. Also make sure that you configure the right baud rate (115200 usually) on /dev/ttyUSB1. You might also have to power-cycle the board and/or press the reset button. Sometimes that helps. If you continue to see no output, perhaps there is a bug in coreboot that prevents the output. Whenever I tested coreboot on the H5U, I could always see output, but I haven't tested it recently. Jonathan Neuschäfer signature.asc Description: PGP signature -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
[coreboot] riscv: how to running coreboot on HiFive Unleashed?
I try to running coreboot on HiFive Unleashed, but nothing come from uart. I tested by the following steps: 1. Write hifive-unleashed-a00-1.0-2018-03-20.gpt to TF card. 2. Change MSEL to 11 and boot linux 3. Copy coreboot.rom via scp 4. Write coreboot.rom to /dev/mtd0 by flashcp. 5. Change MSEL to 15 and boot coreboot. No response on uart. Do you have any suggestions? -- 王翔 安全研究员 广州市腾御安信息科技有限公司 广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024-- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
