Re: [coreboot] Test SeaBIOS AHCI support
-Original Message- From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On Behalf Of Kevin O'Connor Sent: Wednesday, December 29, 2010 09:09 PM To: coreboot@coreboot.org Subject: [coreboot] Test SeaBIOS AHCI support Hi, One of the qemu developers added AHCI support to SeaBIOS. This support has been tested on qemu, but not on real hardware. It would be great if folks with coreboot supported hardware could also test it. (Unfortunately, my coreboot board doesn't have AHCI.) To test, grab the latest seabios git (see: http://seabios.org/Download ), edit src/config.h and enable CONFIG_AHCI. (Be sure to also set the other coreboot settings - see: http://www.coreboot.org/SeaBIOS .) Thanks, -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot Hello Kevin, Thanks a lot. Is this native 16-bit AHCI support that doesn't rely on an option rom? Thanks, Scott -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Test SeaBIOS AHCI support
On Fri, Dec 31, 2010 at 10:21:32AM -0600, Scott Duplichan wrote: > Hello Kevin, > > Thanks a lot. Is this native 16-bit AHCI support that doesn't rely on an > option rom? > ]It's native AHCI DMA support. (No option rom needed.) ]-Kevin That is great to hear. Some HP notebooks have this capability, but I know of no others. This setup should allow cutting seconds from Windows boot time because Windows spends lots of time on IDE drives that are not installed. If all IDE devices are disabled and only AHCI visible, Windows can boot a lot faster. I made an initial test using coreboot+seabios on an AMD RS780/SB700 system. So far it is not detecting the drives. But this test required hacking in code to disable the SB700 IDE device and switch the SATA device from IDE mode to AHCI mode. I have not yet checked to see if that code is even working correctly. I will continue debugging this in a day or two. Thanks, Scott -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Test SeaBIOS AHCI support
On Fri, Dec 31, 2010 at 10:21:32AM -0600, Scott Duplichan wrote: > Hello Kevin, > > Thanks a lot. Is this native 16-bit AHCI support that doesn't rely on an > option rom? > It's native AHCI DMA support. (No option rom needed.) -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Test SeaBIOS AHCI support
Hi Alec, Neo The User wrote: > I have attached the somewhat working port as a patch > (ma785gm-us2h.patch) Cool! > I hope the patch format is correct! Well, I'd say no. It is impossible to review this patch because it duplicates (nearly) all code for another board. It would be very good if you could start with a patch that is simply a diff from the ma785gmt board. Finally, when copying files later, into the new ma785gm directory, please make sure to use svn to do copies, so that patches become much smaller, or at the very least that the history is kept. But please first start with a diff against an existing board. If the differences are small enough maybe the same code can handle both boards. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Test SeaBIOS AHCI support
Hello! New patch :) Sorry about that, I have little to no experience with subversion. Also I found out that the rebooting loop wasn't caused by the AHCI SATA being off, but rather the console level for serial output was below 7 in the coreboot config file... I found it very strange. Anyway, the real result of having AHCI SATA off in SeaBIOS causes the payload to just hang, before it says to press F12. With it on, I can access GRUB but I get kernel panics in any Linux distro. NetBSD also fails. I attached a new patch, using svn copy and such from Tilapia, keeping almost everything the same in the diff. After creating the diff, I poked around a bit more, but I couldn't solve the kernel panics. This isn't really a big concern for me personally but I thought it would be cool to have a board with over 1,100 reviews on newegg that would be supported by Coreboot. Might spark some attention as well. -Alec --- On Tue, 1/4/11, Peter Stuge wrote: > From: Peter Stuge > Subject: Re: [coreboot] Test SeaBIOS AHCI support > To: coreboot@coreboot.org > Date: Tuesday, January 4, 2011, 11:45 AM > Hi Alec, > > Neo The User wrote: > > I have attached the somewhat working port as a patch > > (ma785gm-us2h.patch) > > Cool! > > > > I hope the patch format is correct! > > Well, I'd say no. It is impossible to review this patch > because it > duplicates (nearly) all code for another board. > > It would be very good if you could start with a patch that > is simply > a diff from the ma785gmt board. > > Finally, when copying files later, into the new ma785gm > directory, > please make sure to use svn to do copies, so that patches > become much > smaller, or at the very least that the history is kept. > > But please first start with a diff against an existing > board. If the > differences are small enough maybe the same code can handle > both boards. > > > //Peter > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > ma785gm-us2h.diff Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Test SeaBIOS AHCI support
Hi, I think SATA port 4 and 5 may have some issues on SB700 (not detecting drive in linux and seabios) Dunno why. I did not have time to try AHCI mode yet. But I think we can drop the wait for non BSY in coreboot beacuse the payload/linux should do that. (the sata_drive_detect) Thanks, Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Test SeaBIOS AHCI support
]Hi, ] ]I think SATA port 4 and 5 may have some issues on SB700 (not detecting drive in ]linux and seabios) ] ]Dunno why. I did not have time to try AHCI mode yet. But I think we can drop the ]wait for non BSY in coreboot beacuse the payload/linux should do that. ] ](the sata_drive_detect) ] ]Thanks, ]Rudolf It might have to do with the SB700 combined mode options. Look at 'combined mode configurations' in http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf Thanks, Scott -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Test SeaBIOS AHCI support
Hi Thanks for the hint, I have seen that but it looks OK. I suspect my BootSwitch (SATA/PATA channel select) might play some role... Not sure yet. I think coreboot does not use combined mode at all. It sets all as IDE, and linux switches the combined mode in quirks.c (quirk_amd_ide_mode) Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
