Hi, I just posted a paper on hardware designs for Blowfish and IDEA. The paper was originally for CHES but rejected. As far as I know, this is the only design of Blowfish in an ASIC. The ciphers were designed in Verilog and synthesized to both PLDs and a standard cell library; they haven't been fabbed; that project has stopped, alas. The paper includes descriptions of the cores, timing, performance, and resource consumption (gates, RAM, ROM). The 52k .pdf is http://www.geocities.com/asicipher/fishnchips.pdf and I am willing to answer questions. I am aware that the paper is a bit unfinished. David
