date:20100319

kernel crash while running h264 codec on DM6446 based board

2010-03-19 Thread Yuvraj Pasi

Hi all,
we are using our own custom made board with DM6446. I have written a camera
capture application which
captures images encodes it in H264, decodes it & then display it on fb.
It runs smoothly for some time & then crashes .

How do I debug this crash dump so that i can find the source of the problem.

ortp-m, *pte=essage-get_pictu, *ppte=re_buffer_size 1
07
ortp-messageInternal error: Oops: 7 [#1]
Modules linked in: dsplinkk cmemk
CPU: 0Not tainted  (2.6.23-davinci1 #219)
PC is at SYNC_WaitSEM+0x1d0/0x260 [dsplinkk]
LR is at __atomic_notifier_call_chain+0x1c/0x24
pc : []lr : []psr: 5013
sp : c1975dd0  ip :   fp : c1975e44
r10: c0038e14  r9 : 8000  r8 : c7930008
r7 : c1974000  r6 : c1975de8  r5 : c793  r4 : c1975de0
r3 : 0001  r2 : c04bb900  r1 : 0002  r0 : c04bb900
Flags: nZcV  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 0005317f  Table: 81794000  DAC: 0015
Process linphonec (pid: 1118, stack limit = 0xc1974260)
Stack: (0xc1975dd0 to 0xc1976000)
5dc0:  c04bb900 c0038e14

5de0:   0001 c04bb900 c0038e14 c7930008 c7930008
c0038edc
5e00: 6013   bf02211c  c7932008 c1975e44
8000
5e20: c15174c0 bf02211c c67526e0 bf02210c   c1975e7c
c1975e48
5e40: bf00c4d4 bf00d4c0 bf00b8d8  c1975e8c c1975e8c 
8000
5e60: 7302 c002861c c1974000 00900036 c1975eac c1975e80 bf00c714
bf00c394
5e80:   c1975f0c  c0027ab4 c1975f00 8000
8000
5ea0: c1975efc c1975eb0 bf008930 bf00c5d8 4002 c6687288 
4002
5ec0: 4002b000 4002 c748d23c c1975f1c c1975f0c c1975ee0 c006e18c
43f60170
5ee0:  43f60170  7302 c1975f34 c1975f00 bf008138
bf0081c8
5f00: 8000  40020480 8200 001eff10 8000 c75758a0
ffe7
5f20: 43f60170 0011 c1975f54 c1975f38 c008b490 bf0080b8 c1975f84
c75758a0
5f40: 43f60170  c1975f7c c1975f58 c008b72c c008b42c 8680
c6752714
5f60: fff7 43f60170 7302 c75758a0 c1975fa4 c1975f80 c008b790
c008b4b0
5f80: c0073d9c 0001 001f02b0 43f61000 00215d70 0036 
c1975fa8
5fa0: c0027e20 c008b75c 001f02b0 43f61000 0011 7302 43f60170
00213e60
5fc0: 001f02b0 43f61000 00215d70 0108 00215d34 05a0 
43f6016c
5fe0: 001d6024 43f60110 000221e4 401d2294 8010 0011 020030fe
e220
Backtrace:
[] (SYNC_WaitSEM+0x0/0x260 [dsplinkk]) from []
(UEVENT_AddBufByPid+0x150/0x17c [dsplinkk])
[] (UEVENT_AddBufByPid+0x0/0x17c [dsplinkk]) from []
(NOTIFY_KnlFinalize+0x14c/0x16c [dsplinkk])
[] (NOTIFY_KnlFinalize+0x0/0x16c [dsplinkk]) from []
(DRV_CallAPI+0x778/0x8f0 [dsplinkk])
 r6:8000 r5:8000 r4:c1975f00
[] (DRV_CallAPI+0x0/0x8f0 [dsplinkk]) from []
(DRV_Ioctl+0x90/0x110 [dsplinkk])
 r7:7302 r6: r5:43f60170 r4:
[] (DRV_Ioctl+0x0/0x110 [dsplinkk]) from []
(do_ioctl+0x74/0x84)
 r7:0011 r6:43f60170 r5:ffe7 r4:c75758a0
[] (do_ioctl+0x0/0x84) from [] (vfs_ioctl+0x28c/0x2ac)
 r6: r5:43f60170 r4:c75758a0
[] (vfs_ioctl+0x0/0x2ac) from [] (sys_ioctl+0x44/0x68)
 r7:c75758a0 r6:7302 r5:43f60170 r4:fff7
[] (sys_ioctl+0x0/0x68) from []
(ret_fast_syscall+0x0/0x2c)
 r7:0036 r6:00215d70 r5:43f61000 r4:001f02b0
Code: eb410c34 e597200c e3a03001 e5823000 (e5953010)


-- 
Thanks & regards
yuvraj pasi
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RE: Dm6467 -PCI Host/master driver support

2010-03-19 Thread Srinivasan, Nageswari

Raghu,

There is no support PCI host driver on DM6467 in 2.6.18 kernel release.

There is a patch set submitted by Hemant for later kernel versions at

https://patchwork.kernel.org/patch/38890/

You can use this as a starting point ...

Regards,
Nageswari.S


From: davinci-linux-open-source-bounces+nageswari=ti@linux.davincidsp.com 
[mailto:davinci-linux-open-source-bounces+nageswari=ti@linux.davincidsp.com]
 On Behalf Of Raghu Ramaraj
Sent: Thursday, March 18, 2010 5:03 PM
To: davinci-linux-open-source@linux.davincidsp.com
Subject: Dm6467 -PCI Host/master driver support

Hi,
 We are trying to interface PCI -SATA device using DM6467. We are using 
"linux-2.6.18_pro500" ( mv_pro_5.0).

1)   Does this kernel have PCI Host/master driver setup?
2)   If its there, how to enable that?
3)   If not... do you have any patch for that?


Thanks & Regards,
Raghu



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dma_alloc_coherent and cache fun

2010-03-19 Thread Jon Povey

Hi folks,

We are using an OSD framebuffer allocated with dma_alloc_coherent(),
mmap()ing it to userspace and doing stuff like software alpha blending.
The buffer is double-sized and we do pan() stuff to implement
double-buffering.

The userspace app is taking a lot of cpu (in userspace, not system)
which I suspect may be to do with lots of small reads and writes to this
uncached memory.

I'd like to have write-back caching on for this buffer and explicitly
flush it in the swap-buffer routine.

Are there some functions I can call on the buffer I got from
dma_alloc_coherent to turn cache back on and do this?

Or should I be allocating the buffer some other way?

Thanks,

-- 
Jon Povey
jon.po...@racelogic.co.uk

 
Racelogic is a limited company registered in England. Registered number 2743719 
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Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, 
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error by reply email so that the sender's address records can be corrected. The 
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[PATCH 0/2] ARM: DaVinci: DM646x PCIHOST: Add PCI Host Controller Support

2010-03-19 Thread Raghu Ramaraj

Hi,
 I am trying interface PCI based SATA & other devices. I came to know that 
there is no PCI host driver in linux-2.6.18_pro500 (mv_pro_5.0).
I have seen your patches in the community portal.

Could you please give us some guidance to move forward?

I need the following information 

1)   Does this patch have tested with PCI device?
2)   I can see 2 patches for this PCI-Host Driver. Do I need to use all 
those?
3)   How did u handle the PIN MUX?


Thanks & Regards,
Raghu| Module Lead | MindTree Ltd. | West Campus Phase - 2 Global Village, RVCE 
Post, Mysore Road, Bangalore- 560 059, INDIA | Voice +91 80 26264000  / Fax +91 
80 2626 4100 | Ext 66475|Mob: +91 9886652214 | email: 
raghu_rama...@mindtree.com| www.mindtree.com |



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RE: [PATCH 0/2] ARM: DaVinci: DM646x PCIHOST: Add PCI Host Controller Support

2010-03-19 Thread Subbrathnam, Swaminathan

Raghu,

Any particular reason in looking for a PCI based SATA solution?  DM644x had a 
ATA interface through which you can interface to HDD's.  You can also go for 
USB-SATA dongles if you are looking specifically for SATA .

regards
swami

From: davinci-linux-open-source-boun...@linux.davincidsp.com 
[davinci-linux-open-source-boun...@linux.davincidsp.com] On Behalf Of Raghu 
Ramaraj [raghu_rama...@mindtree.com]
Sent: Friday, March 19, 2010 5:10 PM
To: Pedanekar, Hemant
Cc: davinci-linux-open-source@linux.davincidsp.com
Subject: [PATCH 0/2] ARM: DaVinci: DM646x PCIHOST: Add PCI Host Controller  
Support

Hi,
 I am trying interface PCI based SATA & other devices. I came to know that 
there is no PCI host driver in linux-2.6.18_pro500 (mv_pro_5.0).
I have seen your patches in the community portal.

Could you please give us some guidance to move forward?

I need the following information ….

1)   Does this patch have tested with PCI device?
2)   I can see 2 patches for this PCI-Host Driver. Do I need to use all 
those?
3)   How did u handle the PIN MUX?


Thanks & Regards,
Raghu| Module Lead | MindTree Ltd. | West Campus Phase – 2 Global Village, RVCE 
Post, Mysore Road, Bangalore- 560 059, INDIA | Voice +91 80 26264000  / Fax +91 
80 2626 4100 | Ext 66475|Mob: +91 9886652214 | email: 
raghu_rama...@mindtree.com| www.mindtree.com |



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RE: [PATCH 0/2] ARM: DaVinci: DM646x PCIHOST: Add PCI Host Controller Support

2010-03-19 Thread Raghu Ramaraj

Hi Swami,
We had already PCI interface board which has PCI devices like 
SATA,wifi..etc.. 


Thanks & Regards,
Raghu
 

-Original Message-
From: Subbrathnam, Swaminathan [mailto:swami.i...@ti.com] 
Sent: Friday, March 19, 2010 5:37 PM
To: Raghu Ramaraj; Pedanekar, Hemant
Cc: davinci-linux-open-source@linux.davincidsp.com
Subject: RE: [PATCH 0/2] ARM: DaVinci: DM646x PCIHOST: Add PCI Host Controller 
Support

Raghu,

Any particular reason in looking for a PCI based SATA solution?  DM644x had a 
ATA interface through which you can interface to HDD's.  You can also go for 
USB-SATA dongles if you are looking specifically for SATA .

regards
swami

From: davinci-linux-open-source-boun...@linux.davincidsp.com 
[davinci-linux-open-source-boun...@linux.davincidsp.com] On Behalf Of Raghu 
Ramaraj [raghu_rama...@mindtree.com]
Sent: Friday, March 19, 2010 5:10 PM
To: Pedanekar, Hemant
Cc: davinci-linux-open-source@linux.davincidsp.com
Subject: [PATCH 0/2] ARM: DaVinci: DM646x PCIHOST: Add PCI Host Controller  
Support

Hi,
 I am trying interface PCI based SATA & other devices. I came to know that 
there is no PCI host driver in linux-2.6.18_pro500 (mv_pro_5.0).
I have seen your patches in the community portal.

Could you please give us some guidance to move forward?

I need the following information 

1)   Does this patch have tested with PCI device?
2)   I can see 2 patches for this PCI-Host Driver. Do I need to use all 
those?
3)   How did u handle the PIN MUX?


Thanks & Regards,
Raghu| Module Lead | MindTree Ltd. | West Campus Phase - 2 Global Village, RVCE 
Post, Mysore Road, Bangalore- 560 059, INDIA | Voice +91 80 26264000  / Fax +91 
80 2626 4100 | Ext 66475|Mob: +91 9886652214 | email: 
raghu_rama...@mindtree.com| www.mindtree.com |



http://www.mindtree.com/email/disclaimer.html
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RE: [PATCH v4 2/3] davinci: da8xx/omapl EVM: Specify reserved channels/slots

2010-03-19 Thread Nori, Sekhar

On Thu, Mar 18, 2010 at 17:09:55, I wrote:
> On Wed, Mar 17, 2010 at 22:48:46, Kevin Hilman wrote:

[...]

> >
> > In addition, after looking at this a little closer, the *_edma_info
> > structs in devices-da8xx.c could be __initdata since they are copied
> > during edma_probe() (should be done as a fix before this patch.)  The
> > same for the rsv structs in the board files.
>
> Okay, actually the whole EDMA platform device needs to be __initdata.

... which is incorrect because platform devices can be accessed
later using sysfs. But, just having just the platform_data as
__initdata is also wrong because a persistent object (platform_device)
holds a reference to it. In this case, we "know" the platform data
will not be used, but the kernel detects it and responds with pesky
warnings with CONFIG_DEBUG_SECTION_MISMATCH=y. So, it doesn't look like
*_edma_info structures can be marked __initdata.

Thanks,
Sekhar

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Re: [PATCH v4 2/3] davinci: da8xx/omapl EVM: Specify reserved channels/slots

2010-03-19 Thread Kevin Hilman

"Nori, Sekhar"  writes:

> On Thu, Mar 18, 2010 at 17:09:55, I wrote:
>> On Wed, Mar 17, 2010 at 22:48:46, Kevin Hilman wrote:
>
> [...]
>
>> >
>> > In addition, after looking at this a little closer, the *_edma_info
>> > structs in devices-da8xx.c could be __initdata since they are copied
>> > during edma_probe() (should be done as a fix before this patch.)  The
>> > same for the rsv structs in the board files.
>>
>> Okay, actually the whole EDMA platform device needs to be __initdata.
>
> ... which is incorrect because platform devices can be accessed
> later using sysfs. But, just having just the platform_data as
> __initdata is also wrong because a persistent object (platform_device)
> holds a reference to it. In this case, we "know" the platform data
> will not be used, but the kernel detects it and responds with pesky
> warnings with CONFIG_DEBUG_SECTION_MISMATCH=y. So, it doesn't look like
> *_edma_info structures can be marked __initdata.

If that's the case, then the copies should be removed from _probe as
well, and pointers to original data used.

Kevin
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[PATCH 2/4] Davinci: enable timer clock before use

2010-03-19 Thread Cyril Chemparathy

timer_init() programs timer64 hardware.  The module should ideally be brought
out of reset before this happens.

Signed-off-by: Cyril Chemparathy 
---
 arch/arm/mach-davinci/time.c |6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 9e0b106..b21f763 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -361,13 +361,13 @@ static void __init davinci_timer_init(void)
}
}
 
-   /* init timer hw */
-   timer_init();
-
timer_clk = clk_get(NULL, "timer0");
BUG_ON(IS_ERR(timer_clk));
clk_enable(timer_clk);
 
+   /* init timer hw */
+   timer_init();
+
davinci_clock_tick_rate = clk_get_rate(timer_clk);
 
/* setup clocksource */
-- 
1.6.3.3

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[PATCH 3/4] Davinci: cpintc host map configuration

2010-03-19 Thread Cyril Chemparathy

Host map configuration instructs the interrupt controller to route interrupt
channels to FIQ or IRQ lines.  Currently, DA8xx family of devices leave these
registers at their reset-default values.

TNETV107X however does not have sane reset defaults, and therefore this
architecture needs to reconfigure the host-map such that channels 0 and 1
go to FIQ, and the remaining channels raise IRQs.

This patch adds an optional host map argument to cp_intc_init() for this.

Signed-off-by: Cyril Chemparathy 
---
 arch/arm/mach-davinci/board-da830-evm.c  |2 +-
 arch/arm/mach-davinci/board-da850-evm.c  |2 +-
 arch/arm/mach-davinci/cp_intc.c  |6 +-
 arch/arm/mach-davinci/include/mach/cp_intc.h |2 +-
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/board-da830-evm.c 
b/arch/arm/mach-davinci/board-da830-evm.c
index ea293b8..db5ac0f 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -569,7 +569,7 @@ static __init void da830_evm_irq_init(void)
struct davinci_soc_info *soc_info = &davinci_soc_info;
 
cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA830_N_CP_INTC_IRQ,
-   soc_info->intc_irq_prios);
+   soc_info->intc_irq_prios, NULL);
 }
 
 static void __init da830_evm_map_io(void)
diff --git a/arch/arm/mach-davinci/board-da850-evm.c 
b/arch/arm/mach-davinci/board-da850-evm.c
index 411284d..ef691ae 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -741,7 +741,7 @@ static __init void da850_evm_irq_init(void)
struct davinci_soc_info *soc_info = &davinci_soc_info;
 
cp_intc_init((void __iomem *)DA8XX_CP_INTC_VIRT, DA850_N_CP_INTC_IRQ,
-   soc_info->intc_irq_prios);
+   soc_info->intc_irq_prios, NULL);
 }
 
 static void __init da850_evm_map_io(void)
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 37311d1..2a8d26e 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -101,7 +101,7 @@ static struct irq_chip cp_intc_irq_chip = {
 };
 
 void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-u8 *irq_prio)
+u8 *irq_prio, u32 *host_map)
 {
unsigned num_reg= BITS_TO_LONGS(num_irq);
int i;
@@ -157,6 +157,10 @@ void __init cp_intc_init(void __iomem *base, unsigned 
short num_irq,
cp_intc_write(0x0f0f0f0f, CP_INTC_CHAN_MAP(i));
}
 
+   if (host_map)
+   for (i = 0; host_map[i] != -1; i++)
+   cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
+
/* Set up genirq dispatching for cp_intc */
for (i = 0; i < num_irq; i++) {
set_irq_chip(i, &cp_intc_irq_chip);
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h 
b/arch/arm/mach-davinci/include/mach/cp_intc.h
index c4d27ee..121b114 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -52,6 +52,6 @@
 #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2))
 
 void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
-u8 *irq_prio);
+u8 *irq_prio, u32 *host_map);
 
 #endif /* __ASM_HARDWARE_CP_INTC_H */
-- 
1.6.3.3

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[PATCH 4/4] Davinci: support LPSC SwRstDisable state

2010-03-19 Thread Cyril Chemparathy

The current clock control code always gates the clock (PSC state Disable = 2)
on clk_disable().  Some on-chip peripherals (e.g. LCD controller on TNETV107X)
need to be put into SwRstDisable = 0 on clock disable, to maintain
hardware sanity.

This patch extends the davinci_psc_config() arguments to pass in the desired
module state instead of a boolean enable/disable.  Further, clk_disable() now
checks for the PSC_SWRSTDISABLE clk flag before selecting the target state.

Signed-off-by: Cyril Chemparathy 
---
 arch/arm/mach-davinci/clock.c|   12 +---
 arch/arm/mach-davinci/clock.h|1 +
 arch/arm/mach-davinci/include/mach/psc.h |8 +++-
 arch/arm/mach-davinci/psc.c  |3 +--
 4 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 058c77f..5de60ae 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -43,7 +43,8 @@ static void __clk_enable(struct clk *clk)
if (clk->parent)
__clk_enable(clk->parent);
if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
-   davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1);
+   davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+   PSC_STATE_ENABLE);
 }
 
 static void __clk_disable(struct clk *clk)
@@ -52,7 +53,9 @@ static void __clk_disable(struct clk *clk)
return;
if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
(clk->flags & CLK_PSC))
-   davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
+   davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+   (clk->flags & PSC_SWRSTDISABLE) ?
+   PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
if (clk->parent)
__clk_disable(clk->parent);
 }
@@ -234,7 +237,10 @@ static int __init clk_disable_unused(void)
continue;
 
pr_info("Clocks: disable unused %s\n", ck->name);
-   davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0);
+
+   davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
+   (ck->flags & PSC_SWRSTDISABLE) ?
+   PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
}
spin_unlock_irq(&clockfw_lock);
 
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index aa0a611..9be51bb 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -105,6 +105,7 @@ struct clk {
 #define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
 #define CLK_PLLBIT(4) /* PLL-derived clock */
 #define PRE_PLL BIT(5) /* source is before PLL mult/div */
+#define PSC_SWRSTDISABLEBIT(6) /* Disable state is SwRstDisable */
 
 #define CLK(dev, con, ck)  \
{   \
diff --git a/arch/arm/mach-davinci/include/mach/psc.h 
b/arch/arm/mach-davinci/include/mach/psc.h
index 651f6d8..7dd2962 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -189,13 +189,19 @@
 #define MDSTAT 0x800
 #define MDCTL  0xA00
 
+/* PSC module states */
+#define PSC_STATE_SWRSTDISABLE 0
+#define PSC_STATE_SYNCRST  1
+#define PSC_STATE_DISABLE  2
+#define PSC_STATE_ENABLE   3
+
 #define MDSTAT_STATE_MASK 0x1f
 
 #ifndef __ASSEMBLER__
 
 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-   unsigned int id, char enable);
+   unsigned int id, u32 next_state);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index adf6b5c..d7cb438 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -47,12 +47,11 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, 
unsigned int id)
 
 /* Enable or disable a PSC domain */
 void davinci_psc_config(unsigned int domain, unsigned int ctlr,
-   unsigned int id, char enable)
+   unsigned int id, u32 next_state)
 {
u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
void __iomem *psc_base;
struct davinci_soc_info *soc_info = &davinci_soc_info;
-   u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
 
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
-- 
1.6.3.3

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[PATCH 1/4] Davinci: Allow SOCs based on other ARM CPUs

2010-03-19 Thread Cyril Chemparathy

Preliminary modification prior to adding support for TNETV107X based on
ARM1176.  This change allows for CPUs other than ARM926T to be used for Davinci
derivative SoCs.  Existing devices (DA8x and DMx) operate unchanged.

Signed-off-by: Cyril Chemparathy 
---
 arch/arm/Kconfig  |1 -
 arch/arm/mach-davinci/Kconfig |2 ++
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3b18128..2553c75 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -702,7 +702,6 @@ config ARCH_U300
 
 config ARCH_DAVINCI
bool "TI DaVinci"
-   select CPU_ARM926T
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 0ebe185..0316e20 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -7,6 +7,7 @@ config CP_INTC
bool
 
 config ARCH_DAVINCI_DMx
+   select CPU_ARM926T
bool
 
 menu "TI DaVinci Implementations"
@@ -41,6 +42,7 @@ config ARCH_DAVINCI_DA850
select ARCH_HAS_CPUFREQ
 
 config ARCH_DAVINCI_DA8XX
+   select CPU_ARM926T
bool
 
 config ARCH_DAVINCI_DM365
-- 
1.6.3.3

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Re: [PATCH 3/4] Davinci: cpintc host map configuration

2010-03-19 Thread Sergei Shtylyov


Hello.

Cyril Chemparathy wrote:


Host map configuration instructs the interrupt controller to route interrupt
channels to FIQ or IRQ lines.  Currently, DA8xx family of devices leave these
registers at their reset-default values.

TNETV107X however does not have sane reset defaults, and therefore this
architecture needs to reconfigure the host-map such that channels 0 and 1
go to FIQ, and the remaining channels raise IRQs.

This patch adds an optional host map argument to cp_intc_init() for this.

Signed-off-by: Cyril Chemparathy 


  Hey, if cp_intc.c is used outside arch/arm/mach-davinci/, it needs to 
be moved first, probalby to arch/arm/common/...


WBR, Sergei

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kernel crash while running h264 codec on DM6446 based board

RE: Dm6467 -PCI Host/master driver support

dma_alloc_coherent and cache fun

[PATCH 0/2] ARM: DaVinci: DM646x PCIHOST: Add PCI Host Controller Support

RE: [PATCH 0/2] ARM: DaVinci: DM646x PCIHOST: Add PCI Host Controller Support

RE: [PATCH 0/2] ARM: DaVinci: DM646x PCIHOST: Add PCI Host Controller Support

RE: [PATCH v4 2/3] davinci: da8xx/omapl EVM: Specify reserved channels/slots

Re: [PATCH v4 2/3] davinci: da8xx/omapl EVM: Specify reserved channels/slots

[PATCH 2/4] Davinci: enable timer clock before use

[PATCH 3/4] Davinci: cpintc host map configuration

[PATCH 4/4] Davinci: support LPSC SwRstDisable state

[PATCH 1/4] Davinci: Allow SOCs based on other ARM CPUs

Re: [PATCH 3/4] Davinci: cpintc host map configuration

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