Re: isif - debugging on dm365
Hi Jean-Philippe,
I finally create my patch against f5cef8f45739db4c0c1c346296922cac274c87eb
in attachment, but the problem is that isif_set_hw_if_params is not called
by gstreamer.
If I set in drivers/media/video/davinci/isif.c (and not in
drivers/media/video/davinci/dm365_ccdc.c as I don't have it !!)
'ycswap=YCIN_NOT_SWP'
it works !!
The board file has no effect on my gstreamer command:
gst-launch v4l2src ! video/x-raw-yuv ! filesink location=video_new3.raw
see below for my complete logs.
Here you are the board declaration:
static struct vpfe_subdev_info vpfe_sub_devs[] = {
{
.name = adv7180,
.grp_id = 0,
.num_inputs = ARRAY_SIZE(adv7180_inputs),
.inputs = adv7180_inputs,
.routes = adv7180_routes,
.can_route = 1,
.ccdc_if_params = {
.if_type = VPFE_BT656,
.hdpol = VPFE_PINPOL_POSITIVE,
.vdpol = VPFE_PINPOL_POSITIVE,
.ycswap = YCIN_NOT_SWP,
},
.board_info = {
I2C_BOARD_INFO(adv7180, 0x20),
.platform_data = adv7180_pdata,
},
},
};
The patch is very similar to yours, I change only the name of defines
because they seem more clear to me.
The complete log (setting ycswap=YCIN_SWP inside isif.c file in order to try
to get the correct parameter from my board file) follows:
(isif_set_hw_if_params is not called)
r...@dm365-evm:~# gst-launch v4l2src ! video/x-raw-yuv ! filesink
location=video
_new3.raw
Setting pipeline to PAUSED ...
vpfe-capture vpfe-capture: vpfe_open
vpfe-capture vpfe-capture: vpfe_querycap
vpfe-capture vpfe-capture: vpfe_enum_input
vpfe-capture vpfe-capture: vpfe_enum_input
vpfe-capture vpfe-capture: input information not found for the subdev
vpfe-capture vpfe-capture: vpfe_g_std
vpfe-capture vpfe-capture: vpfe_g_input
vpfe-capture vpfe-capture: vpfe_enum_fmt_vid_cap
vpfe-capture vpfe-capture: vpfe_enum_fmt_vid_cap
vpfe-capture vpfe-capture: vpfe_enum_fmt_vid_cap
vpfe-capture vpfe-capture: vpfe_try_fmt_vid_cap
vpfe-capture vpfe-capture: width = 1, height = 1, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 16, height = 2, bpp = 2,
bytesperline = 32, sizeimage = 64
vpfe-capture vpfe-capture: vpfe_try_fmt_vid_cap
vpfe-capture vpfe-capture: width = 32768, height = 32768, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 720, height = 480, bpp = 2,
bytesperline = 1440, sizeimage = 691200
vpfe-capture vpfe-capture: vpfe_try_fmt_vid_cap
vpfe-capture vpfe-capture: width = 1, height = 1, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 16, height = 2, bpp = 2,
bytesperline = 32, sizeimage = 64
vpfe-capture vpfe-capture: vpfe_try_fmt_vid_cap
vpfe-capture vpfe-capture: width = 32768, height = 32768, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 720, height = 480, bpp = 2,
bytesperline = 1440, sizeimage = 691200
vpfe-capture vpfe-capture: vpfe_g_fmt_vid_cap
vpfe-capture vpfe-capture: vpfe_s_fmt_vid_cap
vpfe-capture vpfe-capture: width = 720, height = 480, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 720, height = 480, bpp = 2,
bytesperline = 1440, sizeimage = 691200
vpfe-capture vpfe-capture: vpfe_g_std
vpfe-capture vpfe-capture: vpfe_reqbufs
vpfe-capture vpfe-capture: vpfe_buffer_setup
vpfe-capture vpfe-capture: count=3, size=1147200
vpfe-capture vpfe-capture: vpfe_querybuf
vpfe-capture vpfe-capture: vpfe_mmap
vpfe-capture vpfe-capture: vpfe_querybuf
vpfe-capture vpfe-capture: vpfe_mmap
vpfe-capture vpfe-capture: vpfe_querybuf
vpfe-capture vpfe-capture: vpfe_mmap
vpfe-capture vpfe-capture: vpfe_qbuf
vpfe-capture vpfe-capture: vpfe_buffer_prepare
vpfe-capture vpfe-capture: vpfe_qbuf
vpfe-capture vpfe-capture: vpfe_buffer_prepare
vpfe-capture vpfe-capture: vpfe_qbuf
vpfe-capture vpfe-capture: vpfe_buffer_prepare
vpfe-capture vpfe-capture: vpfe_streamon
vpfe-capture vpfe-capture: vpfe_buffer_queue
vpfe-capture vpfe-capture: vpfe_buffer_queue
vpfe-capture vpfe-capture: vpfe_buffer_queue
vpfe-capture vpfe-capture: vpfe_calculate_offsets
isif_config_ycbcr - if_type = 0
isif_config_ycbcr - ycswap = 1
isif_config_ycbcr -924
isif_config_ycbcr -927
Pipeline is live and does not need PREROLL ...
Setting pipeline to PLAYING ...
vpfe-capture vpfe-capture: vpfe_poll
New clock: GstSystemClock
2010/4/7 Jean-Philippe François jp.franc...@cynove.com
Raffaele Recalcati a écrit :
I was adding isif_cfg.y_c_swap variable, but it need a modification inside
arch/arm/mach-davinci/dm365.c that I think is not the right direction.
I mean, the isif platform data is not board related, but it is cpu
related.
sensor or decoder connection to the isif is definitely board related.
the ccdc_if_params field of the vpfe_subdev_info struct is used by
the ccdc code in the ccdc_set_hw_if_params function.
Here is a patch that implement an ycswap field.
It is set in the board
Re: isif - debugging on dm365
I suppose it does not work, because isif_set_hw_if params is only called
if the user applications is doing a VIDIOC_S_INPUT.
based on your log, it seems gstreamer does not do that.
I don't know if the driver or the application should be corrected.
May be there is a command switch to gstreamer that allows to specify an input ?
Raffaele Recalcati a écrit :
Hi Jean-Philippe,
I finally create my patch against
f5cef8f45739db4c0c1c346296922cac274c87eb in attachment, but the problem
is that isif_set_hw_if_params is not called by gstreamer.
If I set in drivers/media/video/davinci/isif.c (and not in
drivers/media/video/davinci/dm365_ccdc.c as I don't have it !!)
'ycswap=YCIN_NOT_SWP'
it works !!
The board file has no effect on my gstreamer command:
gst-launch v4l2src ! video/x-raw-yuv ! filesink location=video_new3.raw
see below for my complete logs.
Here you are the board declaration:
static struct vpfe_subdev_info vpfe_sub_devs[] = {
{
.name = adv7180,
.grp_id = 0,
.num_inputs = ARRAY_SIZE(adv7180_inputs),
.inputs = adv7180_inputs,
.routes = adv7180_routes,
.can_route = 1,
.ccdc_if_params = {
.if_type = VPFE_BT656,
.hdpol = VPFE_PINPOL_POSITIVE,
.vdpol = VPFE_PINPOL_POSITIVE,
.ycswap = YCIN_NOT_SWP,
},
.board_info = {
I2C_BOARD_INFO(adv7180, 0x20),
.platform_data = adv7180_pdata,
},
},
};
The patch is very similar to yours, I change only the name of defines
because they seem more clear to me.
The complete log (setting ycswap=YCIN_SWP inside isif.c file in order to
try to get the correct parameter from my board file) follows:
(isif_set_hw_if_params is not called)
r...@dm365-evm:~# gst-launch v4l2src ! video/x-raw-yuv ! filesink
location=video
_new3.raw
Setting pipeline to PAUSED ...
vpfe-capture vpfe-capture: vpfe_open
vpfe-capture vpfe-capture: vpfe_querycap
vpfe-capture vpfe-capture: vpfe_enum_input
vpfe-capture vpfe-capture: vpfe_enum_input
vpfe-capture vpfe-capture: input information not found for the subdev
vpfe-capture vpfe-capture: vpfe_g_std
vpfe-capture vpfe-capture: vpfe_g_input
vpfe-capture vpfe-capture: vpfe_enum_fmt_vid_cap
vpfe-capture vpfe-capture: vpfe_enum_fmt_vid_cap
vpfe-capture vpfe-capture: vpfe_enum_fmt_vid_cap
vpfe-capture vpfe-capture: vpfe_try_fmt_vid_cap
vpfe-capture vpfe-capture: width = 1, height = 1, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 16, height = 2, bpp = 2,
bytesperline = 32, sizeimage = 64
vpfe-capture vpfe-capture: vpfe_try_fmt_vid_cap
vpfe-capture vpfe-capture: width = 32768, height = 32768, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 720, height = 480, bpp = 2,
bytesperline = 1440, sizeimage = 691200
vpfe-capture vpfe-capture: vpfe_try_fmt_vid_cap
vpfe-capture vpfe-capture: width = 1, height = 1, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 16, height = 2, bpp = 2,
bytesperline = 32, sizeimage = 64
vpfe-capture vpfe-capture: vpfe_try_fmt_vid_cap
vpfe-capture vpfe-capture: width = 32768, height = 32768, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 720, height = 480, bpp = 2,
bytesperline = 1440, sizeimage = 691200
vpfe-capture vpfe-capture: vpfe_g_fmt_vid_cap
vpfe-capture vpfe-capture: vpfe_s_fmt_vid_cap
vpfe-capture vpfe-capture: width = 720, height = 480, bpp = 2
vpfe-capture vpfe-capture: adjusted width = 720, height = 480, bpp = 2,
bytesperline = 1440, sizeimage = 691200
vpfe-capture vpfe-capture: vpfe_g_std
vpfe-capture vpfe-capture: vpfe_reqbufs
vpfe-capture vpfe-capture: vpfe_buffer_setup
vpfe-capture vpfe-capture: count=3, size=1147200
vpfe-capture vpfe-capture: vpfe_querybuf
vpfe-capture vpfe-capture: vpfe_mmap
vpfe-capture vpfe-capture: vpfe_querybuf
vpfe-capture vpfe-capture: vpfe_mmap
vpfe-capture vpfe-capture: vpfe_querybuf
vpfe-capture vpfe-capture: vpfe_mmap
vpfe-capture vpfe-capture: vpfe_qbuf
vpfe-capture vpfe-capture: vpfe_buffer_prepare
vpfe-capture vpfe-capture: vpfe_qbuf
vpfe-capture vpfe-capture: vpfe_buffer_prepare
vpfe-capture vpfe-capture: vpfe_qbuf
vpfe-capture vpfe-capture: vpfe_buffer_prepare
vpfe-capture vpfe-capture: vpfe_streamon
vpfe-capture vpfe-capture: vpfe_buffer_queue
vpfe-capture vpfe-capture: vpfe_buffer_queue
vpfe-capture vpfe-capture: vpfe_buffer_queue
vpfe-capture vpfe-capture: vpfe_calculate_offsets
isif_config_ycbcr - if_type = 0
isif_config_ycbcr - ycswap = 1
isif_config_ycbcr -924
isif_config_ycbcr -927
Pipeline is live and does not need PREROLL ...
Setting pipeline to PLAYING ...
vpfe-capture vpfe-capture: vpfe_poll
New clock: GstSystemClock
2010/4/7 Jean-Philippe François jp.franc...@cynove.com
mailto:jp.franc...@cynove.com
Raffaele Recalcati a écrit :
I was adding isif_cfg.y_c_swap variable, but it need a
Re: dm365 - voice codec
Hello everybody. If I'm not wrong it doesn't yet exist the voice codec for dm365. Is there any roadmap to support this peripheral? Thank in advance. 2010/4/1 Raffaele Recalcati lamiapost...@gmail.com It seems that in git kernel this peripheral is not yet supported. I search everywere: ./arch/arm/mach-davinci/dm365.c:CLK(davinci_voicecodec, NULL, voicecodec_clk), ./arch/arm/mach-davinci/dm365.c:.name = davinci_voicecodec, This means that davinci_voicecodec is not really configured. Anybody can please confirm this point and tell me the development roadmap? Thx, Raffaele -- www.opensurf.it ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
RE: SPI Support for DA850 (OMAPL-138).
Mike - I do plan on resubmitting the driver as a replacement driver (remove the old and add the updated version) as suggested by TI. I am just trying to get some other work finished up first. If you want to try the version I submitted, the patch was actually against the arago kernel. You can try patching that version and pulling it into your kernel to see if that fixes your issues. Hopefully I'll get around to resubmitting the driver for consideration some time this week. Brian -Original Message- From: davinci-linux-open-source-boun...@linux.davincidsp.com [mailto:davinci-linux-open-source-boun...@linux.davincidsp.com ] On Behalf Of Mike Williamson Sent: Sunday, April 11, 2010 9:56 AM To: davinci-linux-open-source@linux.davincidsp.com Subject: SPI Support for DA850 (OMAPL-138). Hi, I've been working with Kevin's tree and have been having some problems with the SPI interface for the DA850 (OMAP-L138), SPI version 2. I am getting a lot of failures in the davinci_spi_check_error routine that I'm not sure are real errors. I was googling around and found this thread: http://linux.omap.com/pipermail/davinci-linux-open-source/2009 -July/015025.html The thread raises the same issue that I have found in that the routine is declaring an error if the status of the SPI engine is claiming that the Tx buffer is empty (SPIFLG_TX_INTR_MASK) and there is also a check on a bit (SPIFLG_BUF_INIT_ACTIVE_MASK, bit 24) that is undocumented in the SPI user guide. I found that I had to turn off both of these checks in order for the SPI to work with our device in polled mode with no DMAs.The device is an m25p64 EEPROM, same configuration as on the 850 / OMAPL138 evm. Can anyone confirm if the spi implementation in Kevin's tree is working for VERSION_2 SPI devices (850 specifically), and what SPI configuration you're using? I am also wondering if the SPI patches from Brian Niebuhr have died on the wire (http://linux.davincidsp.com/pipermail/davinci-linux-open-sour ce/2010-March/018077.html). It seemed like he had identified several issues with the driver and had taken a crack at sorting them out. -Mike -- Michael Williamson 315-425-4045x230 www.criticallink.com ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: [PATCH v2 14/16] Davinci: tnetv107x gpio implementation
Hi Kevin, Both the existing functions and the new functions all do basically the same thing: - read base + offset - set/clear bit(s) based on GPIO# - write base + offset Davinci doesn't really do a read-modify-write. Instead, it sets bits into set_data/clr_data registers to indirectly manipulate out_data contents. On the other hand, the tnetv107x controller follows a read-modify-write as you've outlined. This poses a bit of a problem is structuring a common table containing register offsets and bitmasks. Is there a problem with writing to the out_data register instead of set/clr_data? Regards Cyril. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
[PATCH 0/8] davinci common code changes for tnetv107x
This patch series contains a bundle of common code changes that are needed as a precursor to adding tnetv107x soc support. Some of these patches were sent out separately earlier, but have also been included here. This patch series has been boot-up tested on dm365, thanks to Sandeep. Cyril Chemparathy (8): Davinci: iotable based ioremap() interception Davinci: generalized debug macros Davinci: configurable pll divider mask Davinci: gpio - minor cleanup Davinci: gpio - struct renames Davinci: gpio - register layout invariant inlines Davinci: gpio - controller type support Davinci: gpio - fine grained locking arch/arm/mach-davinci/clock.c|9 +- arch/arm/mach-davinci/clock.h|1 + arch/arm/mach-davinci/da830.c|8 +- arch/arm/mach-davinci/da850.c| 10 ++- arch/arm/mach-davinci/dm355.c|1 + arch/arm/mach-davinci/dm365.c|1 + arch/arm/mach-davinci/dm644x.c |1 + arch/arm/mach-davinci/dm646x.c |1 + arch/arm/mach-davinci/gpio.c | 133 ++ arch/arm/mach-davinci/include/mach/common.h |5 + arch/arm/mach-davinci/include/mach/debug-macro.S | 51 +++-- arch/arm/mach-davinci/include/mach/gpio.h| 72 ++--- arch/arm/mach-davinci/include/mach/io.h |4 + arch/arm/mach-davinci/include/mach/serial.h | 13 ++ arch/arm/mach-davinci/include/mach/uncompress.h | 80 ++ arch/arm/mach-davinci/io.c | 33 +- 16 files changed, 293 insertions(+), 130 deletions(-) ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
[PATCH 3/8] Davinci: configurable pll divider mask
This patch allows socs to override the divider ratio mask by setting an
optional field (div_ratio_mask) in the pll_data structure.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Tested-by: Sandeep Paulraj s-paul...@ti.com
---
arch/arm/mach-davinci/clock.c |9 ++---
arch/arm/mach-davinci/clock.h |1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 5de60ae..828f434 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -279,7 +279,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
v = __raw_readl(pll-base + clk-div_reg);
if (v PLLDIV_EN) {
- plldiv = (v PLLDIV_RATIO_MASK) + 1;
+ plldiv = (v pll-div_ratio_mask) + 1;
if (plldiv)
rate /= plldiv;
}
@@ -319,7 +319,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
if (pll-flags PLL_HAS_PREDIV) {
prediv = __raw_readl(pll-base + PREDIV);
if (prediv PLLDIV_EN)
- prediv = (prediv PLLDIV_RATIO_MASK) + 1;
+ prediv = (prediv pll-div_ratio_mask) + 1;
else
prediv = 1;
}
@@ -331,7 +331,7 @@ static unsigned long clk_pllclk_recalc(struct clk *clk)
if (pll-flags PLL_HAS_POSTDIV) {
postdiv = __raw_readl(pll-base + POSTDIV);
if (postdiv PLLDIV_EN)
- postdiv = (postdiv PLLDIV_RATIO_MASK) + 1;
+ postdiv = (postdiv pll-div_ratio_mask) + 1;
else
postdiv = 1;
}
@@ -464,6 +464,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks)
if (clk-lpsc)
clk-flags |= CLK_PSC;
+ if (clk-pll_data !clk-pll_data-div_ratio_mask)
+ clk-pll_data-div_ratio_mask = PLLDIV_RATIO_MASK;
+
clk_register(clk);
num_clocks++;
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 53a0f7b..ce26015 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -76,6 +76,7 @@ struct pll_data {
u32 num;
u32 flags;
u32 input_rate;
+ u32 div_ratio_mask;
};
#define PLL_HAS_PREDIV 0x01
#define PLL_HAS_POSTDIV 0x02
--
1.6.3.3
___
Davinci-linux-open-source mailing list
Davinci-linux-open-source@linux.davincidsp.com
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
[PATCH 7/8] Davinci: gpio - controller type support
This patch allows for gpio controllers that deviate from those found on
traditional davinci socs. davinci_soc_info has an added field to indicate the
soc-specific gpio controller type. The gpio initialization code then bails
out of necessary.
More elements (tnetv107x) to be added later into enum davinci_gpio_type.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Tested-by: Sandeep Paulraj s-paul...@ti.com
---
arch/arm/mach-davinci/da830.c |1 +
arch/arm/mach-davinci/da850.c |1 +
arch/arm/mach-davinci/dm355.c |1 +
arch/arm/mach-davinci/dm365.c |1 +
arch/arm/mach-davinci/dm644x.c |1 +
arch/arm/mach-davinci/dm646x.c |1 +
arch/arm/mach-davinci/gpio.c|3 +++
arch/arm/mach-davinci/include/mach/common.h |1 +
arch/arm/mach-davinci/include/mach/gpio.h |4
9 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 168f277..c4b30c4 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1199,6 +1199,7 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
.intc_irq_prios = da830_default_priorities,
.intc_irq_num = DA830_N_CP_INTC_IRQ,
.timer_info = da830_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
.gpio_num = 128,
.gpio_irq = IRQ_DA8XX_GPIO0,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 27eb32e..2aa9748 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1084,6 +1084,7 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
.intc_irq_prios = da850_default_priorities,
.intc_irq_num = DA850_N_CP_INTC_IRQ,
.timer_info = da850_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
.gpio_num = 144,
.gpio_irq = IRQ_DA8XX_GPIO0,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 5efce70..f9a54ff 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -859,6 +859,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
.intc_irq_prios = dm355_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = dm355_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_num = 104,
.gpio_irq = IRQ_DM355_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 871be5a..d81c440 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1063,6 +1063,7 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
.intc_irq_prios = dm365_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = dm365_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_num = 104,
.gpio_irq = IRQ_DM365_GPIO0,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 23cbe9d..4af349e 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -748,6 +748,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
.intc_irq_prios = dm644x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = dm644x_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_num = 71,
.gpio_irq = IRQ_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index b67b997..899859c 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -858,6 +858,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
.intc_irq_prios = dm646x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = dm646x_timer_info,
+ .gpio_type = GPIO_TYPE_DAVINCI,
.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
.gpio_num = 43, /* Only 33 usable */
.gpio_irq = IRQ_DM646X_GPIOBNK0,
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 082a098..3a78897 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -143,6 +143,9 @@ static int __init
[PATCH 2/8] Davinci: generalized debug macros
This patch adopts a debug uart selection similar to the OMAP model. During
the boot process, the uncompress code determines the physical and virtual base
addresses of the board-specific debug uart. These addresses are then passed
on to the in-kernel debug macros through a small chunk of memory placed just
below the page tables (@0x80003ff8).
Signed-off-by: Cyril Chemparathy cy...@ti.com
Tested-by: Sandeep Paulraj s-paul...@ti.com
---
arch/arm/mach-davinci/include/mach/debug-macro.S | 51 +++---
arch/arm/mach-davinci/include/mach/serial.h | 13
arch/arm/mach-davinci/include/mach/uncompress.h | 80 --
3 files changed, 112 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S
b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 3cd93a8..ac0fa02 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -17,22 +17,51 @@
*/
#include linux/serial_reg.h
+
+#include asm/memory.h
+
+#include mach/serial.h
+
#define UART_SHIFT 2
+ .pushsection .data
+davinci_uart_phys: .word 0
+davinci_uart_virt: .word 0
+ .popsection
+
.macro addruart, rx, tmp
+
+ /* Use davinci_uart_phys/virt if already configured */
+10:mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @ MMU enabled?
+ ldreq \rx, =__virt_to_phys(davinci_uart_phys)
+ ldrne \rx, =davinci_uart_virt
+ ldr \rx, [\rx]
+ cmp \rx, #0 @ is port configured?
+ bne 99f @ already configured
+
+ /* Copy uart phys address from decompressor uart info */
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
- moveq \rx, #0x0100@ physical base address
- movne \rx, #0xfe00@ virtual base
-#if defined(CONFIG_ARCH_DAVINCI_DA8XX) defined(CONFIG_ARCH_DAVINCI_DMx)
-#error Cannot enable DaVinci and DA8XX platforms concurrently
-#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \
- defined(CONFIG_MACH_DAVINCI_DA850_EVM)
- orr \rx, \rx, #0x00d0 @ physical base address
- orr \rx, \rx, #0xd000 @ of UART 2
-#else
- orr \rx, \rx, #0x00c2 @ UART 0
-#endif
+ ldreq \tmp, =__virt_to_phys(davinci_uart_phys)
+ ldrne \tmp, =davinci_uart_phys
+ ldreq \rx, =DAVINCI_UART_INFO
+ ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO)
+ ldr \rx, [\rx, #0]
+ str \rx, [\tmp]
+
+ /* Copy uart virt address from decompressor uart info */
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @ MMU enabled?
+ ldreq \tmp, =__virt_to_phys(davinci_uart_virt)
+ ldrne \tmp, =davinci_uart_virt
+ ldreq \rx, =DAVINCI_UART_INFO
+ ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO)
+ ldr \rx, [\rx, #4]
+ str \rx, [\tmp]
+
+ b 10b
+99:
.endm
.macro senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/serial.h
b/arch/arm/mach-davinci/include/mach/serial.h
index a584697..8829dde 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -11,8 +11,19 @@
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
+#include asm/memory.h
+
#include mach/hardware.h
+/*
+ * Stolen area that contains debug uart physical and virtual addresses. These
+ * addresses are filled in by the uncompress.h code, and are used by the debug
+ * macros in debug-macro.S.
+ *
+ * This area sits just below the page tables (see arch/arm/kernel/head.S).
+ */
+#define DAVINCI_UART_INFO (PHYS_OFFSET + 0x3ff8)
+
#define DAVINCI_MAX_NR_UARTS 3
#define DAVINCI_UART0_BASE (IO_PHYS + 0x2)
#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
@@ -27,11 +38,13 @@
#define UART_DM646X_SCR0x10
#define UART_DM646X_SCR_TX_WATERMARK 0x08
+#ifndef __ASSEMBLY__
struct davinci_uart_config {
/* Bit field of UARTs present; bit 0 -- UART1 */
unsigned int enabled_uarts;
};
extern int davinci_serial_init(struct davinci_uart_config *);
+#endif
#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h
b/arch/arm/mach-davinci/include/mach/uncompress.h
index 33796b4..20c23a3 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -1,8 +1,17 @@
/*
* Serial port stubs for kernel decompress status messages
*
- * Author: Anant Gole
- * (C) Copyright (C) 2006, Texas
[PATCH 4/8] Davinci: gpio - minor cleanup
macroized repeated container_of()s to improve readability.
unified direction in/out functions.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Tested-by: Sandeep Paulraj s-paul...@ti.com
---
arch/arm/mach-davinci/gpio.c | 47 +
1 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 5476ad1..bb55f41 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -28,6 +28,9 @@ struct davinci_gpio {
int irq_base;
};
+#define chip2controller(chip) \
+ container_of(chip, struct davinci_gpio, chip)
+
static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
/* create a non-inlined version */
@@ -54,21 +57,36 @@ static int __init davinci_gpio_irq_setup(void);
* needed, and enable the GPIO clock.
*/
-static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
+static inline int __davinci_direction(struct gpio_chip *chip,
+ unsigned offset, bool out)
{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+ struct davinci_gpio *d = chip2controller(chip);
struct gpio_controller __iomem *g = d-regs;
u32 temp;
spin_lock(gpio_lock);
temp = __raw_readl(g-dir);
- temp |= (1 offset);
+ if (out)
+ temp = ~(1 offset);
+ else
+ temp |= (1 offset);
__raw_writel(temp, g-dir);
spin_unlock(gpio_lock);
return 0;
}
+static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+ return __davinci_direction(chip, offset, false);
+}
+
+static int
+davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
+{
+ return __davinci_direction(chip, offset, true);
+}
+
/*
* Read the pin's value (works even if it's set up as output);
* returns zero/nonzero.
@@ -78,36 +96,19 @@ static int davinci_direction_in(struct gpio_chip *chip,
unsigned offset)
*/
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+ struct davinci_gpio *d = chip2controller(chip);
struct gpio_controller __iomem *g = d-regs;
return (1 offset) __raw_readl(g-in_data);
}
-static int
-davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
-{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
- struct gpio_controller __iomem *g = d-regs;
- u32 temp;
- u32 mask = 1 offset;
-
- spin_lock(gpio_lock);
- temp = __raw_readl(g-dir);
- temp = ~mask;
- __raw_writel(mask, value ? g-set_data : g-clr_data);
- __raw_writel(temp, g-dir);
- spin_unlock(gpio_lock);
- return 0;
-}
-
/*
* Assuming the pin is muxed as a gpio output, set its output value.
*/
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+ struct davinci_gpio *d = chip2controller(chip);
struct gpio_controller __iomem *g = d-regs;
__raw_writel((1 offset), value ? g-set_data : g-clr_data);
@@ -262,7 +263,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
+ struct davinci_gpio *d = chip2controller(chip);
if (d-irq_base = 0)
return d-irq_base + offset;
--
1.6.3.3
___
Davinci-linux-open-source mailing list
Davinci-linux-open-source@linux.davincidsp.com
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
[PATCH 1/8] Davinci: iotable based ioremap() interception
This patch allows for a more flexible ioremap() interception. The mechanism
works by translating physical addresses based on soc-specific iotable
contents (davinci_soc_info.io_desc), once davinci_soc_info is populated by
davinci_common_init().
Signed-off-by: Cyril Chemparathy cy...@ti.com
Tested-by: Sandeep Paulraj s-paul...@ti.com
---
arch/arm/mach-davinci/da830.c |7 +-
arch/arm/mach-davinci/da850.c |9 ++-
arch/arm/mach-davinci/include/mach/io.h |4 +++
arch/arm/mach-davinci/io.c | 33 +++---
4 files changed, 46 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 122e61a..168f277 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1206,9 +1206,14 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
.emac_pdata = da8xx_emac_pdata,
};
+#define da830_early_ioremap(p, s) \
+ __davinci_ioremap(p, s, \
+ davinci_soc_info_da830.io_desc, \
+ davinci_soc_info_da830.io_desc_num)
+
void __init da830_init(void)
{
- da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+ da8xx_syscfg0_base = da830_early_ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
if (WARN(!da8xx_syscfg0_base, Unable to map syscfg0 module))
return;
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index d0fd756..27eb32e 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1093,15 +1093,20 @@ static struct davinci_soc_info davinci_soc_info_da850 =
{
.sram_len = SZ_8K,
};
+#define da850_early_ioremap(p, s) \
+ __davinci_ioremap(p, s, \
+ davinci_soc_info_da850.io_desc, \
+ davinci_soc_info_da850.io_desc_num)
+
void __init da850_init(void)
{
unsigned int v;
- da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+ da8xx_syscfg0_base = da850_early_ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
if (WARN(!da8xx_syscfg0_base, Unable to map syscfg0 module))
return;
- da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
+ da8xx_syscfg1_base = da850_early_ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
if (WARN(!da8xx_syscfg1_base, Unable to map syscfg1 module))
return;
diff --git a/arch/arm/mach-davinci/include/mach/io.h
b/arch/arm/mach-davinci/include/mach/io.h
index 62b0a90..4aa301c 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -25,6 +25,10 @@
#define __arch_ioremap(p, s, t)davinci_ioremap(p, s, t)
#define __arch_iounmap(v) davinci_iounmap(v)
+struct map_desc;
+
+void __iomem *__davinci_ioremap(unsigned long p, size_t size,
+ struct map_desc *io_desc, int io_desc_num);
void __iomem *davinci_ioremap(unsigned long phys, size_t size,
unsigned int type);
void davinci_iounmap(volatile void __iomem *addr);
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index a1c0b6b..3a62f14 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -12,17 +12,42 @@
#include linux/io.h
#include asm/tlb.h
+#include asm/mach/map.h
-#define BETWEEN(p, st, sz) ((p) = (st) (p) ((st) + (sz)))
-#define XLATE(p, pst, vst) ((void __iomem *)((p) - (pst) + (vst)))
+#include mach/common.h
+
+/*
+ * Remap io addresses based on a soc-specific io-descriptor table. This is
+ * useful in early arch init code before davinci_common_init(). After
+ * davinci_common_init(), regular ioremap() calls should be used.
+ */
+void __iomem *__davinci_ioremap(unsigned long p, size_t size,
+ struct map_desc *io_desc, int io_desc_num)
+{
+ int i;
+
+ for (i = 0; i io_desc_num; i++, io_desc++) {
+ unsigned long iophys = __pfn_to_phys(io_desc-pfn);
+ unsigned long iosize = io_desc-length;
+
+ if (p = iophys (p + size) = (iophys + iosize))
+ return __io(io_desc-virtual + p - iophys);
+ }
+
+ return NULL;
+}
/*
* Intercept ioremap() requests for addresses in our fixed mapping regions.
*/
void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
{
- if (BETWEEN(p, IO_PHYS, IO_SIZE))
- return XLATE(p, IO_PHYS, IO_VIRT);
+ void __iomem *ret;
+
+ ret = __davinci_ioremap(p, size, davinci_soc_info.io_desc,
+ davinci_soc_info.io_desc_num);
+ if (ret)
+ return ret;
return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
}
--
1.6.3.3
___
[PATCH 5/8] Davinci: gpio - struct renames
Renamed gpio structures to something more sensible:
struct gpio_controller -- struct davinci_gpio_regs
struct davinci_gpio -- struct davinci_gpio_controller
This change also moves davinci_gpio_controller definition to gpio.h.
Eventually, the gpio registers structure will be moved to gpio.c and no longer
a common cross-soc definition.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Tested-by: Sandeep Paulraj s-paul...@ti.com
---
arch/arm/mach-davinci/gpio.c | 44
arch/arm/mach-davinci/include/mach/gpio.h | 14 ++--
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index bb55f41..58a6fd5 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -22,28 +22,22 @@
static DEFINE_SPINLOCK(gpio_lock);
-struct davinci_gpio {
- struct gpio_chipchip;
- struct gpio_controller __iomem *regs;
- int irq_base;
-};
-
#define chip2controller(chip) \
- container_of(chip, struct davinci_gpio, chip)
+ container_of(chip, struct davinci_gpio_controller, chip)
-static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
+static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
/* create a non-inlined version */
-static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
+static struct davinci_gpio_regs __iomem __init *gpio2controller(unsigned gpio)
{
return __gpio_to_controller(gpio);
}
-static inline struct gpio_controller __iomem *irq2controller(int irq)
+static inline struct davinci_gpio_regs __iomem *irq2controller(int irq)
{
- struct gpio_controller __iomem *g;
+ struct davinci_gpio_regs __iomem *g;
- g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
+ g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
return g;
}
@@ -60,8 +54,8 @@ static int __init davinci_gpio_irq_setup(void);
static inline int __davinci_direction(struct gpio_chip *chip,
unsigned offset, bool out)
{
- struct davinci_gpio *d = chip2controller(chip);
- struct gpio_controller __iomem *g = d-regs;
+ struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_regs __iomem *g = d-regs;
u32 temp;
spin_lock(gpio_lock);
@@ -96,8 +90,8 @@ davinci_direction_out(struct gpio_chip *chip, unsigned
offset, int value)
*/
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio *d = chip2controller(chip);
- struct gpio_controller __iomem *g = d-regs;
+ struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_regs __iomem *g = d-regs;
return (1 offset) __raw_readl(g-in_data);
}
@@ -108,8 +102,8 @@ static int davinci_gpio_get(struct gpio_chip *chip,
unsigned offset)
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
- struct davinci_gpio *d = chip2controller(chip);
- struct gpio_controller __iomem *g = d-regs;
+ struct davinci_gpio_controller *d = chip2controller(chip);
+ struct davinci_gpio_regs __iomem *g = d-regs;
__raw_writel((1 offset), value ? g-set_data : g-clr_data);
}
@@ -171,7 +165,7 @@ pure_initcall(davinci_gpio_setup);
static void gpio_irq_disable(unsigned irq)
{
- struct gpio_controller __iomem *g = irq2controller(irq);
+ struct davinci_gpio_regs __iomem *g = irq2controller(irq);
u32 mask = (u32) get_irq_data(irq);
__raw_writel(mask, g-clr_falling);
@@ -180,7 +174,7 @@ static void gpio_irq_disable(unsigned irq)
static void gpio_irq_enable(unsigned irq)
{
- struct gpio_controller __iomem *g = irq2controller(irq);
+ struct davinci_gpio_regs __iomem *g = irq2controller(irq);
u32 mask = (u32) get_irq_data(irq);
unsigned status = irq_desc[irq].status;
@@ -196,7 +190,7 @@ static void gpio_irq_enable(unsigned irq)
static int gpio_irq_type(unsigned irq, unsigned trigger)
{
- struct gpio_controller __iomem *g = irq2controller(irq);
+ struct davinci_gpio_regs __iomem *g = irq2controller(irq);
u32 mask = (u32) get_irq_data(irq);
if (trigger ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -225,7 +219,7 @@ static struct irq_chip gpio_irqchip = {
static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
- struct gpio_controller __iomem *g = irq2controller(irq);
+ struct davinci_gpio_regs __iomem *g = irq2controller(irq);
u32 mask = 0x;
/* we only care about one bank */
@@ -263,7 +257,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
- struct davinci_gpio *d = chip2controller(chip);
+ struct
[PATCH 8/8] Davinci: gpio - fine grained locking
This patch eliminates the global gpio_lock, and implements a per-controller
lock instead. This also switches to irqsave/irqrestore locks in case gpios
are manipulated in isr.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Tested-by: Sandeep Paulraj s-paul...@ti.com
---
arch/arm/mach-davinci/gpio.c |9 +
arch/arm/mach-davinci/include/mach/gpio.h |3 +++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 3a78897..1486c63 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -33,8 +33,6 @@ struct davinci_gpio_regs {
u32 intstat;
};
-static DEFINE_SPINLOCK(gpio_lock);
-
#define chip2controller(chip) \
container_of(chip, struct davinci_gpio_controller, chip)
@@ -84,16 +82,17 @@ static inline int __davinci_direction(struct gpio_chip
*chip,
{
struct davinci_gpio_controller *d = chip2controller(chip);
struct davinci_gpio_regs __iomem *g = d-regs;
+ unsigned long flags;
u32 temp;
- spin_lock(gpio_lock);
+ spin_lock_irqsave(d-lock, flags);
temp = __raw_readl(g-dir);
if (out)
temp = ~(1 offset);
else
temp |= (1 offset);
__raw_writel(temp, g-dir);
- spin_unlock(gpio_lock);
+ spin_unlock_irqrestore(d-lock, flags);
return 0;
}
@@ -173,6 +172,8 @@ static int __init davinci_gpio_setup(void)
if (chips[i].chip.ngpio 32)
chips[i].chip.ngpio = 32;
+ spin_lock_init(chips[i].lock);
+
regs = gpio2regs(base);
chips[i].regs = regs;
chips[i].set_data = regs-set_data;
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h
b/arch/arm/mach-davinci/include/mach/gpio.h
index 33962c3..2384cd1 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -14,6 +14,8 @@
#define__DAVINCI_GPIO_H
#include linux/io.h
+#include linux/spinlock.h
+
#include asm-generic/gpio.h
#include mach/irqs.h
@@ -51,6 +53,7 @@ enum davinci_gpio_type {
struct davinci_gpio_controller {
struct davinci_gpio_regs __iomem *regs;
+ spinlock_t lock;
struct gpio_chipchip;
int irq_base;
void __iomem*set_data;
--
1.6.3.3
___
Davinci-linux-open-source mailing list
Davinci-linux-open-source@linux.davincidsp.com
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
[PATCH 6/8] Davinci: gpio - register layout invariant inlines
This patch renders the inlined gpio accessors in gpio.h independent of the
underlying controller's register layout. This is done by including three new
fields in davinci_gpio_controller to hold the addresses of the set, clear, and
in data registers.
Other changes:
1. davinci_gpio_regs structure definition moved to gpio.c. This structure is
no longer common across all davinci socs (davinci_gpio_controller is).
2. controller base address calculation code (gpio2controller()) moved to
gpio.c as this was no longer necessary for the inline implementation.
3. modified inline range checks to use davinci_soc_info.gpio_num instead of
DAVINCI_N_GPIO.
Signed-off-by: Cyril Chemparathy cy...@ti.com
Tested-by: Sandeep Paulraj s-paul...@ti.com
---
arch/arm/mach-davinci/gpio.c| 46 +--
arch/arm/mach-davinci/include/mach/common.h |4 ++
arch/arm/mach-davinci/include/mach/gpio.h | 63 +-
3 files changed, 67 insertions(+), 46 deletions(-)
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 58a6fd5..082a098 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -20,6 +20,19 @@
#include asm/mach/irq.h
+struct davinci_gpio_regs {
+ u32 dir;
+ u32 out_data;
+ u32 set_data;
+ u32 clr_data;
+ u32 in_data;
+ u32 set_rising;
+ u32 clr_rising;
+ u32 set_falling;
+ u32 clr_falling;
+ u32 intstat;
+};
+
static DEFINE_SPINLOCK(gpio_lock);
#define chip2controller(chip) \
@@ -28,9 +41,24 @@ static DEFINE_SPINLOCK(gpio_lock);
static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
/* create a non-inlined version */
-static struct davinci_gpio_regs __iomem __init *gpio2controller(unsigned gpio)
+static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
{
- return __gpio_to_controller(gpio);
+ void __iomem *ptr;
+ void __iomem *base = davinci_soc_info.gpio_base;
+
+ if (gpio 32 * 1)
+ ptr = base + 0x10;
+ else if (gpio 32 * 2)
+ ptr = base + 0x38;
+ else if (gpio 32 * 3)
+ ptr = base + 0x60;
+ else if (gpio 32 * 4)
+ ptr = base + 0x88;
+ else if (gpio 32 * 5)
+ ptr = base + 0xb0;
+ else
+ ptr = NULL;
+ return ptr;
}
static inline struct davinci_gpio_regs __iomem *irq2controller(int irq)
@@ -113,6 +141,7 @@ static int __init davinci_gpio_setup(void)
int i, base;
unsigned ngpio;
struct davinci_soc_info *soc_info = davinci_soc_info;
+ struct davinci_gpio_regs *regs;
/*
* The gpio banks conceptually expose a segmented bitmap,
@@ -141,11 +170,18 @@ static int __init davinci_gpio_setup(void)
if (chips[i].chip.ngpio 32)
chips[i].chip.ngpio = 32;
- chips[i].regs = gpio2controller(base);
+ regs = gpio2regs(base);
+ chips[i].regs = regs;
+ chips[i].set_data = regs-set_data;
+ chips[i].clr_data = regs-clr_data;
+ chips[i].in_data = regs-in_data;
gpiochip_add(chips[i].chip);
}
+ soc_info-gpio_ctlrs = chips;
+ soc_info-gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
+
davinci_gpio_irq_setup();
return 0;
}
@@ -358,7 +394,7 @@ static int __init davinci_gpio_irq_setup(void)
gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
/* default trigger: both edges */
- g = gpio2controller(0);
+ g = gpio2regs(0);
__raw_writel(~0, g-set_falling);
__raw_writel(~0, g-set_rising);
@@ -383,7 +419,7 @@ static int __init davinci_gpio_irq_setup(void)
unsignedi;
/* disabled by default, enabled only as needed */
- g = gpio2controller(gpio);
+ g = gpio2regs(gpio);
__raw_writel(~0, g-clr_falling);
__raw_writel(~0, g-clr_rising);
diff --git a/arch/arm/mach-davinci/include/mach/common.h
b/arch/arm/mach-davinci/include/mach/common.h
index 50a955f..c85c795 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -34,6 +34,8 @@ struct davinci_timer_info {
unsigned intclocksource_id;
};
+struct davinci_gpio_controller;
+
/* SoC specific init support */
struct davinci_soc_info {
struct map_desc *io_desc;
@@ -58,6 +60,8 @@ struct davinci_soc_info {
unsignedgpio_num;
unsignedgpio_irq;
unsignedgpio_unbanked;
+ struct davinci_gpio_controller *gpio_ctlrs;
+ int gpio_ctlrs_num;
struct
Removing excessive printing of NAND bad eraseblocks in nand/nand_bbt.c
Howdy, I don't know if this is the proper place for this, so please direct me elsewhere if it is not. I get a LOT of NAND bad eraseblocks when booting my dm6467t DVEVM. I've never dealt with NAND ROM before so I was surprised by how many bad eraseblocks are generated. I've seen elsewhere that this is to be expected. So I'm curious - does it need to be so excessively printed if it is relatively normal? I've made a patch to drivers/mtd/nand/nand_bbt.c to remove printing of each individual block. Instead, a warning message is generated that displays the number of blocks and the location of the first bad eraseblock. Do you think this is something worth doing permanently? Doug ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
