Re: Touchscreen - MFD driver for TPS6507x family

2010-08-02 Thread Nicolas Luna
Hi Sekhar,

Yes there is an other device on the bus, but I removed it and I decreased
the clock to 20khz. I cannot go below because the i2c seems not to work. It
does solved the problem.

I modified the driver to add a while(1) when it got an abnormal termination.
I notified that every time the driver makes this error, I can see a clock
stretch (with a scope) on the last i2c frame.

- The PMIC (tps65070) is rated to work at 400khz, but even at 20khz it seems
to need more time to response when it is addressed to much. I modified the
touchscreen polling period to 100 msec and I still got errors. Maybe if the
touchscreen driver was working by interruption that would leave a chance to
the PMIC.

- Why the i2c driver do not handles clock stretching?

- On a test there was 2 successive reads to register 02h with a delay of 85
msec between. The first went right but while the next read, the salve put
the clock low to stretch it. It sounds like a problem to me because the chip
was not receiving a lot of messages and it stretched the clock. I cannot
find any place in the datasheet that is talking about that issue.

Thank you.

Regards,

Nicolas



On Mon, Aug 2, 2010 at 12:35 PM, Nori, Sekhar  wrote:

>
> Hi Nicolas,
>
> On Fri, Jul 30, 2010 at 23:05:21, Nicolas Luna wrote:
> > Sekhar,
> >
> > We do not have this buffer on our custom hardware and we have the NACK
> > problem. SDA and SCL are directly connected from PMIC to OMAP with
> > pull-up.
> >
> > Is Todd right with the silicon issue? Or a I2C driver issue when it is
> > used too much... ?
>
> There is no silicon issue that I know of. The silicon meets I2C
> specification.
> All the advisories with silicon are documented here:
> http://focus.ti.com/lit/er/sprz301c/sprz301c.pdf
>
> >   i2c_davinci i2c_davinci.1: controller timed out
> >   i2c_davinci i2c_davinci.1: initiating i2c bus recovery
>
> I remember users on the list reporting these errors when a slave device is
> pulling the clock low for a long time. The first thing to try is a lower
> bus frequency - this is done on DM644x EVM to talk to a slow MSP430 based
> slave.
>
> Also, as I remember, this can even be caused by a slave you are not talking
> to.
> Are there other devices on the I2C bus?
>
> Thanks,
> Sekhar
>
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Re: [PATCH 1/2] DA850: move NAND/NOR pin lists to the board file

2010-08-02 Thread Sergei Shtylyov

Hello.

Nori, Sekhar wrote:


On Sun, Aug 01, 2010 at 22:45:16, Sergei Shtylyov wrote:

The NAND/NOR flash pin lists (da850_nand_pins/da850_nor_pins) are purely board
specific



Have you come across any board which uses different set of pins?


   I think you have been replied already.


On NAND the ALE/CLE pins could (theoretically) be different on different boards
but as long as you are booting from NAND, you are stuck with the same address 
lines
as that used by ROM code.


   And?


On NOR, a board with 8-bit NOR could probably do with less number of pins so 
may be
that could be included in the common list and the board file could optionally 
list
pins 8-15?


   The "common" lists (in da8[35]0.c) were meant to be per-module lists, not 
per module function lists, so there could be no NAND/NOR lists there. Those 
lists are not always useful, I agree -- but that was the design.



Thanks,
Sekhar


WBR, Sergei

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Re: [PATCH 2/2] DA850: move MII/RMII pin lists to the board file

2010-08-02 Thread Sergei Shtylyov

Hello.

Nori, Sekhar wrote:


The CPGMAC pin list in da850.c was incorrectly split into two MII/RMII mode
specific pin lists, while what pin group is used is a function of how the board
is wired.  Copy the pin lists to board-da850-evm.c, renaming them accordingly,
and merge the two lists in da850.c into one, da850_cpgmac_pins[], representing
the CPGMAC module as a whole...


da850_cpgmac_pins[] is not going to be useful 


   I know. Nevertheless, in da850.c we should have the generic pin lists, per 
module. Not always useful, but that's the rule.



because the board can either be
in MII or RMII mode. The pins for the unused mode are likely be used for other
purposes.



How about creating a common list of pins and two other lists for MII and RMII
pins which could probably be placed in the board file.


   I thought that was what I did...


Thanks,
Sekhar


WBR, Sergei
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Re: [PATCH 1/2] DA850: move NAND/NOR pin lists to the board file

2010-08-02 Thread Michael Williamson
 On 8/2/2010 12:04 PM, Nori, Sekhar wrote:
> Hi Sergei,
>
> On Sun, Aug 01, 2010 at 22:45:16, Sergei Shtylyov wrote:
>> The NAND/NOR flash pin lists (da850_nand_pins/da850_nor_pins) are purely 
>> board
>> specific
> Have you come across any board which uses different set of pins?
>
> On NAND the ALE/CLE pins could (theoretically) be different on different 
> boards
> but as long as you are booting from NAND, you are stuck with the same address 
> lines
> as that used by ROM code.
>
> On NOR, a board with 8-bit NOR could probably do with less number of pins so 
> may be
> that could be included in the common list and the board file could optionally 
> list
> pins 8-15?

There are boards using da850 architecture that use 16-bit NAND instead of 8-bit.
So at least having separate lists (or an extension) to support the upper data
lines for the NAND pins might be nice if the lists are maintained in a common 
location...

-Mike
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RE: Touchscreen - MFD driver for TPS6507x family

2010-08-02 Thread Nori, Sekhar

Hi Nicolas,

On Fri, Jul 30, 2010 at 23:05:21, Nicolas Luna wrote:
> Sekhar,
>
> We do not have this buffer on our custom hardware and we have the NACK
> problem. SDA and SCL are directly connected from PMIC to OMAP with
> pull-up.
>
> Is Todd right with the silicon issue? Or a I2C driver issue when it is
> used too much... ?

There is no silicon issue that I know of. The silicon meets I2C specification.
All the advisories with silicon are documented here: 
http://focus.ti.com/lit/er/sprz301c/sprz301c.pdf

>   i2c_davinci i2c_davinci.1: controller timed out
>   i2c_davinci i2c_davinci.1: initiating i2c bus recovery

I remember users on the list reporting these errors when a slave device is
pulling the clock low for a long time. The first thing to try is a lower
bus frequency - this is done on DM644x EVM to talk to a slow MSP430 based
slave.

Also, as I remember, this can even be caused by a slave you are not talking to.
Are there other devices on the I2C bus?

Thanks,
Sekhar
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RE: [PATCH 2/2] DA850: move MII/RMII pin lists to the board file

2010-08-02 Thread Nori, Sekhar
On Sun, Aug 01, 2010 at 22:47:00, Sergei Shtylyov wrote:
> The CPGMAC pin list in da850.c was incorrectly split into two MII/RMII mode
> specific pin lists, while what pin group is used is a function of how the 
> board
> is wired.  Copy the pin lists to board-da850-evm.c, renaming them accordingly,
> and merge the two lists in da850.c into one, da850_cpgmac_pins[], representing
> the CPGMAC module as a whole...

da850_cpgmac_pins[] is not going to be useful because the board can either be
in MII or RMII mode. The pins for the unused mode are likely be used for other
purposes.

How about creating a common list of pins and two other lists for MII and RMII
pins which could probably be placed in the board file.

Thanks,
Sekhar

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RE: [PATCH 1/2] DA850: move NAND/NOR pin lists to the board file

2010-08-02 Thread Nori, Sekhar

Hi Sergei,

On Sun, Aug 01, 2010 at 22:45:16, Sergei Shtylyov wrote:
> The NAND/NOR flash pin lists (da850_nand_pins/da850_nor_pins) are purely board
> specific

Have you come across any board which uses different set of pins?

On NAND the ALE/CLE pins could (theoretically) be different on different boards
but as long as you are booting from NAND, you are stuck with the same address 
lines
as that used by ROM code.

On NOR, a board with 8-bit NOR could probably do with less number of pins so 
may be
that could be included in the common list and the board file could optionally 
list
pins 8-15?

Thanks,
Sekhar


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RE: [PATCH v5 1/1] davinci: spi: replace existing driver

2010-08-02 Thread Nori, Sekhar

Hi Brian,

On Mon, Aug 02, 2010 at 19:40:29, Brian Niebuhr wrote:
> Grant -
>

>  For my part, I've already sunk way more time into this than I ever
> intended, and I really have no clue how to break this patch down into
> smaller patches.  I don't really care much if the patch gets accepted
> or not - I am just trying to help out all of the other users that are
> stuck with a broken driver like I was.  Maybe if TI wants to give
> their customers a driver that actually works they'll pick it up and do
> the rest of the work that's necessary to get it accepted.

Thanks for all the work on this so far. We will work on breaking
this patch up and getting the fixes accepted upstream.

Regards,
Sekhar
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[PATCH v2] DaVinci: dm365: Added clockout2 management.

2010-08-02 Thread Raffaele Recalcati
From: Davide Bonfanti 

Clockout2 is added as a child of pll1_sysclk9, because they have
the same pll divisor.
Added dm365_clkout2_set_rate to properly set clockout2 frequency.
Modified the davinci_set_sysclk_rate function in order
to get the right ancestor.

This patch has been developed against the
http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
git tree and tested on bmx board.

Signed-off-by: Davide Bonfanti 
Signed-off-by: Raffaele Recalcati 
---
 arch/arm/mach-davinci/clock.c  |   32 
 arch/arm/mach-davinci/clock.h  |5 ++
 arch/arm/mach-davinci/dm365.c  |   57 
 arch/arm/mach-davinci/include/mach/dm365.h |1 +
 4 files changed, 87 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index f29a526..6e45808 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -254,7 +254,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
u32 v, plldiv;
struct pll_data *pll;
unsigned long rate = clk->rate;
+   struct clk *parent = clk;
 
+   if (clk == NULL || IS_ERR(clk))
+   return -EINVAL;
+   while (parent->parent->parent)
+   parent = parent->parent;
+
+   if (parent == clk)
+   return -EPERM;
/* If this is the PLL base clock, no more calculations needed */
if (clk->pll_data)
return rate;
@@ -262,13 +270,13 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
if (WARN_ON(!clk->parent))
return rate;
 
-   rate = clk->parent->rate;
+   rate = parent->rate;
+
 
/* Otherwise, the parent must be a PLL */
-   if (WARN_ON(!clk->parent->pll_data))
+   if (WARN_ON(!parent->pll_data))
return rate;
-
-   pll = clk->parent->pll_data;
+   pll = parent->pll_data;
 
/* If pre-PLL, source clock is before the multiplier and divider(s) */
if (clk->flags & PRE_PLL)
@@ -293,26 +301,33 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned 
long rate)
struct pll_data *pll;
unsigned long input;
unsigned ratio = 0;
+   struct clk *parent = clk;
+
+   /* searching the right ancestor (pll1_clk or pll2_clk) */
+   while (parent->parent->parent)
+   parent = parent->parent;
+   if (parent == clk)
+   return -EPERM;
 
/* If this is the PLL base clock, wrong function to call */
if (clk->pll_data)
return 0;
 
/* There must be a parent... */
-   if (WARN_ON(!clk->parent))
+   if (WARN_ON(!parent))
return 0;
 
/* ... the parent must be a PLL... */
-   if (WARN_ON(!clk->parent->pll_data))
+   if (WARN_ON(!parent->pll_data))
return 0;
 
/* ... and this clock must have a divider. */
if (WARN_ON(!clk->div_reg))
return 0;
 
-   pll = clk->parent->pll_data;
+   pll = parent->pll_data;
 
-   input = clk->parent->rate;
+   input = parent->rate;
 
/* If pre-PLL, source clock is before the multiplier and divider(s) */
if (clk->flags & PRE_PLL)
@@ -343,6 +358,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long 
rate)
 
return 0;
 }
+EXPORT_SYMBOL(davinci_set_sysclk_rate);
 
 static unsigned long clk_leafclk_recalc(struct clk *clk)
 {
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a717d98..df36d73 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -50,6 +50,11 @@
 #define PLLDIV_EN   BIT(15)
 #define PLLDIV_RATIO_MASK 0x1f
 
+#define PERI_CLKCTL0x48
+#define CLOCKOUT2EN2
+#define CLOCKOUT1EN1
+#define CLOCKOUT0EN0
+
 /*
  * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
  * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 42fd4a4..902e9a0 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -40,6 +40,11 @@
 #include "mux.h"
 
 #define DM365_REF_FREQ 2400/* 24 MHz on the DM365 EVM */
+#define PINMUX00x00
+#define PINMUX10x04
+#define PINMUX20x08
+#define PINMUX30x0c
+#define PINMUX40x10
 
 static struct pll_data pll1_data = {
.num= 1,
@@ -124,6 +129,7 @@ static struct clk pll1_sysclk6 = {
.parent = &pll1_clk,
.flags  = CLK_PLL,
.div_reg= PLLDIV6,
+   .set_rate   = davinci_set_sysclk_rate,
 };
 
 static struct clk pll1_sysclk7 = {
@@ -145,6 +151,14 @@ static struct clk pll1_sysclk9 = {
.parent = &pll1_clk,
.flags  = CLK_PLL,
.div_reg   

Multiple NAND chips on OMAPL137

2010-08-02 Thread 詹成江
Hi,

 We want to use tow NADN chips on Omapl137 device,They are selected by CS3 
and CS4 on EMFIA,Now I can use one Nandflash chip on CS3 with MTD. The chip can 
be found by uboot or Linux kernel,when linux kernel starting ,the nandflash was 
created to 5  MTD partitions on "nand_davinci.0" as below:
 0x-0x0002 : "bootloader"
 0x0002-0x0004 : "params"
 0x0020-0x0040 : "kernel"
 0x0040-0x0080 : "RamDisk"
 0x0080-0x0400 : "yaffs2"
It's ok.   Now I want to use another chip for file system,2Gbits.But I don't 
know how to use it,Is there any project to use linux MTD like this,or omapl37 
can't support two chips at the same time?  Any thoughts/pitfalls would be 
appreciated.

thanks.
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FB problem in arago linux 2.6.3.2-rc2-davinci1

2010-08-02 Thread amr ali

Hi,
I am trying to use the kernel stated above from the arago tree.
The fb does not work.
I have notice during rebooting only I see some figures.
During normal operation, nothing appears on the screen.
Is this related to the fb device driver? Is there a patch for that?
--
Amr Ali Abdel-Naby
Embedded Systems Developer
www.embedded-tips.blogspot.com


  
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Re: Symbol names

2010-08-02 Thread Steve Chen
On Mon, Aug 2, 2010 at 5:06 AM, Tobias Waldekranz (Knutsson) <
tobias.knuts...@gmail.com> wrote:

> nm  | grep  should
> narrow it down pretty much.
>
> On Mon, May 17, 2010 at 07:42, Vijay Soni  wrote:
>
>> Does anyone know how I can get symbols names from their addresses. I am
>> trying to debug an kernel oops which gives function address in the
>> Backtrace. I know I can turn on KALLSYMS but I cannot rebuild my kernel
>> because of other module dependency. Can we get this info from vmlinux? If so
>> how?
>>
>>
>
>
The other option is to use

addr2line -e <.../vmlinux> -f 

Regards,

Steve
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Re: Symbol names

2010-08-02 Thread Tobias Waldekranz (Knutsson)
nm  | grep  should
narrow it down pretty much.

On Mon, May 17, 2010 at 07:42, Vijay Soni  wrote:

> Does anyone know how I can get symbols names from their addresses. I am
> trying to debug an kernel oops which gives function address in the
> Backtrace. I know I can turn on KALLSYMS but I cannot rebuild my kernel
> because of other module dependency. Can we get this info from vmlinux? If so
> how?
>
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>


-- 

Hälsningar/Regards
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Re: Kernel Booting Problem

2010-08-02 Thread Tobias Waldekranz (Knutsson)
2010/6/23 amr ali :
> I tried my new kernel with my new file system, I build with buildroot.
> The kernel booted and passed by the free init message, the current log is:
> "Freeing init memory: 124K
>
> Warning: unable to open an initial console.

This message is usually given when init cannot open /dev/console. The
bare minimum to boot is /dev/console and /dev/null.
>
> warning: `proftpd' uses 32-bit capabilities (legacy support in use)"
> and nothing happens after.
>
> Any help?
> --
> Amr Ali Abdel-Naby
> Embedded Systems Developer
> www.embedded-tips.blogspot.com
>
>
>
>
>> From: caglarak...@gmail.com
>> To: amra...@hotmail.com
>> Subject: Re: Kernel Booting Problem
>> Date: Wed, 23 Jun 2010 13:42:18 +0300
>> CC: davinci-linux-open-source@linux.davincidsp.com
>>
>> On Wednesday 23 June 2010 01:31:05 pm amr ali wrote:
>> > I have a new file system, I generated it by buildroot.
>> > What should be in that filesystem. I do not have device nodes, how do I
>> > create them automatically? --
>>
>> I guess you extracti! ng a tar image for NFS use, if so then you should
>> extract
>> file system image with root permissions otherwise device nodes won't be
>> populated.
>>
>> If you still have problems, then please give Narcissus a go.
>>
>> Regards,
>> Caglar
>>
>> > Amr Ali Abdel-Naby
>> > Embedded Systems Developer
>> > www.embedded-tips.blogspot.com
>> >
>> > > From: caglarak...@gmail.com
>> > > To: davinci-linux-open-source@linux.davincidsp.com
>> > > Subject: Re: Kernel Booting Problem
>> > > Date: Wed, 23 Jun 2010 13:23:17 +0300
>> > > CC: amra...@hotmail.com
>> > >
>> > > On Wednesday 23 June 2010 01:03:25 pm amr ali wrote:
>> > > > I downloaded the standard Linux kernel 2.6.33.2 and compiled it with
>> > > > the default TI Davinci kernel configuration. I am booting the kernel
>> > > > with NFS! as Root FS. Kernel boots till I get the message Freeing
>> > > > INIT
>> > > > memory and nothing happens. When I try to boot withh montavista
>> > > > .6.10
>> > > > kernel with the same file systems it continue booting with no
>> > > > problems.
>> > > > The booting log can for the non-working kernel can be found here @
>> > >
>> > > I'm not suprised that it is not working. This is an EABI/OABI issue,
>> > > besides many other things changed for C library as well.
>> > >
>> > > In short, you need a new file system. May I suggest narcissus [1]?
>> > >
>> > > Regards,
>> > > Caglar
>> > >
>> > > [1] http://www.angstrom-distribution.org/narcissus/
>> > >
>> > > > http://pastebin.org/354048 Any ideas, why the kernel is not running
>> > > > my
>> > > > init application?
>> > > >
>> > > > --
>> > > > Amr Ali Abdel-Naby
>> > > > Embedded ! Systems Developer
>> > > > www.embedded-tips.blogspot.com
>> > > >
>> > > >
>> > > >
>> > > > _
>> > > > Your E-mail and More On-the-Go. Get Windows Live Hotmail Free.
>> > > > https://signup.live.com/signup.aspx?id=60969
>> >
>> > _
>> > Hotmail: Trusted email with Microsoft’s powerful SPAM protection.
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>> >
>
> 
> Hotmail: Trusted email with Microsoft’s powerful SPAM protection. Sign up
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>



-- 

Hälsningar/Regards
Tobias Waldekranz
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