Android2.2 on DM355
Hi, has anyone ported Android2.2 on DM355? Can anyone give me directions. azam. -- Happiness keeps you Sweet, Trials keep you Strong, Sorrows keep you Human, Failures keep you humble , Success keeps You Glowing, but Only God keeps You Going! ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
PLL1 bypass on DM355
Hi Steve, I was able to put PLL0 in bypass mode on DM355. But I am unable to put PLL1 in bypass mode since PLL1 supplies clock to DDR memory. Can you please tell me how do I make DDR memory to use the internal clock instead of PLL1 clock? Is it possible to put PLL1 in bypass mode? Thanks, azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: Suppression of power consumption in Deep Sleep Mode on the DM355
Dear INAGAKI and SUZUKI, I used your patch for putting DM355 in deep sleep. While going to deep sleep the code works fine. But when I try to wake up DM355 it fails sometime, wake-up fails randomly. Please can you suggest me what can be the problem. I am using kernel version 2.6.10 and I added the patch as it is. Thanks, azam. INAGAKI Takahiko Tue, 28 Oct 2008 22:26:48 -0700 Dear all, I and Suzuki made a patch to bring the DM355 into Deep Sleep Mode. It is for TI LSP 1.20 (Linux 2.6.10), and based on: http://www.mail-archive.com/davinci-linux-open-source@linux.davincidsp.com/msg04407.html Running command below, DM355 will go to Deep Sleep Mode: # echo mem /sys/power/state In the process, DM355 sends a register write command to MSP430, offset = 0x19 and data = 0. You should implement a register 0x19 write function for MSP430 to assert its DS_ENABLE pin low. Asserted DS_ENABLE pin high, DM355 will exit Deep Sleep Mode. A proglem is that this code stops the ARM subsystem, but its consumption current does not seem to change. Any idea to reduce the current is welcome. INAGAKI Takahiko ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
DM355 PLL register write problem
Hi Steve, When I try to write PLLEN bit in PLLCTL register of PLL1 it crashes. But When I read it works fine. Can you please suggest me how do I write the pll registers? Below is how I try to write PLL register. pllcnt = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLCTL); davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, pllcnt ~BIT(0)); udelay(50); davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, (pllcnt ~BIT(0)) | PLLRST); Then kernel fails to write: davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, pllcnt ~BIT(0)); Thanks, Azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: DM355 PLL register write problem
Hi Steve, Thank you. I found the problem. Problem was with the order of the parameter that I was passing to davinci_writel() function. It takes davinci_writel(value, address) and I was passing it davinci_writel(address, value). After I changed the order of the parameter everything worked fine. Thanks a lot for the help. Thanks, azam. On Thu, Jul 23, 2009 at 5:36 PM, Steve Chen sc...@mvista.com wrote: On Thu, 2009-07-23 at 15:41 +0530, Azam Ansari wrote: Hi Steve, When I try to write PLLEN bit in PLLCTL register of PLL1 it crashes. But When I read it works fine. Can you please suggest me how do I write the pll registers? Below is how I try to write PLL register. pllcnt = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLCTL); davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, pllcnt ~BIT(0)); udelay(50); davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, (pllcnt ~BIT(0)) | PLLRST); Then kernel fails to write: davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, pllcnt ~BIT(0)); Try ... #include linux/io.h ... /* optionally you can use __raw_readl(IO_ADDRESS(DAVINCI_PLL_CNTRL0_BASE + PLLCTL)); pllcnt = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLCTL); __raw_writel(pllcnt ~BIT(0), IO_ADDRESS(DAVINCI_PLL_CNTRL0_BASE + PLLCTL)); ... Regards, Steve ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
PLL Bypass Problem
Hi All,
I have written following function to do pll bypass.
void davinci_clk_at24MHz(void)
{
struct clk *clkp;
static struct clk *board_clks;
int count = 0, num_clks;
unsigned long pllcnt;
if (cpu_is_davinci_dm355()) {
pllcnt = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLCTL);
davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, pllcnt ~BIT(0));
udelay(4);
davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, (pllcnt ~BIT(0))
| PLLRST);
fixedrate = 2400;
armrate = fixedrate;
commonrate = armrate / 2;
board_clks = davinci_dm355_clks;
num_clks = ARRAY_SIZE(davinci_dm355_clks);
} else if (cpu_is_davinci_dm6467()) {
fixedrate = 2400;
div_by_four = ((PLL1_PLLM + 1) * 2700) / 4;
div_by_six = ((PLL1_PLLM + 1) * 2700) / 6;
div_by_eight = ((PLL1_PLLM + 1) * 2700) / 8;
armrate = ((PLL1_PLLM + 1) * 2700) / 2;
board_clks = davinci_dm6467_clks;
num_clks = ARRAY_SIZE(davinci_dm6467_clks);
} else {
fixedrate = 2700;
armrate = (PLL1_PLLM + 1) * (fixedrate / 2);
commonrate = armrate / 3;
board_clks = davinci_dm644x_clks;
num_clks = ARRAY_SIZE(davinci_dm644x_clks);
}
for (clkp = board_clks; count num_clks; count++, clkp++) {
clk_register(clkp);
/* Turn on clocks that have been enabled in the
* table above */
if (clkp-usecount) {
clk_enable(clkp);
}
}
}
I call this function through power management modules main.c file
enter_state() function.
I do following to enable PLL bypass mode.
# echo pllbypass /sys/power/state
But I get following kernel dump after that:
Storing State to pllbypass
Unable to handle kernel paging request at virtual address df400040
pgd = c6c74000
[df400040] *pgd=
Internal error: Oops: 805 [#1]
Modules linked in: dm350mmap cmemk
CPU: 0
PC is at davinci_clk_at24MHz+0x38/0x23c
LR is at enter_state+0x68/0x1cc
pc : [c0044c8c]lr : [c006fea0]Not tainted
sp : c08cbea0 ip : c08cbec8 fp : c08cbec4
r10: 000a r9 : c08cbf78 r8 :
r7 : 0009 r6 : df40 r5 : 01c40900 r4 : 0040
r3 : e104 r2 : 0350 r1 : r0 : 0005
Flags: nZCv IRQs on FIQs on Mode SVC_32 Segment user
Control: 5317F Table: 86C74000 DAC: 0015
Process sh (pid: 972, stack limit = 0xc08ca1a0)
Stack: (0xc08cbea0 to 0xc08cc000)
bea0: 000f 0005 0005 0009 c02f2854 c08cbeec
c08cbec8
bec0: c006fea0 c0044c64 c0052c04 c71b6000 c02f2844 0005 0009
c02f2830
bee0: c08cbf14 c08cbef0 c0070140 c006fe48 000a 40018000 c6c3cb20
bf00: c6c3cb38 c6c38680 c08cbf24 c08cbf18 c00c92fc c00700c4 c08cbf54
c08cbf28
bf20: c00c95ec c00c92e0 000a c6c38680 40018000 c08cbf78
c00362f4
bf40: c08ca000 0094 c08cbf74 c08cbf58 c0092ec0 c00c94ec
bf60: c6c38680 0004 c08cbfa4 c08cbf78 c0092fb4 c0092e10
bf80: c0092444 00017a80 000a 4020c798 40018000
c08cbfa8
bfa0: c0035b60 c0092f7c 000a 4020c798 0001 40018000 000a
bfc0: 000a 4020c798 40018000 000a 400178c0 0a5c 4020c000
000bd744
bfe0: befff724 401a5a4c 401a5a68 6010 0001 0400
Backtrace:
[c0044c54] (davinci_clk_at24MHz+0x0/0x23c) from [c006fea0]
(enter_state+0x68/0x1cc)
r8 = C02F2854 r7 = 0009 r6 = 0005 r5 = 0005
r4 =
[c006fe38] (enter_state+0x0/0x1cc) from [c0070140]
(state_store+0x8c/0xa0)
r8 = C02F2830 r7 = 0009 r6 = 0005 r5 = C02F2844
r4 = C71B6000
[c00700b4] (state_store+0x0/0xa0) from [c00c92fc]
(subsys_attr_store+0x2c/0x38)
[c00c92d0] (subsys_attr_store+0x0/0x38) from [c00c95ec]
(sysfs_write_file+0x110/0x15c)
[c00c94dc] (sysfs_write_file+0x0/0x15c) from [c0092ec0]
(vfs_write+0xc0/0xf8)
[c0092e00] (vfs_write+0x0/0xf8) from [c0092fb4] (sys_write+0x48/0x74)
r7 = 0004 r6 = C6C38680 r5 = r4 =
[c0092f6c] (sys_write+0x0/0x74) from [c0035b60]
(ret_fast_syscall+0x0/0x2c)
r6 = 40018000 r5 = 4020C798 r4 = 000A
Code: e5934900 e59f61c0 e59f51c0 e3c44001 (e7845006)
MontaVista(R) Linux(R) Professional Edition 4.0.1 (0502020)
192.168.0.104 login:
I found that when I use davinci_readl() function it works fine. But when I
use davinci_writel() function to write the same read register it gives the
kernel dumt.
davinci_writel(DAVINCI_PLL_CNTRL0_BASE + PLLCTL, pllcnt ~BIT(0));
(Hangs at this line)
Please can anyone help?
thanks,
azam.
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Re: Suppression of power consumption in Deep Sleep Mode on the DM355
Dear All, I integrated the PM patch send by you with kernel version 2.6.10. But when I do $ echo mem /sys/power/state the kernel hangs. Below is the kernel dump. r...@192.168.0.104:/sys/power# echo mem state Stopping tasks: ==| Unable to handle kernel NULL pointer dereference at virtual address 006b pgd = c5334000 [006b] *pgd=86b8a031, *pte=, *ppte= Internal error: Oops: 801 [#1] Modules linked in: CPU: 0 PC is at add_wait_queue+0x44/0x74 LR is at 0x4013 pc : [c0069898]lr : [4013]Not tainted sp : c6babdd8 ip : 0067 fp : c6babde4 r10: c6babe00 r9 : r8 : c06679a0 r7 : r6 : c0667900 r5 : c6baa000 r4 : c6babdf8 r3 : c6babe0c r2 : c6baa000 r1 : c6babe00 r0 : c06679a0 Flags: nZcv IRQs off FIQs on Mode SVC_32 Segment user Control: 5317F Table: 85334000 DAC: 0015 Process bash (pid: 1076, stack limit = 0xc6baa1a0) Stack: (0xc6babdd8 to 0xc6bac000) bdc0: c6babe44 c6babde8 bde0: c01e6124 c0069864 c7399820 c004da6c 000c be00: c7399820 c004da6c 0067 c0300508 c0667900 be20: 0003 c02f0590 c02ff474 0003 c02ff494 c6babe5c c6babe48 be40: c01e7270 c01e60c4 00baa000 c02f0590 c6babe6c c6babe60 c01ea804 c01e7264 be60: c6babe84 c6babe70 c0173ff0 c01ea7e0 c02ff464 c02f0620 c6babe94 c6babe88 be80: c01751f4 c0173fc8 c6babec4 c6babe98 c01752c0 c01751c8 0025 bea0: 0003 0003 c035f284 c02f284c c6babf78 c6db96c0 c6babeec c6babec8 bec0: c006fa70 c0175210 c0075f10 c6ca8000 c02f283c 0003 0003 0004 bee0: c6babf14 c6babef0 c006fc78 c006f9c0 c6babf78 0004 000af408 c717d860 bf00: c717d878 c6babf24 c6babf18 c00c8e2c c006fc08 c6babf54 c6babf28 bf20: c00c911c c00c8e10 0002 0004 c6db96c0 000af408 c6babf78 c00362f4 bf40: c6baa000 0094 c6babf74 c6babf58 c00929f0 c00c901c bf60: c6db96c0 0004 c6babfa4 c6babf78 c0092ae4 c0092940 bf80: c0091f74 000576ec 0004 4017c798 000af408 c6babfa8 bfa0: c0035b60 c0092aac 0004 4017c798 0001 000af408 0004 bfc0: 0004 4017c798 000af408 0004 400178e0 0001 bfe0: befff9ac 40115a4c 40115a68 6010 0001 efff Backtrace: [c0069854] (add_wait_queue+0x0/0x74) from [c01e6124] (__mmc_claim_host+0x70/0x148) [c01e60b4] (__mmc_claim_host+0x0/0x148) from [c01e7270] (mmc_suspend_host+0x1c/0x3c) [c01e7254] (mmc_suspend_host+0x0/0x3c) from [c01ea804] (davinci_mmcsd_suspend+0x34/0x40) r4 = C02F0590 [c01ea7d0] (davinci_mmcsd_suspend+0x0/0x40) from [c0173ff0] (platform_suspend+0x38/0x8c) [c0173fb8] (platform_suspend+0x0/0x8c) from [c01751f4] (suspend_device+0x3c/0x48) r5 = C02F0620 r4 = C02FF464 [c01751b8] (suspend_device+0x0/0x48) from [c01752c0] (device_suspend+0xc0/0x200) [c0175200] (device_suspend+0x0/0x200) from [c006fa70] (enter_state+0xc0/0x198) [c006f9b0] (enter_state+0x0/0x198) from [c006fc78] (state_store+0x80/0x90) r8 = 0004 r7 = 0003 r6 = 0003 r5 = C02F283C r4 = C6CA8000 [c006fbf8] (state_store+0x0/0x90) from [c00c8e2c] (subsys_attr_store+0x2c/0x38) r8 = C717D878 r7 = r6 = C717D860 r5 = 000AF408 r4 = 0004 [c00c8e00] (subsys_attr_store+0x0/0x38) from [c00c911c] (sysfs_write_file+0x110/0x15c) [c00c900c] (sysfs_write_file+0x0/0x15c) from [c00929f0] (vfs_write+0xc0/0xf8) [c0092930] (vfs_write+0x0/0xf8) from [c0092ae4] (sys_write+0x48/0x74) r7 = 0004 r6 = C6DB96C0 r5 = r4 = [c0092a9c] (sys_write+0x0/0x74) from [c0035b60] (ret_fast_syscall+0x0/0x2c) r6 = 000AF408 r5 = 4017C798 r4 = 0004 Code: e5823004 e590c000 e281300c e581c00c (e58c3004) 6note: bash[1076] exited with preempt_count 1 BUG: scheduling while atomic: bash/0x4001/1076 caller is __cond_resched+0x60/0x80 BUG: scheduling while atomic: bash/0x4001/1076 caller is __cond_resched+0x60/0x80 BUG: scheduling while atomic: bash/0x4001/1076 caller is __cond_resched+0x60/0x80 BUG: scheduling while atomic: bash/0x4001/1076 caller is __cond_resched+0x60/0x80 BUG: scheduling while atomic: bash/0x4001/1076 caller is __cond_resched+0x60/0x80 BUG: scheduling while atomic: bash/0x0001/1076 caller is do_exit+0xd3c/0xda0 Please let me know where should I look for the problem. Thanks, azam. INAGAKI Takahiko Tue, 28 Oct 2008 22:26:48 -0700 Dear all, I and Suzuki made a patch to bring the DM355 into Deep Sleep Mode. It is for TI LSP 1.20 (Linux 2.6.10), and based on: http://www.mail-archive.com/davinci-linux-open-source@linux.davincidsp.com/msg04407.html Running command below, DM355 will go to Deep Sleep Mode: # echo mem /sys/power/state In the process, DM355 sends a register write command to MSP430, offset = 0x19 and data = 0. You should implement a register 0x19 write function for MSP430 to assert its DS_ENABLE pin low. Asserted DS_ENABLE pin high, DM355 will exit
DM355 MMC hang problem
Hi All, I am trying to put DM355 in Deep Sleep mode. When I call the deep sleep function it gives me kernel dump while putting MMC device in to deep sleep. I don't know much about the MMC module. Does anyone know what can be the reason. Thanks, azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: DM355 Power Management Problem
Hi Steve, Where can I get the latest kernel version from? I check TI website but I didn't find it. Thanks, Azam. On Fri, Jul 10, 2009 at 3:52 AM, Steve Chen sc...@mvista.com wrote: On Thu, 2009-07-09 at 21:00 +0530, Azam Ansari wrote: ... constant arch/arm/mach-davinci/io.c:53: error: (near initialization for `davinci_io_desc[2].physical') arch/arm/mach-davinci/io.c:56: error: initializer element is not constant arch/arm/mach-davinci/io.c:56: error: (near initialization for `davinci_io_desc[2]') arch/arm/mach-davinci/io.c: In function `davinci_map_common_io': arch/arm/mach-davinci/io.c: 111: warning: too few arguments for format Kind of difficult to tell without having the source code available. Just dawn on me after looking at the patch, you are using 2.6.10 kernel right? The problem is that the kernel is too old for the patch. The compiler issues are relatively easy to fix, but there is no guarantee that power management will work after getting pass the compiler issue. So bypass this error I commented following lines in arch/arm/mach-davinci/io.c file: .pfn= phys_to_pfn(DDR2_CTRL_PHYS), .pfn= phys_to_pfn(TCM_PHYS), In 2.6.10, you want to use .physical instead of .pfn. But then I get following error during linking. arch/arm/mach-davinci/built-in.o(.text+0x4fd4): In function `davinci_pm_idle': arch/arm/mach-davinci/sleep.S: undefined reference to `timer_dyn_reprogram' arch/arm/mach-davinci/built-in.o(.text +0x5004):arch/arm/mach-davinci/sleep.S: undefined reference to `timer_dyn_reprogram' arch/arm/mach-davinci/built-in.o(.init.text+0x14cc): In function `davinci_pm_init': arch/arm/mach-davinci/sleep.S: undefined reference to `suspend_set_ops' I didn't find suspend_set_ops() and timer_dyn_reprogram() functions suspend_set_ops is defined newer kernels in kernel/power/main.c. The 2.6.10 kernel predates power management patches. It seems that your option at this point are 1. Move to a newer kernel with power management support (2.6.21 or later I believe. Please correct me if I am mistaken). 2. Backport power management to your existing kernel As for timer_dyn_repgrogram(), you may want to reference 0faf34c154a511cb419ea2e142293f950fcfe619. Regards, Steve ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: DM355 Power Management Problem
Hi Steve,
I have attached the files with the mail.
Below is the link where I took the patch from.
http://www.mail-archive.com/davinci-linux-open-source@linux.davincidsp.com/msg04407.html
Thanks,
azam.
On Thu, Jul 9, 2009 at 4:46 PM, Steve Chen sc...@mvista.com wrote:
On Thu, 2009-07-09 at 10:22 +0530, Azam Ansari wrote:
Hi Steve,
I added the patch for Power Management in DM355. But during
compilation I get following error:
arch/arm/mach-davinci/io.c:47: error: unknown field `pfn' specified in
initializer
arch/arm/mach-davinci/io.c:47: warning: implicit declaration of
function `phys_to_pfn'
arch/arm/mach-davinci/io.c:47: error: initializer element is not
constant
arch/arm/mach-davinci/io.c:47: error: (near initialization for
`davinci_io_desc[1].physical')
arch/arm/mach-davinci/io.c:50: error: initializer element is not
constant
arch/arm/mach-davinci/io.c:50: error: (near initialization for
`davinci_io_desc[1]')
arch/arm/mach-davinci/io.c:53: error: unknown field `pfn' specified in
initializer
arch/arm/mach-davinci/io.c:53: error: initializer element is not
constant
arch/arm/mach-davinci/io.c:53: error: (near initialization for
`davinci_io_desc[2].physical')
arch/arm/mach-davinci/io.c:56: error: initializer element is not
constant
arch/arm/mach-davinci/io.c:56: error: (near initialization for
`davinci_io_desc[2]')
arch/arm/mach-davinci/io.c: In function `davinci_map_common_io':
arch/arm/mach-davinci/io.c:
111: warning: too few arguments for format
Kind of difficult to tell without having the source code available.
So bypass this error I commented following lines in
arch/arm/mach-davinci/io.c file:
.pfn= phys_to_pfn(DDR2_CTRL_PHYS),
.pfn= phys_to_pfn(TCM_PHYS),
But then I get following error during linking.
arch/arm/mach-davinci/built-in.o(.text+0x4fd4): In function
`davinci_pm_idle':
arch/arm/mach-davinci/sleep.S: undefined reference to
`timer_dyn_reprogram'
arch/arm/mach-davinci/built-in.o(.text
+0x5004):arch/arm/mach-davinci/sleep.S: undefined reference to
`timer_dyn_reprogram'
arch/arm/mach-davinci/built-in.o(.init.text+0x14cc): In function
`davinci_pm_init':
arch/arm/mach-davinci/sleep.S: undefined reference to
`suspend_set_ops'
I didn't find suspend_set_ops() and timer_dyn_reprogram() functions
defined in the kernel source tree.
Please let me know where will I find the following function
definition?
Also how do I correct the compilation error that I am getting in io.c
file?
I don't know. If you share the patch, I can look at it and perhaps come
up with a few suggestions.
Regards,
Steve
/*
* linux/arch/arm/mach-davinci/pm.c
*
* DaVinci Power Management Routines
*
* Copyright 2008 Dirk Behme [EMAIL PROTECTED]
*
* Based on arch/arm/mach-omap2/pm.c from:
*
* Copyright (C) 2005 Texas Instruments, Inc.
* Copyright (C) 2006 Nokia Corporation
*
* Written by:
* Richard Woodruff [EMAIL PROTECTED]
* Tony Lindgren
* Juha Yrjola
* Amit Kucheria [EMAIL PROTECTED]
* Igor Stoppa [EMAIL PROTECTED]
*
* Based on pm.c for omap1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include linux/suspend.h
#include linux/interrupt.h
#include linux/sysfs.h
#include linux/module.h
#include asm/mach/time.h
#include asm/mach/irq.h
#include asm/arch/edma.h
#include asm/arch/tcm.h
#include asm/arch/pm.h
static void (*davinci_tcm_idle)(void);
static void (*davinci_tcm_suspend)(void);
static void (*saved_idle)(void);
static unsigned short enable_standby;
static unsigned int count_idle;
static unsigned int count_standby;
static ssize_t davinci_pm_idle_show(struct kset *subsys, char *buf)
{
return sprintf(buf, %hu\n, count_idle);
}
static struct subsys_attribute idle_attr = {
.attr = {
.name = __stringify(count_idle),
.mode = 0644,
},
.show = davinci_pm_idle_show,
};
static ssize_t davinci_pm_standby_show(struct kset *subsys, char *buf)
{
return sprintf(buf, %hu\n, count_standby);
}
static struct subsys_attribute standby_attr = {
.attr = {
.name = __stringify(count_standby),
.mode = 0644,
},
.show = davinci_pm_standby_show,
};
static int davinci_irq_pending(void)
{
u32 pending, enabled0, enabled1;
enabled0 = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
enabled1 = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
/* Any enabled FIQ0 pending? */
pending = davinci_irq_readl(FIQ_REG0_OFFSET);
if (~pending enabled0)
return 1;
/* Any enabled FIQ1 pending? */
pending = davinci_irq_readl(FIQ_REG1_OFFSET);
if (~pending enabled1)
return 1;
/* Any enabled IRQ0 pending? */
pending
DM355 Power Management Problem
Hi All, I added the patch for Power Management in DM355. But during compilation I get following error: arch/arm/mach-davinci/io.c:47: error: unknown field `pfn' specified in initializer arch/arm/mach-davinci/io.c:47: warning: implicit declaration of function `phys_to_pfn' arch/arm/mach-davinci/io.c:47: error: initializer element is not constant arch/arm/mach-davinci/io.c:47: error: (near initialization for `davinci_io_desc[1].physical') arch/arm/mach-davinci/io.c:50: error: initializer element is not constant arch/arm/mach-davinci/io.c:50: error: (near initialization for `davinci_io_desc[1]') arch/arm/mach-davinci/io.c:53: error: unknown field `pfn' specified in initializer arch/arm/mach-davinci/io.c:53: error: initializer element is not constant arch/arm/mach-davinci/io.c:53: error: (near initialization for `davinci_io_desc[2].physical') arch/arm/mach-davinci/io.c:56: error: initializer element is not constant arch/arm/mach-davinci/io.c:56: error: (near initialization for `davinci_io_desc[2]') arch/arm/mach-davinci/io.c: In function `davinci_map_common_io': arch/arm/mach-davinci/io.c:111: warning: too few arguments for format So bypass this error I commented following lines in arch/arm/mach-davinci/io.c file: .pfn= phys_to_pfn(DDR2_CTRL_PHYS), .pfn= phys_to_pfn(TCM_PHYS), But then I get following error during linking. arch/arm/mach-davinci/built-in.o(.text+0x4fd4): In function `davinci_pm_idle': arch/arm/mach-davinci/sleep.S: undefined reference to `timer_dyn_reprogram' arch/arm/mach-davinci/built-in.o(.text+0x5004):arch/arm/mach-davinci/sleep.S: undefined reference to `timer_dyn_reprogram' arch/arm/mach-davinci/built-in.o(.init.text+0x14cc): In function `davinci_pm_init': arch/arm/mach-davinci/sleep.S: undefined reference to `suspend_set_ops' I didn't find suspend_set_ops() and timer_dyn_reprogram() functions defined in the kernel source tree. Please let me know where will I find the following function definition? Also how do I correct the compilation error that I am getting in io.c file? Thanks, azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
DM355 Power Management Problem
Hi All, I added the patch for Power Management in DM355. But during compilation I get following error: arch/arm/mach-davinci/io.c:47: error: unknown field `pfn' specified in initializer arch/arm/mach-davinci/io.c:47: warning: implicit declaration of function `phys_to_pfn' arch/arm/mach-davinci/io.c:47: error: initializer element is not constant arch/arm/mach-davinci/io.c:47: error: (near initialization for `davinci_io_desc[1].physical') arch/arm/mach-davinci/io.c:50: error: initializer element is not constant arch/arm/mach-davinci/io.c:50: error: (near initialization for `davinci_io_desc[1]') arch/arm/mach-davinci/io.c:53: error: unknown field `pfn' specified in initializer arch/arm/mach-davinci/io.c:53: error: initializer element is not constant arch/arm/mach-davinci/io.c:53: error: (near initialization for `davinci_io_desc[2].physical') arch/arm/mach-davinci/io.c:56: error: initializer element is not constant arch/arm/mach-davinci/io.c:56: error: (near initialization for `davinci_io_desc[2]') arch/arm/mach-davinci/io.c: In function `davinci_map_common_io': arch/arm/mach-davinci/io.c:111: warning: too few arguments for format So bypass this error I commented following lines in arch/arm/mach-davinci/io.c file: .pfn= phys_to_pfn(DDR2_CTRL_PHYS), .pfn= phys_to_pfn(TCM_PHYS), But then I get following error during linking. arch/arm/mach-davinci/built-in.o(.text+0x4fd4): In function `davinci_pm_idle': arch/arm/mach-davinci/sleep.S: undefined reference to `timer_dyn_reprogram' arch/arm/mach-davinci/built-in.o(.text+0x5004):arch/arm/mach-davinci/sleep.S: undefined reference to `timer_dyn_reprogram' arch/arm/mach-davinci/built-in.o(.init.text+0x14cc): In function `davinci_pm_init': arch/arm/mach-davinci/sleep.S: undefined reference to `suspend_set_ops' I didn't find suspend_set_ops() and timer_dyn_reprogram() functions defined in the kernel source tree. Please let me know where will I find the following function definition? Also how do I correct the compilation error that I am getting in io.c file? Thanks, azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
DM355 Power Management Problem
Hi Steve, I added the patch for Power Management in DM355. But during compilation I get following error: arch/arm/mach-davinci/io.c:47: error: unknown field `pfn' specified in initializer arch/arm/mach-davinci/io.c:47: warning: implicit declaration of function `phys_to_pfn' arch/arm/mach-davinci/io.c:47: error: initializer element is not constant arch/arm/mach-davinci/io.c:47: error: (near initialization for `davinci_io_desc[1].physical') arch/arm/mach-davinci/io.c:50: error: initializer element is not constant arch/arm/mach-davinci/io.c:50: error: (near initialization for `davinci_io_desc[1]') arch/arm/mach-davinci/io.c:53: error: unknown field `pfn' specified in initializer arch/arm/mach-davinci/io.c:53: error: initializer element is not constant arch/arm/mach-davinci/io.c:53: error: (near initialization for `davinci_io_desc[2].physical') arch/arm/mach-davinci/io.c:56: error: initializer element is not constant arch/arm/mach-davinci/io.c:56: error: (near initialization for `davinci_io_desc[2]') arch/arm/mach-davinci/io.c: In function `davinci_map_common_io': arch/arm/mach-davinci/io.c:111: warning: too few arguments for format So bypass this error I commented following lines in arch/arm/mach-davinci/io.c file: .pfn= phys_to_pfn(DDR2_CTRL_PHYS), .pfn= phys_to_pfn(TCM_PHYS), But then I get following error during linking. arch/arm/mach-davinci/built-in.o(.text+0x4fd4): In function `davinci_pm_idle': arch/arm/mach-davinci/sleep.S: undefined reference to `timer_dyn_reprogram' arch/arm/mach-davinci/built-in.o(.text+0x5004):arch/arm/mach-davinci/sleep.S: undefined reference to `timer_dyn_reprogram' arch/arm/mach-davinci/built-in.o(.init.text+0x14cc): In function `davinci_pm_init': arch/arm/mach-davinci/sleep.S: undefined reference to `suspend_set_ops' I didn't find suspend_set_ops() and timer_dyn_reprogram() functions defined in the kernel source tree. Please let me know where will I find the following function definition? Also how do I correct the compilation error that I am getting in io.c file? Thanks, azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Supporting multiple codecs
Hi,
I am using 2 different audio codecs. It seems that the davinci audio
supports only one codec at a time. How can I support more than one codec?
file: sound/oss/davinci-audio.c
int audio_register_codec(audio_state_t * codec_state)
{
int ret;
FN_IN;
/* We dont handle multiple codecs now */
if (audio_state.hw_init) {
DPRINTK(Codec Already registered\n);
return -EPERM;
}
I want /dev/sound/dsp0 for McBSP0 and /dev/sound/dsp1 for McBSP1.
Thanks,
Azam.
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Re: McBSP DMA Event [DM355]
Hi Steve, Thanks for the help. I got the McBSP0 working for my audio chip. Other than the changes you suggested I had to disable the internal clock of McBSP0. Thanks a lot for your help. Best Regards, Azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: McBSP DMA Event [DM355]
Hi Steve,
I have tried setting PINMUX3 to 0x3F as well as 0x00. In both the cases I
get the same error frame sync not detected
Below is the code snippet where I get this error:
pcrtemp = PCR;
/*Enable the transmitters pins as GPIO*/
PCR = PCR | RIOENABLE;
/*Wait for the first frame sync*/
/*Loop count assumes CPU clock is around 300MHZ*/
/* Start the sample generator */
//w = DAVINCI_MCBSP_READ(io_base, SPCR2);
//DAVINCI_MCBSP_WRITE(io_base, SPCR2, w | (1 6));
/* Enable receiver */
//w = DAVINCI_MCBSP_READ(io_base, SPCR1);
//DAVINCI_MCBSP_WRITE(io_base, SPCR1, w | 1);
//DAVINCI_MCBSP_WRITE(io_base, SPCR1, w | RRST);
//udelay(100);
/* Start frame sync */
//w = DAVINCI_MCBSP_READ(io_base, SPCR2);
//DAVINCI_MCBSP_WRITE(io_base, SPCR2, w | (1 7));
for (i = 0; (i 5000) (PCRFSRPOLARITY); i++);
for (i = 0; (i 5000) (!(PCRFSRPOLARITY)); i++);
/*Disabe the transmitter pins as GPIO*/
PCR = PCR ~RIOENABLE;
/*Restore the PCR initial value*/
PCR = pcrtemp;
/*Enable the transmitter */
if (i 5000) {
SPCR = SPCR | RRESET;
/*Restore the PCR initial value*/
} else {
printk(KERN_INFO frame sync not detected\n);
error
spin_unlock_irqrestore(rrstlock, flags);
return;
}
If I dont get the frame sync then in that case what should I check?
Thanks,
Azam.
On Thu, Apr 30, 2009 at 5:02 AM, Steve Chen sc...@mvista.com wrote:
On Wed, 2009-04-29 at 23:57 +0530, Azam Ansari wrote:
Hi Steve,
Were you getting frame sync before the change?
No. I was not getting frame sync before the change either. Does it
mean that PINMUX setup is not correct?
Currently is set PINMUX3 = 0x3F.
Did you try the suggestions in my previous e-mail about updating
mux_cfg.c which will make pinmux3=0.
Regards,
Steve
and I noticed in function
audio_aic33_init in sound/oss/dm644x/davinci-
audio-aic33.c contains
...
if (cpu_is_davinci_dm355()) {
input_stream.dma_dev = DM355_DMA_MCBSP1_RX;
output_stream.dma_dev = DM355_DMA_MCBSP1_TX;
...
May want to try
if (cpu_is_davinci_dm355()) {
input_stream.dma_dev = DM355_DMA_MCBSP0_RX;
output_stream.dma_dev = DM355_DMA_MCBSP0_TX;
Also, file arch/arm/mach-davinci/mcbsp.c function
davinci_mcbsp_recv_buffer may want to try replacing
if (!cpu_is_davinci_dm355())
davinci_set_dma_src_params(mcbsp[id].dma_rx_lch,
(unsigned long) DAVINCI_MCBSP_BASE,
0,
0);
else
davinci_set_dma_src_params(mcbsp[id].dma_rx_lch,
(unsigned long)
DAVINCI_MCBSP1_BASE, 0,
0);
with just
davinci_set_dma_src_params(mcbsp[id].dma_rx_lch,
(unsigned long) DAVINCI_MCBSP_BASE,
0,
0);
I am using DM355 board. I have already modified the change suggest but
it is not working.
Any thing else that I need to check?
Thanks,
Azam.
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Re: McBSP DMA Event [DM355]
Dear Liu,
I am using following configuration for McBSP0
#define MCBSP_DXR 0x01E02004
#define MCBSP_DRR 0x01E02000
static audio_stream_t output_stream = {
.id = FM11 out,
.dma_dev = DAVINCI_DMA_MCBSP_TX,
.input_or_output = FMODE_WRITE,
.mcbsp_id = 0
};
static audio_stream_t input_stream = {
.id = FM11 in,
.dma_dev = DAVINCI_DMA_MCBSP_RX,
.input_or_output = FMODE_READ,
.mcbsp_id = 0
};
I have question about MCLK that is used for MCBSP1.
#define MCLK 27
What clock should be used for MCBSP0?
Thanks,
Azam.
On Thu, Apr 30, 2009 at 7:45 AM, Liu Yebo liuy...@covond.com wrote:
Hi
May be you should check below codes in file davinci-audio-dma-intfc.c.
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E04004 : 0x01E02004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E04000 : 0x01E02000)
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* Steve Chen sc...@mvista.com
*Cc:* davinci-linux-open-source@linux.davincidsp.com
*Sent:* Thursday, April 30, 2009 2:27 AM
*Subject:* Re: McBSP DMA Event [DM355]
Hi Steve,
Were you getting frame sync before the change?
No. I was not getting frame sync before the change either. Does it mean
that PINMUX setup is not correct?
Currently is set PINMUX3 = 0x3F.
and I noticed in function
audio_aic33_init in sound/oss/dm644x/davinci- audio-aic33.c contains
...
if (cpu_is_davinci_dm355()) {
input_stream.dma_dev = DM355_DMA_MCBSP1_RX;
output_stream.dma_dev = DM355_DMA_MCBSP1_TX;
...
May want to try
if (cpu_is_davinci_dm355()) {
input_stream.dma_dev = DM355_DMA_MCBSP0_RX;
output_stream.dma_dev = DM355_DMA_MCBSP0_TX;
Also, file arch/arm/mach-davinci/mcbsp.c function
davinci_mcbsp_recv_buffer may want to try replacing
if (!cpu_is_davinci_dm355())
davinci_set_dma_src_params(mcbsp[id].dma_rx_lch,
(unsigned long) DAVINCI_MCBSP_BASE, 0,
0);
else
davinci_set_dma_src_params(mcbsp[id].dma_rx_lch,
(unsigned long) DAVINCI_MCBSP1_BASE, 0,
0);
with just
davinci_set_dma_src_params(mcbsp[id].dma_rx_lch,
(unsigned long) DAVINCI_MCBSP_BASE, 0,
0);
I am using DM355 board. I have already modified the change suggest but it
is not working.
Any thing else that I need to check?
Thanks,
Azam.
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GIT Kernel for DM355
Hi All, Does GIT kernel support DM355? If it supports DM355 then where will I find all codes related to McBSP? I downloaded the latest git kernel. When I do make menuconfig it gives error as below: Makefile:317: warning: overriding commands for target `/home/azam/work/Linux' Makefile:115: warning: ignoring old commands for target `/home/azam/work/Linux' Makefile:318: /home/azam/work/Linux: No such file or directory Makefile:318: kernel/linux-davinci/scripts/Kbuild.include: No such file or directory Makefile:456: /home/azam/work/Linux: No such file or directory Makefile:456: kernel/linux-davinci/arch/arm/Makefile: No such file or directory make: *** No rule to make target `kernel/linux-davinci/arch/arm/Makefile'. Stop. I tried other config options also but it doesn't work. Thanks, Azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: McBSP DMA Event [DM355]
Hi Steve, After looking into the PINMUX I found that the pinmux setting is being done when I call board_setup_psc(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_McBSP0, 1); This does the PINMUX settings for McBSP0. I found two patchs on the mailing list for McBSP0 setup... tx_swap.patch rx_swap.patch http://www.mail-archive.com/davinci-linux-open-source@linux.davincidsp.com/msg10133.html I tried applying the patches but the patches are not getting applied. So I manually checked the patch and added it. After that I get following error for audio recording frame sync not detected. It seems that the frames are not getting detected. Also I found ASP1 uses CLKS pin for clock. So I changed it to use CLKR pin for ASP0 by setting SCLKME bit in PCR. I found few code in mcbsp.c and davinci-audio-dma-intf.c file that is only for ASP1 and not for ASP0. So I modified it too but still recording is not working. *Example:* *OLD:* if (!cpu_is_davinci_dm355()) davinci_set_dma_dest_params(mcbsp[id].dma_tx_lch, (unsigned long) (DAVINCI_MCBSP_BASE + 4), 0, 0); else davinci_set_dma_dest_params(mcbsp[id].dma_tx_lch, (unsigned long) (DAVINCI_MCBSP1_BASE + 4), 0, 0); *NEW:* if (cpu_is_davinci_dm355()) davinci_set_dma_dest_params(mcbsp[id].dma_tx_lch, (unsigned long) (DAVINCI_MCBSP_BASE + 4), 0, 0); else davinci_set_dma_dest_params(mcbsp[id].dma_tx_lch, (unsigned long) (DAVINCI_MCBSP1_BASE + 4), 0, 0); Please help... On Mon, Apr 27, 2009 at 7:27 PM, Steve Chen sc...@mvista.com wrote: On Mon, 2009-04-27 at 18:22 +0530, Azam Ansari wrote: Hi Steve, When I check /proc/pinmux it shows that Pinmux is configured for McBSP 29:34 but when I see the schematics it shows that McBSP pins are on 25:30. Can you please tell me how do i enable event mux for McBSP0 pin 25:30? There is a pinmux layer that is used to manage pinmux settings. The definitions are in In file, arch/arm/mach-davinci/mux_cfg.c. Please take a look at davinci_dm355_pins. With MV kernel pinmux is setup automatically when clk_enable is called. You can see the actual call to setup pinmux in arch/arm/mach-davinci/board-dm355-evm.c function dm355_setup_pinmux. It seems the code is setting pinmux register 3 bits 0-5 as 1's (following code segment comes from davinci_dm355_pins in arch/arm/mach-davinci/mux_cfg.c. ... MUX_CFG(MCBSP0_BDX,3, 0, 1, 1, 0) MUX_CFG(MCBSP0_X, 3, 1, 1, 1, 0) MUX_CFG(MCBSP0_BFSX, 3, 2, 1, 1, 0) MUX_CFG(MCBSP0_BDR,3, 3, 1, 1, 0) MUX_CFG(MCBSP0_R, 3, 4, 1, 1, 0) MUX_CFG(MCBSP0_BFSR, 3, 5, 1, 1, 0) ... It is not immediately obvious looking at the datasheet that 1 is the correct setting. perhaps try setting to 0's and see if it works for you. ... MUX_CFG(MCBSP0_BDX,3, 0, 1, 0, 0) MUX_CFG(MCBSP0_X, 3, 1, 1, 0, 0) MUX_CFG(MCBSP0_BFSX, 3, 2, 1, 0, 0) MUX_CFG(MCBSP0_BDR,3, 3, 1, 0, 0) MUX_CFG(MCBSP0_R, 3, 4, 1, 0, 0) MUX_CFG(MCBSP0_BFSR, 3, 5, 1, 0, 0) ... If you have a scope to look at the clocks and data, it would be helpful in debugging as well. Regards, Steve On Mon, Apr 27, 2009 at 5:18 PM, Steve Chen sc...@mvista.com wrote: On Mon, 2009-04-27 at 14:20 +0530, Azam Ansari wrote: Hi, I have enabled McBSP0 in the board-dm355-evm.c file. I have configure McBSP0 for audio but it is not working( Currently I am using McBSP0 for only recording purpose...). May want to check the pinmux settings.. just a thought. Regards, Steve ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: McBSP DMA Event [DM355]
Hi Steve,
Were you getting frame sync before the change?
No. I was not getting frame sync before the change either. Does it mean that
PINMUX setup is not correct?
Currently is set PINMUX3 = 0x3F.
and I noticed in function
audio_aic33_init in sound/oss/dm644x/davinci- audio-aic33.c contains
...
if (cpu_is_davinci_dm355()) {
input_stream.dma_dev = DM355_DMA_MCBSP1_RX;
output_stream.dma_dev = DM355_DMA_MCBSP1_TX;
...
May want to try
if (cpu_is_davinci_dm355()) {
input_stream.dma_dev = DM355_DMA_MCBSP0_RX;
output_stream.dma_dev = DM355_DMA_MCBSP0_TX;
Also, file arch/arm/mach-davinci/mcbsp.c function
davinci_mcbsp_recv_buffer may want to try replacing
if (!cpu_is_davinci_dm355())
davinci_set_dma_src_params(mcbsp[id].dma_rx_lch,
(unsigned long) DAVINCI_MCBSP_BASE, 0,
0);
else
davinci_set_dma_src_params(mcbsp[id].dma_rx_lch,
(unsigned long) DAVINCI_MCBSP1_BASE, 0,
0);
with just
davinci_set_dma_src_params(mcbsp[id].dma_rx_lch,
(unsigned long) DAVINCI_MCBSP_BASE, 0,
0);
I am using DM355 board. I have already modified the change suggest but it is
not working.
Any thing else that I need to check?
Thanks,
Azam.
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McBSP DMA Event [DM355]
Hi,
I have enabled McBSP0 in the board-dm355-evm.c file.
I have configure McBSP0 for audio but it is not working( Currently I am
using McBSP0 for only recording purpose...).
I found that McBSP1 EDMA event is enable in mcbsp.c file by following code:
if (cpu_is_davinci_dm355()) {
__REG(EDMA_EVTMUX) = ~(0x3);/* enable EDMA event for MCBSP1 */
How do I enable EDMA event for McBSP0?
Below is configuration done for McBSP0 that I am using...
spcr2= FREE | XINTM(3),
spcr1= RINTM(3),
rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/* configure McBSP to be the I2S slave */
pcr0 = CLKXP | CLKRP,
I have also tried using CLKX PIN as CLKS PIN for recoding. But it doesn't
work...
I have went through all the McBSP related email chain to get McBSP0 work but
it hasn't...
Any idea guys how to make McBSP0 work for PCM audio?
Thanks.
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Re: McBSP DMA Event [DM355]
Hi Steve, When I check /proc/pinmux it shows that Pinmux is configured for McBSP 29:34 but when I see the schematics it shows that McBSP pins are on 25:30. Can you please tell me how do i enable event mux for McBSP0 pin 25:30? On Mon, Apr 27, 2009 at 5:18 PM, Steve Chen sc...@mvista.com wrote: On Mon, 2009-04-27 at 14:20 +0530, Azam Ansari wrote: Hi, I have enabled McBSP0 in the board-dm355-evm.c file. I have configure McBSP0 for audio but it is not working( Currently I am using McBSP0 for only recording purpose...). May want to check the pinmux settings.. just a thought. Regards, Steve ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
DM355 GPIO6 interrupt handling problem
Hi All,
I have got an issue when using GPIO6 for motion detection.
I am using GPIO6 for motion detection.
Whenever motion is detected interrupt is generated and IRQ handler is
called.
From IRQ handler I just call tasklet_schedule()
below is code for IRQ:
static irqreturn_t vpfe_motion_isr(int irq, void *dev_id, struct pt_regs
*regs)
{
vpfe_obj *vpfe = vpfe_device;
tasklet_schedule(motion_night_isr_work);
return IRQ_RETVAL(1);
}
In tasklet I do I2C Write and then I2C Read to get detection information and
based on the detection information I wake-up the thread. But I get kernel
panic error.
Below is code for tasklet:
[code]
static void motion_night_detection_handler(unsigned long info)
{
int ret = 0;
void *tmp = (void *)info;
tw2835_interrupt_info interrupt_info = { 0 };
tw2835_params *tmp_device_info = (tw2835_params*)tmp;
/// check what has caused the interrupt
ret = tw2835_find_interrupt_cause(interrupt_info);
if(interrupt_info.motion_channel)
{
tmp_device_info-motion_detection_flag = 1;
tmp_device_info-motion_channel = interrupt_info.motion_channel;
wake_up_interruptible(tw2835_motion_detection_queue);
}
if(interrupt_info.night_channel)
{
tmp_device_info-night_detection_flag = 1;
tmp_device_info-night_channel = interrupt_info.night_channel;
wake_up_interruptible(tw2835_night_detection_queue);
}
if(interrupt_info.nvideo_channel)
{
tmp_device_info-nvideo_detection_flag = 1;
tmp_device_info-nvideo_channel = interrupt_info.nvideo_channel;
wake_up_interruptible(tw2835_nvideo_detection_queue);
}
if(interrupt_info.blind_channel)
{
tmp_device_info-blind_detection_flag = 1;
tmp_device_info-blind_channel = interrupt_info.blind_channel;
wake_up_interruptible(tw2835_blind_detection_queue);
}
}
int tw2835_find_interrupt_cause(tw2835_interrupt_info *info)
{
int ret = 0;
u8 data = 0;
ret |= tw2835_write_value(PAGE1, 0x76, 0x00);
info-motion_channel = 0;
if(tw2835_global_motion_flag)
{
ret |= tw2835_read_value(PAGE1, 0x79, data);
info-motion_channel = (data 0x0F);
}
return ret;
}
[\code]
Below is the dump of the error:
[error]
BUG: scheduling while atomic: swapper/0x0103/0
caller is schedule+0xec/0x12c
BUG: scheduling from the idle thread!
Unable to handle kernel NULL pointer dereference at virtual address 0004
pgd = c0004000
[0004] *pgd=
Internal error: Oops: 17 [#1]
Modules linked in:
CPU: 0
PC is at dequeue_task+0xc/0x78
LR is at deactivate_task+0x28/0x34
pc : [c0048398]lr : [c00486d4]Not tainted
sp : c02e9d28 ip : c02e9d38 fp : c02e9d34
r10: c02e8000 r9 : c0353810 r8 : c02ea0c0
r7 : c02fe14c r6 : 4013 r5 : c02fe144 r4 : c02ea0c0
r3 : r2 : r1 : r0 : c02ea0c0
Flags: nZCv IRQs off FIQs on Mode SVC_32 Segment kernel
Control: 5317F Table: 85F9 DAC: 0017
Process swapper (pid: 0, stack limit = 0xc02e81a0)
Stack: (0xc02e9d28 to 0xc02ea000)
9d20: c02e9d4c c02e9d38 c00486d4 c004839c c029f388
c029f388
9d40: c02e9d9c c02e9d50 c029ee44 c00486bc c02e9ddc c7297cd0 c036a9b4
00989680
9d60: d5905180 00989643 c02ea21c c02e9d94 c02e8000 c02fe144
4013
9d80: c02fe14c c02ea0c0 c034eca0 c0358aa0 c02e9dbc c02e9da0 c029f388
c029ec70
9da0: 8013 c02e8000 c02e9dfc c02e9dc0 c029e9dc
c029f2ac
9dc0: 0001 c02ea0c0 c004927c c02fe14c c02fe14c c02e9dfc
c02fe128
9de0: c02fe144 0001 c0358af0 000a c02e9e2c c02e9e00 c029e88c
c029e900
9e00: c02fe128 c02e9e38 0001 c018cb24 c02fe128 c018a888 0001
0042
9e20: c02e9e5c c02e9e30 c018d33c c018a84c c0007601 0042
0003
9e40: c02e9e30 0006 c02e9e90 c02e9e6c c02e9e60 c018d5d8
c018d2d4
9e60: c02e9e8c c02e9e70 c0192bf8 c018d5c4 c02e8000 002e8000 c036b5e0
9e80: c02e9eac c02e9e90 c0197dc8 c0192bd8 c02e9ea0
c0358ac4
9ea0: c02e9ec4 c02e9eb0 c0052c78 c0197db4 c02e8000 0103 c02e9eec
c02e9ec8
9ec0: c0052730 c0052c08 c02e8000 c0033f9c 0002 c02e8000
c02e9f58
9ee0: c02e9f04 c02e9ef0 c005280c c00526ec c02e8000 c02e8000 c02e9f1c
c02e9f08
9f00: c00529c4 c00527e4 c0033f9c c02e9f8c c02e9f54 c02e9f20 c00334c0
c0052988
9f20: d32df780 00989643 00989680 c02e9f8c e1048000 c0033f9c 0002
c02e8000
9f40: 0001 8002a580 c02e9fb4 c02e9f58 c0031780 c00333b0
0005317f
9f60: 0005217f 6013 c02e8000 6093 c035b704 c037a764 8002a5b0
41069265
9f80: 8002a580 c02e9fb4 c02e9fa0 c02e9fa0 c0033f9c c0033fac 6013
9fa0: c02e8000 c0033f34 c02e9fcc c02e9fb8 c0034004 c0033f44 00053175
c034e7dc
9fc0: c02e9ffc c02e9fd0 c00087d8 c0033fc4 c0008304
c034fc38
9fe0: 00053175 c034fc1c c02eafd0 c02ea000 8000809c
c0008660
Backtrace:
[c004838c] (dequeue_task+0x0/0x78) from [c00486d4]
(deactivate_task+0x28/0x34)
Configure McBSP for PCM
Hi All, I need to configure McBSP for PCM interface. Is it possible to configure McBSP for PCM interface? If it is possible then please let me know how to configure McBSP? -Azam ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Configure McBSP for PCM interface
Hi All, Can we configure McBSP on DM355 to support PCM interface? 4 line interface: PCMCLK PCMSYNC PCMI PCMO The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is transmitted or received at the PCMCLK speed once every PCMSYN cycle. If we can support PCM interface then how to configure McBSP for PCM interface? Please let me know? -Azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Configure McBSP for PCM interface
Hi, Can we configure McBSP on DM355 to support PCM interface? 4 line interface: PCMCLK PCMSYNC PCMI PCMO The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is transmitted or received at the PCMCLK speed once every PCMSYN cycle. If we can support PCM interface then how to configure McBSP for PCM interface? Please let me know? -Azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
DM355 IRQ settings
Hi, There is a interrupt line connected to GIO6 pin on DM355. Whenever motion is detected the GIO6 pin is set High. Below is what I have done to configure the GIO6 for interrupt. ret = request_irq(IRQ_DM355_GPIO6, vpfe_motion_isr, SA_INTERRUPT, dm355v4l2, (void *)vpfe_device); Do I need to do anything else to configure it as interrupt line? Thanks, Azam. -- Happiness keeps u Sweet, Trials keep u Strong, Sorrow keeps u Human, Failure Keeps u Humble, Success keeps u Glowing, But only GOD Keeps u Going. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: DM355 daughter sound card problem
Hi Liu,
The Clock that I get on the FSR PIN is 2MHz and on Sync pin is 6.5KHz.
But there is no interrupt generated. Please let me know if Any extra
settings are required for or the readings are incorrect.
Thanks,
Azam.
2009/3/5 Liu Yebo liuy...@covond.com
HI,
The clock(For Ex: 8KHZ) is present on FSR PIN not CLKR PIN of DM355.
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* Liu Yebo liuy...@covond.com
*Cc:* Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 5:15 PM
*Subject:* Re: DM355 daughter sound card problem
Hi Liu,
I am making driver for TechWell TW2835 chip. It is a audio/video mux.
2009/3/4 Liu Yebo liuy...@covond.com
Are you working with AIC33 on your daughter sound board ?
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* liuy...@covond.com ; Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 4:34 PM
*Subject:* Re: DM355 daughter sound card problem
Hi,
I tried your suggestion. Still recording doesn't work. Anything else that
I need to try?
2009/3/4 liuy...@covond.com
Try the following to set CLKX PIN as CLKS PIN for recoding.
initial_config.srgr2 = initial_config.srgr2 | CLKSM;
initial_config.pcr0 = (initial_config.pcr0 | SCLKME);
SCLKME CLKSM Input Clock For Sample Rate Generator
0 0 Signal on CLKS pin
0 1 ASP internal input clock
1 0 Signal on CLKR pin
1 1 Signal on CLKX pin
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* liuy...@covond.com ;
Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 2:28 PM
*Subject:* Re: DM355 daughter sound card problem
DM355 is slave. below is configuration done for pcr0 and srgr2:
pcr0 = CLKXP | CLKRP
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1)
2009/3/4 liuy...@covond.com
Hi,
Does DM355 is the master ?
You should to do some settings for srgr2 and pcr0 because MCBSP0 has no
CLKS PIN.
SCLKME CLKSM Input Clock For Sample Rate Generator
0 0 Signal on CLKS pin
0 1 ASP internal input clock
1 0 Signal on CLKR pin
1 1 Signal on CLKX pin
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* liuy...@covond.com ;
Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 1:22 PM
*Subject:* Re: DM355 daughter sound card problem
Hi,
I am sorry I didn't say this before. I am already using the setting
suggested by you.
Below is the detailed setting that I am using for configuring MCBSP0:
#define MCLK 27
#define DAVINCI_DMA_MCBSP_TX 2
#define DAVINCI_DMA_MCBSP_RX 3
#define DEFAULT_BITPERSAMPLE 256
#define AUDIO_RATE_DEFAULT8000
output_stream.dma_dev = DAVINCI_DMA_MCBSP_TX
input_stream.dma_dev = DAVINCI_DMA_MCBSP_RX
/* MCBSP register settings for I2S */
spcr2 = FREE | XINTM(3),
spcr1 = RINTM(3),
rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/* configure McBSP to be the I2S slave */
pcr0 = CLKXP | CLKRP,
/* MCBSP0 information */
struct davinci_mcbsp_info mcbsp_davinci = {
.virt_base = IO_ADDRESS(DAVINCI_MCBSP0_BASE),
.dma_rx_sync = DM355_DMA_MCBSP0_RX,
.dma_tx_sync = DM355_DMA_MCBSP0_TX,
.rx_irq = IRQ_MBRINT,
.tx_irq = IRQ_MBXINT
},
Is there any thing else that I will have to do?
Please help...
2009/3/3 liuy...@covond.com
Hi，
I know your means.
Following codes are used for configuaring MCBSP0 on my board:
input_stream.dma_dev = DM355_DMA_MCBSP0_RX;
output_stream.dma_dev = DM355_DMA_MCBSP0_TX;
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E02000:0x01E04000)
Hi,
I am using MCBSP0 for I2S data transfer. The daughter sound is
connected to
MCBSP0 through DC3. Also for recoding the daughter card works in
Master
mode. The default code is already configured for using MCBSP1.
Configuration
suggested by you are used for configuring MCBSP1 and not MCBSP0. I am
using
MCBSP0 for I2S.
On Tue, Mar 3, 2009 at 3:04 PM, liuy...@covond.com wrote:
Step 1: modify the following code with McBSP1 DMA params (
DM355_DMA_MCBSP0_RX, DM355_DMA_MCBSP1_TX)in file
davinci-audio-aic33.c.
input_stream.dma_dev = DM355_DMA_MCBSP1_RX;
output_stream.dma_dev = DM355_DMA_MCBSP1_TX;
Step 2 : modefy the following code
Re: Need help
Hi, What is the Codec that you are using? Does it support line mixing? Thanks. On Mon, Mar 9, 2009 at 3:38 PM, Prabhu Kalyan Rout prabhu_r...@mindtree.com wrote: Hi, My requirement is to capture from both LINE IN and MIC. But current OSS functionality does not allow us to do that Can any body tell me how to achieve this functionality using OSS as the driver? Thanks http://www.mindtree.com/email/disclaimer.html ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- Happiness keeps u Sweet, Trials keep u Strong, Sorrow keeps u Human, Failure Keeps u Humble, Success keeps u Glowing, But only GOD Keeps u Going. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: DM355 daughter sound card problem
Hi,
I tried your suggestion. Still recording doesn't work. Anything else that I
need to try?
2009/3/4 liuy...@covond.com
Try the following to set CLKX PIN as CLKS PIN for recoding.
initial_config.srgr2 = initial_config.srgr2 | CLKSM;
initial_config.pcr0 = (initial_config.pcr0 | SCLKME);
SCLKME CLKSM Input Clock For Sample Rate Generator
0 0 Signal on CLKS pin
0 1 ASP internal input clock
1 0 Signal on CLKR pin
1 1 Signal on CLKX pin
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* liuy...@covond.com ; Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 2:28 PM
*Subject:* Re: DM355 daughter sound card problem
DM355 is slave. below is configuration done for pcr0 and srgr2:
pcr0 = CLKXP | CLKRP
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1)
2009/3/4 liuy...@covond.com
Hi,
Does DM355 is the master ?
You should to do some settings for srgr2 and pcr0 because MCBSP0 has no
CLKS PIN.
SCLKME CLKSM Input Clock For Sample Rate Generator
0 0 Signal on CLKS pin
0 1 ASP internal input clock
1 0 Signal on CLKR pin
1 1 Signal on CLKX pin
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* liuy...@covond.com ;
Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 1:22 PM
*Subject:* Re: DM355 daughter sound card problem
Hi,
I am sorry I didn't say this before. I am already using the setting
suggested by you.
Below is the detailed setting that I am using for configuring MCBSP0:
#define MCLK 27
#define DAVINCI_DMA_MCBSP_TX 2
#define DAVINCI_DMA_MCBSP_RX 3
#define DEFAULT_BITPERSAMPLE 256
#define AUDIO_RATE_DEFAULT8000
output_stream.dma_dev = DAVINCI_DMA_MCBSP_TX
input_stream.dma_dev = DAVINCI_DMA_MCBSP_RX
/* MCBSP register settings for I2S */
spcr2 = FREE | XINTM(3),
spcr1 = RINTM(3),
rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/* configure McBSP to be the I2S slave */
pcr0 = CLKXP | CLKRP,
/* MCBSP0 information */
struct davinci_mcbsp_info mcbsp_davinci = {
.virt_base = IO_ADDRESS(DAVINCI_MCBSP0_BASE),
.dma_rx_sync = DM355_DMA_MCBSP0_RX,
.dma_tx_sync = DM355_DMA_MCBSP0_TX,
.rx_irq = IRQ_MBRINT,
.tx_irq = IRQ_MBXINT
},
Is there any thing else that I will have to do?
Please help...
2009/3/3 liuy...@covond.com
Hi，
I know your means.
Following codes are used for configuaring MCBSP0 on my board:
input_stream.dma_dev = DM355_DMA_MCBSP0_RX;
output_stream.dma_dev = DM355_DMA_MCBSP0_TX;
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E02000:0x01E04000)
Hi,
I am using MCBSP0 for I2S data transfer. The daughter sound is
connected to
MCBSP0 through DC3. Also for recoding the daughter card works in Master
mode. The default code is already configured for using MCBSP1.
Configuration
suggested by you are used for configuring MCBSP1 and not MCBSP0. I am
using
MCBSP0 for I2S.
On Tue, Mar 3, 2009 at 3:04 PM, liuy...@covond.com wrote:
Step 1: modify the following code with McBSP1 DMA params (
DM355_DMA_MCBSP0_RX, DM355_DMA_MCBSP1_TX)in file
davinci-audio-aic33.c.
input_stream.dma_dev = DM355_DMA_MCBSP1_RX;
output_stream.dma_dev = DM355_DMA_MCBSP1_TX;
Step 2 : modefy the following code in file davinci-audio-dma-intfc.c
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E04004 :
0x01E02004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E04000 :
0x01E02000)
like this
#define MCBSP_DXR (cpu_is_davinci_dm355() ?
0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ?
0x01E02000:0x01E04000)
I do it so , GOOD LUCK!
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* Davinci-linux-open-source@linux.davincidsp.com ;
liuy...@covond.com
*Sent:* Tuesday, March 03, 2009 4:53 PM
*Subject:* Re: DM355 daughter sound card problem
Please can you provide some more details
Which clock to configure?
How to configure the clock?
2009/3/3 Kapil Pendse kapil.pen...@gmail.com
Hi All,
I am developing driver for daughter sound card on DM355 by modifying
the
AIC33 driver.
I2C is working fine and the ioctl's are working fine but recording is
not
working
Re: DM355 daughter sound card problem
Hi Liu,
I am making driver for TechWell TW2835 chip. It is a audio/video mux.
2009/3/4 Liu Yebo liuy...@covond.com
Are you working with AIC33 on your daughter sound board ?
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* liuy...@covond.com ; Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 4:34 PM
*Subject:* Re: DM355 daughter sound card problem
Hi,
I tried your suggestion. Still recording doesn't work. Anything else that I
need to try?
2009/3/4 liuy...@covond.com
Try the following to set CLKX PIN as CLKS PIN for recoding.
initial_config.srgr2 = initial_config.srgr2 | CLKSM;
initial_config.pcr0 = (initial_config.pcr0 | SCLKME);
SCLKME CLKSM Input Clock For Sample Rate Generator
0 0 Signal on CLKS pin
0 1 ASP internal input clock
1 0 Signal on CLKR pin
1 1 Signal on CLKX pin
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* liuy...@covond.com ; Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 2:28 PM
*Subject:* Re: DM355 daughter sound card problem
DM355 is slave. below is configuration done for pcr0 and srgr2:
pcr0 = CLKXP | CLKRP
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1)
2009/3/4 liuy...@covond.com
Hi,
Does DM355 is the master ?
You should to do some settings for srgr2 and pcr0 because MCBSP0 has no
CLKS PIN.
SCLKME CLKSM Input Clock For Sample Rate Generator
0 0 Signal on CLKS pin
0 1 ASP internal input clock
1 0 Signal on CLKR pin
1 1 Signal on CLKX pin
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* liuy...@covond.com ;
Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 1:22 PM
*Subject:* Re: DM355 daughter sound card problem
Hi,
I am sorry I didn't say this before. I am already using the setting
suggested by you.
Below is the detailed setting that I am using for configuring MCBSP0:
#define MCLK 27
#define DAVINCI_DMA_MCBSP_TX 2
#define DAVINCI_DMA_MCBSP_RX 3
#define DEFAULT_BITPERSAMPLE 256
#define AUDIO_RATE_DEFAULT8000
output_stream.dma_dev = DAVINCI_DMA_MCBSP_TX
input_stream.dma_dev = DAVINCI_DMA_MCBSP_RX
/* MCBSP register settings for I2S */
spcr2 = FREE | XINTM(3),
spcr1 = RINTM(3),
rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/* configure McBSP to be the I2S slave */
pcr0 = CLKXP | CLKRP,
/* MCBSP0 information */
struct davinci_mcbsp_info mcbsp_davinci = {
.virt_base = IO_ADDRESS(DAVINCI_MCBSP0_BASE),
.dma_rx_sync = DM355_DMA_MCBSP0_RX,
.dma_tx_sync = DM355_DMA_MCBSP0_TX,
.rx_irq = IRQ_MBRINT,
.tx_irq = IRQ_MBXINT
},
Is there any thing else that I will have to do?
Please help...
2009/3/3 liuy...@covond.com
Hi，
I know your means.
Following codes are used for configuaring MCBSP0 on my board:
input_stream.dma_dev = DM355_DMA_MCBSP0_RX;
output_stream.dma_dev = DM355_DMA_MCBSP0_TX;
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E02000:0x01E04000)
Hi,
I am using MCBSP0 for I2S data transfer. The daughter sound is
connected to
MCBSP0 through DC3. Also for recoding the daughter card works in
Master
mode. The default code is already configured for using MCBSP1.
Configuration
suggested by you are used for configuring MCBSP1 and not MCBSP0. I am
using
MCBSP0 for I2S.
On Tue, Mar 3, 2009 at 3:04 PM, liuy...@covond.com wrote:
Step 1: modify the following code with McBSP1 DMA params (
DM355_DMA_MCBSP0_RX, DM355_DMA_MCBSP1_TX)in file
davinci-audio-aic33.c.
input_stream.dma_dev = DM355_DMA_MCBSP1_RX;
output_stream.dma_dev = DM355_DMA_MCBSP1_TX;
Step 2 : modefy the following code in file davinci-audio-dma-intfc.c
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E04004 :
0x01E02004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E04000 :
0x01E02000)
like this
#define MCBSP_DXR (cpu_is_davinci_dm355() ?
0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ?
0x01E02000:0x01E04000)
I do it so , GOOD LUCK!
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* Davinci-linux-open-source@linux.davincidsp.com ;
liuy...@covond.com
*Sent:* Tuesday, March 03, 2009 4
Re: DM355 daughter sound card problem
Please can you provide some more details Which clock to configure? How to configure the clock? 2009/3/3 Kapil Pendse kapil.pen...@gmail.com Hi All, I am developing driver for daughter sound card on DM355 by modifying the AIC33 driver. I2C is working fine and the ioctl's are working fine but recording is not working. There are 2 McBSP bus (McBSP1 and McBSP2) used for DMA transfer out of which McBSP1 is used for the sound daughter card. Audio format is I2S. Following is the configuration that I tried: #define DEFAULT_BITPERSAMPLE 256 #define AUDIO_RATE_DEFAULT 8000 #defineAUDIO_MCBSP DAVINCI_MCBSP1 McBSP1 is configured as slave for recording. Below is configuration for McBSP1: .spcr2 = FREE | XINTM(3), .spcr1 = RINTM(3), .rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1), .rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16), .xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG, .xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16), .srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1), .srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1), /* configure McBSP to be the I2S master */ .pcr0 = FSXM | FSRM | CLKXM | CLKRM | CLKXP | CLKRP, Daughter card is configured for 16bit word, 8000KHz and 256bits per sample. AIC33 uses McBSP2 while my audio daughter card uses McBSP1. Also, the default bits per sample for AIC33 is 16, I've changed it to 256. But I don't get any interrupt for recording. Please can anyone help to sort out the problem. Thanks, Azam. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source -- Happiness keeps u Sweet, Trials keep u Strong, Sorrow keeps u Human, Failure Keeps u Humble, Success keeps u Glowing, But only GOD Keeps u Going. ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
Re: DM355 daughter sound card problem
Hi,
I am sorry I didn't say this before. I am already using the setting
suggested by you.
Below is the detailed setting that I am using for configuring MCBSP0:
#define MCLK 27
#define DAVINCI_DMA_MCBSP_TX 2
#define DAVINCI_DMA_MCBSP_RX 3
#define DEFAULT_BITPERSAMPLE 256
#define AUDIO_RATE_DEFAULT8000
output_stream.dma_dev = DAVINCI_DMA_MCBSP_TX
input_stream.dma_dev = DAVINCI_DMA_MCBSP_RX
/* MCBSP register settings for I2S */
spcr2 = FREE | XINTM(3),
spcr1 = RINTM(3),
rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/* configure McBSP to be the I2S slave */
pcr0 = CLKXP | CLKRP,
/* MCBSP0 information */
struct davinci_mcbsp_info mcbsp_davinci = {
.virt_base = IO_ADDRESS(DAVINCI_MCBSP0_BASE),
.dma_rx_sync = DM355_DMA_MCBSP0_RX,
.dma_tx_sync = DM355_DMA_MCBSP0_TX,
.rx_irq = IRQ_MBRINT,
.tx_irq = IRQ_MBXINT
},
Is there any thing else that I will have to do?
Please help...
2009/3/3 liuy...@covond.com
Hi，
I know your means.
Following codes are used for configuaring MCBSP0 on my board:
input_stream.dma_dev = DM355_DMA_MCBSP0_RX;
output_stream.dma_dev = DM355_DMA_MCBSP0_TX;
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E02000:0x01E04000)
Hi,
I am using MCBSP0 for I2S data transfer. The daughter sound is connected
to
MCBSP0 through DC3. Also for recoding the daughter card works in Master
mode. The default code is already configured for using MCBSP1.
Configuration
suggested by you are used for configuring MCBSP1 and not MCBSP0. I am
using
MCBSP0 for I2S.
On Tue, Mar 3, 2009 at 3:04 PM, liuy...@covond.com wrote:
Step 1: modify the following code with McBSP1 DMA params (
DM355_DMA_MCBSP0_RX, DM355_DMA_MCBSP1_TX)in file davinci-audio-aic33.c.
input_stream.dma_dev = DM355_DMA_MCBSP1_RX;
output_stream.dma_dev = DM355_DMA_MCBSP1_TX;
Step 2 : modefy the following code in file davinci-audio-dma-intfc.c
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E04004 :
0x01E02004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E04000 :
0x01E02000)
like this
#define MCBSP_DXR (cpu_is_davinci_dm355() ?
0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ?
0x01E02000:0x01E04000)
I do it so , GOOD LUCK!
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* Davinci-linux-open-source@linux.davincidsp.com ;
liuy...@covond.com
*Sent:* Tuesday, March 03, 2009 4:53 PM
*Subject:* Re: DM355 daughter sound card problem
Please can you provide some more details
Which clock to configure?
How to configure the clock?
2009/3/3 Kapil Pendse kapil.pen...@gmail.com
Hi All,
I am developing driver for daughter sound card on DM355 by modifying
the
AIC33 driver.
I2C is working fine and the ioctl's are working fine but recording is
not
working.
There are 2 McBSP bus (McBSP1 and McBSP2) used for DMA transfer out of
which McBSP1 is used for the sound daughter card.
Audio format is I2S.
Following is the configuration that I tried:
#define DEFAULT_BITPERSAMPLE 256
#define AUDIO_RATE_DEFAULT 8000
#defineAUDIO_MCBSP DAVINCI_MCBSP1
McBSP1 is configured as slave for recording.
Below is configuration for McBSP1:
.spcr2 = FREE | XINTM(3),
.spcr1 = RINTM(3),
.rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
.rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
.xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
.xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
.srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
.srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/* configure McBSP to be the I2S master */
.pcr0 = FSXM | FSRM | CLKXM | CLKRM | CLKXP | CLKRP,
Daughter card is configured for 16bit word, 8000KHz and 256bits per
sample.
AIC33 uses McBSP2 while my audio daughter card uses McBSP1. Also, the
default bits per sample for AIC33 is 16, I've changed it to 256.
But I don't get any interrupt for recording.
Please can anyone help to sort out the problem.
Thanks,
Azam.
___
Davinci-linux-open-source mailing list
Davinci-linux-open-source@linux.davincidsp.com
http://linux.davincidsp.com/mailman/listinfo/davinci-linux-open-source
--
Happiness keeps u Sweet
Re: DM355 daughter sound card problem
Hi,
I missed to say about one more setting that I am using
#define MCBSP_DXR 0x01E02004
#define MCBSP_DRR 0x01E02000
2009/3/4 Azam Ansari aazamans...@gmail.com
Hi,
I am sorry I didn't say this before. I am already using the setting
suggested by you.
Below is the detailed setting that I am using for configuring MCBSP0:
#define MCLK 27
#define DAVINCI_DMA_MCBSP_TX 2
#define DAVINCI_DMA_MCBSP_RX 3
#define DEFAULT_BITPERSAMPLE 256
#define AUDIO_RATE_DEFAULT8000
output_stream.dma_dev = DAVINCI_DMA_MCBSP_TX
input_stream.dma_dev = DAVINCI_DMA_MCBSP_RX
/* MCBSP register settings for I2S */
spcr2 = FREE | XINTM(3),
spcr1 = RINTM(3),
rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/* configure McBSP to be the I2S slave */
pcr0 = CLKXP | CLKRP,
/* MCBSP0 information */
struct davinci_mcbsp_info mcbsp_davinci = {
.virt_base = IO_ADDRESS(DAVINCI_MCBSP0_BASE),
.dma_rx_sync = DM355_DMA_MCBSP0_RX,
.dma_tx_sync = DM355_DMA_MCBSP0_TX,
.rx_irq = IRQ_MBRINT,
.tx_irq = IRQ_MBXINT
},
Is there any thing else that I will have to do?
Please help...
2009/3/3 liuy...@covond.com
Hi，
I know your means.
Following codes are used for configuaring MCBSP0 on my board:
input_stream.dma_dev = DM355_DMA_MCBSP0_RX;
output_stream.dma_dev = DM355_DMA_MCBSP0_TX;
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E02000:0x01E04000)
Hi,
I am using MCBSP0 for I2S data transfer. The daughter sound is connected
to
MCBSP0 through DC3. Also for recoding the daughter card works in Master
mode. The default code is already configured for using MCBSP1.
Configuration
suggested by you are used for configuring MCBSP1 and not MCBSP0. I am
using
MCBSP0 for I2S.
On Tue, Mar 3, 2009 at 3:04 PM, liuy...@covond.com wrote:
Step 1: modify the following code with McBSP1 DMA params (
DM355_DMA_MCBSP0_RX, DM355_DMA_MCBSP1_TX)in file davinci-audio-aic33.c.
input_stream.dma_dev = DM355_DMA_MCBSP1_RX;
output_stream.dma_dev = DM355_DMA_MCBSP1_TX;
Step 2 : modefy the following code in file davinci-audio-dma-intfc.c
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E04004 :
0x01E02004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E04000 :
0x01E02000)
like this
#define MCBSP_DXR (cpu_is_davinci_dm355() ?
0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ?
0x01E02000:0x01E04000)
I do it so , GOOD LUCK!
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* Davinci-linux-open-source@linux.davincidsp.com ;
liuy...@covond.com
*Sent:* Tuesday, March 03, 2009 4:53 PM
*Subject:* Re: DM355 daughter sound card problem
Please can you provide some more details
Which clock to configure?
How to configure the clock?
2009/3/3 Kapil Pendse kapil.pen...@gmail.com
Hi All,
I am developing driver for daughter sound card on DM355 by modifying
the
AIC33 driver.
I2C is working fine and the ioctl's are working fine but recording is
not
working.
There are 2 McBSP bus (McBSP1 and McBSP2) used for DMA transfer out of
which McBSP1 is used for the sound daughter card.
Audio format is I2S.
Following is the configuration that I tried:
#define DEFAULT_BITPERSAMPLE 256
#define AUDIO_RATE_DEFAULT 8000
#defineAUDIO_MCBSP DAVINCI_MCBSP1
McBSP1 is configured as slave for recording.
Below is configuration for McBSP1:
.spcr2 = FREE | XINTM(3),
.spcr1 = RINTM(3),
.rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
.rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
.xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
.xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
.srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
.srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/* configure McBSP to be the I2S master */
.pcr0 = FSXM | FSRM | CLKXM | CLKRM | CLKXP | CLKRP,
Daughter card is configured for 16bit word, 8000KHz and 256bits per
sample.
AIC33 uses McBSP2 while my audio daughter card uses McBSP1. Also, the
default bits per sample for AIC33 is 16, I've changed it to 256.
But I don't get any interrupt for recording.
Please can anyone help to sort out the problem.
Thanks,
Azam
Re: DM355 daughter sound card problem
DM355 is slave. below is configuration done for pcr0 and srgr2:
pcr0 = CLKXP | CLKRP
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1)
2009/3/4 liuy...@covond.com
Hi,
Does DM355 is the master ?
You should to do some settings for srgr2 and pcr0 because MCBSP0 has no
CLKS PIN.
SCLKME CLKSM Input Clock For Sample Rate Generator
0 0 Signal on CLKS pin
0 1 ASP internal input clock
1 0 Signal on CLKR pin
1 1 Signal on CLKX pin
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* liuy...@covond.com ; Davinci-linux-open-source@linux.davincidsp.com
*Sent:* Wednesday, March 04, 2009 1:22 PM
*Subject:* Re: DM355 daughter sound card problem
Hi,
I am sorry I didn't say this before. I am already using the setting
suggested by you.
Below is the detailed setting that I am using for configuring MCBSP0:
#define MCLK 27
#define DAVINCI_DMA_MCBSP_TX 2
#define DAVINCI_DMA_MCBSP_RX 3
#define DEFAULT_BITPERSAMPLE 256
#define AUDIO_RATE_DEFAULT8000
output_stream.dma_dev = DAVINCI_DMA_MCBSP_TX
input_stream.dma_dev = DAVINCI_DMA_MCBSP_RX
/* MCBSP register settings for I2S */
spcr2 = FREE | XINTM(3),
spcr1 = RINTM(3),
rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1),
srgr2 = FSGM | FPER(DEFAULT_BITPERSAMPLE * 2 - 1),
/* configure McBSP to be the I2S slave */
pcr0 = CLKXP | CLKRP,
/* MCBSP0 information */
struct davinci_mcbsp_info mcbsp_davinci = {
.virt_base = IO_ADDRESS(DAVINCI_MCBSP0_BASE),
.dma_rx_sync = DM355_DMA_MCBSP0_RX,
.dma_tx_sync = DM355_DMA_MCBSP0_TX,
.rx_irq = IRQ_MBRINT,
.tx_irq = IRQ_MBXINT
},
Is there any thing else that I will have to do?
Please help...
2009/3/3 liuy...@covond.com
Hi，
I know your means.
Following codes are used for configuaring MCBSP0 on my board:
input_stream.dma_dev = DM355_DMA_MCBSP0_RX;
output_stream.dma_dev = DM355_DMA_MCBSP0_TX;
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E02000:0x01E04000)
Hi,
I am using MCBSP0 for I2S data transfer. The daughter sound is connected
to
MCBSP0 through DC3. Also for recoding the daughter card works in Master
mode. The default code is already configured for using MCBSP1.
Configuration
suggested by you are used for configuring MCBSP1 and not MCBSP0. I am
using
MCBSP0 for I2S.
On Tue, Mar 3, 2009 at 3:04 PM, liuy...@covond.com wrote:
Step 1: modify the following code with McBSP1 DMA params (
DM355_DMA_MCBSP0_RX, DM355_DMA_MCBSP1_TX)in file davinci-audio-aic33.c.
input_stream.dma_dev = DM355_DMA_MCBSP1_RX;
output_stream.dma_dev = DM355_DMA_MCBSP1_TX;
Step 2 : modefy the following code in file davinci-audio-dma-intfc.c
#define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E04004 :
0x01E02004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E04000 :
0x01E02000)
like this
#define MCBSP_DXR (cpu_is_davinci_dm355() ?
0x01E02004:0x01E04004)
#define MCBSP_DRR (cpu_is_davinci_dm355() ?
0x01E02000:0x01E04000)
I do it so , GOOD LUCK!
- Original Message -
*From:* Azam Ansari aazamans...@gmail.com
*To:* Davinci-linux-open-source@linux.davincidsp.com ;
liuy...@covond.com
*Sent:* Tuesday, March 03, 2009 4:53 PM
*Subject:* Re: DM355 daughter sound card problem
Please can you provide some more details
Which clock to configure?
How to configure the clock?
2009/3/3 Kapil Pendse kapil.pen...@gmail.com
Hi All,
I am developing driver for daughter sound card on DM355 by modifying
the
AIC33 driver.
I2C is working fine and the ioctl's are working fine but recording is
not
working.
There are 2 McBSP bus (McBSP1 and McBSP2) used for DMA transfer out of
which McBSP1 is used for the sound daughter card.
Audio format is I2S.
Following is the configuration that I tried:
#define DEFAULT_BITPERSAMPLE 256
#define AUDIO_RATE_DEFAULT 8000
#defineAUDIO_MCBSP DAVINCI_MCBSP1
McBSP1 is configured as slave for recording.
Below is configuration for McBSP1:
.spcr2 = FREE | XINTM(3),
.spcr1 = RINTM(3),
.rcr2 = RWDLEN2(DAVINCI_MCBSP_WORD_16) | RDATDLY(1),
.rcr1 = RFRLEN1(1) | RWDLEN1(DAVINCI_MCBSP_WORD_16),
.xcr2 = XWDLEN2(DAVINCI_MCBSP_WORD_16) | XDATDLY(1) | XFIG,
.xcr1 = XFRLEN1(1) | XWDLEN1(DAVINCI_MCBSP_WORD_16),
.srgr1 = FWID(DEFAULT_BITPERSAMPLE - 1
