This is the code for my 24bit RGB SVGA driver, as I haven't yet been able to
see it yet I can't guarantee that it works but everything looks ok on the scope
(~40MHz clock, ~37.8kHz Hsync, ~60Hz Vsync). Hope it's useful for someone, let
me know if it works :P
Euan
void vpbe_davincifb_svga_prgb_config(void)
{
volatile unsigned int venc, lcdout;
venc = dispc_reg_in(VENC_VMOD) VENC_VMOD_VENC;
lcdout = dispc_reg_in(VENC_LCDOUT);
vpbe_set_display_default();
/* Clear component and composite mode registers
(applicable to Analog DACS) */
dispc_reg_out(VENC_CVBS, 0);
dispc_reg_out(VENC_CMPNT, 0);
/* Set PINMUX0 - RGB888 Enable */
dispc_reg_merge(PINMUX0, 1 PINMUX0_RGB888_SHIFT,
PINMUX0_RGB888);
dispc_reg_merge(PINMUX0, 1 PINMUX0_LOEEN_SHIFT,
PINMUX0_LOEEN);
/* dispc_reg_out(PINMUX1, 0x0); */
/* Set Base Pixel X and Base Pixel Y */
dispc_reg_out(OSD_BASEPX, dm-videomode.basepx);//0xC8);
dispc_reg_out(OSD_BASEPY, dm-videomode.basepy);//0x18);
/* Set VIDCTL to select VCLKE = 1,
VCLKZ =1, SYDIR = 0 (set o/p), DOMD = 0 */
dispc_reg_merge(VENC_VIDCTL, 1 VENC_VIDCTL_VCLKE_SHIFT,
VENC_VIDCTL_VCLKE);
dispc_reg_merge(VENC_VIDCTL, 0 VENC_VIDCTL_VCLKZ_SHIFT,
VENC_VIDCTL_VCLKZ);
dispc_reg_merge(VENC_VIDCTL, 0 VENC_VIDCTL_SYDIR_SHIFT,
VENC_VIDCTL_SYDIR);
dispc_reg_merge(VENC_VIDCTL, 0 VENC_VIDCTL_YCDIR_SHIFT,
VENC_VIDCTL_YCDIR);
dispc_reg_merge(VENC_DCLKCTL,
1 VENC_DCLKCTL_DCKEC_SHIFT,
VENC_DCLKCTL_DCKEC);
dispc_reg_out(VENC_DCLKPTN0, 0x1);
//vpbe_set_display_timing(dm-videomode);
//***
dispc_reg_out(VENC_HSPLS, 0x80);// 128
dispc_reg_out(VENC_HSTART, 0x3C);// 60
dispc_reg_out(VENC_HVALID, 0x320);// 800
dispc_reg_out(VENC_HINT, 0x418);// 1048
dispc_reg_out(VENC_VSPLS, 0x4);// 4
dispc_reg_out(VENC_VSTART, 0xD);// 13
dispc_reg_out(VENC_VVALID, 0x258);// 600
dispc_reg_out(VENC_VINT, 0x276);// 630
//***
dispc_reg_out(VENC_SYNCCTL,
(VENC_SYNCCTL_SYEV |
VENC_SYNCCTL_SYEH | VENC_SYNCCTL_HPL
| VENC_SYNCCTL_VPL));
/* Set OSD clock and OSD Sync Adavance registers */
dispc_reg_out(VENC_OSDCLK0, 0);
dispc_reg_out(VENC_OSDCLK1, 1);
/* set VPSS clock */
dispc_reg_out(VPSS_CLKCTL, 0x09);
/* set PLL2 DIV1 to generate ~40MHz clock */
dispc_reg_out(VPSS_PLL2M, 0x0015); //multiply by 22
dispc_reg_out(VPSS_PLL2DIV1, 0x000E);//divde by 15
dispc_reg_out(VPSS_PLL2DIV1, 0x800E);//(27*22)/15=39.6 ~=40
/* Configure VMOD. No change in VENC bit */
dispc_reg_out(VENC_VMOD, 0x2010 | venc);
dispc_reg_out(VENC_LCDOUT, lcdout);
/* Change window parameters for progressive display */
change_win_param(FB_VMODE_NONINTERLACED);
}
-Original Message-
From: Albert Burbea [mailto:[EMAIL PROTECTED]
Sent: 14 December 2007 12:59
To: Cochrane, Euan
Subject: Re: DC5 output level?
Hi Euan,
it would be very nice of you if you could publish your final source code for
the VGA driver here
Thanks in advance
Albert
On 12/14/07, Cochrane, Euan [EMAIL PROTECTED] mailto:[EMAIL PROTECTED]
wrote:
Well, surprise surprise it didn't work! everything looks fine on the scope but
it seems that the signal level is too low to be picked up properly by our frame
grabber. Hopefully this will be the last time I need to ask for help. Is there
any way to increase the output level of the signals on DC5? currently they have
an amplitude of only ~1.7v. I looked through the registers for the VPBE and the
closest I could find to what I'm looking for was YCOLVL (Yout and Cout Level),
originally it was set to 0x00 so I tried setting it to 0xFF (it's maximum value
for both Yout and Cout) but there was no change in the output. does anyone know
if/how I can increase the output level of DC5? I am outputting 24bit RGB along
with the pixel clock, hsync, vsync and lcd_oe all of which have an output level
of ~1.7v.
Thanks,
Euan
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Tel/Fax + 972-3-7526016
Mobile: +972-52-3541842
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