Ignore this!
Completely a lame mistake by me! My script that compiles the kernel runs
a make clean, which applies montavista patches, hence overwrites my
code!! Only discovered it after losing all my changes!
When it doubt, its something simple!
Andrew
Andrew Armstrong wrote:
Guys, Amol,
Did you ever get this working with the RTC Kernel driver? I can access
my non-evm clock fine via my own interface, but I have not managed to
get the davinci-rtc.c to talk properly with my device, which is strange
as I have just copied over working code!
Looking on my scope it seems that the I2C waveforms produced via
davinci-rtc.c I2C calls are not right at all.
This is a really strange one? Should I be looking at scrapping the
Davinci RTC code and writing a module from scratch? It seems a little
long winded but I am running out of ideas!
Regards,
Andrew
On Sat, 2007-01-20 at 22:18 -0800, Amol Lad wrote:
I'm connecting external RTC (ISl1208) to Davinci on I2C. It's slave address as
per device spec is 0xDE. BUT in davinci the device is responding at address 0x6F
In my all other platforms the device responds at 0xDE.
I use davinci_i2c_read/davinci_i2c_write APIs ? One more point. 0x6F 1 ==
0xDE
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Today's Topics:
1. Re: Can the ARM and DSP accessing the RAM simulatenously?
(Andy Ngo)
--
Message: 1
Date: Thu, 18 Jan 2007 02:16:21 -0800 (PST)
From: Andy Ngo [EMAIL PROTECTED]
Subject: Re: Can the ARM and DSP accessing the RAM simulatenously?
To: Griffis, Brad [EMAIL PROTECTED], [EMAIL PROTECTED],
davinci-linux-open-source@linux.davincidsp.com
Message-ID: [EMAIL PROTECTED]
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Brad / Brandon,
Thanks for your responses. So basically, what you are saying is that in the
current DVEVM DDR memory mapping (the one shown
below) which the codec examples are using, if no cache is being used, the
application on the ARM (as well as any other application / system
process in the Linux kernel that runs in DDR RAM) never runs at the same time (in parallel) as the code server (DSP/BIOS) task on
the DSP side, since they both access the same DDR device. Is that correct? It's almost as though it's a single processor system. So,
assuming we keep the same single DDR device memory mapping, the only way to fix
this contention to allow both sides to run in parallel
most of the time is via using cache (assuming we get cache hits most of the
time). Where I can fix examples/documents on setting up
the cache for the DaVinci and how to split them between the ARM and DSP? I
guess for the CE server, it's specified in the *.cfg and
*.tcf files, is that correct?
Regards,
Andy
- Original Message
From: Griffis, Brad [EMAIL PROTECTED]
To: Andy Ngo [EMAIL PROTECTED]; davinci-linux-open-source@linux.davincidsp.com
Sent: Wednesday, January 17, 2007 6:12:07 PM
Subject: RE: Can the ARM and DSP accessing the RAM simulatenously?
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Andy,
Perhaps the following info will help you
in deciding whether to add a second RAM device.
Keep in mind that both the ARM and DSP have
cache. The cache greatly reduces the number of DDR2 accesses which also
reduces the number of conflicts. Also, the switched central resource has
software configurable priorities for the masters such that you can control who
you
want to have access to the DDR2 in the case of a conflict. This is further
documented in “Table 3-12. DM6446 Default Bus
