Bug#773205: libatomic-ops-dev: FTBFS on mips64el

2016-11-03 Thread Tobias Hansen 
Hi Ian,

the response on the upstream bug report looks like it could take a while
with the new release. With regard to the upcoming freeze, could you
please apply the patches so that the package can migrate to testing?

Best,
Tobias

On Tue, 1 Nov 2016 11:23:19 +1100 Ian Wienand  wrote:
> I'm sorry about this. I must have misread the history of that branch
> 
> My preference is to be in sync with upstream, so I have asked if we
> can get this in a 7.4.5 release [1]
> 
> If no response, or not possible, I'll add these back in
> 
> Thanks,
> 
> -i
> 
> [1] https://github.com/ivmai/libatomic_ops/issues/20
> 
> On Fri, Oct 28, 2016 at 8:31 PM, James Cowgill  wrote:
> > Control: found -1 7.4.4-1
> > Control: severity -1 serious
> >
> > Hi,
> >
> > In 7.4.4-1 the patches adding mips64el support were removed from the
> > package. While they've applied upstream in the 'master' branch not all
> > of them were applied to the 'release-7_4' branch and libatomic-ops FTBFS
> > on mips64el again.
> >
> > These have been applied to 7.4.4-1 (which is good):
> >  0002-Remove-inclusion-of-acquire_release_volatile.h-on-mi.patch
> >  0003-Minor-fix-of-code-alignment-in-mips-AO_compare_and_s.patch
> >
> > Please reapply these patches from 7.4.2-3:
> >  0001-Use-LLD-and-SCD-instructions-on-mips64.patch
> >  0004-Support-n32-ABI-for-mips64.patch
> >
> > Thanks,
> > James
> >
> 
>

Bug#773205: libatomic-ops-dev: FTBFS on mips64el

2016-10-31 Thread Ian Wienand 
I'm sorry about this. I must have misread the history of that branch

My preference is to be in sync with upstream, so I have asked if we
can get this in a 7.4.5 release [1]

If no response, or not possible, I'll add these back in

Thanks,

-i

[1] https://github.com/ivmai/libatomic_ops/issues/20

On Fri, Oct 28, 2016 at 8:31 PM, James Cowgill  wrote:
> Control: found -1 7.4.4-1
> Control: severity -1 serious
>
> Hi,
>
> In 7.4.4-1 the patches adding mips64el support were removed from the
> package. While they've applied upstream in the 'master' branch not all
> of them were applied to the 'release-7_4' branch and libatomic-ops FTBFS
> on mips64el again.
>
> These have been applied to 7.4.4-1 (which is good):
>  0002-Remove-inclusion-of-acquire_release_volatile.h-on-mi.patch
>  0003-Minor-fix-of-code-alignment-in-mips-AO_compare_and_s.patch
>
> Please reapply these patches from 7.4.2-3:
>  0001-Use-LLD-and-SCD-instructions-on-mips64.patch
>  0004-Support-n32-ABI-for-mips64.patch
>
> Thanks,
> James
>

Bug#773205: libatomic-ops-dev: FTBFS on mips64el

2016-10-28 Thread James Cowgill 
Control: found -1 7.4.4-1
Control: severity -1 serious

Hi,

In 7.4.4-1 the patches adding mips64el support were removed from the
package. While they've applied upstream in the 'master' branch not all
of them were applied to the 'release-7_4' branch and libatomic-ops FTBFS
on mips64el again.

These have been applied to 7.4.4-1 (which is good):
 0002-Remove-inclusion-of-acquire_release_volatile.h-on-mi.patch
 0003-Minor-fix-of-code-alignment-in-mips-AO_compare_and_s.patch

Please reapply these patches from 7.4.2-3:
 0001-Use-LLD-and-SCD-instructions-on-mips64.patch
 0004-Support-n32-ABI-for-mips64.patch

Thanks,
James



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Bug#773205: libatomic-ops-dev: FTBFS on mips64el

2015-04-27 Thread James Cowgill 
Hi,

Now that jessie's been released, please can you update libatomic-ops to
a version with the mips64el patches in. This is needed to build make
(through guile-2.0 - libgc - libatomic-ops) and thus is quite
important for the port.

Merged pull request:
https://github.com/ivmai/libatomic_ops/pull/12

Thanks,
James


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Bug#773205: libatomic-ops-dev: FTBFS on mips64el

2015-01-08 Thread James Cowgill 
Control: clone -1 -2 -3
Control: reassign -2 libgc 1:7.2d-6.4
Control: retitle -2 libgc: update libatomic-ops for mips64el
Control: reassign -3 gauche 0.9.4-5
Control: retitle -3 gauche: update libatomic-ops for mips64el
Control: block -2 by -1
Control: block -3 by -1
Control: forwarded -1 https://github.com/ivmai/libatomic_ops/pull/12/files

Hi,

I've forwarded the patch upstream. I've also cloned this bug to the
other packages shipping libatomic-ops so that they don't forget to
update - although they probably shouldn't until upstream / this package
has.

Thanks,
James


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Bug#773205: libatomic-ops-dev: FTBFS on mips64el

2014-12-16 Thread James Cowgill 
Hi,

There was a small mistake in the previous patch so here's a new one.

The only change is to remove the include of
'../loadstore/acquire_release_volatile.h' because in most mips64
processors, use of volatile variables does not have acquire/release
semantics. I also don't think that this is an absolute requirement of
any mips processor (according to the ISA manuals I've found), so I've
removed it for both mips32 and mips64 just to be safe.

Thanks,
James
From 9a876e1fbc85d84ffce52a27f628484d4e7b64d2 Mon Sep 17 00:00:00 2001
From: James Cowgill james...@cowgill.org.uk
Date: Tue, 16 Dec 2014 11:42:26 +
Subject: [PATCH] Use LLD / SCD instructions on mips64

---
 src/atomic_ops/sysdeps/gcc/mips.h | 56 +--
 1 file changed, 30 insertions(+), 26 deletions(-)

diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h
index a891de6..f3796ea 100644
--- a/src/atomic_ops/sysdeps/gcc/mips.h
+++ b/src/atomic_ops/sysdeps/gcc/mips.h
@@ -15,26 +15,33 @@
  * FIXME:  This should probably make finer distinctions.  SGI MIPS is
  * much more strongly ordered, and in fact closer to sequentially
  * consistent.  This is really aimed at modern embedded implementations.
- * It looks to me like this assumes a 32-bit ABI.  -HB
  */
 
 #include ../all_aligned_atomic_load_store.h
 
-#include ../loadstore/acquire_release_volatile.h
-
 #include ../test_and_set_t_is_ao_t.h
 
 /* Data dependence does not imply read ordering.  */
 #define AO_NO_DD_ORDERING
 
+#ifdef __mips64
+# define AO_MIPS_SET_ISA   .set mips3\n
+# define AO_MIPS_LL_1(args)lld  args \n
+# define AO_MIPS_SC(args)  scd  args \n
+#else
+# define AO_MIPS_SET_ISA   .set mips2\n
+# define AO_MIPS_LL_1(args)ll  args \n
+# define AO_MIPS_SC(args)  sc  args \n
+# define AO_T_IS_INT
+#endif
+
 #ifdef AO_ICE9A1_LLSC_WAR
   /* ICE9 rev A1 chip (used in very few systems) is reported to */
   /* have a low-frequency bug that causes LL to fail.   */
   /* To workaround, just issue the second 'LL'. */
-# define AO_MIPS_LL_FIX(args_str) \
- llargs_str \n
+# define AO_MIPS_LL(args) AO_MIPS_LL_1(args) AO_MIPS_LL_1(args)
 #else
-# define AO_MIPS_LL_FIX(args_str) 
+# define AO_MIPS_LL(args) AO_MIPS_LL_1(args)
 #endif
 
 AO_INLINE void
@@ -42,7 +49,7 @@ AO_nop_full(void)
 {
   __asm__ __volatile__(
  .set push   \n
- .set mips2  \n
+  AO_MIPS_SET_ISA
  .set noreorder  \n
  .set nomacro\n
  sync\n
@@ -60,13 +67,13 @@ AO_fetch_and_add(volatile AO_t *addr, AO_t incr)
 
   __asm__ __volatile__(
  .set push\n
- .set mips2\n
+  AO_MIPS_SET_ISA
  .set noreorder\n
  .set nomacro\n
-  1: ll   %0, %2\n
-  AO_MIPS_LL_FIX(%0, %2)
+  1: 
+  AO_MIPS_LL(%0, %2)
  addu %1, %0, %3\n
- sc   %1, %2\n
+  AO_MIPS_SC(%1, %2)
  beqz %1, 1b\n
  nop\n
  .set pop 
@@ -85,13 +92,13 @@ AO_test_and_set(volatile AO_TS_t *addr)
 
   __asm__ __volatile__(
  .set push\n
- .set mips2\n
+  AO_MIPS_SET_ISA
  .set noreorder\n
  .set nomacro\n
-  1: ll   %0, %2\n
-  AO_MIPS_LL_FIX(%0, %2)
+  1: 
+  AO_MIPS_LL(%0, %2)
  move %1, %3\n
- sc   %1, %2\n
+  AO_MIPS_SC(%1, %2)
  beqz %1, 1b\n
  nop\n
  .set pop 
@@ -114,14 +121,14 @@ AO_test_and_set(volatile AO_TS_t *addr)
 
 __asm__ __volatile__(
.set push   \n
-   .set mips2  \n
+AO_MIPS_SET_ISA
.set noreorder  \n
.set nomacro\n
-1: ll  %0, %1  \n
-AO_MIPS_LL_FIX(%0, %1)
+1: 
+AO_MIPS_LL(%0, %1)
bne %0, %4, 2f  \n
 move   %0, %3  \n
-   sc  %0, %1  \n
+AO_MIPS_SC(%0, %1)
.set pop\n
beqz%0, 1b  \n
li  %2, 1   \n
@@ -142,14 +149,14 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
 
   __asm__ __volatile__(
  .set push\n
- .set mips2\n
+  AO_MIPS_SET_ISA
  .set noreorder\n
  .set nomacro\n
-  1: ll   %0, %2\n
-  AO_MIPS_LL_FIX(%0, %2)
+  1: 
+  AO_MIPS_LL(%0, %2)
  bne  %0, %4, 2f\n
  move %1, %3\n
- sc   %1, %2\n
+  AO_MIPS_SC(%1, %2)
  beqz %1, 1b\n
  nop\n
  .set pop\n
@@ -167,6 +174,3 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
 /* CAS primitives with acquire, release and full semantics are  */
 /* generated automatically (and AO_int_... primitives are   */
 /* defined

Bug#773205: libatomic-ops-dev: FTBFS on mips64el

2014-12-15 Thread James Cowgill 
Package: libatomic-ops-dev
Version: 7.4.2-1
Severity: important
Tags: upstream patch

Hi,

libatomic-ops FTBFS on mips64el due to the testsuite hanging. The code
in the mips specific header assumes that sizeof(AO_t) == 4, which isn't
the case on mips64el which is 64-bits.

I've attached a patch to fix this. Instead of using the 32-bit LL and SC
instructions, it uses the 64-bit LLD and SCD instructions when compiled
on mips64.

Thanks,
James

From 80e8ad2494db151fa35843a2908ff7f11d278ce0 Mon Sep 17 00:00:00 2001
From: James Cowgill james...@cowgill.org.uk
Date: Mon, 15 Dec 2014 14:42:15 +
Subject: [PATCH] Use LLD / SCD instructions on mips64

---
 src/atomic_ops/sysdeps/gcc/mips.h | 54 ++-
 1 file changed, 30 insertions(+), 24 deletions(-)

diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h
index a891de6..83a6bd3 100644
--- a/src/atomic_ops/sysdeps/gcc/mips.h
+++ b/src/atomic_ops/sysdeps/gcc/mips.h
@@ -15,7 +15,6 @@
  * FIXME:  This should probably make finer distinctions.  SGI MIPS is
  * much more strongly ordered, and in fact closer to sequentially
  * consistent.  This is really aimed at modern embedded implementations.
- * It looks to me like this assumes a 32-bit ABI.  -HB
  */
 
 #include ../all_aligned_atomic_load_store.h
@@ -27,14 +26,24 @@
 /* Data dependence does not imply read ordering.  */
 #define AO_NO_DD_ORDERING
 
+#ifdef __mips64
+# define AO_MIPS_SET_ISA   .set mips3\n
+# define AO_MIPS_LL_1(args)lld  args \n
+# define AO_MIPS_SC(args)  scd  args \n
+#else
+# define AO_MIPS_SET_ISA   .set mips2\n
+# define AO_MIPS_LL_1(args)ll  args \n
+# define AO_MIPS_SC(args)  sc  args \n
+# define AO_T_IS_INT
+#endif
+
 #ifdef AO_ICE9A1_LLSC_WAR
   /* ICE9 rev A1 chip (used in very few systems) is reported to */
   /* have a low-frequency bug that causes LL to fail.   */
   /* To workaround, just issue the second 'LL'. */
-# define AO_MIPS_LL_FIX(args_str) \
- llargs_str \n
+# define AO_MIPS_LL(args) AO_MIPS_LL_1(args) AO_MIPS_LL_1(args)
 #else
-# define AO_MIPS_LL_FIX(args_str) 
+# define AO_MIPS_LL(args) AO_MIPS_LL_1(args)
 #endif
 
 AO_INLINE void
@@ -42,7 +51,7 @@ AO_nop_full(void)
 {
   __asm__ __volatile__(
  .set push   \n
- .set mips2  \n
+  AO_MIPS_SET_ISA
  .set noreorder  \n
  .set nomacro\n
  sync\n
@@ -60,13 +69,13 @@ AO_fetch_and_add(volatile AO_t *addr, AO_t incr)
 
   __asm__ __volatile__(
  .set push\n
- .set mips2\n
+  AO_MIPS_SET_ISA
  .set noreorder\n
  .set nomacro\n
-  1: ll   %0, %2\n
-  AO_MIPS_LL_FIX(%0, %2)
+  1: 
+  AO_MIPS_LL(%0, %2)
  addu %1, %0, %3\n
- sc   %1, %2\n
+  AO_MIPS_SC(%1, %2)
  beqz %1, 1b\n
  nop\n
  .set pop 
@@ -85,13 +94,13 @@ AO_test_and_set(volatile AO_TS_t *addr)
 
   __asm__ __volatile__(
  .set push\n
- .set mips2\n
+  AO_MIPS_SET_ISA
  .set noreorder\n
  .set nomacro\n
-  1: ll   %0, %2\n
-  AO_MIPS_LL_FIX(%0, %2)
+  1: 
+  AO_MIPS_LL(%0, %2)
  move %1, %3\n
- sc   %1, %2\n
+  AO_MIPS_SC(%1, %2)
  beqz %1, 1b\n
  nop\n
  .set pop 
@@ -114,14 +123,14 @@ AO_test_and_set(volatile AO_TS_t *addr)
 
 __asm__ __volatile__(
.set push   \n
-   .set mips2  \n
+AO_MIPS_SET_ISA
.set noreorder  \n
.set nomacro\n
-1: ll  %0, %1  \n
-AO_MIPS_LL_FIX(%0, %1)
+1: 
+AO_MIPS_LL(%0, %1)
bne %0, %4, 2f  \n
 move   %0, %3  \n
-   sc  %0, %1  \n
+AO_MIPS_SC(%0, %1)
.set pop\n
beqz%0, 1b  \n
li  %2, 1   \n
@@ -142,14 +151,14 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
 
   __asm__ __volatile__(
  .set push\n
- .set mips2\n
+  AO_MIPS_SET_ISA
  .set noreorder\n
  .set nomacro\n
-  1: ll   %0, %2\n
-  AO_MIPS_LL_FIX(%0, %2)
+  1: 
+  AO_MIPS_LL(%0, %2)
  bne  %0, %4, 2f\n
  move %1, %3\n
- sc   %1, %2\n
+  AO_MIPS_SC(%1, %2)
  beqz %1, 1b\n
  nop\n
  .set pop\n
@@ -167,6 +176,3 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
 /* CAS primitives with acquire, release and full semantics are  */
 /* generated automatically (and AO_int_... primitives are   */
 /* defined properly after the first generalization pass).   */
-
-/* FIXME: 32-bit ABI is assumed.