On 12/17/18 04:25, John Paul Adrian Glaubitz wrote:
> Hi Thomas!
>
> On 12/17/18 8:27 AM, Thomas D Dial wrote:
>> I have found debian-10.0-sparc64-NETINST-1.iso (apparent date 5/18/18
>> and debian-9.0-sparc64-NETINST-1.iso (apparent date 4/4/18) at
>> cdimage.debian.org. Is there a later version of either?
>
> I'm working on a newer release, but I need to fix GRUB2 on sparc64 first
> which currently fails to build there due to a change in binutils.
Thanks to everyone who answered. The result of booting from the
installation CD_ROM of 20180516-10:56 is below. I generated the
diagnostic report because of reported CD-ROM failure on a prior attempt:
/pci@8,70/scsi@6
Target 6
Unit 0 Removable Read Only deviceTOSHIBA DVD-ROM SD-M14011007
{0} ok boot cdrom
Boot device: /pci@8,70/scsi@6/disk@6,0:f File and args:
Can't open boot device
This was not a problem except with a serial console, and did not recur
after I removed a D-Link DGE-530T gigabit ethernet card that had been
/pci@8,70: Device 2.
I apologize for the length, but don't know enough about the hardware or
Linux internals to be confident in excluding anything.
@(#)OBP 4.16.4 2004/12/18 05:18
Power-On Reset
Executing Power On SelfTest
0:0>
0:0>@(#) Sun Fire[TM] V280, Sun Blade[TM] 1000 POST 4.16.3 2004/11/05 20:02
/dat/fw/common-source/firmware_re/post/post-build-4.16.3/Camelot/excal/integrated
(firmware_re)
0:0>Copyright � 2004 Sun Microsystems, Inc. All rights reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
0:0>Jump from OBP->POST.
0:0>diag-switch? configuration variable set TRUE.
0:0>Diag level set to MIN.
0:0>MFG scrpt mode set to NONE
0:0>I/O port set to serial TTYA.
0:0>Done with First Init, reset system.
0:0>Current CPU frequency is 400 MHz.
0:0>Resetting to 900
0:0>Clock Synth Reset.
0:0>
0:0>Start selftest...
0:0>CPUs present in system: 0:0 1:0
0:0>Test CPU(s).
0:0>Init CPU
0:0>UltraSparc_III_base Version 5.11
0:0>DMMU Registers Access
0:0>DMMU TLB DATA RAM Access
0:0>DMMU TLB TAGS Access
0:0>IMMU Registers Access
0:0>IMMU TLB DATA RAM Access
0:0>IMMU TLB TAGS Access
0:0>Probe Ecache
0:0>Size = .0080...
0:0>Ecache Data Bitwalk
0:0>Ecache Address Bitwalk
0:0>Scrub and Setup Ecache
0:0>Setup and Enable DMMU
0:0>Setup DMMU Miss Handler
0:0>Test and Init Temp Mailbox
1:0>Init CPU
1:0>UltraSparc_III_base Version 5.11
1:0>DMMU Registers Access
1:0>DMMU TLB DATA RAM Access
1:0>DMMU TLB TAGS Access
1:0>IMMU Registers Access
1:0>IMMU TLB DATA RAM Access
1:0>IMMU TLB TAGS Access
1:0>Probe Ecache
1:0>Size = .0080...
1:0>Ecache Data Bitwalk
1:0>Ecache Address Bitwalk
1:0>Scrub and Setup Ecache
1:0>Setup and Enable DMMU
1:0>Setup DMMU Miss Handler
1:0>Test and Init Temp Mailbox
0:0>Init Scan/I2C.
0:0>Initializing Scan Database
0:0>BBC:1483203b
0:0>SCSI: 15060045
0:0>ICHIP: 0d1e203b
0:0>RIO:13e5d03b
0:0>IO-Bridge: 307be06d
0:0>CPMS0: 1142903b
0:0>CPMS1: 1142903b
0:0>CPMS2: 1142903b
0:0>CPMS3: 1142903b
0:0>CPMS4: 1142903b
0:0>CPMS5: 1142903b
0:0>Init I2C
0:0>Unquiesce Safari
0:0>Blast Fans
0:0>Set Trip Temp CPU 0 to 110C
0:0>Set Trip Temp CPU 1 to 110C
0:0>TUES DEC 18 3:44:00 GMT 18
0:0>Safari quick check
0:0> to IO-bridge_0
0:0>Safari full check
0:0> to IO-bridge_0
0:0>Basic Memory Test.
0:0>Probe and Setup Memory
0:0>INFO: 4096MB Bank 0
0:0>INFO: 4096MB Bank 1
0:0>INFO: 4096MB Bank 2
0:0>INFO: 4096MB Bank 3
0:0>
0:0>Data Bitwalk on Master
0:0>Test Bank 0.
0:0>Test Bank 1.
0:0>Test Bank 2.
0:0>Test Bank 3.
0:0>Address Bitwalk on Master
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 0: . to
0001..
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 1: 0001. to
0002..
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 2: 0002. to
0003..
0:0>
0:0>INFO: Addr walk mem test on CPU 0:0 Bank 3: 0003. to
0004..
0:0>Set Mailbox
0:0>Setup Final DMMU Entries
0:0>Post Image Region Scrub
0:0>Run POST from Memory
0:0>Verifying checksum on copied image.
0:0>The Memory's CHECKSUM value is c3b1.
0:0>The Memory's Content Size value is 9b29c.
0:0>Success... Checksum on Memory Validated.
1:0>Safari quick check
1:0> to IO-bridge_0
1:0>Safari full check
1:0> to IO-bridge_0
1:0>Probe and Setup Memory
1:0>INFO: No memory on cpu 1
1:0>Set Mailbox
1:0>Data Bitwalk on mem
1:0>Test Bank 0.
1:0>Test Bank 1.
1:0>Test Bank 2.
1:0>Test Bank 3.
1:0>Setup Final DMMU Entries
1:0>Map Slave POST to master memory
1:0>Print Mem Config
1:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is OFF.
0:0>Memory Block.
0:0>Print Mem Config
0:0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is OFF.
0:0>Memory in non-interleave config:
0:0>Bank 0 4096MB : .
