[dpdk-dev] [PATCH v5] examples/l2fwd-cat: PQoS CAT and CDP, example of libpqos usage
This patch implements PQoS as a sample application. PQoS allows management of the CPUs last level cache, which can be useful for DPDK to ensure quality of service. The sample app links against the existing 01.org PQoS library (https://github.com/01org/intel-cmt-cat). White paper demonstrating example use case "Increasing Platform Determinism with Platform Quality of Service for the Data Plane Development Kit" (http://www.intel.com/content/www/us/en/communications/increasing-platform-determinism-pqos-dpdk-white-paper.html) Signed-off-by: Wojciech Andralojc Signed-off-by: Tomasz Kantecki Signed-off-by: Marcel D Cornu --- Version 5: * Example app renamed to "l2fwd-cat" * Updated rst doc, added link to white paper Version 4: * PQOS_INSTALL_PATH must be defined to build example file * Updated example's Makefiles, MAINTAINERS and rst doc, Version 3: * Updated rst docs * Fixed checkpatch warnings * Updated comments in code Version 2: * Added signal handlers to do clean-up on SIGINT and SIGTERM * Clean-up function modified to zero globals (needed for testing) * Init function modified to return more applicable errnos Version 1: * Initial version Details of "--l3ca" app parameter to configure Intel CAT and CDP features: --l3ca=bitmask@ --l3ca=(code_bitmask,data_bitmask)@ makes selected CPU's use specified CAT bitmasks, bitmasks must be expressed in hexadecimal form CAT and CDP features allow management of the CPU's last level cache. CAT introduces classes of service (COS) that are essentially bitmasks. In current CAT implementations, a bit in a COS bitmask corresponds to one cache way in the last level cache. A CPU core is always assigned to one of the CAT classes. By programming CPU core assignment and COS bitmasks, applications can be given exclusive, shared, or mixed access to the CPU's last level cache. CDP extends CAT so that there are two bitmasks per COS, one for data and one for code. The number of classes and number of valid bits in a COS bitmask is CPU model specific and COS bitmasks need to be contiguous. Sample code calls this bitmask a cbm or a capacity bitmask. By default, after reset, all CPU cores are assigned to COS 0 and all classes are programmed to allow fill into all cache ways. CDP is off by default. For more information about CAT please see https://github.com/01org/intel-cmt-cat Known issues and limitations: - --l3ca must be a first app parameter --- MAINTAINERS | 4 + doc/guides/sample_app_ug/index.rst | 1 + doc/guides/sample_app_ug/l2_forward_cat.rst | 245 +++ examples/Makefile | 3 + examples/l2fwd-cat/Makefile | 70 ++ examples/l2fwd-cat/cat.c| 996 examples/l2fwd-cat/cat.h| 72 ++ examples/l2fwd-cat/l2fwd-cat.c | 224 +++ 8 files changed, 1615 insertions(+) create mode 100644 doc/guides/sample_app_ug/l2_forward_cat.rst create mode 100644 examples/l2fwd-cat/Makefile create mode 100644 examples/l2fwd-cat/cat.c create mode 100644 examples/l2fwd-cat/cat.h create mode 100644 examples/l2fwd-cat/l2fwd-cat.c diff --git a/MAINTAINERS b/MAINTAINERS index f10b26a..6d420f0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -624,3 +624,7 @@ F: doc/guides/sample_app_ug/vmdq_dcb_forwarding.rst M: Pablo de Lara M: Daniel Mrzyglod F: examples/ptpclient/ + +M: Tomasz Kantecki +F: doc/guides/sample_app_ug/l2_forward_cat.rst +F: examples/l2wd-cat/ diff --git a/doc/guides/sample_app_ug/index.rst b/doc/guides/sample_app_ug/index.rst index 88375d2..eea6a45 100644 --- a/doc/guides/sample_app_ug/index.rst +++ b/doc/guides/sample_app_ug/index.rst @@ -49,6 +49,7 @@ Sample Applications User Guide keep_alive l2_forward_job_stats l2_forward_real_virtual +l2_forward_cat l3_forward l3_forward_power_man l3_forward_access_ctrl diff --git a/doc/guides/sample_app_ug/l2_forward_cat.rst b/doc/guides/sample_app_ug/l2_forward_cat.rst new file mode 100644 index 000..b6ab54d --- /dev/null +++ b/doc/guides/sample_app_ug/l2_forward_cat.rst @@ -0,0 +1,245 @@ +.. BSD LICENSE +Copyright(c) 2016 Intel Corporation. All rights reserved. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +* Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in +the documentation and/or other materials provided with the +distribution. +* Neither the name of Intel Corporation nor the names of its +contributors may be used to endorse or promote products derived +from this software with
[dpdk-dev] [PATCH v4] examples/skeleton-cat: PQoS CAT and CDP, example of libpqos usage
This patch implements PQoS as an sample application. PQoS allows management of the CPUs last level cache, which can be useful for DPDK to ensure quality of service. The sample app links against the existing 01.org PQoS library (https://github.com/01org/intel-cmt-cat). Signed-off-by: Wojciech Andralojc Signed-off-by: Tomasz Kantecki Signed-off-by: Marcel D Cornu --- Version 4: * PQOS_INSTALL_PATH must be defined to build example * Updated example's Makefiles, MAINTAINERS and rst doc, Version 3: * Updated rst docs * Fixed checkpatch warnings * Updated comments in code Version 2: * Added signal handlers to do clean-up on SIGINT and SIGTERM * Clean-up function modified to zero globals (needed for testing) * Init function modified to return more applicable errnos Version 1: * Initial version Details of "--l3ca" app parameter to configure Intel CAT and CDP features: --l3ca=bitmask@ --l3ca=(code_bitmask,data_bitmask)@ makes selected CPU's use specified CAT bitmasks, bitmasks must be expressed in hexadecimal form CAT and CDP features allow management of the CPU's last level cache. CAT introduces classes of service (COS) that are essentially bitmasks. In current CAT implementations, a bit in a COS bitmask corresponds to one cache way in the last level cache. A CPU core is always assigned to one of the CAT classes. By programming CPU core assignment and COS bitmasks, applications can be given exclusive, shared, or mixed access to the CPU's last level cache. CDP extends CAT so that there are two bitmasks per COS, one for data and one for code. The number of classes and number of valid bits in a COS bitmask is CPU model specific and COS bitmasks need to be contiguous. Sample code calls this bitmask a cbm or a capacity bitmask. By default, after reset, all CPU cores are assigned to COS 0 and all classes are programmed to allow fill into all cache ways. CDP is off by default. For more information about CAT please see https://github.com/01org/intel-cmt-cat Known issues and limitations: - --l3ca must be a first app parameter --- MAINTAINERS | 4 + doc/guides/sample_app_ug/index.rst| 1 + doc/guides/sample_app_ug/skeleton-cat.rst | 240 +++ examples/Makefile | 3 + examples/skeleton-cat/Makefile| 70 +++ examples/skeleton-cat/basicfwd-cat.c | 224 +++ examples/skeleton-cat/cat.c | 996 ++ examples/skeleton-cat/cat.h | 72 +++ 8 files changed, 1610 insertions(+) create mode 100644 doc/guides/sample_app_ug/skeleton-cat.rst create mode 100644 examples/skeleton-cat/Makefile create mode 100644 examples/skeleton-cat/basicfwd-cat.c create mode 100644 examples/skeleton-cat/cat.c create mode 100644 examples/skeleton-cat/cat.h diff --git a/MAINTAINERS b/MAINTAINERS index f10b26a..6aba0bf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -624,3 +624,7 @@ F: doc/guides/sample_app_ug/vmdq_dcb_forwarding.rst M: Pablo de Lara M: Daniel Mrzyglod F: examples/ptpclient/ + +M: Tomasz Kantecki +F: doc/guides/sample_app_ug/skeleton-cat.rst +F: examples/skeleton-cat/ diff --git a/doc/guides/sample_app_ug/index.rst b/doc/guides/sample_app_ug/index.rst index 88375d2..01d01c8 100644 --- a/doc/guides/sample_app_ug/index.rst +++ b/doc/guides/sample_app_ug/index.rst @@ -41,6 +41,7 @@ Sample Applications User Guide exception_path hello_world skeleton +skeleton-cat rxtx_callbacks ip_frag ipv4_multicast diff --git a/doc/guides/sample_app_ug/skeleton-cat.rst b/doc/guides/sample_app_ug/skeleton-cat.rst new file mode 100644 index 000..ea63911 --- /dev/null +++ b/doc/guides/sample_app_ug/skeleton-cat.rst @@ -0,0 +1,240 @@ +.. BSD LICENSE +Copyright(c) 2016 Intel Corporation. All rights reserved. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +* Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in +the documentation and/or other materials provided with the +distribution. +* Neither the name of Intel Corporation nor the names of its +contributors may be used to endorse or promote products derived +from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +
[dpdk-dev] [PATCH v3] examples/skeleton-cat: PQoS CAT and CDP, example of libpqos usage
This patch implements PQoS as an sample application. PQoS allows management of the CPUs last level cache, which can be useful for DPDK to ensure quality of service. The sample app links against the existing 01.org PQoS library (https://github.com/01org/intel-cmt-cat). Signed-off-by: Wojciech Andralojc Signed-off-by: Tomasz Kantecki Signed-off-by: Marcel D Cornu --- Version 3: * Updated rst docs * Fixed checkpatch warnings * Updated comments in code Version 2: * Added signal handlers to do clean-up on SIGINT and SIGTERM * Clean-up function modified to zero globals (needed for testing) * Init function modified to return more applicable errnos Version 1: * Initial version Details of "--l3ca" app parameter to configure Intel CAT and CDP features: --l3ca=bitmask@ --l3ca=(code_bitmask,data_bitmask)@ makes selected CPU's use specified CAT bitmasks, bitmasks must be expressed in hexadecimal form CAT and CDP features allow management of the CPU's last level cache. CAT introduces classes of service (COS) that are essentially bitmasks. In current CAT implementations, a bit in a COS bitmask corresponds to one cache way in the last level cache. A CPU core is always assigned to one of the CAT classes. By programming CPU core assignment and COS bitmasks, applications can be given exclusive, shared, or mixed access to the CPU's last level cache. CDP extends CAT so that there are two bitmasks per COS, one for data and one for code. The number of classes and number of valid bits in a COS bitmask is CPU model specific and COS bitmasks need to be contiguous. Sample code calls this bitmask a cbm or a capacity bitmask. By default, after reset, all CPU cores are assigned to COS 0 and all classes are programmed to allow fill into all cache ways. CDP is off by default. For more information about CAT please see https://github.com/01org/intel-cmt-cat Known issues and limitations: - --l3ca must be a first app parameter --- MAINTAINERS | 4 + doc/guides/sample_app_ug/index.rst| 1 + doc/guides/sample_app_ug/skeleton-cat.rst | 241 examples/Makefile | 1 + examples/skeleton-cat/Makefile| 68 ++ examples/skeleton-cat/basicfwd-cat.c | 224 +++ examples/skeleton-cat/cat.c | 996 ++ examples/skeleton-cat/cat.h | 72 +++ 8 files changed, 1607 insertions(+) create mode 100644 doc/guides/sample_app_ug/skeleton-cat.rst create mode 100644 examples/skeleton-cat/Makefile create mode 100644 examples/skeleton-cat/basicfwd-cat.c create mode 100644 examples/skeleton-cat/cat.c create mode 100644 examples/skeleton-cat/cat.h diff --git a/MAINTAINERS b/MAINTAINERS index 628bc05..7a6702b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -600,3 +600,7 @@ F: doc/guides/sample_app_ug/vmdq_dcb_forwarding.rst M: Pablo de Lara M: Daniel Mrzyglod F: examples/ptpclient/ + +M: Tomasz Kantecki +F: examples/skeleton-cat/ +F: doc/guides/sample_app_ug/skeleton-cat.rst \ No newline at end of file diff --git a/doc/guides/sample_app_ug/index.rst b/doc/guides/sample_app_ug/index.rst index 8a646dd..f065e54 100644 --- a/doc/guides/sample_app_ug/index.rst +++ b/doc/guides/sample_app_ug/index.rst @@ -41,6 +41,7 @@ Sample Applications User Guide exception_path hello_world skeleton +skeleton-cat rxtx_callbacks ip_frag ipv4_multicast diff --git a/doc/guides/sample_app_ug/skeleton-cat.rst b/doc/guides/sample_app_ug/skeleton-cat.rst new file mode 100644 index 000..44c59f2 --- /dev/null +++ b/doc/guides/sample_app_ug/skeleton-cat.rst @@ -0,0 +1,241 @@ +.. BSD LICENSE +Copyright(c) 2016 Intel Corporation. All rights reserved. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +* Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in +the documentation and/or other materials provided with the +distribution. +* Neither the name of Intel Corporation nor the names of its +contributors may be used to endorse or promote products derived +from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SU
[dpdk-dev] [PATCH v2] examples/skeleton-cat: PQoS CAT and CDP, example of libpqos usage
Because of the feedback that we have received off the mailing list, that extending EAL commands is not an option due to the Intel Architecture nature of CAT, we have changed the design of PQoS patch. The current V2 patch implements a sample code, based on the DPDK skeleton example app, that links against the existing 01.org PQoS library (https://github.com/01org/intel-cmt-cat). This eliminates the need for librte_pqos and EAL extensions introduced in the V1 patch. The sample code implements a C module that parses the application specific part of the command line with CAT configuration options (--l3ca, same format as the V1 patch EAL command, but expects CPU ids rather than lcores). The module is easy to re-use in other applications as needed. Signed-off-by: Wojciech Andralojc Signed-off-by: Tomasz Kantecki Signed-off-by: Marcel D Cornu --- Version 2: * Added signal handlers to do clean-up on SIGINT and SIGTERM * Clean-up function modified to zero globals (needed for testing) * Init function modified to return more applicable errnos Version 1: * Initial version Details of "--l3ca" app parameter to configure Intel CAT and CDP features: --l3ca=bitmask@ --l3ca=(code_bitmask,data_bitmask)@ makes selected CPU's use specified CAT bitmasks, bitmasks must be expressed in hexadecimal form CAT and CDP features allow management of the CPU's last level cache. CAT introduces classes of service (COS) that are essentially bitmasks. In current CAT implementations, a bit in a COS bitmask corresponds to one cache way in the last level cache. A CPU core is always assigned to one of the CAT classes. By programming CPU core assignment and COS bitmasks, applications can be given exclusive, shared, or mixed access to the CPU's last level cache. CDP extends CAT so that there are two bitmasks per COS, one for data and one for code. The number of classes and number of valid bits in a COS bitmask is CPU model specific and COS bitmasks need to be contiguous. Sample code calls this bitmask a cbm or a capacity bitmask. By default, after reset, all CPU cores are assigned to COS 0 and all classes are programmed to allow fill into all cache ways. CDP is off by default. For more information about CAT please see https://github.com/01org/intel-cmt-cat Known issues and limitations: - --l3ca must be a first app parameter --- MAINTAINERS | 4 + doc/guides/sample_app_ug/index.rst| 1 + doc/guides/sample_app_ug/skeleton-cat.rst | 461 ++ examples/Makefile | 1 + examples/skeleton-cat/Makefile| 68 ++ examples/skeleton-cat/basicfwd-cat.c | 220 +++ examples/skeleton-cat/cat.c | 992 ++ examples/skeleton-cat/cat.h | 72 +++ 8 files changed, 1819 insertions(+) create mode 100644 doc/guides/sample_app_ug/skeleton-cat.rst create mode 100644 examples/skeleton-cat/Makefile create mode 100644 examples/skeleton-cat/basicfwd-cat.c create mode 100644 examples/skeleton-cat/cat.c create mode 100644 examples/skeleton-cat/cat.h diff --git a/MAINTAINERS b/MAINTAINERS index 628bc05..7a6702b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -600,3 +600,7 @@ F: doc/guides/sample_app_ug/vmdq_dcb_forwarding.rst M: Pablo de Lara M: Daniel Mrzyglod F: examples/ptpclient/ + +M: Tomasz Kantecki +F: examples/skeleton-cat/ +F: doc/guides/sample_app_ug/skeleton-cat.rst \ No newline at end of file diff --git a/doc/guides/sample_app_ug/index.rst b/doc/guides/sample_app_ug/index.rst index 8a646dd..f065e54 100644 --- a/doc/guides/sample_app_ug/index.rst +++ b/doc/guides/sample_app_ug/index.rst @@ -41,6 +41,7 @@ Sample Applications User Guide exception_path hello_world skeleton +skeleton-cat rxtx_callbacks ip_frag ipv4_multicast diff --git a/doc/guides/sample_app_ug/skeleton-cat.rst b/doc/guides/sample_app_ug/skeleton-cat.rst new file mode 100644 index 000..cc174fc --- /dev/null +++ b/doc/guides/sample_app_ug/skeleton-cat.rst @@ -0,0 +1,461 @@ +.. BSD LICENSE +Copyright(c) 2016 Intel Corporation. All rights reserved. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +* Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in +the documentation and/or other materials provided with the +distribution. +* Neither the name of Intel Corporation nor the names of its +contributors may be used to endorse or promote products derived +from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +&
[dpdk-dev] [PATCH] examples/skeleton-cat: PQoS CAT and CDP, example of libpqos usage
Because of the feedback that we have received off the mailing list, that extending EAL commands is not an option due to the Intel Architecture nature of CAT, we have changed the design of PQoS patch. The current V2 patch implements a sample code, based on the DPDK skeleton example app, that links against the existing 01.org PQoS library (https://github.com/01org/intel-cmt-cat). This eliminates the need for librte_pqos and EAL extensions introduced in the V1 patch. The sample code implements a C module that parses the application specific part of the command line with CAT configuration options (--l3ca, same format as the V1 patch EAL command, but expects CPU ids rather than lcores). The module is easy to re-use in other applications as needed. Signed-off-by: Wojciech Andralojc Signed-off-by: Tomasz Kantecki Signed-off-by: Marcel D Cornu --- Details of "--l3ca" app parameter to configure Intel CAT and CDP features: --l3ca=bitmask@ --l3ca=(code_bitmask,data_bitmask)@ - makes selected CPU's use specified CAT bitmasks CAT and CDP features allow management of the CPU's last level cache. CAT introduces classes of service (COS) that are essentially bitmasks. In current CAT implementations, a bit in a COS bitmask corresponds to one cache way in the last level cache. A CPU core is always assigned to one of the CAT classes. By programming CPU core assignment and COS bitmasks, applications can be given exclusive, shared, or mixed access to the CPU's last level cache. CDP extends CAT so that there are two bitmasks per COS, one for data and one for code. The number of classes and number of valid bits in a COS bitmask is CPU model specific and COS bitmasks need to be contiguous. Sample code calls this bitmask a cbm or a capacity bitmask. By default, after reset, all CPU cores are assigned to COS 0 and all classes are programmed to allow fill into all cache ways. CDP is off by default. For more information about CAT please see https://github.com/01org/intel-cmt-cat Known issues and limitations: - --l3ca must be a first app parameter --- MAINTAINERS | 4 + doc/guides/sample_app_ug/index.rst| 1 + doc/guides/sample_app_ug/skeleton-cat.rst | 461 ++ examples/Makefile | 1 + examples/skeleton-cat/Makefile| 68 +++ examples/skeleton-cat/basicfwd-cat.c | 220 +++ examples/skeleton-cat/cat.c | 957 ++ examples/skeleton-cat/cat.h | 70 +++ 8 files changed, 1782 insertions(+) create mode 100644 doc/guides/sample_app_ug/skeleton-cat.rst create mode 100644 examples/skeleton-cat/Makefile create mode 100644 examples/skeleton-cat/basicfwd-cat.c create mode 100644 examples/skeleton-cat/cat.c create mode 100644 examples/skeleton-cat/cat.h diff --git a/MAINTAINERS b/MAINTAINERS index 628bc05..7a6702b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -600,3 +600,7 @@ F: doc/guides/sample_app_ug/vmdq_dcb_forwarding.rst M: Pablo de Lara M: Daniel Mrzyglod F: examples/ptpclient/ + +M: Tomasz Kantecki +F: examples/skeleton-cat/ +F: doc/guides/sample_app_ug/skeleton-cat.rst \ No newline at end of file diff --git a/doc/guides/sample_app_ug/index.rst b/doc/guides/sample_app_ug/index.rst index 8a646dd..f065e54 100644 --- a/doc/guides/sample_app_ug/index.rst +++ b/doc/guides/sample_app_ug/index.rst @@ -41,6 +41,7 @@ Sample Applications User Guide exception_path hello_world skeleton +skeleton-cat rxtx_callbacks ip_frag ipv4_multicast diff --git a/doc/guides/sample_app_ug/skeleton-cat.rst b/doc/guides/sample_app_ug/skeleton-cat.rst new file mode 100644 index 000..6684f61 --- /dev/null +++ b/doc/guides/sample_app_ug/skeleton-cat.rst @@ -0,0 +1,461 @@ +.. BSD LICENSE +Copyright(c) 2016 Intel Corporation. All rights reserved. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +* Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in +the documentation and/or other materials provided with the +distribution. +* Neither the name of Intel Corporation nor the names of its +contributors may be used to endorse or promote products derived +from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE F
[dpdk-dev] [PATCH] eal: Initial implementation of PQoS EAL extension
EAL extension allows CAT and CDP technologies to be configured via "--l3ca*" parameters. Reworking existing applications to make use of DPDK PQoS library is a heavy lift. This EAL extension is to make it easier by adding new command line options. These new options allow to leverage CAT and CDP technologies with existing code base without any additional development effort. Signed-off-by: Wojciech Andralojc --- Adds EAL "--l3ca*" parameters to configure Intel CAT and CDP features --l3ca-dump - lists current CAT configuration --l3ca-reset=[cdp-on|cdp-off] - performs CAT reset. It can switch CDP on or off. --l3ca=bitmask@ --l3ca=(code_bitmask,data_bitmask)@ - makes selected cores use specified CAT bitmasks Known issues: - checkpatches.sh LONG_LINE warnings; config/common_linuxapp| 4 + config/defconfig_i686-native-linuxapp-gcc | 3 +- config/defconfig_i686-native-linuxapp-icc | 3 +- config/defconfig_x86_64-native-linuxapp-clang | 3 +- config/defconfig_x86_64-native-linuxapp-gcc | 3 +- config/defconfig_x86_64-native-linuxapp-icc | 3 +- config/defconfig_x86_x32-native-linuxapp-gcc | 3 +- lib/librte_eal/common/eal_common_lcore.c | 4 + lib/librte_eal/common/eal_common_options.c| 354 ++-- lib/librte_eal/common/eal_common_pqos.c | 590 ++ lib/librte_eal/common/eal_internal_cfg.h | 34 ++ lib/librte_eal/common/eal_options.h | 11 + lib/librte_eal/common/eal_private.h | 12 + lib/librte_eal/common/include/rte_lcore.h | 3 + lib/librte_eal/linuxapp/eal/Makefile | 10 + lib/librte_eal/linuxapp/eal/eal.c | 5 + 16 files changed, 1009 insertions(+), 36 deletions(-) create mode 100644 lib/librte_eal/common/eal_common_pqos.c diff --git a/config/common_linuxapp b/config/common_linuxapp index 553e640..bf30f1e 100644 --- a/config/common_linuxapp +++ b/config/common_linuxapp @@ -520,6 +520,10 @@ CONFIG_RTE_LIBRTE_VHOST_DEBUG=n # LIBRTE_PQOS is for librte_pqos only CONFIG_RTE_LIBRTE_PQOS=n CONFIG_RTE_LIBRTE_PQOS_DEBUG=n +# LIBRTE_PQOS_OPTS is for enabling PQoS in EAL +# (initialization, configuration and cmd line options) +CONFIG_RTE_LIBRTE_PQOS_OPTS=n + # #Compile Xen domain0 support diff --git a/config/defconfig_i686-native-linuxapp-gcc b/config/defconfig_i686-native-linuxapp-gcc index a73b999..ee8ff9f 100644 --- a/config/defconfig_i686-native-linuxapp-gcc +++ b/config/defconfig_i686-native-linuxapp-gcc @@ -51,4 +51,5 @@ CONFIG_RTE_LIBRTE_KNI=n CONFIG_RTE_IXGBE_INC_VECTOR=n # Enable PQoS -CONFIG_RTE_LIBRTE_PQOS=y \ No newline at end of file +CONFIG_RTE_LIBRTE_PQOS=y +CONFIG_RTE_LIBRTE_PQOS_OPTS=y \ No newline at end of file diff --git a/config/defconfig_i686-native-linuxapp-icc b/config/defconfig_i686-native-linuxapp-icc index f454955..85d1f53 100644 --- a/config/defconfig_i686-native-linuxapp-icc +++ b/config/defconfig_i686-native-linuxapp-icc @@ -51,4 +51,5 @@ CONFIG_RTE_LIBRTE_KNI=n CONFIG_RTE_IXGBE_INC_VECTOR=n # Enable PQoS -CONFIG_RTE_LIBRTE_PQOS=y \ No newline at end of file +CONFIG_RTE_LIBRTE_PQOS=y +CONFIG_RTE_LIBRTE_PQOS_OPTS=y \ No newline at end of file diff --git a/config/defconfig_x86_64-native-linuxapp-clang b/config/defconfig_x86_64-native-linuxapp-clang index 57a7ad5..a93f7d9 100644 --- a/config/defconfig_x86_64-native-linuxapp-clang +++ b/config/defconfig_x86_64-native-linuxapp-clang @@ -42,4 +42,5 @@ CONFIG_RTE_TOOLCHAIN="clang" CONFIG_RTE_TOOLCHAIN_CLANG=y # Enable PQoS -CONFIG_RTE_LIBRTE_PQOS=y \ No newline at end of file +CONFIG_RTE_LIBRTE_PQOS=y +CONFIG_RTE_LIBRTE_PQOS_OPTS=y \ No newline at end of file diff --git a/config/defconfig_x86_64-native-linuxapp-gcc b/config/defconfig_x86_64-native-linuxapp-gcc index d4ba885..66621a5 100644 --- a/config/defconfig_x86_64-native-linuxapp-gcc +++ b/config/defconfig_x86_64-native-linuxapp-gcc @@ -42,4 +42,5 @@ CONFIG_RTE_TOOLCHAIN="gcc" CONFIG_RTE_TOOLCHAIN_GCC=y # Enable PQoS -CONFIG_RTE_LIBRTE_PQOS=y \ No newline at end of file +CONFIG_RTE_LIBRTE_PQOS=y +CONFIG_RTE_LIBRTE_PQOS_OPTS=y \ No newline at end of file diff --git a/config/defconfig_x86_64-native-linuxapp-icc b/config/defconfig_x86_64-native-linuxapp-icc index 829b8f3..49b2062 100644 --- a/config/defconfig_x86_64-native-linuxapp-icc +++ b/config/defconfig_x86_64-native-linuxapp-icc @@ -42,4 +42,5 @@ CONFIG_RTE_TOOLCHAIN="icc" CONFIG_RTE_TOOLCHAIN_ICC=y # Enable PQoS -CONFIG_RTE_LIBRTE_PQOS=y \ No newline at end of file +CONFIG_RTE_LIBRTE_PQOS=y +CONFIG_RTE_LIBRTE_PQOS_OPTS=y \ No newline at end of file diff --git a/config/defconfig_x86_x32-native-linuxapp-gcc b/config/defconfig_x86_x32-native-linuxapp-gcc index 4140a95..98df235 100644 --- a/config/defconfig_x86_x32-native-linuxapp-gcc +++ b/config/defconfig_x86_x32-native-linuxapp-gcc @@ -46,4 +46,5 @@ CONFIG_RTE_TOOLCHAIN_GCC=y CONFIG_RTE_LIBRTE_KNI=n # Enable PQoS -CO
[dpdk-dev] [PATCH] lib: Initial implementation of PQoS lib with CAT and CDP support
Please see initial implementation of DPDK PQoS library which enables Cache Allocation Technology (CAT) and its extension, Code Data Prioritization (CDP). Current library version uses MSR registers to program these technologies. This is due to lack of broad enabling in OS frameworks. As the OS support becomes available the implementation will change to make use of available OS interfaces. Signed-off-by: Wojciech Andralojc --- CAT and CDP features allow to manage CPU's last level cache. CAT introduces classes of service (COS) that essentially are bitmasks. In current CAT implementations, a bit in a COS bitmask corresponds to one cache way in last level cache. CPU cores can be assigned to one of the classes. By programming CPU core assignment and COS bitmasks applications can be given exclusive, shared, or mixed access to CPU's last level cache. CDP extends CAT so that there are two bitmasks per COS, one for data and one for code. The number of classes and number of valid bits in a COS bitmask is CPU model specific and they are discovered by the library. By default, after reset, all CPU cores are assigned to COS 0 and all classes are programmed to allow fill into all cache ways. CDP is off by default. Patch introducing EAL parameters to configure CAT and CDP will follow. Known issues: - checkpatches.sh LONG_LINE warnings; - lcore_id cannot be treated as a logical core id anymore, need to retrieve logical core id corresponding to lcore_id in the library MAINTAINERS | 4 + config/common_linuxapp| 8 + config/defconfig_i686-native-linuxapp-gcc | 3 + config/defconfig_i686-native-linuxapp-icc | 3 + config/defconfig_x86_64-native-linuxapp-clang | 3 + config/defconfig_x86_64-native-linuxapp-gcc | 3 + config/defconfig_x86_64-native-linuxapp-icc | 3 + config/defconfig_x86_x32-native-linuxapp-gcc | 3 + lib/Makefile | 1 + lib/librte_eal/common/eal_common_lcore.c | 38 ++ lib/librte_eal/common/eal_private.h | 9 + lib/librte_eal/common/include/rte_eal.h | 4 + lib/librte_eal/common/include/rte_lcore.h | 188 lib/librte_eal/common/include/rte_log.h | 3 + lib/librte_eal/linuxapp/eal/Makefile | 3 + lib/librte_eal/linuxapp/eal/eal.c | 8 + lib/librte_eal/linuxapp/eal/eal_lcore.c | 25 ++ lib/librte_pqos/Makefile | 53 +++ lib/librte_pqos/allocation.c | 561 lib/librte_pqos/capabilities.c| 598 ++ lib/librte_pqos/rte_pqos.h| 248 +++ lib/librte_pqos/rte_pqos_common.c | 141 ++ lib/librte_pqos/rte_pqos_common.h | 183 lib/librte_pqos/rte_pqos_version.map | 16 + mk/rte.app.mk | 2 + 25 files changed, 2111 insertions(+) create mode 100644 lib/librte_pqos/Makefile create mode 100644 lib/librte_pqos/allocation.c create mode 100644 lib/librte_pqos/capabilities.c create mode 100644 lib/librte_pqos/rte_pqos.h create mode 100644 lib/librte_pqos/rte_pqos_common.c create mode 100644 lib/librte_pqos/rte_pqos_common.h create mode 100644 lib/librte_pqos/rte_pqos_version.map diff --git a/MAINTAINERS b/MAINTAINERS index b90aeea..aa593d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -233,6 +233,10 @@ F: lib/librte_cryptodev/ F: app/test/test_cryptodev* F: examples/l2fwd-crypto/ +PQoS API +M: Kantecki, Tomasz +K: RTE_LIBRTE_PQOS +F: lib/librte_pqos/ Drivers --- diff --git a/config/common_linuxapp b/config/common_linuxapp index 74bc515..553e640 100644 --- a/config/common_linuxapp +++ b/config/common_linuxapp @@ -99,6 +99,7 @@ CONFIG_RTE_NEXT_ABI=y CONFIG_RTE_LIBRTE_EAL=y CONFIG_RTE_MAX_LCORE=128 CONFIG_RTE_MAX_NUMA_NODES=8 +CONFIG_RTE_MAX_PHY_PKGS=8 CONFIG_RTE_MAX_MEMSEG=256 CONFIG_RTE_MAX_MEMZONE=2560 CONFIG_RTE_MAX_TAILQ=32 @@ -514,6 +515,13 @@ CONFIG_RTE_LIBRTE_VHOST_NUMA=n CONFIG_RTE_LIBRTE_VHOST_DEBUG=n # +# Compile librte_pqos +# IA only +# LIBRTE_PQOS is for librte_pqos only +CONFIG_RTE_LIBRTE_PQOS=n +CONFIG_RTE_LIBRTE_PQOS_DEBUG=n + +# #Compile Xen domain0 support # CONFIG_RTE_LIBRTE_XEN_DOM0=n diff --git a/config/defconfig_i686-native-linuxapp-gcc b/config/defconfig_i686-native-linuxapp-gcc index a90de9b..a73b999 100644 --- a/config/defconfig_i686-native-linuxapp-gcc +++ b/config/defconfig_i686-native-linuxapp-gcc @@ -49,3 +49,6 @@ CONFIG_RTE_LIBRTE_KNI=n # Vectorized PMD is not supported on 32-bit # CONFIG_RTE_IXGBE_INC_VECTOR=n + +# Enable PQoS +CONFIG_RTE_LIBRTE_PQOS=y \ No newline at end of file diff --git a/config/defconfig_i686-native-linuxapp-icc b/config/defconfig_i686-native-linuxapp-icc index c021321..f454955 100644 --- a/config/defconfig_i686-native-linuxapp-icc +++ b/config/defconfig_i686-native-linuxapp-icc @@ -49,3 +49,6 @@ CONFIG_RTE_LI
[dpdk-dev] [PATCH v3] Patch introducing API to read/write Intel Architecture Model Specific Registers (MSR)...
Patch reworked.
Signed-off-by: Wojciech Andralojc
---
lib/librte_eal/common/include/arch/x86/rte_msr.h | 88 +
lib/librte_eal/linuxapp/eal/Makefile | 1 +
lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c | 116 +++
3 files changed, 205 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/x86/rte_msr.h
create mode 100644 lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c
diff --git a/lib/librte_eal/common/include/arch/x86/rte_msr.h
b/lib/librte_eal/common/include/arch/x86/rte_msr.h
new file mode 100644
index 000..fc49107
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/x86/rte_msr.h
@@ -0,0 +1,88 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_MSR_X86_64_H_
+#define _RTE_MSR_X86_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file
+ *
+ * API to read/write Intel Architecture Model Specific Registers (MSR).
+ *
+ */
+
+/**
+ * Function to read CPU's MSR
+ *
+ * @param [in] cpuid
+ * CPU logical core id
+ *
+ * @param [in] reg
+ * MSR reg to read
+ *
+ * @param [out] value
+ * Read value of MSR reg
+ *
+ * @return
+ * Operations status
+*/
+extern int rte_msr_read(const unsigned cpuid, const uint32_t reg,
+ uint64_t *value);
+
+/**
+ * Function to write CPU's MSR
+ *
+ * @param [in] cpuid
+ * CPU logical core id
+ *
+ * @param [in] reg
+ * MSR reg to write
+ *
+ * @param [in] value
+ * Value to be written to MSR reg
+ *
+ * @return
+ * Operations status
+*/
+extern int rte_msr_write(const unsigned cpuid, const uint32_t reg,
+ const uint64_t value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MSR_X86_64_H_ */
diff --git a/lib/librte_eal/linuxapp/eal/Makefile
b/lib/librte_eal/linuxapp/eal/Makefile
index 26eced5..4b6047f 100644
--- a/lib/librte_eal/linuxapp/eal/Makefile
+++ b/lib/librte_eal/linuxapp/eal/Makefile
@@ -68,6 +68,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_alarm.c
ifeq ($(CONFIG_RTE_LIBRTE_IVSHMEM),y)
SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_ivshmem.c
endif
+SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += ./arch/x86/rte_msr.c
# from common dir
SRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_lcore.c
diff --git a/lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c
b/lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c
new file mode 100644
index 000..a702b6c
--- /dev/null
+++ b/lib/librte_eal/linuxapp/eal/arch/x86/rte_msr.c
@@ -0,0 +1,116 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this s
[dpdk-dev] [PATCH v2] Patch introducing API to read/write Intel Architecture Model Specific Registers (MSR)...
Patch rework based on feedback, only x86 specific functions left under
lib/librte_eal/common/include/arch/x86/.
Signed-off-by: Wojciech Andralojc
---
lib/librte_eal/common/include/arch/x86/rte_msr.h | 158 +++
1 file changed, 158 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/x86/rte_msr.h
diff --git a/lib/librte_eal/common/include/arch/x86/rte_msr.h
b/lib/librte_eal/common/include/arch/x86/rte_msr.h
new file mode 100644
index 000..9d16633
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/x86/rte_msr.h
@@ -0,0 +1,158 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2016 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_MSR_X86_64_H_
+#define _RTE_MSR_X86_64_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include //O_RDONLY
+#include //pread
+
+#include
+#include
+
+#define CPU_MSR_PATH "/dev/cpu/%u/msr"
+#define CPU_MSR_PATH_MAX_LEN 32
+
+/**
+ * This function should not be called directly.
+ * Function to open CPU's MSR file
+ */
+static int
+__msr_open_file(const unsigned lcore, int flags)
+{
+ char fname[CPU_MSR_PATH_MAX_LEN] = {0};
+ int fd = -1;
+
+ snprintf(fname, sizeof(fname) - 1, CPU_MSR_PATH, lcore);
+
+ fd = open(fname, flags);
+
+ if (fd < 0)
+ RTE_LOG(ERR, PQOS, "Error opening file '%s'!\n", fname);
+
+ return fd;
+}
+
+/**
+ * Function to read CPU's MSR
+ *
+ * @param [in] lcore
+ * CPU logical core id
+ *
+ * @param [in] reg
+ * MSR reg to read
+ *
+ * @param [out] value
+ * Read value of MSR reg
+ *
+ * @return
+ * Operations status
+*/
+
+static inline int
+rte_msr_read(const unsigned lcore, const uint32_t reg, uint64_t *value)
+{
+ int fd = -1;
+ int ret = -1;
+
+ RTE_VERIFY(value != NULL);
+ if (value == NULL)
+ return -1;
+
+ fd = __msr_open_file(lcore, O_RDONLY);
+
+ if (fd >= 0) {
+ ssize_t read_ret = 0;
+
+ read_ret = pread(fd, value, sizeof(value[0]), (off_t)reg);
+
+ if (read_ret != sizeof(value[0])) {
+ RTE_LOG(ERR, PQOS, "RDMSR failed for reg[0x%x] on lcore
%u\n",
+ (unsigned)reg, lcore);
+ } else
+ ret = 0;
+
+ close(fd);
+ }
+
+ return ret;
+}
+
+/**
+ * Function to write CPU's MSR
+ *
+ * @param [in] lcore
+ * CPU logical core id
+ *
+ * @param [in] reg
+ * MSR reg to write
+ *
+ * @param [in] value
+ * Value to be written to MSR reg
+ *
+ * @return
+ * Operations status
+*/
+static inline int
+rte_msr_write(const unsigned lcore, const uint32_t reg, const uint64_t value)
+{
+ int fd = -1;
+ int ret = -1;
+
+ fd = __msr_open_file(lcore, O_WRONLY);
+
+ if (fd >= 0) {
+ ssize_t write_ret = 0;
+
+ write_ret = pwrite(fd, &value, sizeof(value), (off_t)reg);
+ if (write_ret != sizeof(value)) {
+ RTE_LOG(ERR, PQOS, "WRMSR failed for reg[0x%x] <-
value[0x%llx] on "
+ "lcore %u\n", (unsigned)reg, (unsigned
long long)value, lcore);
+ } else
+ ret = 0;
+
+ close(fd);
+ }
+
+ return ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MSR_X86_64_H_ */
--
1.9.3
[dpdk-dev] [PATCH] Patch introducing API to read/write Intel Architecture Model Specific Registers (MSR), rte_msr_read and rte_msr_write functions.
There is work in progress to implement Intel Cache Allocation Technology (CAT)
support in DPDK, this technology is programmed through MSRs.
In the future it will be possible to program CAT through Linux cgroups and DPDK
CAT implementation will take advantage of it.
MSR R/W's are privileged ring 0 operations and they must be done in kernel
space. For this reason implementation utilizes Linux MSR driver.
Signed-off-by: Wojciech Andralojc
---
lib/librte_eal/common/Makefile | 1 +
lib/librte_eal/common/include/arch/arm/rte_msr.h | 65 ++
.../common/include/arch/ppc_64/rte_msr.h | 65 ++
lib/librte_eal/common/include/arch/tile/rte_msr.h | 65 ++
lib/librte_eal/common/include/arch/x86/rte_msr.h | 143 +
lib/librte_eal/common/include/generic/rte_msr.h| 78 +++
lib/librte_eal/common/include/rte_lcore.h | 18 +++
7 files changed, 435 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_msr.h
create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_msr.h
create mode 100644 lib/librte_eal/common/include/arch/tile/rte_msr.h
create mode 100644 lib/librte_eal/common/include/arch/x86/rte_msr.h
create mode 100644 lib/librte_eal/common/include/generic/rte_msr.h
diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile
index f5ea0ee..567c206 100644
--- a/lib/librte_eal/common/Makefile
+++ b/lib/librte_eal/common/Makefile
@@ -48,6 +48,7 @@ endif
GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h
GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h
+GENERIC_INC += rte_msr.h
# defined in mk/arch/$(RTE_ARCH)/rte.vars.mk
ARCH_DIR ?= $(RTE_ARCH)
ARCH_INC := $(notdir $(wildcard
$(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h))
diff --git a/lib/librte_eal/common/include/arch/arm/rte_msr.h
b/lib/librte_eal/common/include/arch/arm/rte_msr.h
new file mode 100644
index 000..85c009c
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_msr.h
@@ -0,0 +1,65 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Intel Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_MSR_ARM_H_
+#define _RTE_MSR_ARM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_msr.h"
+
+/* Function to read CPU's MSR */
+static inline int
+rte_msr_read(__attribute__((unused)) const unsigned lcore,
+ __attribute__((unused)) const uint32_t reg,
+ __attribute__((unused)) uint64_t *value)
+{
+ return -1;
+}
+
+/* Function to write CPU's MSR */
+static inline int
+rte_msr_write(__attribute__((unused)) const unsigned lcore,
+ __attribute__((unused)) const uint32_t reg,
+ __attribute__((unused)) const uint64_t value)
+{
+ return -1;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MSR_ARM_H_ */
diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_msr.h
b/lib/librte_eal/common/include/arch/ppc_64/rte_msr.h
new file mode 100644
index 000..44f3de2
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_msr.h
@@ -0,0 +1,65 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and us
