[dpdk-dev] [PATCH] net/i40e: fix fdir configure failed issue in X710

[Wu, Jingjing]

> -Original Message-
> From: Guo, Jia
> Sent: Thursday, October 20, 2016 10:48 AM
> To: Zhang, Helin ; Wu, Jingjing  intel.com>
> Cc: dev at dpdk.org; Guo, Jia ; Yigit, Ferruh 
> 
> Subject: [PATCH] net/i40e: fix fdir configure failed issue in X710
> 
> The correct way to distinguish the behavior of X722 and X710
> or other NICs should be using the mac type but not X722 macro.
> 
The code change looks fine, but the commit log looks  Just don't know what the 
fdir configuration failure is.
Could you describe it in your commit log?
And a minor comment is like

I40E_RSS_HENA_ALL seems a part of I40E_RSS_HENA_ALL_X722, why not

#define I40E_RSS_HENA_ALL_ X722  I40E_RSS_HENA_ALL | I40E_FILTER_PCTYPE_XX

Thanks
Jingjing

[dpdk-dev] [PATCH] net/i40e: fix fdir configure failed issue in X710

[Jeff Guo]

The correct way to distinguish the behavior of X722 and X710
or other NICs should be using the mac type but not X722 macro.

Fixes: 8c5cb3c11513 (?net/i40e: add packet type translation for X722?)
Signed-off-by: Jeff Guo 
---
 drivers/net/i40e/i40e_ethdev.c| 103 +-
 drivers/net/i40e/i40e_ethdev.h|  17 +++
 drivers/net/i40e/i40e_ethdev_vf.c |  16 --
 drivers/net/i40e/i40e_fdir.c  |  55 
 4 files changed, 112 insertions(+), 79 deletions(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 5af0e43..db5f808 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -6164,7 +6164,7 @@ DONE:

 /* Configure hash enable flags for RSS */
 uint64_t
-i40e_config_hena(uint64_t flags)
+i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
 {
uint64_t hena = 0;

@@ -6173,42 +6173,42 @@ i40e_config_hena(uint64_t flags)

if (flags & ETH_RSS_FRAG_IPV4)
hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
-   if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
-#ifdef X722_SUPPORT
-   hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
-   (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
-#else
-   hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
-#endif
-   if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
-#ifdef X722_SUPPORT
-   hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
-   (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
-   (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
-#else
-   hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
-#endif
+   if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
+   if (type == I40E_MAC_X722) {
+   hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
+(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
+   } else
+   hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
+   }
+   if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
+   if (type == I40E_MAC_X722) {
+   hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
+(1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
+(1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
+   } else
+   hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
+   }
if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
if (flags & ETH_RSS_FRAG_IPV6)
hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
-   if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
-#ifdef X722_SUPPORT
-   hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
-   (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
-#else
-   hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
-#endif
-   if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
-#ifdef X722_SUPPORT
-   hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
-   (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
-   (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
-#else
-   hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
-#endif
+   if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
+   if (type == I40E_MAC_X722) {
+   hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
+(1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
+   } else
+   hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
+   }
+   if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
+   if (type == I40E_MAC_X722) {
+   hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
+(1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
+(1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
+   } else
+   hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
+   }
if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
@@ -6282,7 +6282,10 @@ i40e_pf_disable_rss(struct i40e_pf *pf)

hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
-   hena &= ~I40E_RSS_HENA_ALL;
+   if (hw->mac.type == I40E_MAC_X722)
+   hena &= ~I40E_RSS_HENA_ALL_X722;
+   else
+   hena &= ~I40E_RSS_HENA_ALL;
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >>