[dpdk-dev] [PATCH 1/2] crypto/qat: rework request builder for performance

2016-10-24 Thread Jain, Deepak K


> -Original Message-
> From: Trahe, Fiona
> Sent: Monday, October 24, 2016 1:00 PM
> To: dev at dpdk.org
> Cc: De Lara Guarch, Pablo ; Trahe, Fiona
> ; Griffin, John ; Jain,
> Deepak K ; Kusztal, ArkadiuszX
> 
> Subject: [PATCH 1/2] crypto/qat: rework request builder for performance
> 
> QAT PMD adjusts the buffer start address and offsets passed to the device
> so that the DMAs in and out of the device are 64-byte aligned.
> This gives more consistent throughput, which had been variable depending
> on how the application set up the mbuf.
> The message builder code had to be considerably re-factored to do this
> efficiently.
> 
> Signed-off-by: Fiona Trahe 
> ---
>  drivers/crypto/qat/qat_adf/icp_qat_hw.h  |   5 +
>  drivers/crypto/qat/qat_adf/qat_algs.h|   1 +
>  drivers/crypto/qat/qat_adf/qat_algs_build_desc.c |   2 +
>  drivers/crypto/qat/qat_crypto.c  | 239 
> ---
>  4 files changed, 176 insertions(+), 71 deletions(-)
> 
> diff --git a/drivers/crypto/qat/qat_adf/icp_qat_hw.h
> b/drivers/crypto/qat/qat_adf/icp_qat_hw.h
> index a08094f..ebe245f 100644
> --- a/drivers/crypto/qat/qat_adf/icp_qat_hw.h
> --
> 2.5.0
Acked-By: Deepak Kumar Jain 


[dpdk-dev] [PATCH 1/2] crypto/qat: rework request builder for performance

2016-10-24 Thread Fiona Trahe
QAT PMD adjusts the buffer start address and offsets passed
to the device so that the DMAs in and out of the device are
64-byte aligned.
This gives more consistent throughput, which had been
variable depending on how the application set up the mbuf.
The message builder code had to be considerably re-factored
to do this efficiently.

Signed-off-by: Fiona Trahe 
---
 drivers/crypto/qat/qat_adf/icp_qat_hw.h  |   5 +
 drivers/crypto/qat/qat_adf/qat_algs.h|   1 +
 drivers/crypto/qat/qat_adf/qat_algs_build_desc.c |   2 +
 drivers/crypto/qat/qat_crypto.c  | 239 ---
 4 files changed, 176 insertions(+), 71 deletions(-)

diff --git a/drivers/crypto/qat/qat_adf/icp_qat_hw.h 
b/drivers/crypto/qat/qat_adf/icp_qat_hw.h
index a08094f..ebe245f 100644
--- a/drivers/crypto/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/crypto/qat/qat_adf/icp_qat_hw.h
@@ -237,6 +237,11 @@ enum icp_qat_hw_cipher_dir {
ICP_QAT_HW_CIPHER_DECRYPT = 1,
 };

+enum icp_qat_hw_auth_op {
+   ICP_QAT_HW_AUTH_VERIFY = 0,
+   ICP_QAT_HW_AUTH_GENERATE = 1,
+};
+
 enum icp_qat_hw_cipher_convert {
ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h 
b/drivers/crypto/qat/qat_adf/qat_algs.h
index 78a92f3..dcc0df5 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -98,6 +98,7 @@ struct qat_session {
enum icp_qat_hw_cipher_dir qat_dir;
enum icp_qat_hw_cipher_mode qat_mode;
enum icp_qat_hw_auth_algo qat_hash_alg;
+   enum icp_qat_hw_auth_op auth_op;
struct qat_alg_cd cd;
uint8_t *cd_cur_ptr;
phys_addr_t cd_paddr;
diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c 
b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 0b66b37..8900668 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -625,11 +625,13 @@ int qat_alg_aead_session_create_content_desc_auth(struct 
qat_session *cdesc,
ICP_QAT_FW_LA_NO_RET_AUTH_RES);
ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_CMP_AUTH_RES);
+   cdesc->auth_op = ICP_QAT_HW_AUTH_VERIFY;
} else {
ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
   ICP_QAT_FW_LA_RET_AUTH_RES);
ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
   ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
+   cdesc->auth_op = ICP_QAT_HW_AUTH_GENERATE;
}

/*
diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index f8db12f..798cd98 100644
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -951,6 +951,13 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t 
*out_msg)
struct icp_qat_fw_la_cipher_req_params *cipher_param;
struct icp_qat_fw_la_auth_req_params *auth_param;
register struct icp_qat_fw_la_bulk_req *qat_req;
+   uint8_t do_auth = 0, do_cipher = 0;
+   uint32_t cipher_len = 0, cipher_ofs = 0;
+   uint32_t auth_len = 0, auth_ofs = 0;
+   uint32_t min_ofs = 0;
+   uint32_t digest_appended = 1;
+   uint64_t buf_start = 0;
+

 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
@@ -975,88 +982,173 @@ qat_write_hw_desc_entry(struct rte_crypto_op *op, 
uint8_t *out_msg)
qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
+   cipher_param = (void *)_req->serv_specif_rqpars;
+   auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));

-   qat_req->comn_mid.dst_length =
-   qat_req->comn_mid.src_length =
-   rte_pktmbuf_data_len(op->sym->m_src);
+   if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
+   ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
+   do_auth = 1;
+   do_cipher = 1;
+   } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
+   do_auth = 1;
+   do_cipher = 0;
+   } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
+   do_auth = 0;
+   do_cipher = 1;
+   }

-   qat_req->comn_mid.dest_data_addr =
-   qat_req->comn_mid.src_data_addr =
-   rte_pktmbuf_mtophys(op->sym->m_src);
+   if (do_cipher) {

-   if (unlikely(op->sym->m_dst != NULL)) {
-   qat_req->comn_mid.dest_data_addr =
-   rte_pktmbuf_mtophys(op->sym->m_dst);
-   qat_req->comn_mid.dst_length =
-