Re: [Article] NuttX on Star64 JH7110: RISC-V Semihosting and Initial RAM Disk

2023-07-27 Thread Tomek CEDRO
On Fri, Jul 28, 2023 at 1:10 AM Lee, Lup Yuen wrote:
> NuttX crashes on Star64 JH7110 RISC-V SBC because there's no Semihosting.
> But no worries! We modified NuttX to boot with an Initial RAM Disk instead
> (initrd).
>
> In this article, we find out…
> (1) What’s RISC-V Semihosting
> (2) Why it crashes NuttX on Star64
> (3) How it affects the Apps Filesystem in NuttX
> (4) How we replaced Semihosting by Initial RAM Disk “initrd”
> (5) After testing on QEMU Emulator
> (6) Thanks to NuttX on LiteX Arty-A7 for the guidance!
>
> Check out the article: https://lupyuen.codeberg.page/articles/semihost.html

So much new knowledge! Congratulations Lup! :-)

-- 
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info


[Article] NuttX on Star64 JH7110: RISC-V Semihosting and Initial RAM Disk

2023-07-27 Thread Lee, Lup Yuen
NuttX crashes on Star64 JH7110 RISC-V SBC because there's no Semihosting.
But no worries! We modified NuttX to boot with an Initial RAM Disk instead
(initrd).

In this article, we find out…
(1) What’s RISC-V Semihosting
(2) Why it crashes NuttX on Star64
(3) How it affects the Apps Filesystem in NuttX
(4) How we replaced Semihosting by Initial RAM Disk “initrd”
(5) After testing on QEMU Emulator
(6) Thanks to NuttX on LiteX Arty-A7 for the guidance!

Check out the article: https://lupyuen.codeberg.page/articles/semihost.html

Lup


Question about SMP and up_cpu_paused

2023-07-27 Thread Ville Juven
Hi all,

I have been bughunting an issue with
https://github.com/apache/nuttx/pull/9577 which implements (again) lazy FPU
save and restore for risc-v. It crashes with SMP targets randomly.

I have been looking at the SMP implementation of NuttX for a while now
trying to understand what can cause such random behavior, specifically I
have been trying to understand what up_cpu_paused does. It saves the
integer registers and then waits for a spin lock to be released.

I assume the task that was scheduled out can be scheduled on another CPU
while the waiting CPU waits. So my question is, should I do a full context
save in up_cpu_paused ? Meaning integer + FPU registers both ? Now it only
saves the integer registers which I think is the issue here.

Any insight on this is greatly appreciated!

Br,
Ville Juven