[edk2-devel] [PATCH v2] [edk2-platforms] Silicon/Intel/FitGen: Fix CheckOverlap would do incorrect split BiosModule action in corner case

[Lin, Jason1]

From: Jason1 Lin 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3922

[Description]
CheckOverlap function would do incorrect split on the BiosModule
which not happen overlap.
This would cause incorrect value locate in FIT entry record.

[Condition]
- This BiosModule base address is lower than input address.
- This BiosModule size is smaller than input size.

[Resolution]
- Do the check on BiosModule size and input size value to prevent possible
  nagative value.

Signed-off-by: Jason1 Lin 
Cc: Bob Feng 
Cc: Liming Gao 
Cc: Yuwei Chen 
Cc: Dakota Chiang 
Cc: Vanessa Chuang 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 31 +++-
 Silicon/Intel/Tools/FitGen/FitGen.h |  4 +--
 2 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index 290e688f6e..0cdba56a48 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -2,7 +2,7 @@
 This utility is part of build process for IA32/X64 FD.
 It generates FIT table.
 
-Copyright (c) 2010-2021, Intel Corporation. All rights reserved.
+Copyright (c) 2010-2022, Intel Corporation. All rights reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -755,11 +755,40 @@ CheckOverlap (
   IN UINT32 Address,
   IN UINT32 Size
   )
+/*++
+Routine Description:
+
+  Check wheather the input address and size is overlap with any BiosModule.
+  If happen overlap, need to be deal with this case.
+  ---  +--+ <-- BiosModule A Base   
+--+
+   |   |  | |  
|
+   |  | |  
BiosModule  |
+   |  | |  A   
|
+   |  | |  
|
+  BiosModule A +--+ <-- [Input] Address >   
+--+
+  Size |  ||
+   |  ||[Input] Size
+   +--+  -- 
+--+
+   |  | |  
BiosModule  |
+   |   |  | |  B   
|
+  ---  +--+ 
+--+
+
+Arguments:
+
+  Address - The address of the buffer that required to check.
+  Size- The size of the buffer that required to check.
+
+Returns:
+
+  None
+
+--*/
 {
   INTN  Index;
 
   for (Index = 0; Index < (INTN)gFitTableContext.BiosModuleNumber; Index ++) {
 if ((gFitTableContext.BiosModule[Index].Address <= Address) &&
+(gFitTableContext.BiosModule[Index].Size >= Size)   &&
 ((gFitTableContext.BiosModule[Index].Size - Size) >= (Address - 
gFitTableContext.BiosModule[Index].Address))) {
   UINT32  TempSize;
   INT32   SubIndex;
diff --git a/Silicon/Intel/Tools/FitGen/FitGen.h 
b/Silicon/Intel/Tools/FitGen/FitGen.h
index 5add6a8870..b7de0a6b2d 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.h
+++ b/Silicon/Intel/Tools/FitGen/FitGen.h
@@ -1,7 +1,7 @@
 /**@file
 Definitions for the FitGen utility.
 
-Copyright (c) 2010-2020, Intel Corporation. All rights reserved.
+Copyright (c) 2010-2022, Intel Corporation. All rights reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -31,7 +31,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 // Utility version information
 //
 #define UTILITY_MAJOR_VERSION 0
-#define UTILITY_MINOR_VERSION 64
+#define UTILITY_MINOR_VERSION 65
 #define UTILITY_DATE  __DATE__
 
 //
-- 
2.26.2.windows.1



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Re: [edk2-devel] [PATCH v1] [edk2-platforms] Silicon/Intel/FitGen: Fix CheckOverlap would do incorrect split BiosModule action in corner case

[Lin, Jason1]

Hi Bob,

Agree.
Check the size first is more readable than do the type conversion.
That would be align with the address check.
I would send out patch v2 based on this change.

Thanks,
Jason.

-Original Message-
From: Feng, Bob C  
Sent: Saturday, June 4, 2022 12:08
To: Lin, Jason1 ; devel@edk2.groups.io
Cc: Gao, Liming ; Chen, Christine 
; Chiang, Dakota ; Chuang, 
Vanessa 
Subject: RE: [PATCH v1] [edk2-platforms] Silicon/Intel/FitGen: Fix CheckOverlap 
would do incorrect split BiosModule action in corner case

Hi Jason,

Do you think the code could be more understandable if adding a check for the 
size? 

if ((gFitTableContext.BiosModule[Index].Address <= Address) && 
(gFitTableContext.BiosModule[Index].Size >= Size) &&
((gFitTableContext.BiosModule[Index].Size - Size) >= (Address - 
gFitTableContext.BiosModule[Index].Address)))


Thanks,
Bob

-Original Message-
From: Lin, Jason1  
Sent: Thursday, May 26, 2022 4:52 PM
To: devel@edk2.groups.io
Cc: Lin, Jason1 ; Feng, Bob C ; 
Gao, Liming ; Chen, Christine ; 
Chiang, Dakota ; Chuang, Vanessa 

Subject: [PATCH v1] [edk2-platforms] Silicon/Intel/FitGen: Fix CheckOverlap 
would do incorrect split BiosModule action in corner case

From: Jason1 Lin 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3922

[Description]
CheckOverlap function would do incorrect split on the BiosModule which not 
happen overlap. This would cause incorrect value locate in FIT entry record.

[Condition]
- This BiosModule base address is lower than input address.
- This BiosModule size is smaller than input size.

[Resolution]
- Do the type coversion to UINT64 to prevent overflow when the value shuld be 
nagative.
- Do the type coversion from UINT64 to INT64 to do the comparsion with possible 
nagative value.

Signed-off-by: Jason1 Lin 
Cc: Bob Feng 
Cc: Liming Gao 
Cc: Yuwei Chen 
Cc: Dakota Chiang 
Cc: Vanessa Chuang 
---
 Silicon/Intel/Tools/FitGen/FitGen.c | 30 +++-  
Silicon/Intel/Tools/FitGen/FitGen.h |  2 +-
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c 
b/Silicon/Intel/Tools/FitGen/FitGen.c
index 290e688f6e..9d7185dc55 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.c
+++ b/Silicon/Intel/Tools/FitGen/FitGen.c
@@ -755,12 +755,40 @@ CheckOverlap (
   IN UINT32 Address,   IN UINT32 Size   )+/*+++Routine Description:++  Check 
wheather the input address and size is overlap with any BiosModule.+  If happen 
overlap, need to be deal with this case.+  ---  +--+ 
<-- BiosModule A Base   +--++   |   |   
   | |  |+   |  
| |  BiosModule  |+   | 
 | |  A   |+
   |  | |  |+  
BiosModule A +--+ <-- [Input] Address >   
+--++  Size |  ||+   |  
||[Input] Size+   +--+  --  
   +--++   |  | 
|  BiosModule  |+   |   |  |
 |  B   |+  ---  +--+   
  +--+++Arguments:++  Address - The 
address of the buffer that required to check.+  Size- The size of the 
buffer that required to check.++Returns:++  None++--*/ {   INTN  Index;for 
(Index = 0; Index < (INTN)gFitTableContext.BiosModuleNumber; Index ++) { if 
((gFitTableContext.BiosModule[Index].Address <= Address) &&-
((gFitTableContext.BiosModule[Index].Size - Size) >= (Address - 
gFitTableContext.BiosModule[Index].Address))) {+
((INT64)((UINT64)gFitTableContext.BiosModule[Index].Size - (UINT64)Size) >= 
(INT64)((UINT64)Address - (UINT64)gFitTableContext.BiosModule[Index].Address))) 
{   UINT32  TempSize;   INT32   SubIndex; diff --git 
a/Silicon/Intel/Tools/FitGen/FitGen.h b/Silicon/Intel/Tools/FitGen/FitGen.h
index 5add6a8870..4943ee259c 100644
--- a/Silicon/Intel/Tools/FitGen/FitGen.h
+++ b/Silicon/Intel/Tools/FitGen/FitGen.h
@@ -31,7 +31,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 // Utility version information // #define UTILITY_MAJOR_VERSION 0-#define 
UTILITY_MINOR_VERSION 64+#define UTILITY_MINOR_VERSION 65 #define UTILITY_DATE  
__DATE__  //-- 
2.36.1.windows.1



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[edk2-devel] Event: TianoCore Bug Triage - APAC / NAMO - 06/07/2022 #cal-reminder

[Group Notification]

*Reminder: TianoCore Bug Triage - APAC / NAMO*

*When:*
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6:30pm to 7:30pm
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*Where:*
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Re: [edk2-devel] [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Heng Luo]

Reviewed-by: Heng Luo 

> -Original Message-
> From: Desimone, Nathaniel L 
> Sent: Tuesday, June 7, 2022 6:51 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Sinha, Ankit
> ; Kubacki, Michael ;
> Luo, Heng 
> Subject: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate 
> the
> width of the clock duty cycle to OS power management
> 
> Cc: Sai Chaganty 
> Cc: Ankit Sinha 
> Cc: Michael Kubacki 
> Cc: Heng Luo 
> Signed-off-by: Nate DeSimone 
> ---
>  .../TigerlakeURvp/OpenBoardPkgPcd.dsc  | 10 +-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> index ebbbc7b9f9..aba3c8d6d0 100644
> ---
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> +++
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> +++ .dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the TigerlakeURvp board.
>  #
> -#  Copyright (c) 2021, Intel Corporation. All rights reserved.
> +#  Copyright (c) 2021 - 2022, Intel Corporation. All rights
> +reserved.
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent  #  ## @@ -118,6 +118,14 @@
>gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x1000
>  #!endif
>gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x4
> +
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>  [PcdsFeatureFlag.common]
>##
># Edk2 Configuration
> --
> 2.27.0.windows.1



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Re: [edk2-devel] [edk2-platforms] [PATCH V2 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

Reviewed-by: Michael Kubacki 

On 6/6/2022 7:16 PM, Nate DeSimone wrote:

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu 
Cc: Michael Kubacki 
Cc: Benjamin Doron 
Cc: Jeremy Soller 
Signed-off-by: Nate DeSimone 
---
  .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc |  9 -
  .../GalagoPro3/OpenBoardPkgPcd.dsc|  8 +++-
  .../KabylakeRvp3/OpenBoardPkgPcd.dsc  | 11 +--
  3 files changed, 24 insertions(+), 4 deletions(-)

diff --git 
a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index 21ee86403d..02080aa864 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
  ## @file
  #  PCD configuration build description file for the Aspire VN7-572G board.
  #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -346,6 +346,13 @@
gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and BIOS 
Guard not present, measured boot enforcement checking code not present
gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
  
+  #

+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
##
# Platform Configuration
##
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index 44dacdf082..dce4db17c2 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
  ## @file
  #  PCD configuration build description file for the GalagoPro3 board.
  #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -251,6 +251,12 @@
gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
  
+  #

+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3

gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress

gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
  
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc

index 725596cbf7..ccf757e202 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
  ## @file
  #  PCD configuration build description file for the KabylakeRvp3 board.
  #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -78,6 +78,7 @@
# so FSP needs more temporary memory for FSP heap + stack size.
#
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
+
#
# FSP API mode does not need to enlarge the boot loader stack size
# since the stacks are separate.
@@ -290,6 +291,13 @@
gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
  
+  #

+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
##
# Platform Configuration
##
@@ -346,7 +354,6 @@
gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 
0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
0x00}
  !endif
  
-

##
# Board Configuration
##



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[edk2-devel] Now: Tools, CI, Code base construction meeting series - 06/06/2022 #cal-notice

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*Tools, CI, Code base construction meeting series*

*When:*
06/06/2022
4:30pm to 5:30pm
(UTC-07:00) America/Los Angeles

*Where:*
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Microsoft and Intel will be hosting a series of open meetings to discuss build, 
CI, tools, and other related topics. If you are interested, have ideas/opinions 
please join us. These meetings will be Monday 4:30pm Pacific Time on Microsoft 
Teams.

MS Teams Link in following discussion: * 
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* tianocore/edk2: EDK II (github.com)
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allowing for a more robust and plugin based build system and tool execution 
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[edk2-devel] [edk2-platforms] [PATCH V2 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu 
Cc: Michael Kubacki 
Signed-off-by: Nate DeSimone 
---
 .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 -
 .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc  | 9 -
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
index 84d4ec1331..8f3cc6ba28 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the UpXtreme board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -259,6 +259,13 @@
   gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
   
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ##
   # Platform Configuration
   ##
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index 4a7ba4d5f0..4a5d5ef03b 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the WhiskeylakeURvp board.
 #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -242,6 +242,13 @@
   ##
   
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ##
   # Platform Configuration
   ##
-- 
2.27.0.windows.1



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[edk2-devel] [edk2-platforms] [PATCH V2 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Sai Chaganty 
Cc: Michael Kubacki 
Cc: Heng Luo 
Signed-off-by: Nate DeSimone 
---
 .../TigerlakeURvp/OpenBoardPkgPcd.dsc  | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git 
a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc 
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index ebbbc7b9f9..aba3c8d6d0 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the TigerlakeURvp board.
 #
-#  Copyright (c) 2021, Intel Corporation. All rights reserved.
+#  Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -118,6 +118,14 @@
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x1000
 #!endif
   gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x4
+
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
 [PcdsFeatureFlag.common]
   ##
   # Edk2 Configuration
-- 
2.27.0.windows.1



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[edk2-devel] [edk2-platforms] [PATCH V2 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu 
Cc: Michael Kubacki 
Cc: Rangasai V Chaganty 
Cc: Deepika Kethi Reddy 
Cc: Kathappan Esakkithevar 
Signed-off-by: Nate DeSimone 
---
 .../CometlakeURvp/OpenBoardPkgPcd.dsc| 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git 
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc 
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 589b002d06..68dd08423b 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the CometlakeURvp board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -253,6 +253,13 @@
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   #
   # The PCDs are used to control the Windows SMM Security Mitigations Table - 
Protection Flags
   #
-- 
2.27.0.windows.1



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[edk2-devel] [edk2-platforms] [PATCH V2 0/4] Enable CPU pwr mgmt in FADT for Intel client boards

[Nate DeSimone]

Changes in V2:
 - Moved FSP dispatch mode PCD additions for GalagoPro3 to a seperate patch 
series

This patch series sets the DUTY_OFFSET and DUTY_WIDTH fields in the ACPI FADT
to 1 and 3 respectively. This will enable OS power management to set the CPU
clock speed in the P_CNT register on these platforms.

Cc: Chasel Chiu 
Cc: Ankit Sinha 
Cc: Sai Chaganty 
Cc: Michael Kubacki 
Cc: Heng Luo 
Cc: Deepika Kethi Reddy 
Cc: Kathappan Esakkithevar 
Cc: Benjamin Doron 
Cc: Jeremy Soller 
Signed-off-by: Nate DeSimone 

Nate DeSimone (4):
  KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

 .../CometlakeURvp/OpenBoardPkgPcd.dsc |  9 -
 .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc |  9 -
 .../GalagoPro3/OpenBoardPkgPcd.dsc|  8 +++-
 .../KabylakeRvp3/OpenBoardPkgPcd.dsc  | 11 +--
 .../TigerlakeURvp/OpenBoardPkgPcd.dsc | 10 +-
 .../UpXtreme/OpenBoardPkgPcd.dsc  |  9 -
 .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc   |  9 -
 7 files changed, 57 insertions(+), 8 deletions(-)

-- 
2.27.0.windows.1



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Thanks for the feedback Michael. This has been addressed in the new V2 series.

-Original Message-
From: Michael Kubacki  
Sent: Monday, June 6, 2022 3:56 PM
To: devel@edk2.groups.io; Desimone, Nathaniel L 
Cc: Chiu, Chasel ; Sinha, Ankit ; 
Kubacki, Michael ; Benjamin Doron 
; Soller, Jeremy 
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: 
Indicate width of CLK duty cycle in FADT

It seems the FSP changes should at least be in a separate commit even if a part 
of this overall series.

Regards,
Michael

On 6/6/2022 6:50 PM, Nate DeSimone wrote:
> Set the location of the DUTY_CYCLE field in the P_CNT register and 
> indicate the width of the clock duty cycle to OS power management
> 
> Merged missing PCD settings into GalagoPro3
> 
> Cc: Chasel Chiu 
> Cc: Ankit Sinha 
> Cc: Michael Kubacki 
> Cc: Benjamin Doron 
> Cc: Jeremy Soller 
> Signed-off-by: Nate DeSimone 
> ---
>   .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc |  9 +++-
>   .../GalagoPro3/OpenBoardPkgPcd.dsc| 52 +--
>   .../KabylakeRvp3/OpenBoardPkgPcd.dsc  | 11 +++-
>   3 files changed, 65 insertions(+), 7 deletions(-)
> 
> diff --git 
> a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc 
> b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> index 21ee86403d..02080aa864 100644
> --- 
> a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP
> +++ kgPcd.dsc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the Aspire VN7-572G board.
>   #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights 
> reserved.
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights 
> +reserved.
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -346,6 +346,13 @@
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and 
> BIOS Guard not present, measured boot enforcement checking code not present
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>   
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  # 
> + and indicate the width of the clock duty cycle to OS power 
> + management  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
> ##
> # Platform Configuration
> ##
> diff --git 
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc 
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> index 44dacdf082..26e2c16aae 100644
> --- 
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.d
> +++ sc
> @@ -1,7 +1,7 @@
>   ## @file
>   #  PCD configuration build description file for the GalagoPro3 board.
>   #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights 
> reserved.
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights 
> +reserved.
>   #
>   # SPDX-License-Identifier: BSD-2-Clause-Patent
>   #
> @@ -40,6 +40,26 @@
> #
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
>   
> +  #
> +  # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
> +  #(both inside FSP and outside FSP).
> +  #Pros:
> +  #  * PEI Main is re-built from source and is always the latest 
> version
> +  #  * Platform code can link any desired LibraryClass to PEI Main
> +  #(Ex: Custom DebugLib instance, SerialPortLib, etc.)
> +  #Cons:
> +  #  * The PEI Main being used to execute FSP PEIMs is not the PEI 
> Main
> +  #that the FSP PEIMs were tested with, adding risk of breakage.
> +  #  * Two copies of PEI Main will exist in the final binary,
> +  ##1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
> +  #executed, wasting space.
> +  #
> +  # TRUE:  The PEI Main included in FSP is used to dispatch all PEIMs
> +  #(both inside FSP and outside FSP). PEI Main will not be included 
> in
> +  #FvPreMemory. This is the default and is the recommended choice.
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
> +
> #
> # FSP Base address PCD will be updated in FDF basing on flash map.
> #
> @@ -52,6 +72,7 @@
> gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x0004
> gSiPkgTokenSpaceGuid.PcdTsegSize|0x100
>   
> +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
> #
> # FSP API mode does not share stack with the boot loader,
> # so FSP needs more temporary memory for FSP heap + stack size.
> @@ -63,6 +84,24 @@
> # since the stacks are separate.
> #
> gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x2
> +!else
> +  #
> +  # In FSP 

[edk2-devel] [edk2-platforms] [PATCH V2 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu 
Cc: Michael Kubacki 
Cc: Benjamin Doron 
Cc: Jeremy Soller 
Signed-off-by: Nate DeSimone 
---
 .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc |  9 -
 .../GalagoPro3/OpenBoardPkgPcd.dsc|  8 +++-
 .../KabylakeRvp3/OpenBoardPkgPcd.dsc  | 11 +--
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git 
a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index 21ee86403d..02080aa864 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the Aspire VN7-572G board.
 #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -346,6 +346,13 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and BIOS 
Guard not present, measured boot enforcement checking code not present
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ##
   # Platform Configuration
   ##
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index 44dacdf082..dce4db17c2 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the GalagoPro3 board.
 #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -251,6 +251,12 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
   
gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
   
gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
diff --git 
a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 725596cbf7..ccf757e202 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the KabylakeRvp3 board.
 #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -78,6 +78,7 @@
   # so FSP needs more temporary memory for FSP heap + stack size.
   #
   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
+
   #
   # FSP API mode does not need to enlarge the boot loader stack size
   # since the stacks are separate.
@@ -290,6 +291,13 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ##
   # Platform Configuration
   ##
@@ -346,7 +354,6 @@
   gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 
0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
0x00}
 !endif
 
-
   ##
   # Board Configuration
   ##
-- 
2.27.0.windows.1



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Re: [edk2-devel] [edk2-platforms] [PATCH V1] KabylakeOpenBoardPkg/GalagoPro3: Add FSP Dispatch Mode PCDs

[Sinha, Ankit]

Reviewed-by: Ankit Sinha 

> -Original Message-
> From: Desimone, Nathaniel L 
> Sent: Monday, June 6, 2022 4:09 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Sinha, Ankit
> ; Kubacki, Michael
> ; Soller, Jeremy
> 
> Subject: [edk2-platforms] [PATCH V1] KabylakeOpenBoardPkg/GalagoPro3:
> Add FSP Dispatch Mode PCDs
> 
> Adds missing FSP dispatch mode PCDs to the Galago Pro 3.
> 
> Cc: Chasel Chiu 
> Cc: Ankit Sinha 
> Cc: Michael Kubacki 
> Cc: Jeremy Soller 
> Signed-off-by: Nate DeSimone 
> ---
>  .../GalagoPro3/OpenBoardPkgPcd.dsc| 46 +--
>  1 file changed, 42 insertions(+), 4 deletions(-)
> 
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.ds
> c
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.ds
> c
> index 44dacdf082..28f044df5e 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.ds
> c
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.ds
> c
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the GalagoPro3 board.
>  #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights
> +reserved.
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -40,6 +40,26 @@
>#
>gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
> 
> +  #
> +  # FALSE: The PEI Main included in FvPreMemory is used to dispatch all
> PEIMs
> +  #(both inside FSP and outside FSP).
> +  #Pros:
> +  #  * PEI Main is re-built from source and is always the latest 
> version
> +  #  * Platform code can link any desired LibraryClass to PEI Main
> +  #(Ex: Custom DebugLib instance, SerialPortLib, etc.)
> +  #Cons:
> +  #  * The PEI Main being used to execute FSP PEIMs is not the PEI 
> Main
> +  #that the FSP PEIMs were tested with, adding risk of breakage.
> +  #  * Two copies of PEI Main will exist in the final binary,
> +  ##1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
> +  #executed, wasting space.
> +  #
> +  # TRUE:  The PEI Main included in FSP is used to dispatch all PEIMs
> +  #(both inside FSP and outside FSP). PEI Main will not be included 
> in
> +  #FvPreMemory. This is the default and is the recommended choice.
> +  #
> +
> gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TR
> UE
> +
>#
># FSP Base address PCD will be updated in FDF basing on flash map.
>#
> @@ -52,6 +72,7 @@
>gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x0004
>gSiPkgTokenSpaceGuid.PcdTsegSize|0x100
> 
> +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
>#
># FSP API mode does not share stack with the boot loader,
># so FSP needs more temporary memory for FSP heap + stack size.
> @@ -63,6 +84,24 @@
># since the stacks are separate.
>#
>gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x2
> +!else
> +  #
> +  # In FSP Dispatch mode boot loader stack size must be large
> +  # enough for executing both boot loader and FSP.
> +  #
> +  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x4
> +!endif
> +
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE)
> ||
> +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
> +
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpa
> ceGui
> +d.PcdPciExpressBaseAddress
> +
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTok
> enSp
> +aceGuid.PcdPciExpressRegionLength
> +!else
> +  #
> +  # FSP Dispatch mode requires more platform memory as boot loader and
> +FSP sharing the same
> +  # platform memory.
> +  #
> +  gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x550
> +!endif
> 
>  [PcdsFeatureFlag.common]
>##
> @@ -222,7 +261,7 @@
>gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
>gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1
>gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2
> -
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE)
> ||
> +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
>#
># In non-FSP build (EDK2 build) or FSP API mode below PCD are
> FixedAtBuild
># (They will be DynamicEx in FSP Dispatch mode) @@ -242,6 +281,7 @@
>#  3: Place AP in the Run-Loop state.
># @Prompt The AP wait loop state.
>gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
> +!endif
> 
>##
># Silicon Configuration
> @@ -251,8 +291,6 @@
>gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
>gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
> 
> -
> gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpac
> eGuid.PcdPciExpressBaseAddress
> -
> gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgToke
> 

Re: [edk2-devel] [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Sinha, Ankit]

Reviewed-by: Ankit Sinha 

> -Original Message-
> From: Desimone, Nathaniel L 
> Sent: Monday, June 6, 2022 3:51 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Sinha, Ankit
> ; Kubacki, Michael
> ; Luo, Heng 
> Subject: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate
> the width of the clock duty cycle to OS power management
> 
> Cc: Sai Chaganty 
> Cc: Ankit Sinha 
> Cc: Michael Kubacki 
> Cc: Heng Luo 
> Signed-off-by: Nate DeSimone 
> ---
>  .../TigerlakeURvp/OpenBoardPkgPcd.dsc  | 10 +-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> .dsc
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> .dsc
> index ebbbc7b9f9..aba3c8d6d0 100644
> ---
> a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> .dsc
> +++
> b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> +++ .dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the TigerlakeURvp board.
>  #
> -#  Copyright (c) 2021, Intel Corporation. All rights reserved.
> +#  Copyright (c) 2021 - 2022, Intel Corporation. All rights
> +reserved.
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent  #  ## @@ -118,6 +118,14
> @@
>gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x1000
>  #!endif
>gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x4
> +
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>  [PcdsFeatureFlag.common]
>##
># Edk2 Configuration
> --
> 2.27.0.windows.1



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Sinha, Ankit]

Reviewed-by: Ankit Sinha 

> -Original Message-
> From: Desimone, Nathaniel L 
> Sent: Monday, June 6, 2022 3:50 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Sinha, Ankit
> ; Kubacki, Michael
> ; Chaganty, Rangasai V
> ; Kethi Reddy, Deepika
> ; Esakkithevar, Kathappan
> 
> Subject: [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate
> the width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu 
> Cc: Ankit Sinha 
> Cc: Michael Kubacki 
> Cc: Sai Chaganty 
> Cc: Deepika Kethi Reddy 
> Cc: Kathappan Esakkithevar 
> Signed-off-by: Nate DeSimone 
> ---
>  .../CometlakeURvp/OpenBoardPkgPcd.dsc| 9 -
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd.dsc
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd.dsc
> index 589b002d06..68dd08423b 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd.dsc
> +++
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkg
> Pcd
> +++ .dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the CometlakeURvp board.
>  #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights
> +reserved.
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -253,6 +253,13 @@
>gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
>gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>#
># The PCDs are used to control the Windows SMM Security Mitigations
> Table - Protection Flags
>#
> --
> 2.27.0.windows.1



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Sinha, Ankit]

Reviewed-by: Ankit Sinha 

> -Original Message-
> From: Desimone, Nathaniel L 
> Sent: Monday, June 6, 2022 3:50 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Sinha, Ankit
> ; Kubacki, Michael
> 
> Subject: [edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg:
> Indicate width of CLK duty cycle in FADT
> 
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate
> the width of the clock duty cycle to OS power management
> 
> Cc: Chasel Chiu 
> Cc: Ankit Sinha 
> Cc: Michael Kubacki 
> Signed-off-by: Nate DeSimone 
> ---
>  .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9
> -
>  .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc  | 9 -
>  2 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.
> dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.
> dsc
> index 84d4ec1331..8f3cc6ba28 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.
> dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.
> ds
> +++ c
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the UpXtreme board.
>  #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights
> +reserved.
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -259,6 +259,13 @@
>gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
> 
> gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgToken
> SpaceGuid.PcdPciExpressRegionLength
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>##
># Platform Configuration
>##
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> PkgPcd.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> PkgPcd.dsc
> index 4a7ba4d5f0..4a5d5ef03b 100644
> ---
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> PkgPcd.dsc
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoard
> Pk
> +++ gPcd.dsc
> @@ -1,7 +1,7 @@
>  ## @file
>  #  PCD configuration build description file for the WhiskeylakeURvp board.
>  #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights
> +reserved.
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -242,6 +242,13 @@
>##
> 
> gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgToken
> SpaceGuid.PcdPciExpressRegionLength
> 
> +  #
> +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>##
># Platform Configuration
>##
> --
> 2.27.0.windows.1



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[edk2-devel] [edk2-platforms] [PATCH V1] KabylakeOpenBoardPkg/GalagoPro3: Add FSP Dispatch Mode PCDs

[Nate DeSimone]

Adds missing FSP dispatch mode PCDs to the Galago Pro 3.

Cc: Chasel Chiu 
Cc: Ankit Sinha 
Cc: Michael Kubacki 
Cc: Jeremy Soller 
Signed-off-by: Nate DeSimone 
---
 .../GalagoPro3/OpenBoardPkgPcd.dsc| 46 +--
 1 file changed, 42 insertions(+), 4 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index 44dacdf082..28f044df5e 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the GalagoPro3 board.
 #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -40,6 +40,26 @@
   #
   gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
 
+  #
+  # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
+  #(both inside FSP and outside FSP).
+  #Pros:
+  #  * PEI Main is re-built from source and is always the latest 
version
+  #  * Platform code can link any desired LibraryClass to PEI Main
+  #(Ex: Custom DebugLib instance, SerialPortLib, etc.)
+  #Cons:
+  #  * The PEI Main being used to execute FSP PEIMs is not the PEI Main
+  #that the FSP PEIMs were tested with, adding risk of breakage.
+  #  * Two copies of PEI Main will exist in the final binary,
+  ##1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
+  #executed, wasting space.
+  #
+  # TRUE:  The PEI Main included in FSP is used to dispatch all PEIMs
+  #(both inside FSP and outside FSP). PEI Main will not be included in
+  #FvPreMemory. This is the default and is the recommended choice.
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
+
   #
   # FSP Base address PCD will be updated in FDF basing on flash map.
   #
@@ -52,6 +72,7 @@
   gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x0004
   gSiPkgTokenSpaceGuid.PcdTsegSize|0x100
 
+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
   #
   # FSP API mode does not share stack with the boot loader,
   # so FSP needs more temporary memory for FSP heap + stack size.
@@ -63,6 +84,24 @@
   # since the stacks are separate.
   #
   gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x2
+!else
+  #
+  # In FSP Dispatch mode boot loader stack size must be large
+  # enough for executing both boot loader and FSP.
+  #
+  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x4
+!endif
+
+!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || 
(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
+  
gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+  
gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
+!else
+  #
+  # FSP Dispatch mode requires more platform memory as boot loader and FSP 
sharing the same
+  # platform memory.
+  #
+  gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x550
+!endif
 
 [PcdsFeatureFlag.common]
   ##
@@ -222,7 +261,7 @@
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2
-
+!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || 
(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
   #
   # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
   # (They will be DynamicEx in FSP Dispatch mode)
@@ -242,6 +281,7 @@
   #  3: Place AP in the Run-Loop state.
   # @Prompt The AP wait loop state.
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
+!endif
 
   ##
   # Silicon Configuration
@@ -251,8 +291,6 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
-  
gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
-  
gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
   ##
   # Platform Configuration
-- 
2.27.0.windows.1



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

Reviewed-by: Michael Kubacki 

On 6/6/2022 6:50 PM, Nate DeSimone wrote:

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Sai Chaganty 
Cc: Ankit Sinha 
Cc: Michael Kubacki 
Cc: Heng Luo 
Signed-off-by: Nate DeSimone 
---
  .../TigerlakeURvp/OpenBoardPkgPcd.dsc  | 10 +-
  1 file changed, 9 insertions(+), 1 deletion(-)

diff --git 
a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc 
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index ebbbc7b9f9..aba3c8d6d0 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
  ## @file
  #  PCD configuration build description file for the TigerlakeURvp board.
  #
-#  Copyright (c) 2021, Intel Corporation. All rights reserved.
+#  Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
  #  SPDX-License-Identifier: BSD-2-Clause-Patent
  #
  ##
@@ -118,6 +118,14 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x1000
  #!endif
gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x4
+
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
  [PcdsFeatureFlag.common]
##
# Edk2 Configuration



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

Reviewed-by: Michael Kubacki 

On 6/6/2022 6:50 PM, Nate DeSimone wrote:

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu 
Cc: Ankit Sinha 
Cc: Michael Kubacki 
Cc: Sai Chaganty 
Cc: Deepika Kethi Reddy 
Cc: Kathappan Esakkithevar 
Signed-off-by: Nate DeSimone 
---
  .../CometlakeURvp/OpenBoardPkgPcd.dsc| 9 -
  1 file changed, 8 insertions(+), 1 deletion(-)

diff --git 
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc 
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 589b002d06..68dd08423b 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
  ## @file
  #  PCD configuration build description file for the CometlakeURvp board.
  #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -253,6 +253,13 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
  
+  #

+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
#
# The PCDs are used to control the Windows SMM Security Mitigations Table - 
Protection Flags
#



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

Reviewed-by: Michael Kubacki 

On 6/6/2022 6:50 PM, Nate DeSimone wrote:

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu 
Cc: Ankit Sinha 
Cc: Michael Kubacki 
Signed-off-by: Nate DeSimone 
---
  .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 -
  .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc  | 9 -
  2 files changed, 16 insertions(+), 2 deletions(-)

diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
index 84d4ec1331..8f3cc6ba28 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
  ## @file
  #  PCD configuration build description file for the UpXtreme board.
  #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -259,6 +259,13 @@
gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2

gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
  
+  #

+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
##
# Platform Configuration
##
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index 4a7ba4d5f0..4a5d5ef03b 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
  ## @file
  #  PCD configuration build description file for the WhiskeylakeURvp board.
  #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -242,6 +242,13 @@
##

gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
  
+  #

+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
##
# Platform Configuration
##



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Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Michael Kubacki]

It seems the FSP changes should at least be in a separate commit even if 
a part of this overall series.


Regards,
Michael

On 6/6/2022 6:50 PM, Nate DeSimone wrote:

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Merged missing PCD settings into GalagoPro3

Cc: Chasel Chiu 
Cc: Ankit Sinha 
Cc: Michael Kubacki 
Cc: Benjamin Doron 
Cc: Jeremy Soller 
Signed-off-by: Nate DeSimone 
---
  .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc |  9 +++-
  .../GalagoPro3/OpenBoardPkgPcd.dsc| 52 +--
  .../KabylakeRvp3/OpenBoardPkgPcd.dsc  | 11 +++-
  3 files changed, 65 insertions(+), 7 deletions(-)

diff --git 
a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index 21ee86403d..02080aa864 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
  ## @file
  #  PCD configuration build description file for the Aspire VN7-572G board.
  #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -346,6 +346,13 @@
gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and BIOS 
Guard not present, measured boot enforcement checking code not present
gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
  
+  #

+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
##
# Platform Configuration
##
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index 44dacdf082..26e2c16aae 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
  ## @file
  #  PCD configuration build description file for the GalagoPro3 board.
  #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
  #
  # SPDX-License-Identifier: BSD-2-Clause-Patent
  #
@@ -40,6 +40,26 @@
#
gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
  
+  #

+  # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
+  #(both inside FSP and outside FSP).
+  #Pros:
+  #  * PEI Main is re-built from source and is always the latest 
version
+  #  * Platform code can link any desired LibraryClass to PEI Main
+  #(Ex: Custom DebugLib instance, SerialPortLib, etc.)
+  #Cons:
+  #  * The PEI Main being used to execute FSP PEIMs is not the PEI Main
+  #that the FSP PEIMs were tested with, adding risk of breakage.
+  #  * Two copies of PEI Main will exist in the final binary,
+  ##1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
+  #executed, wasting space.
+  #
+  # TRUE:  The PEI Main included in FSP is used to dispatch all PEIMs
+  #(both inside FSP and outside FSP). PEI Main will not be included in
+  #FvPreMemory. This is the default and is the recommended choice.
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
+
#
# FSP Base address PCD will be updated in FDF basing on flash map.
#
@@ -52,6 +72,7 @@
gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x0004
gSiPkgTokenSpaceGuid.PcdTsegSize|0x100
  
+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1

#
# FSP API mode does not share stack with the boot loader,
# so FSP needs more temporary memory for FSP heap + stack size.
@@ -63,6 +84,24 @@
# since the stacks are separate.
#
gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x2
+!else
+  #
+  # In FSP Dispatch mode boot loader stack size must be large
+  # enough for executing both boot loader and FSP.
+  #
+  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x4
+!endif
+
+!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || 
(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
+  
gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+  
gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
+!else
+  #
+  # FSP Dispatch mode requires more platform memory as boot loader and FSP 
sharing the same
+  # platform memory.
+  #
+  

[edk2-devel] [edk2-platforms] [PATCH V1 2/4] WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu 
Cc: Ankit Sinha 
Cc: Michael Kubacki 
Signed-off-by: Nate DeSimone 
---
 .../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 9 -
 .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc  | 9 -
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
index 84d4ec1331..8f3cc6ba28 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the UpXtreme board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -259,6 +259,13 @@
   gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber|2
   
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ##
   # Platform Configuration
   ##
diff --git 
a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index 4a7ba4d5f0..4a5d5ef03b 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the WhiskeylakeURvp board.
 #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -242,6 +242,13 @@
   ##
   
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ##
   # Platform Configuration
   ##
-- 
2.27.0.windows.1



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[edk2-devel] [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Sai Chaganty 
Cc: Ankit Sinha 
Cc: Michael Kubacki 
Cc: Heng Luo 
Signed-off-by: Nate DeSimone 
---
 .../TigerlakeURvp/OpenBoardPkgPcd.dsc  | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git 
a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc 
b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index ebbbc7b9f9..aba3c8d6d0 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the TigerlakeURvp board.
 #
-#  Copyright (c) 2021, Intel Corporation. All rights reserved.
+#  Copyright (c) 2021 - 2022, Intel Corporation. All rights reserved.
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -118,6 +118,14 @@
   gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x1000
 #!endif
   gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x4
+
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
 [PcdsFeatureFlag.common]
   ##
   # Edk2 Configuration
-- 
2.27.0.windows.1



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[edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Merged missing PCD settings into GalagoPro3

Cc: Chasel Chiu 
Cc: Ankit Sinha 
Cc: Michael Kubacki 
Cc: Benjamin Doron 
Cc: Jeremy Soller 
Signed-off-by: Nate DeSimone 
---
 .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc |  9 +++-
 .../GalagoPro3/OpenBoardPkgPcd.dsc| 52 +--
 .../KabylakeRvp3/OpenBoardPkgPcd.dsc  | 11 +++-
 3 files changed, 65 insertions(+), 7 deletions(-)

diff --git 
a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index 21ee86403d..02080aa864 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the Aspire VN7-572G board.
 #
-# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -346,6 +346,13 @@
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2  # FIXME: Boot Guard and BIOS 
Guard not present, measured boot enforcement checking code not present
   gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   ##
   # Platform Configuration
   ##
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc 
b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index 44dacdf082..26e2c16aae 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the GalagoPro3 board.
 #
-# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -40,6 +40,26 @@
   #
   gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
 
+  #
+  # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
+  #(both inside FSP and outside FSP).
+  #Pros:
+  #  * PEI Main is re-built from source and is always the latest 
version
+  #  * Platform code can link any desired LibraryClass to PEI Main
+  #(Ex: Custom DebugLib instance, SerialPortLib, etc.)
+  #Cons:
+  #  * The PEI Main being used to execute FSP PEIMs is not the PEI Main
+  #that the FSP PEIMs were tested with, adding risk of breakage.
+  #  * Two copies of PEI Main will exist in the final binary,
+  ##1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
+  #executed, wasting space.
+  #
+  # TRUE:  The PEI Main included in FSP is used to dispatch all PEIMs
+  #(both inside FSP and outside FSP). PEI Main will not be included in
+  #FvPreMemory. This is the default and is the recommended choice.
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
+
   #
   # FSP Base address PCD will be updated in FDF basing on flash map.
   #
@@ -52,6 +72,7 @@
   gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x0004
   gSiPkgTokenSpaceGuid.PcdTsegSize|0x100
 
+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
   #
   # FSP API mode does not share stack with the boot loader,
   # so FSP needs more temporary memory for FSP heap + stack size.
@@ -63,6 +84,24 @@
   # since the stacks are separate.
   #
   gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x2
+!else
+  #
+  # In FSP Dispatch mode boot loader stack size must be large
+  # enough for executing both boot loader and FSP.
+  #
+  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x4
+!endif
+
+!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) || 
(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
+  
gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+  
gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
+!else
+  #
+  # FSP Dispatch mode requires more platform memory as boot loader and FSP 
sharing the same
+  # platform memory.
+  #
+  gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x550
+!endif
 
 [PcdsFeatureFlag.common]
   ##
@@ -222,7 +261,7 @@
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
   

[edk2-devel] [edk2-platforms] [PATCH V1 3/4] CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

[Nate DeSimone]

Set the location of the DUTY_CYCLE field in the P_CNT register
and indicate the width of the clock duty cycle to OS power management

Cc: Chasel Chiu 
Cc: Ankit Sinha 
Cc: Michael Kubacki 
Cc: Sai Chaganty 
Cc: Deepika Kethi Reddy 
Cc: Kathappan Esakkithevar 
Signed-off-by: Nate DeSimone 
---
 .../CometlakeURvp/OpenBoardPkgPcd.dsc| 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git 
a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc 
b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 589b002d06..68dd08423b 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -1,7 +1,7 @@
 ## @file
 #  PCD configuration build description file for the CometlakeURvp board.
 #
-# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -253,6 +253,13 @@
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
 
+  #
+  # Set the location of the DUTY_CYCLE field in the P_CNT register
+  # and indicate the width of the clock duty cycle to OS power management
+  #
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
+  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
+
   #
   # The PCDs are used to control the Windows SMM Security Mitigations Table - 
Protection Flags
   #
-- 
2.27.0.windows.1



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[edk2-devel] [edk2-platforms] [PATCH V1 0/4] Enable CPU pwr mgmt in FADT for Intel client boards

[Nate DeSimone]

This patch series sets the DUTY_OFFSET and DUTY_WIDTH fields in the ACPI FADT
to 1 and 3 respectively. This will enable OS power management to set the CPU
clock speed in the P_CNT register on these platforms.

Cc: Chasel Chiu 
Cc: Ankit Sinha 
Cc: Sai Chaganty 
Cc: Michael Kubacki 
Cc: Heng Luo 
Cc: Deepika Kethi Reddy 
Cc: Kathappan Esakkithevar 
Cc: Benjamin Doron 
Cc: Jeremy Soller 
Signed-off-by: Nate DeSimone 

Nate DeSimone (4):
  KabylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  WhiskeylakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  CometlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
  TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

 .../CometlakeURvp/OpenBoardPkgPcd.dsc |  9 +++-
 .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc |  9 +++-
 .../GalagoPro3/OpenBoardPkgPcd.dsc| 52 +--
 .../KabylakeRvp3/OpenBoardPkgPcd.dsc  | 11 +++-
 .../TigerlakeURvp/OpenBoardPkgPcd.dsc | 10 +++-
 .../UpXtreme/OpenBoardPkgPcd.dsc  |  9 +++-
 .../WhiskeylakeURvp/OpenBoardPkgPcd.dsc   |  9 +++-
 7 files changed, 98 insertions(+), 11 deletions(-)

-- 
2.27.0.windows.1



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Re: [edk2-devel] [edk2-platforms][PATCH v1 0/3] MinPlatformPkg: Add FADT duty offset and width PCDs

[Nate DeSimone]

The series has been pushed as ~3018b1f..61af470

-Original Message-
From: mikub...@linux.microsoft.com  
Sent: Monday, April 11, 2022 1:58 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Gao, Liming ; Dong, 
Eric 
Subject: [edk2-platforms][PATCH v1 0/3] MinPlatformPkg: Add FADT duty offset 
and width PCDs

From: Michael Kubacki 

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3543

Adds PCDs to the MinPlatformPkg DEC file so MinPlatformPkg consumers (board 
packages) can customize the DUTY_OFFSET and DUTY_CYCLE values in their build 
files.

The copy of AcpiPlatform in SimicsOpenBoardPkg is also updated to keep the 
change in sync with the source MinPlatformPkg module.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Eric Dong 
Signed-off-by: Michael Kubacki 

Michael Kubacki (3):
  MinPlatformPkg: Add FADT duty offset and duty width PCDs
  MinPlatformPkg/AcpiPlatform: Use FADT duty offset and width PCDs
  SimicsOpenBoardPkg/AcpiPlatform: Use FADT duty offset and width PCDs

 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c   
 |  3 +++
 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c  
 |  4 ++--
 
Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.c
   |  3 +++
 Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/Fadt/Fadt.c 
 |  4 ++--
 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf 
 |  2 ++
 Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec   
 | 15 +++
 
Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf
 |  2 ++
 7 files changed, 29 insertions(+), 4 deletions(-)

--
2.28.0.windows.1



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Re: [edk2-devel] [edk2-platforms][PATCH v1 0/3] MinPlatformPkg: Add FADT duty offset and width PCDs

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: mikub...@linux.microsoft.com  
Sent: Monday, April 11, 2022 1:58 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Gao, Liming ; Dong, 
Eric 
Subject: [edk2-platforms][PATCH v1 0/3] MinPlatformPkg: Add FADT duty offset 
and width PCDs

From: Michael Kubacki 

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3543

Adds PCDs to the MinPlatformPkg DEC file so MinPlatformPkg consumers (board 
packages) can customize the DUTY_OFFSET and DUTY_CYCLE values in their build 
files.

The copy of AcpiPlatform in SimicsOpenBoardPkg is also updated to keep the 
change in sync with the source MinPlatformPkg module.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Cc: Eric Dong 
Signed-off-by: Michael Kubacki 

Michael Kubacki (3):
  MinPlatformPkg: Add FADT duty offset and duty width PCDs
  MinPlatformPkg/AcpiPlatform: Use FADT duty offset and width PCDs
  SimicsOpenBoardPkg/AcpiPlatform: Use FADT duty offset and width PCDs

 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c   
 |  3 +++
 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c  
 |  4 ++--
 
Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.c
   |  3 +++
 Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/Fadt/Fadt.c 
 |  4 ++--
 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf 
 |  2 ++
 Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec   
 | 15 +++
 
Platform/Intel/SimicsOpenBoardPkg/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf
 |  2 ++
 7 files changed, 29 insertions(+), 4 deletions(-)

--
2.28.0.windows.1



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Re: [edk2-devel] [PATCH V1 1/1] .pytool: UncrustifyCheck: Set IgnoreFiles path relative to package path

[Michael Kubacki]

Reviewed-by: Michael Kubacki 

On 6/6/2022 3:52 PM, Kun Qin wrote:

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3942

`IgnoreFiles` tag is specified in the CI YAML files in each individual
packages. The current logic for UncrustifyCheck script bases specified
file paths from workspace, which requires the package name to be included
in each entry.

This change updates the ignore checking logic to be based on current
package path in order to reduce redundancy. It also keeps the consistency
of `IgnoreFiles` field other pytools such as SpellCheck and EccCheck.

Cc: Sean Brogan 
Cc: Bret Barkelew 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Michael Kubacki 

Signed-off-by: Kun Qin 
---
  .pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py 
b/.pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py
index 00d78864656f..8dc9ffe6945a 100644
--- a/.pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py
+++ b/.pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py
@@ -290,7 +290,7 @@ class UncrustifyCheck(ICiBuildPlugin):
  # This information is only used for reporting (not used here) and
  # the ignore lines are being passed directly as they are given to
  # this plugin.
-return parse_gitignore_lines(ignored_files, "Package configuration 
file", self._abs_workspace_path)
+return parse_gitignore_lines(ignored_files, "Package configuration 
file", self._abs_package_path)
  
  def _get_git_ignored_paths(self) -> List[str]:

  



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[edk2-devel] [PATCH V1 1/1] .pytool: UncrustifyCheck: Set IgnoreFiles path relative to package path

[Kun Qin]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3942

`IgnoreFiles` tag is specified in the CI YAML files in each individual
packages. The current logic for UncrustifyCheck script bases specified
file paths from workspace, which requires the package name to be included
in each entry.

This change updates the ignore checking logic to be based on current
package path in order to reduce redundancy. It also keeps the consistency
of `IgnoreFiles` field other pytools such as SpellCheck and EccCheck.

Cc: Sean Brogan 
Cc: Bret Barkelew 
Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Michael Kubacki 

Signed-off-by: Kun Qin 
---
 .pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py 
b/.pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py
index 00d78864656f..8dc9ffe6945a 100644
--- a/.pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py
+++ b/.pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py
@@ -290,7 +290,7 @@ class UncrustifyCheck(ICiBuildPlugin):
 # This information is only used for reporting (not used here) and
 # the ignore lines are being passed directly as they are given to
 # this plugin.
-return parse_gitignore_lines(ignored_files, "Package configuration 
file", self._abs_workspace_path)
+return parse_gitignore_lines(ignored_files, "Package configuration 
file", self._abs_package_path)
 
 def _get_git_ignored_paths(self) -> List[str]:
 
-- 
2.35.1.windows.2



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[edk2-devel] [PATCH V1 0/1] UncrustifyCheck ignore file list paths reduction

[Kun Qin]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3942

When UncrustifyCheck plugin checks against "IgnoreFiles" tag, the script
references the files relative to the workspace.

This will require all files listed under such category to specify the
package name in the corresponding package CI YAML file.

To resolve this issue, the ignore files' paths are changed to be based on
the applicable package path.

Patch v1 branch: https://github.com/kuqin12/edk2/pull/new/uncrustify_ignore_pkg

Cc: Sean Brogan 
Cc: Bret Barkelew 
Cc: Michael D Kinney 
Cc: Liming Gao 


Kun Qin (1):
  .pytool: UncrustifyCheck: Set IgnoreFiles path relative to package
path

 .pytool/Plugin/UncrustifyCheck/UncrustifyCheck.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.35.1.windows.2



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Re: [edk2-devel] [GSOC 2022] Adding Rust support to EDK II: Introducing Myself

[Michael Kubacki]

Hi Ayush,

We will be meeting weekly on Microsoft Teams. We're finalizing proposed 
meeting times given the three mentor time zones.


I will be sending you a meeting series invitation this week when that is 
done to check your availability as well.


Regards,
Michael

On 6/6/2022 7:54 AM, Ayush Singh wrote:

Hi Michael,

I was wondering when we can start the discussions about the project.
After doing some more research, I would like to make some changes to
the proposed schedule and iron out some implementation details.

So it would be great if you can clarify how and where the discussions
should take place.

Yours Sincerely
Ayush Singh

On Thu, May 26, 2022 at 2:20 AM Michael Kubacki
 wrote:


Hi Ayush,

Welcome! I'm excited about this project too and I look forward to
working you.

We will be reaching out soon to set up our regularly scheduled
discussions and meet you.

Regards,
Michael

On 5/21/2022 1:09 AM, Ayush Singh wrote:

Hello Everyone,

I am Ayush Singh, a 2nd-year university student from the Indian
Institute of Technology (Indian School of Mines), Dhanbad, India. In
Google Summer of Code 2022, I will be working on Adding Rust support
to EDK II. The original Task from the wiki can be found here:
https://github.com/tianocore/tianocore.github.io/wiki/Tasks-Add-Rust-Support-to-EDK-II

This email is just to formally introduce myself to the mailing list. I
hope I will be able to help improve the EDK II project during the
course of Google Summer of Code,  and even after that.

According to the GSoC dashboard, Michael Kinney and Michael Kubacki
are the mentors for this project, so I would like to get in touch with
them soon as well.

I look forward to working on this wonderful and exciting project.

Yours Sincerely
Ayush Singh







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[edk2-devel][PATCH v1 1/2] MdeModulePkg: Add EDKII_PCI_DEVICE_PPI definition

[Maciej Czajkowski]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3907

This commit introduces EDKII_PCI_DEVICE_PPI. The purpose of this PPI is
to provide a way of accessing PCI devices to drvice drivers such as
NvmExpressPei or AhciPei.

Cc: Hao A Wu 
Cc: Ray Ni 
Cc: Liming Gao 
Signed-off-by: Maciej Czajkowski 
---
 MdeModulePkg/Include/Ppi/PciDevice.h | 32 
 MdeModulePkg/MdeModulePkg.dec|  3 ++
 2 files changed, 35 insertions(+)

diff --git a/MdeModulePkg/Include/Ppi/PciDevice.h 
b/MdeModulePkg/Include/Ppi/PciDevice.h
new file mode 100644
index ..3e391c61f6d9
--- /dev/null
+++ b/MdeModulePkg/Include/Ppi/PciDevice.h
@@ -0,0 +1,32 @@
+/** @file
+
+  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _EDKII_PCI_DEVICE_PPI_H_
+#define _EDKII_PCI_DEVICE_PPI_H_
+
+#include 
+#include 
+
+///
+/// Global ID for the EDKII_PCI_DEVICE_PPI_GUID.
+///
+#define EDKII_PCI_DEVICE_PPI_GUID \
+  { \
+0x1597ab4f, 0xd542, 0x4efe, { 0x9a, 0xf7, 0xb2, 0x44, 0xec, 0x54, 0x4c, 
0x0b } \
+  }
+
+///
+/// PCI Device PPI structure.
+///
+typedef struct {
+  EFI_PCI_IO_PROTOCOL   PciIo;
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;
+} EDKII_PCI_DEVICE_PPI;
+
+extern EFI_GUID  gEdkiiPeiPciDevicePpiGuid;
+
+#endif
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 2bcb9f9453af..7d989108324a 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -509,6 +509,9 @@ [Ppis]
   ## Include/Ppi/NvmExpressPassThru.h
   gEdkiiPeiNvmExpressPassThruPpiGuid= { 0x6af31b2c, 0x3be, 0x46c1, { 0xb1, 
0x2d, 0xea, 0x4a, 0x36, 0xdf, 0xa7, 0x4c } }
 
+  ## Include/Ppi/PciDevice.h
+  gEdkiiPeiPciDevicePpiGuid = { 0x1597ab4f, 0xd542, 0x4efe, { 
0x9a, 0xf7, 0xb2, 0x44, 0xec, 0x54, 0x4c, 0x0b } }
+
   ## Include/Ppi/CapsuleOnDisk.h
   gEdkiiPeiCapsuleOnDiskPpiGuid = { 0x71a9ea61, 0x5a35, 0x4a5d, { 
0xac, 0xef, 0x9c, 0xf8, 0x6d, 0x6d, 0x67, 0xe0 } }
   gEdkiiPeiBootInCapsuleOnDiskModePpiGuid   = { 0xb08a11e4, 0xe2b7, 0x4b75, { 
0xb5, 0x15, 0xaf, 0x61, 0x6, 0x68, 0xbf, 0xd1  } }
-- 
2.27.0.windows.1

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[edk2-devel][PATCH v1 2/2] MdeModulePkg/AhciPei: Use PCI_DEVICE_PPI to manage AHCI device

[Maciej Czajkowski]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3907

This change modifies AhciPei library to allow usage both EDKII_PCI_DEVICE_PPI
and EDKII_PEI_ATA_AHCI_HOST_CONTROLLER_PPI to manage ATA HDD working under
AHCI mode.

Cc: Hao A Wu 
Cc: Ray Ni 
Signed-off-by: Maciej Czajkowski 
---
 MdeModulePkg/Bus/Ata/AhciPei/AhciPei.c| 615 +++-
 MdeModulePkg/Bus/Ata/AhciPei/DevicePath.c |  44 --
 MdeModulePkg/Bus/Ata/AhciPei/AhciPei.inf  |   5 +-
 3 files changed, 458 insertions(+), 206 deletions(-)

diff --git a/MdeModulePkg/Bus/Ata/AhciPei/AhciPei.c 
b/MdeModulePkg/Bus/Ata/AhciPei/AhciPei.c
index 208b7e9a3606..31bb3c0760ab 100644
--- a/MdeModulePkg/Bus/Ata/AhciPei/AhciPei.c
+++ b/MdeModulePkg/Bus/Ata/AhciPei/AhciPei.c
@@ -9,6 +9,47 @@
 **/
 
 #include "AhciPei.h"
+#include 
+#include 
+#include 
+
+/**
+  Callback for EDKII_ATA_AHCI_HOST_CONTROLLER_PPI installation.
+
+  @param[in] PeiServices Pointer to PEI Services Table.
+  @param[in] NotifyDescriptorPointer to the descriptor for the Notification
+ event that caused this function to execute.
+  @param[in] Ppi Pointer to the PPI data associated with this 
function.
+
+  @retval EFI_SUCCESSThe function completes successfully
+
+**/
+EFI_STATUS
+EFIAPI
+AtaAhciHostControllerPpiInstallationCallback (
+  IN EFI_PEI_SERVICES   **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
+  IN VOID   *Ppi
+  );
+
+/**
+  Callback for EDKII_PCI_DEVICE_PPI installation.
+
+  @param[in] PeiServices Pointer to PEI Services Table.
+  @param[in] NotifyDescriptorPointer to the descriptor for the Notification
+ event that caused this function to execute.
+  @param[in] Ppi Pointer to the PPI data associated with this 
function.
+
+  @retval EFI_SUCCESSThe function completes successfully
+
+**/
+EFI_STATUS
+EFIAPI
+AtaAhciPciDevicePpiInstallationCallback (
+  IN EFI_PEI_SERVICES   **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
+  IN VOID   *Ppi
+  );
 
 EFI_PEI_PPI_DESCRIPTOR  mAhciAtaPassThruPpiListTemplate = {
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
@@ -40,6 +81,18 @@ EFI_PEI_NOTIFY_DESCRIPTOR  mAhciEndOfPeiNotifyListTemplate = 
{
   AhciPeimEndOfPei
 };
 
+EFI_PEI_NOTIFY_DESCRIPTOR  mAtaAhciHostControllerNotify = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | 
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  AtaAhciHostControllerPpiInstallationCallback
+};
+
+EFI_PEI_NOTIFY_DESCRIPTOR  mPciDevicePpiNotify = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | 
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  ,
+  AtaAhciPciDevicePpiInstallationCallback
+};
+
 /**
   Free the DMA resources allocated by an ATA AHCI controller.
 
@@ -111,33 +164,28 @@ AhciPeimEndOfPei (
 }
 
 /**
-  Entry point of the PEIM.
+  Initialize and install PrivateData PPIs.
 
-  @param[in] FileHandle Handle of the file being invoked.
-  @param[in] PeiServicesDescribes the list of possible PEI Services.
-
-  @retval EFI_SUCCESSPPI successfully installed.
+  @param[in] PrivateA pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA data
+structure.
 
+  @retval EFI_SUCCESS  AHCI controller initialized and PPIs installed
+  @retval others   Failed to initialize AHCI controller
 **/
 EFI_STATUS
-EFIAPI
-AtaAhciPeimEntry (
-  IN EFI_PEI_FILE_HANDLE FileHandle,
-  IN CONST EFI_PEI_SERVICES  **PeiServices
+AtaAhciInitPrivateData (
+  IN UINTN MmioBase,
+  IN EFI_DEVICE_PATH_PROTOCOL  *DevicePath,
+  IN UINTN DevicePathLength
   )
 {
-  EFI_STATUS  Status;
-  EFI_BOOT_MODE   BootMode;
-  EDKII_ATA_AHCI_HOST_CONTROLLER_PPI  *AhciHcPpi;
-  UINT8   Controller;
-  UINTN   MmioBase;
-  UINTN   DevicePathLength;
-  EFI_DEVICE_PATH_PROTOCOL*DevicePath;
-  UINT32  PortBitMap;
-  PEI_AHCI_CONTROLLER_PRIVATE_DATA*Private;
-  UINT8   NumberOfPorts;
+  EFI_STATUSStatus;
+  UINT32PortBitMap;
+  UINT8 NumberOfPorts;
+  PEI_AHCI_CONTROLLER_PRIVATE_DATA  *Private;
+  EFI_BOOT_MODE BootMode;
 
-  DEBUG ((DEBUG_INFO, "%a: Enters.\n", __FUNCTION__));
+  DEBUG ((DEBUG_INFO, "Initializing private data for ATA\n"));
 
   //
   // Get the current boot mode.
@@ -149,19 +197,149 @@ AtaAhciPeimEntry (
   }
 
   //
-  // Locate the ATA AHCI host controller PPI.
-  //
-  Status = PeiServicesLocatePpi (
- ,
- 0,
- NULL,
- (VOID **)
- );
+  // Check validity of the device path of the ATA AHCI controller.
+  //
+  Status = 

[edk2-devel][PATCH v1 0/2] Add EDKII_PCI_DEVICE_PPI support to EDK2

[Maciej Czajkowski]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3907

The purpose of those changes is to introduce the way to enumerate and assign 
resources in PEI
for the systems with more than one PCI root. Here is a need to have an 
interface that will
support such a mechanizm.
For now, the part that performs the enumeration will be implemented in the 
silicon code.
Sample code can be seen here: 
https://github.com/mczaj/edk2-platforms/commit/d443062e58f9fba228869b54f2546d9735b3b506

Cc: Hao A Wu 
Cc: Ray Ni 
Cc: Liming Gao 

Maciej Czajkowski (2):
  MdeModulePkg: Add EDKII_PCI_DEVICE_PPI definition
  MdeModulePkg/AhciPei: Use PCI_DEVICE_PPI to manage AHCI device

 MdeModulePkg/Bus/Ata/AhciPei/AhciPei.c| 615 +++-
 MdeModulePkg/Bus/Ata/AhciPei/DevicePath.c |  44 --
 MdeModulePkg/Bus/Ata/AhciPei/AhciPei.inf  |   5 +-
 MdeModulePkg/Include/Ppi/PciDevice.h  |  32 +
 MdeModulePkg/MdeModulePkg.dec |   3 +
 5 files changed, 493 insertions(+), 206 deletions(-)
 create mode 100644 MdeModulePkg/Include/Ppi/PciDevice.h

-- 
2.27.0.windows.1

-
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Re: [edk2-devel] [GSOC 2022] Adding Rust support to EDK II: Introducing Myself

[Ayush Singh]

Hi Michael,

I was wondering when we can start the discussions about the project.
After doing some more research, I would like to make some changes to
the proposed schedule and iron out some implementation details.

So it would be great if you can clarify how and where the discussions
should take place.

Yours Sincerely
Ayush Singh

On Thu, May 26, 2022 at 2:20 AM Michael Kubacki
 wrote:
>
> Hi Ayush,
>
> Welcome! I'm excited about this project too and I look forward to
> working you.
>
> We will be reaching out soon to set up our regularly scheduled
> discussions and meet you.
>
> Regards,
> Michael
>
> On 5/21/2022 1:09 AM, Ayush Singh wrote:
> > Hello Everyone,
> >
> > I am Ayush Singh, a 2nd-year university student from the Indian
> > Institute of Technology (Indian School of Mines), Dhanbad, India. In
> > Google Summer of Code 2022, I will be working on Adding Rust support
> > to EDK II. The original Task from the wiki can be found here:
> > https://github.com/tianocore/tianocore.github.io/wiki/Tasks-Add-Rust-Support-to-EDK-II
> >
> > This email is just to formally introduce myself to the mailing list. I
> > hope I will be able to help improve the EDK II project during the
> > course of Google Summer of Code,  and even after that.
> >
> > According to the GSoC dashboard, Michael Kinney and Michael Kubacki
> > are the mentors for this project, so I would like to get in touch with
> > them soon as well.
> >
> > I look forward to working on this wonderful and exciting project.
> >
> > Yours Sincerely
> > Ayush Singh
> >
> >
> > 
> >


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Re: [edk2-devel] [PATCH 5/5] CpuException: Add InitializeSeparateExceptionStacks

[Dong, Eric]

Acked-by: Eric Dong 

-Original Message-
From: Ni, Ray  
Sent: Friday, May 20, 2022 10:16 PM
To: devel@edk2.groups.io
Cc: Dong, Eric ; Wang, Jian J 
Subject: [PATCH 5/5] CpuException: Add InitializeSeparateExceptionStacks

Today InitializeCpuExceptionHandlersEx is called from three modules:
1. DxeCore (links to DxeCpuExceptionHandlerLib)
DxeCore expects it initializes the IDT entries as well as
assigning separate stacks for #DF and #PF.
2. CpuMpPei (links to PeiCpuExceptionHandlerLib)
   and CpuDxe (links to DxeCpuExceptionHandlerLib)
It's called for each thread for only assigning separate stacks for
#DF and #PF. The IDT entries initialization is skipped because
caller sets InitData->X64.InitDefaultHandlers to FALSE.

Additionally, SecPeiCpuExceptionHandlerLib, SmmCpuExceptionHandlerLib also 
implement such API and the behavior of the API is simply to initialize IDT 
entries only.

Because it mixes the IDT entries initialization and separate stacks assignment 
for certain exception handlers together, in order to know whether the function 
call only initializes IDT entries, or assigns stacks, we need to check:
1. value of InitData->X64.InitDefaultHandlers 2. library instance

This patch cleans up the code to separate the stack assignment to a new API:
InitializeSeparateExceptionStacks().

Only when caller calls the new API, the separate stacks are assigned.
With this change, the SecPei and Smm instance can return unsupported which 
gives caller a very clear status.

The old API InitializeCpuExceptionHandlersEx() is removed in this patch.
Because no platform module is consuming the old API, the impact is none.

Signed-off-by: Ray Ni 
Cc: Eric Dong 
Cc: Jian J Wang 
---
 MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c   |  2 +-
 .../Include/Library/CpuExceptionHandlerLib.h  | 24 ++---
 .../CpuExceptionHandlerLibNull.c  | 26 ++
 UefiCpuPkg/CpuDxe/CpuMp.c |  6 +-
 UefiCpuPkg/CpuMpPei/CpuMpPei.c|  4 +-
 .../CpuExceptionHandlerLib/DxeException.c | 91 ++-
 .../CpuExceptionHandlerLib/PeiCpuException.c  | 51 ++-
 .../SecPeiCpuException.c  | 27 ++
 .../CpuExceptionHandlerLib/SmmException.c | 27 ++
 9 files changed, 74 insertions(+), 184 deletions(-)

diff --git a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c 
b/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c
index 2c27fc0695..83f49d7c00 100644
--- a/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c
+++ b/MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c
@@ -253,7 +253,7 @@ DxeMain (
 VectorInfoList = (EFI_VECTOR_HANDOFF_INFO *)(GET_GUID_HOB_DATA (GuidHob)); 
  } -  Status = InitializeCpuExceptionHandlersEx (VectorInfoList, NULL);+  
Status = InitializeCpuExceptionHandlers (VectorInfoList);   ASSERT_EFI_ERROR 
(Status);//diff --git 
a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h 
b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
index d4649bebe1..9a495081f7 100644
--- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
+++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
@@ -103,32 +103,20 @@ InitializeCpuExceptionHandlers (
   );  /**-  Initializes all CPU exceptions entries with optional extra 
initializations.+  Setup separate stacks for certain exception handlers. -  By 
default, this method should include all functionalities implemented by-  
InitializeCpuExceptionHandlers(), plus extra initialization works, if any.-  
This could be done by calling InitializeCpuExceptionHandlers() directly-  in 
this method besides the extra works.+  InitData is optional and processor arch 
dependent. -  InitData is optional and its use and content are processor arch 
dependent.-  The typical usage of it is to convey resources which have to be 
reserved-  elsewhere and are necessary for the extra initializations of 
exception.+  @param[in]  InitData  Pointer to data optional for information 
about how+to assign stacks for certain exception 
handlers. -  @param[in]  VectorInfoPointer to reserved vector list.-  
@param[in]  InitData  Pointer to data optional for extra initializations-   
 of exception.--  @retval EFI_SUCCESS The 
exceptions have been successfully-  
initialized.-  @retval EFI_INVALID_PARAMETER   VectorInfo or InitData contains 
invalid-  content.+  @retval EFI_SUCCESS
 The stacks are assigned successfully.   @retval EFI_UNSUPPORTED 
This function is not supported.  **/ EFI_STATUS 
EFIAPI-InitializeCpuExceptionHandlersEx (-  IN EFI_VECTOR_HANDOFF_INFO  
*VectorInfo OPTIONAL,+InitializeSeparateExceptionStacks (   IN 
CPU_EXCEPTION_INIT_DATA  *InitData OPTIONAL   ); diff --git 
a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c 
b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c
index 54f38788fe..8aeedcb4d1 100644
--- 

Re: [edk2-devel] [PATCH 4/5] CpuException: Remove InitializeCpuInterruptHandlers

[Dong, Eric]

Acked-by: Eric Dong eric.d...@intel.com

From: Ni, Ray 
Sent: Tuesday, May 24, 2022 4:04 PM
To: Wang, Jian J ; devel@edk2.groups.io
Cc: Dong, Eric 
Subject: Re: [edk2-devel] [PATCH 4/5] CpuException: Remove 
InitializeCpuInterruptHandlers

Jian,
I think we need discussion on where to put the common CPU_INTERRUPT_NUM 
definition.

Do you agree that we can leave that to another patch?


From: Wang, Jian J mailto:jian.j.w...@intel.com>>
Sent: Monday, May 23, 2022 0:27
To: devel@edk2.groups.io; Ni, Ray
Cc: Dong, Eric
Subject: RE: [edk2-devel] [PATCH 4/5] CpuException: Remove 
InitializeCpuInterruptHandlers

Hi Ray,

Both CpuDxe.c and CpuExceptionCommon.h have CPU_INTERRUPT_NUM defined.
I'd suggest to move it to a common place, such as BaseLib.h. I don't see any 
issue
if they are defined to different value. It just gives me a feeling that it 
might cause
potential problems sometimes in the future.


Regards,
Jian

> -Original Message-
> From: devel@edk2.groups.io 
> mailto:devel@edk2.groups.io>> On Behalf Of Ni, Ray
> Sent: Friday, May 20, 2022 10:16 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric mailto:eric.d...@intel.com>>
> Subject: [edk2-devel] [PATCH 4/5] CpuException: Remove
> InitializeCpuInterruptHandlers
>
> InitializeCpuExceptionHandlers() expects caller allocates IDT while
> InitializeCpuInterruptHandlers() allocates 256 IDT entries itself.
>
> InitializeCpuExceptionHandlers() fills max 32 IDT entries allocated
> by caller. If caller allocates 10 entries, the API just fills 10 IDT
> entries.
>
> The inconsistency between the two APIs makes code hard to
> unerstand and hard to share.
>
> Because there is only one caller (CpuDxe) for
> InitializeCpuInterruptHandler(), this patch updates CpuDxe driver
> to allocates 256 IDT entries then call
> InitializeCpuExceptionHandlers().
>
> With this change, InitializeCpuInterruptHandlers() is removed
> completely.
>
> And InitializeCpuExceptionHandlers() fills max 32 entries for PEI
> and SMM instance, max 256 entries for DXE instance.
> Such behavior matches to the original one.
>
> Signed-off-by: Ray Ni mailto:ray...@intel.com>>
> Cc: Eric Dong mailto:eric.d...@intel.com>>
> ---
>  .../Include/Library/CpuExceptionHandlerLib.h  | 28 +--
>  .../CpuExceptionHandlerLibNull.c  | 31 +--
>  UefiCpuPkg/CpuDxe/CpuDxe.c| 33 ++--
>  .../CpuExceptionHandlerLib/DxeException.c | 80 ++-
>  .../CpuExceptionHandlerLib/PeiCpuException.c  | 61 +-
>  .../PeiDxeSmmCpuException.c   | 19 ++---
>  .../SecPeiCpuException.c  | 31 +--
>  .../CpuExceptionHandlerLib/SmmException.c | 35 ++--
>  8 files changed, 56 insertions(+), 262 deletions(-)
>
> diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> index 22a4408f9f..d4649bebe1 100644
> --- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> +++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
> @@ -2,7 +2,7 @@
>CPU Exception library provides the default CPU interrupt/exception handler.
>
>It also provides capability to register user interrupt/exception handler.
>
>
>
> -  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
>
> +  Copyright (c) 2012 - 2022, Intel Corporation. All rights reserved.
>
>SPDX-License-Identifier: BSD-2-Clause-Patent
>
>
>
>  **/
>
> @@ -132,28 +132,6 @@ InitializeCpuExceptionHandlersEx (
>IN CPU_EXCEPTION_INIT_DATA  *InitData OPTIONAL
>
>);
>
>
>
> -/**
>
> -  Initializes all CPU interrupt/exceptions entries and provides the default
> interrupt/exception handlers.
>
> -
>
> -  Caller should try to get an array of interrupt and/or exception vectors 
> that are
> in use and need to
>
> -  persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
>
> -  If caller cannot get reserved vector list or it does not exists, set 
> VectorInfo to
> NULL.
>
> -  If VectorInfo is not NULL, the exception vectors will be initialized per 
> vector
> attribute accordingly.
>
> -
>
> -  @param[in]  VectorInfoPointer to reserved vector list.
>
> -
>
> -  @retval EFI_SUCCESS   All CPU interrupt/exception entries have been
> successfully initialized
>
> -with default interrupt/exception handlers.
>
> -  @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if
> VectorInfo is not NULL.
>
> -  @retval EFI_UNSUPPORTED   This function is not supported.
>
> -
>
> -**/
>
> -EFI_STATUS
>
> -EFIAPI
>
> -InitializeCpuInterruptHandlers (
>
> -  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL
>
> -  );
>
> -
>
>  /**
>
>Registers a function to be called from the processor interrupt handler.
>
>
>
> @@ -161,8 +139,8 @@ InitializeCpuInterruptHandlers (
>

Re: [edk2-devel] [PATCH 3/5] CpuException: Avoid allocating page but using global variables

[Dong, Eric]

Acked-by: Eric Dong 

-Original Message-
From: Ni, Ray  
Sent: Friday, May 20, 2022 10:16 PM
To: devel@edk2.groups.io
Cc: Dong, Eric 
Subject: [PATCH 3/5] CpuException: Avoid allocating page but using global 
variables

Signed-off-by: Ray Ni 
Cc: Eric Dong 
---
 .../CpuExceptionHandlerLib/DxeException.c | 24 ---
 1 file changed, 5 insertions(+), 19 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
index da5b96d6c6..f139131a7c 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
@@ -14,8 +14,8 @@
 

 CONST UINTN  mDoFarReturnFlag = 0;

 

-RESERVED_VECTORS_DATA  mReservedVectorsData[CPU_EXCEPTION_NUM];

-EFI_CPU_INTERRUPT_HANDLER  mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];

+RESERVED_VECTORS_DATA  mReservedVectorsData[CPU_INTERRUPT_NUM];

+EFI_CPU_INTERRUPT_HANDLER  mExternalInterruptHandlerTable[CPU_INTERRUPT_NUM];

 EXCEPTION_HANDLER_DATA mExceptionHandlerData = {

   0,   // To be fixed

   0,   // To be fixed

@@ -96,27 +96,15 @@ InitializeCpuInterruptHandlers (
   IA32_DESCRIPTOR IdtDescriptor;

   UINTN   IdtEntryCount;

   EXCEPTION_HANDLER_TEMPLATE_MAP  TemplateMap;

-  RESERVED_VECTORS_DATA   *ReservedVectors;

-  EFI_CPU_INTERRUPT_HANDLER   *ExternalInterruptHandler;

-

-  Status = gBS->AllocatePool (

-  EfiBootServicesCode,

-  sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM,

-  (VOID **)

-  );

-  ASSERT (!EFI_ERROR (Status) && ReservedVectors != NULL);

-  SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * 
CPU_INTERRUPT_NUM, 0xff);

+

+  SetMem ((VOID *)mReservedVectorsData, sizeof (RESERVED_VECTORS_DATA) * 
CPU_INTERRUPT_NUM, 0xff);

   if (VectorInfo != NULL) {

-Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, 
CPU_INTERRUPT_NUM);

+Status = ReadAndVerifyVectorInfo (VectorInfo, mReservedVectorsData, 
CPU_INTERRUPT_NUM);

 if (EFI_ERROR (Status)) {

-  FreePool (ReservedVectors);

   return EFI_INVALID_PARAMETER;

 }

   }

 

-  ExternalInterruptHandler = AllocateZeroPool (sizeof 
(EFI_CPU_INTERRUPT_HANDLER) * CPU_INTERRUPT_NUM);

-  ASSERT (ExternalInterruptHandler != NULL);

-

   //

   // Read IDT descriptor and calculate IDT size

   //

@@ -137,8 +125,6 @@ InitializeCpuInterruptHandlers (
   ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);

 

   mExceptionHandlerData.IdtEntryCount= CPU_INTERRUPT_NUM;

-  mExceptionHandlerData.ReservedVectors  = ReservedVectors;

-  mExceptionHandlerData.ExternalInterruptHandler = ExternalInterruptHandler;

   InitializeSpinLock ();

 

   UpdateIdtTable (IdtTable, , );

-- 
2.35.1.windows.2



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Re: [edk2-devel] [PATCH 2/5] CpuException: Init global variables in-place

[Dong, Eric]

Acked-by: Eric Dong 

-Original Message-
From: Ni, Ray  
Sent: Friday, May 20, 2022 10:16 PM
To: devel@edk2.groups.io
Cc: Dong, Eric 
Subject: [PATCH 2/5] CpuException: Init global variables in-place

Additionally removed two useless global variables:
"SPIN_LOCK  mDisplayMessageSpinLock" from SMM instance.
"UINTN mEnabledInterruptNum" from DXE instance.

Signed-off-by: Ray Ni 
Cc: Eric Dong 
---
 .../Library/CpuExceptionHandlerLib/DxeException.c  | 11 ++-  
.../Library/CpuExceptionHandlerLib/SmmException.c  | 14 ++
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
index 5083c4b8e8..da5b96d6c6 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
@@ -16,9 +16,12 @@ CONST UINTN  mDoFarReturnFlag = 0;
  RESERVED_VECTORS_DATA  mReservedVectorsData[CPU_EXCEPTION_NUM]; 
EFI_CPU_INTERRUPT_HANDLER  
mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];-UINTN  
mEnabledInterruptNum = 0;--EXCEPTION_HANDLER_DATA  
mExceptionHandlerData;+EXCEPTION_HANDLER_DATA mExceptionHandlerData = {+  
0,   // To be fixed+  0,   // To be fixed+  mReservedVectorsData,+  
mExternalInterruptHandlerTable+};  UINT8  
mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *  
CPU_KNOWN_GOOD_STACK_SIZE];@@ -62,8 +65,6 @@ InitializeCpuExceptionHandlers (
   IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL   ) {-  
mExceptionHandlerData.ReservedVectors  = mReservedVectorsData;-  
mExceptionHandlerData.ExternalInterruptHandler = 
mExternalInterruptHandlerTable;   InitializeSpinLock 
();   return 
InitializeCpuExceptionHandlersWorker (VectorInfo, ); 
}diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
index 77ee74579f..9f0af4120a 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
@@ -11,14 +11,14 @@
  CONST UINTN  mDoFarReturnFlag = 1; -//-// Spin lock for CPU information 
display-//-SPIN_LOCK  mDisplayMessageSpinLock;- RESERVED_VECTORS_DATA  
mReservedVectorsData[CPU_EXCEPTION_NUM]; EFI_CPU_INTERRUPT_HANDLER  
mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];-EXCEPTION_HANDLER_DATA 
mExceptionHandlerData;+EXCEPTION_HANDLER_DATA mExceptionHandlerData = {+  
0,   // To be fixed+  0,   // To be fixed+  mReservedVectorsData,+  
mExternalInterruptHandlerTable+};  /**   Common exception handler.@@ -58,8 
+58,6 @@ InitializeCpuExceptionHandlers (
   IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL   ) {-  
mExceptionHandlerData.ReservedVectors  = mReservedVectorsData;-  
mExceptionHandlerData.ExternalInterruptHandler = 
mExternalInterruptHandlerTable;   InitializeSpinLock 
();   return 
InitializeCpuExceptionHandlersWorker (VectorInfo, ); }-- 
2.35.1.windows.2



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Re: [edk2-devel] [PATCH 1/5] CpuException: Avoid allocating code pages for DXE instance

[Dong, Eric]

Acked-by: Eric Dong 

From: Ni, Ray 
Sent: Tuesday, May 24, 2022 4:02 PM
To: Wang, Jian J ; devel@edk2.groups.io
Cc: Dong, Eric 
Subject: Re: [edk2-devel] [PATCH 1/5] CpuException: Avoid allocating code pages 
for DXE instance

Jian,
Ia32/ExceptionHandlerAsm.nasm is used by 32bit DxeCpuExceptionHandlerLib 
instance.

I agree the commit message is not correct. The commit message says
SEC still creates 32 entries but 32bit SEC creates 256 entries.

I will update the commit message to align to code behavior.

Thanks,
Ray


From: Wang, Jian J mailto:jian.j.w...@intel.com>>
Sent: Monday, May 23, 2022 0:40
To: devel@edk2.groups.io; Ni, Ray
Cc: Dong, Eric
Subject: RE: [edk2-devel] [PATCH 1/5] CpuException: Avoid allocating code pages 
for DXE instance

Ray,

You changed "%rep 32" to "%rep 256" in Ia32/ExceptionHandlerAsm.nasm.
According to my understanding and your comments, this should be done
only to X64 code, right?

Regards,
Jian

> -Original Message-
> From: devel@edk2.groups.io 
> mailto:devel@edk2.groups.io>> On Behalf Of Ni, Ray
> Sent: Friday, May 20, 2022 10:16 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric mailto:eric.d...@intel.com>>
> Subject: [edk2-devel] [PATCH 1/5] CpuException: Avoid allocating code pages
> for DXE instance
>
> Today the DXE instance allocates code page and then copies the IDT
> vectors to the allocated code page. Then it fixes up the vector number
> in the IDT vector.
>
> But if we update the NASM file to generate 256 IDT vectors, there is
> no need to do the copy and fix-up.
>
> A side effect is up to 4096 bytes (HOOKAFTER_STUB_SIZE * 256) is
> used for 256 IDT vectors. While 32 IDT vectors only require 512 bytes.
>
> But considering the code logic simplification, 3.5K space is not a big
> deal. SEC instance still generates 32 IDT vectors so no impact to SEC.
> If 3.5K is too much a waste in PEI phase, we can enhance the code
> further to generate 32 vectors for PEI.
>
> Signed-off-by: Ray Ni mailto:ray...@intel.com>>
> Cc: Eric Dong mailto:eric.d...@intel.com>>
> ---
>  .../CpuExceptionHandlerLib/DxeException.c | 22 ---
>  .../Ia32/ExceptionHandlerAsm.nasm |  4 ++--
>  .../X64/ExceptionHandlerAsm.nasm  |  2 ++
>  .../X64/Xcode5ExceptionHandlerAsm.nasm|  9 
>  4 files changed, 9 insertions(+), 28 deletions(-)
>
> diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> index 61f11e98f8..5083c4b8e8 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
> @@ -95,9 +95,6 @@ InitializeCpuInterruptHandlers (
>IA32_DESCRIPTOR IdtDescriptor;
>
>UINTN   IdtEntryCount;
>
>EXCEPTION_HANDLER_TEMPLATE_MAP  TemplateMap;
>
> -  UINTN   Index;
>
> -  UINTN   InterruptEntry;
>
> -  UINT8   *InterruptEntryCode;
>
>RESERVED_VECTORS_DATA   *ReservedVectors;
>
>EFI_CPU_INTERRUPT_HANDLER   *ExternalInterruptHandler;
>
>
>
> @@ -138,25 +135,6 @@ InitializeCpuInterruptHandlers (
>AsmGetTemplateAddressMap ();
>
>ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);
>
>
>
> -  Status = gBS->AllocatePool (
>
> -  EfiBootServicesCode,
>
> -  TemplateMap.ExceptionStubHeaderSize * CPU_INTERRUPT_NUM,
>
> -  (VOID **)
>
> -  );
>
> -  ASSERT (!EFI_ERROR (Status) && InterruptEntryCode != NULL);
>
> -
>
> -  InterruptEntry = (UINTN)InterruptEntryCode;
>
> -  for (Index = 0; Index < CPU_INTERRUPT_NUM; Index++) {
>
> -CopyMem (
>
> -  (VOID *)InterruptEntry,
>
> -  (VOID *)TemplateMap.ExceptionStart,
>
> -  TemplateMap.ExceptionStubHeaderSize
>
> -  );
>
> -AsmVectorNumFixup ((VOID *)InterruptEntry, (UINT8)Index, (VOID
> *)TemplateMap.ExceptionStart);
>
> -InterruptEntry += TemplateMap.ExceptionStubHeaderSize;
>
> -  }
>
> -
>
> -  TemplateMap.ExceptionStart = (UINTN)InterruptEntryCode;
>
>mExceptionHandlerData.IdtEntryCount= CPU_INTERRUPT_NUM;
>
>mExceptionHandlerData.ReservedVectors  = ReservedVectors;
>
>mExceptionHandlerData.ExternalInterruptHandler = ExternalInterruptHandler;
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nas
> m
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nas
> m
> index 3fe9aed1e8..8ed2b8f455 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nas
> m
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ExceptionHandlerAsm.nas
> m
> @@ -33,7 +33,7 @@ ALIGN   8
>  ;
>
>  AsmIdtVectorBegin:
>
>  %assign Vector 0
>
> -%rep  32
>
> +%rep