[edk2-devel] 回复: [Patch 1/1] MdePkg/Library/UefiDevicePathLib: Add back StandaloneMm INF file

[gaoliming via groups.io]

Reviewed-by: Liming Gao 

> -邮件原件-
> 发件人: Michael D Kinney 
> 发送时间: 2022年8月10日 12:38
> 收件人: devel@edk2.groups.io
> 抄送: Liming Gao ; Zhiguang Liu
> ; Mateusz Albecki ;
> Yanbo Huang 
> 主题: [Patch 1/1] MdePkg/Library/UefiDevicePathLib: Add back
> StandaloneMm INF file
> 
> REF: https://github.com/tianocore/edk2/pull/3130
> 
> The above PR removed UefiDevicePathLibStandaloneMm.inf, which is
> a non-backwards compatible change and does not provide time for
> downstream platforms to use the UefiDevicePathLibBase.inf.
> 
> Add UefiDevicePathLibStandaloneMm.inf back, but add comments that
> it is deprecated and that UefiDevicePathLibBase.inf should be used
> instead.
> 
> Cc: Liming Gao  [lgao4]
> Cc: Zhiguang Liu  [LiuZhiguang001]
> Cc: Mateusz Albecki 
> Cc: Yanbo Huang 
> Signed-off-by: Michael D Kinney 
> ---
>  .../UefiDevicePathLibStandaloneMm.inf | 78
> +++
>  MdePkg/MdePkg.dsc |  1 +
>  2 files changed, 79 insertions(+)
>  create mode 100644
> MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
> 
> diff --git
> a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
> b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
> new file mode 100644
> index ..97db485e23f8
> --- /dev/null
> +++
> b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
> @@ -0,0 +1,78 @@
> +## @file
> +# Instance of Device Path Library based on Memory Allocation Library.
> +#
> +# Device Path Library that layers on top of the Memory Allocation
Library.
> +#
> +# This library instances is deprecated and should no longer be used.  Ue
> +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf instead.
> +#
> +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) Microsoft Corporation.
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION= 0x00010005
> +  BASE_NAME  =
> UefiDevicePathLibStandaloneMm
> +  MODULE_UNI_FILE= UefiDevicePathLib.uni
> +  FILE_GUID  =
> 7B60A2BC-9259-48A8-8279-971412EECAB3
> +  MODULE_TYPE= BASE
> +  PI_SPECIFICATION_VERSION   = 0x00010032
> +  VERSION_STRING = 1.0
> +  LIBRARY_CLASS  = DevicePathLib
> +
> +
> +#
> +#  VALID_ARCHITECTURES   = IA32 X64 EBC
> +#
> +
> +[Sources]
> +  DevicePathUtilities.c
> +  DevicePathUtilitiesBase.c
> +  DevicePathToText.c
> +  DevicePathFromText.c
> +  UefiDevicePathLib.c
> +  UefiDevicePathLib.h
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> +  BaseLib
> +  MemoryAllocationLib
> +  DebugLib
> +  BaseMemoryLib
> +  PcdLib
> +  PrintLib
> +
> +[Guids]
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiVTUTF8Guid
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiVT100Guid
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiVT100PlusGuid
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiPcAnsiGuid
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiUartDevicePathGuid
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiSasDevicePathGuid
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiVirtualDiskGuid
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiVirtualCdGuid
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiPersistentVirtualDiskGuid
> +  ## SOMETIMES_CONSUMES  ## GUID
> +  gEfiPersistentVirtualCdGuid
> +
> +[Protocols]
> +  gEfiDevicePathProtocolGuid##
> SOMETIMES_CONSUMES
> +  gEfiDebugPortProtocolGuid ## UNDEFINED
> +
> +[Pcd]
> +  gEfiMdePkgTokenSpaceGuid.PcdMaximumDevicePathNodeCount##
> SOMETIMES_CONSUMES
> diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
> index 9daee93523e5..cc1ac196a931 100644
> --- a/MdePkg/MdePkg.dsc
> +++ b/MdePkg/MdePkg.dsc
> @@ -112,6 +112,7 @@ [Components]
>MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
>MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
>MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf
> +  MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
> 
> MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathPro
> tocol.inf
> 
> MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDe
> vicePathProtocol.inf
>MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> --
> 2.37.1.windows.1





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Re: [edk2-devel] [Patch V2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flag

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Wednesday, August 10, 2022 1:37 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R 
> Subject: [Patch V2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new
> mIsShadowStack flag
> 
> This patch is code refactoring and doesn't change any functionality.
> Add a new IsShadowStack flag to identify whether current memory is
> shadow stack. Previous smm code logic regards a RO range as shadow
> stack and set the dirty bit in corresponding page table entry if
> mInternalCr3 is not 0, which may be confusing.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 8
> +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> index 1f7cc15727..237742d7e6 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> @@ -33,6 +33,7 @@ PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {
>  };
> 
>  UINTN  mInternalCr3;
> +UINTN  mIsShadowStack = FALSE;
> 
>  /**
>Set the internal page table base address.
> @@ -249,7 +250,7 @@ ConvertPageEntryAttribute (
>if ((Attributes & EFI_MEMORY_RO) != 0) {
>  if (IsSet) {
>NewPageEntry &= ~(UINT64)IA32_PG_RW;
> -  if (mInternalCr3 != 0) {
> +  if (mIsShadowStack) {
>  // Environment setup
>  // ReadOnly page need set Dirty bit for shadow stack
>  NewPageEntry |= IA32_PG_D;
> @@ -734,10 +735,11 @@ SetShadowStack (
>EFI_STATUS  Status;
> 
>SetPageTableBase (Cr3);
> -
> -  Status = SmmSetMemoryAttributes (BaseAddress, Length,
> EFI_MEMORY_RO);
> +  mIsShadowStack = TRUE;
> +  Status = SmmSetMemoryAttributes (BaseAddress, Length,
> EFI_MEMORY_RO);
> 
>SetPageTableBase (0);
> +  mIsShadowStack = FALSE;
> 
>return Status;
>  }
> --
> 2.31.1.windows.1



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Re: [edk2-devel] [Patch V2 0/2] Remove clearing CR0.WP when protecting pagetable

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of duntan
> Sent: Wednesday, August 10, 2022 1:34 PM
> To: devel@edk2.groups.io
> Subject: [edk2-devel] [Patch V2 0/2] Remove clearing CR0.WP when
> protecting pagetable
> 
> Splited previos patch to two patches for different pkg.
> 
> Dun Tan (2):
>   MdeModulePkg/DxeIpl: Remove clearing CR0.WP when protecting
> pagetable
>   UefiPayloadPkg: Remove clearing CR0.WP when protecting pagetable
> 
>  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c| 7 +--
>  UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c | 7 +--
>  2 files changed, 2 insertions(+), 12 deletions(-)
> 
> --
> 2.31.1.windows.1
> 
> 
> 
> 
> 



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[edk2-devel] [Patch V2 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm

[duntan]

This patch is code refactoring and doesn't change any functionality.
Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous
code, mInternalCr3 is used to pass address of page table which is
different from Cr3 register in different level of SetMemoryAttributes
function. Now remove it and pass the page table base address from the
root function parameter to simplify the code logic.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  30 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h |  26 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 110 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  73 
+++--
 4 files changed, 94 insertions(+), 145 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
index 8ec8790c05..97058a2810 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
@@ -28,26 +28,6 @@ EnableCet (
   VOID
   );
 
-/**
-  Get page table base address and the depth of the page table.
-
-  @param[out] BasePage table base address.
-  @param[out] FiveLevels  TRUE means 5 level paging. FALSE means 4 level 
paging.
-**/
-VOID
-GetPageTable (
-  OUT UINTN*Base,
-  OUT BOOLEAN  *FiveLevels OPTIONAL
-  )
-{
-  *Base = ((mInternalCr3 == 0) ?
-   (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :
-   mInternalCr3);
-  if (FiveLevels != NULL) {
-*FiveLevels = FALSE;
-  }
-}
-
 /**
   Create PageTable for SMM use.
 
@@ -297,10 +277,10 @@ SetPageTableAttributes (
 DEBUG ((DEBUG_INFO, "Start...\n"));
 PageTableSplitted = FALSE;
 
-GetPageTable (, NULL);
-L3PageTable = (UINT64 *)PageTableBase;
+PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
+L3PageTable   = (UINT64 *)PageTableBase;
 
-SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, 
EFI_MEMORY_RO, );
+SmmSetMemoryAttributesEx (PageTableBase, FALSE, 
(EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, );
 PageTableSplitted = (PageTableSplitted || IsSplitted);
 
 for (Index3 = 0; Index3 < 4; Index3++) {
@@ -309,7 +289,7 @@ SetPageTableAttributes (
 continue;
   }
 
-  SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, 
SIZE_4KB, EFI_MEMORY_RO, );
+  SmmSetMemoryAttributesEx (PageTableBase, FALSE, 
(EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, );
   PageTableSplitted = (PageTableSplitted || IsSplitted);
 
   for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
@@ -323,7 +303,7 @@ SetPageTableAttributes (
   continue;
 }
 
-SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, 
SIZE_4KB, EFI_MEMORY_RO, );
+SmmSetMemoryAttributesEx (PageTableBase, FALSE, 
(EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, );
 PageTableSplitted = (PageTableSplitted || IsSplitted);
   }
 }
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index dfeceec2aa..ef8bf5947d 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -264,7 +264,7 @@ extern UINTN mMaxNumberOfCpus;
 extern UINTN mNumberOfCpus;
 extern EFI_SMM_CPU_PROTOCOL  mSmmCpu;
 extern EFI_MM_MP_PROTOCOLmSmmMp;
-extern UINTN mInternalCr3;
+extern BOOLEAN   m5LevelPagingNeeded;
 
 ///
 /// The mode of the CPU at the time an SMI occurs
@@ -682,7 +682,6 @@ SmmBlockingStartupThisAp (
 
 **/
 EFI_STATUS
-EFIAPI
 SmmSetMemoryAttributes (
   IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
   IN  UINT64Length,
@@ -712,7 +711,6 @@ SmmSetMemoryAttributes (
 
 **/
 EFI_STATUS
-EFIAPI
 SmmClearMemoryAttributes (
   IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
   IN  UINT64Length,
@@ -957,22 +955,12 @@ SetPageTableAttributes (
   VOID
   );
 
-/**
-  Get page table base address and the depth of the page table.
-
-  @param[out] BasePage table base address.
-  @param[out] FiveLevels  TRUE means 5 level paging. FALSE means 4 level 
paging.
-**/
-VOID
-GetPageTable (
-  OUT UINTN*Base,
-  OUT BOOLEAN  *FiveLevels OPTIONAL
-  );
-
 /**
   This function sets the attributes for the memory region specified by 
BaseAddress and
   Length from their current attributes to the attributes specified by 
Attributes.
 
+  @param[in]   PageTableBaseThe page table base.
+  @param[in]   EnablePML5Paging If PML5 paging is enabled.
   @param[in]   BaseAddress  The physical address that is the start address 
of a memory region.
   @param[in]   Length   The 

[edk2-devel] [Patch V2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flag

[duntan]

This patch is code refactoring and doesn't change any functionality.
Add a new IsShadowStack flag to identify whether current memory is
shadow stack. Previous smm code logic regards a RO range as shadow
stack and set the dirty bit in corresponding page table entry if
mInternalCr3 is not 0, which may be confusing.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index 1f7cc15727..237742d7e6 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -33,6 +33,7 @@ PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {
 };
 
 UINTN  mInternalCr3;
+UINTN  mIsShadowStack = FALSE;
 
 /**
   Set the internal page table base address.
@@ -249,7 +250,7 @@ ConvertPageEntryAttribute (
   if ((Attributes & EFI_MEMORY_RO) != 0) {
 if (IsSet) {
   NewPageEntry &= ~(UINT64)IA32_PG_RW;
-  if (mInternalCr3 != 0) {
+  if (mIsShadowStack) {
 // Environment setup
 // ReadOnly page need set Dirty bit for shadow stack
 NewPageEntry |= IA32_PG_D;
@@ -734,10 +735,11 @@ SetShadowStack (
   EFI_STATUS  Status;
 
   SetPageTableBase (Cr3);
-
-  Status = SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
+  mIsShadowStack = TRUE;
+  Status = SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
 
   SetPageTableBase (0);
+  mIsShadowStack = FALSE;
 
   return Status;
 }
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V2 0/2] Remove mInternalCr3 and Add a new mIsShadowStack

[duntan]

Changed IsShadowStack to mIsShadowStack.
Updated the commit message to explain this code refactoring.

Dun Tan (2):
  UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flag
  UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm

 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  30 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h |  26 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 116 
+---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  73 
+++--
 4 files changed, 98 insertions(+), 147 deletions(-)

-- 
2.31.1.windows.1



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[edk2-devel] [Patch V2 2/2] UefiPayloadPkg: Remove clearing CR0.WP when protecting pagetable

[duntan]

Remove clearing CR0.WP when marking the memory used for page table
as read-only in the page table itself created by UefiPayloadEntry.
This page table address is written to Cr3 after these protection
steps. Till this, the memory used for page table is always RW.

Signed-off-by: Dun Tan 
Cc: Guo Dong 
Cc: Ray Ni 
Cc: Maurice Ma 
Cc: Benjamin You 
Cc: Sean Rhodes 
---
 UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c 
b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index 74b667a62a..a586941352 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -622,12 +622,7 @@ EnablePageTableProtection (
   }
 
   //
-  // Disable write protection, because we need to mark page table to be write
-  // protected.
-  //
-  AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
-
-  //
+  // No need to clear CR0.WP since PageTableBase has't been written to CR3 yet.
   // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
   // remember original one in advance.
   //
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V2 1/2] MdeModulePkg/DxeIpl: Remove clearing CR0.WP when protecting pagetable

[duntan]

Remove clearing CR0.WP when marking the memory used for page table
as read-only in the page table itself created by DxeIpl. This page
table address is written to Cr3 after these protection steps. Till
this, the memory used for page table is always RW.

Signed-off-by: Dun Tan 
Cc: Dandan Bi 
Cc: Liming Gao 
Cc: Ray Ni 
---
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c 
b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index a451ca1604..18b121d768 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -626,12 +626,7 @@ EnablePageTableProtection (
   }
 
   //
-  // Disable write protection, because we need to mark page table to be write
-  // protected.
-  //
-  AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
-
-  //
+  // No need to clear CR0.WP since PageTableBase has't been written to CR3 yet.
   // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
   // remember original one in advance.
   //
-- 
2.31.1.windows.1



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[edk2-devel] [Patch V2 0/2] Remove clearing CR0.WP when protecting pagetable

[duntan]

Splited previos patch to two patches for different pkg.

Dun Tan (2):
  MdeModulePkg/DxeIpl: Remove clearing CR0.WP when protecting pagetable
  UefiPayloadPkg: Remove clearing CR0.WP when protecting pagetable

 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c| 7 +--
 UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c | 7 +--
 2 files changed, 2 insertions(+), 12 deletions(-)

-- 
2.31.1.windows.1



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Re: [edk2-devel] [PATCH v2] MdeModulePkg: Update the SMBIOS version by UPL

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Liu, KasimX 
> Sent: Tuesday, August 9, 2022 1:40 PM
> To: devel@edk2.groups.io
> Cc: Liu, KasimX ; Dong, Guo ;
> Ni, Ray ; Lu, James ; Guo, Gua
> 
> Subject: [PATCH v2] MdeModulePkg: Update the SMBIOS version by UPL
> 
> From: KasimX Liu 
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4013
> 
> For the SMBIOS version can be update by UPL,we create
> the gUniversalPayloadSmbios3TableGuid HOB to store
> the value then updated version.
> 
> Cc: Guo Dong 
> Cc: Ray Ni 
> Cc: James Lu 
> Cc: Gua Guo 
> Signed-off-by: KasimX Liu 
> ---
>  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c | 25
> 
>  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h | 12 +++---
>  2 files changed, 29 insertions(+), 8 deletions(-)
> 
> diff --git a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
> b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
> index 81df59cd0f..7c1e2adc02 100644
> --- a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
> +++ b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
> @@ -1447,7 +1447,9 @@ BOOLEAN
>  IsValidSmbios20Table (
> 
>IN  VOID   *TableEntry,
> 
>OUT VOID   **TableAddress,
> 
> -  OUT UINTN  *TableMaximumSize
> 
> +  OUT UINTN  *TableMaximumSize,
> 
> +  OUT UINT8  *MajorVersion,
> 
> +  OUT UINT8  *MinorVersion
> 
>)
> 
>  {
> 
>UINT8 Checksum;
> 
> @@ -1478,6 +1480,8 @@ IsValidSmbios20Table (
>if (SmbiosTable->MajorVersion < 2) {
> 
>  return FALSE;
> 
>}
> 
> +  *MajorVersion = SmbiosTable->MajorVersion;
> 
> +  *MinorVersion = SmbiosTable->MinorVersion;
> 
> 
> 
>//
> 
>// The whole struct check sum should be zero
> 
> @@ -1522,7 +1526,9 @@ BOOLEAN
>  IsValidSmbios30Table (
> 
>IN  VOID   *TableEntry,
> 
>OUT VOID   **TableAddress,
> 
> -  OUT UINTN  *TableMaximumSize
> 
> +  OUT UINTN  *TableMaximumSize,
> 
> +  OUT UINT8  *MajorVersion,
> 
> +  OUT UINT8  *MinorVersion
> 
>)
> 
>  {
> 
>UINT8 Checksum;
> 
> @@ -1541,6 +1547,8 @@ IsValidSmbios30Table (
>if (SmbiosTable->MajorVersion < 3) {
> 
>  return FALSE;
> 
>}
> 
> +  *MajorVersion = SmbiosTable->MajorVersion;
> 
> +  *MinorVersion = SmbiosTable->MinorVersion;
> 
> 
> 
>//
> 
>// The whole struct check sum should be zero
> 
> @@ -1575,7 +1583,9 @@ EFI_STATUS
>  ParseAndAddExistingSmbiosTable (
> 
>IN EFI_HANDLEImageHandle,
> 
>IN SMBIOS_STRUCTURE_POINTER  Smbios,
> 
> -  IN UINTN Length
> 
> +  IN UINTN Length,
> 
> +  IN UINT8 MajorVersion,
> 
> +  IN UINT8 MinorVersion
> 
>)
> 
>  {
> 
>EFI_STATUSStatus;
> 
> @@ -1583,6 +1593,9 @@ ParseAndAddExistingSmbiosTable (
>EFI_SMBIOS_HANDLE SmbiosHandle;
> 
>SMBIOS_STRUCTURE_POINTER  SmbiosEnd;
> 
> 
> 
> +  mPrivateData.Smbios.MajorVersion = MajorVersion;
> 
> +  mPrivateData.Smbios.MinorVersion = MinorVersion;
> 
> +
> 
>SmbiosEnd.Raw = Smbios.Raw + Length;
> 
> 
> 
>if ((Smbios.Raw >= SmbiosEnd.Raw) || (Smbios.Raw == NULL)) {
> 
> @@ -1692,6 +1705,8 @@ RetrieveSmbiosFromHob (
>UNIVERSAL_PAYLOAD_GENERIC_HEADER  *GenericHeader;
> 
>VOID  *TableAddress;
> 
>UINTN TableMaximumSize;
> 
> +  UINT8 MajorVersion;
> 
> +  UINT8 MinorVersion;
> 
> 
> 
>Status = EFI_NOT_FOUND;
> 
> 
> 
> @@ -1709,9 +1724,9 @@ RetrieveSmbiosFromHob (
>  //
> 
>  SmBiosTableAdress = (UNIVERSAL_PAYLOAD_SMBIOS_TABLE
> *)GET_GUID_HOB_DATA (GuidHob);
> 
>  if (GenericHeader->Length >=
> UNIVERSAL_PAYLOAD_SIZEOF_THROUGH_FIELD
> (UNIVERSAL_PAYLOAD_SMBIOS_TABLE, SmBiosEntryPoint)) {
> 
> -  if (mIsSmbiosTableValid[Index].IsValid ((VOID
> *)(UINTN)SmBiosTableAdress->SmBiosEntryPoint, ,
> )) {
> 
> +  if (mIsSmbiosTableValid[Index].IsValid ((VOID
> *)(UINTN)SmBiosTableAdress->SmBiosEntryPoint, ,
> ,,)) {
> 
>  Smbios.Raw = TableAddress;
> 
> -Status = ParseAndAddExistingSmbiosTable (ImageHandle, Smbios,
> TableMaximumSize);
> 
> +Status = ParseAndAddExistingSmbiosTable (ImageHandle, Smbios,
> TableMaximumSize,MajorVersion,MinorVersion);
> 
>  if (EFI_ERROR (Status)) {
> 
>DEBUG ((DEBUG_ERROR, "RetrieveSmbiosFromHob: Failed to parse
> preinstalled tables from Guid Hob\n"));
> 
>Status = EFI_UNSUPPORTED;
> 
> diff --git a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h
> b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h
> index 019798ea77..f1500beabd 100644
> --- a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h
> +++ b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h
> @@ -136,7 +136,9 @@ BOOLEAN
>  IsValidSmbios30Table (
> 
>IN  VOID   *TableEntry,
> 
>OUT VOID   **TableAddress,
> 
> -  OUT UINTN  *TableMaximumSize
> 
> +  OUT UINTN  

Re: [edk2-devel] [PATCH 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Tan, Dun 
> Sent: Wednesday, August 10, 2022 9:46 AM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R 
> Subject: [PATCH 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3
> in PiSmmCpuDxeSmm
> 
> Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. Currently,
> mInternalCr3 is used to pass address of pagetable which is different
> from Cr3 register. Now remove it and pass the page table base address
> from the root function to simplify the code logic.
> 
> Change-Id: I8f58158b94a01cf829f1b4fb2b8c763dcdda0662
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> Signed-off-by: Dun Tan 
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  30 +--
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h |  26
> +-
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 107
> +--
> 
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  73
> +++--
>  4 files changed, 94 insertions(+), 142 deletions(-)
> 
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
> index 8ec8790c05..97058a2810 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
> @@ -28,26 +28,6 @@ EnableCet (
>VOID
>);
> 
> -/**
> -  Get page table base address and the depth of the page table.
> -
> -  @param[out] BasePage table base address.
> -  @param[out] FiveLevels  TRUE means 5 level paging. FALSE means 4 level
> paging.
> -**/
> -VOID
> -GetPageTable (
> -  OUT UINTN*Base,
> -  OUT BOOLEAN  *FiveLevels OPTIONAL
> -  )
> -{
> -  *Base = ((mInternalCr3 == 0) ?
> -   (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :
> -   mInternalCr3);
> -  if (FiveLevels != NULL) {
> -*FiveLevels = FALSE;
> -  }
> -}
> -
>  /**
>Create PageTable for SMM use.
> 
> @@ -297,10 +277,10 @@ SetPageTableAttributes (
>  DEBUG ((DEBUG_INFO, "Start...\n"));
>  PageTableSplitted = FALSE;
> 
> -GetPageTable (, NULL);
> -L3PageTable = (UINT64 *)PageTableBase;
> +PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
> +L3PageTable   = (UINT64 *)PageTableBase;
> 
> -SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase,
> SIZE_4KB, EFI_MEMORY_RO, );
> +SmmSetMemoryAttributesEx (PageTableBase, FALSE,
> (EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO,
> );
>  PageTableSplitted = (PageTableSplitted || IsSplitted);
> 
>  for (Index3 = 0; Index3 < 4; Index3++) {
> @@ -309,7 +289,7 @@ SetPageTableAttributes (
>  continue;
>}
> 
> -  SmmSetMemoryAttributesEx
> ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO,
> );
> +  SmmSetMemoryAttributesEx (PageTableBase, FALSE,
> (EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO,
> );
>PageTableSplitted = (PageTableSplitted || IsSplitted);
> 
>for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
> @@ -323,7 +303,7 @@ SetPageTableAttributes (
>continue;
>  }
> 
> -SmmSetMemoryAttributesEx
> ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO,
> );
> +SmmSetMemoryAttributesEx (PageTableBase, FALSE,
> (EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO,
> );
>  PageTableSplitted = (PageTableSplitted || IsSplitted);
>}
>  }
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
> b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
> index dfeceec2aa..ef8bf5947d 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
> @@ -264,7 +264,7 @@ extern UINTN mMaxNumberOfCpus;
>  extern UINTN mNumberOfCpus;
>  extern EFI_SMM_CPU_PROTOCOL  mSmmCpu;
>  extern EFI_MM_MP_PROTOCOLmSmmMp;
> -extern UINTN mInternalCr3;
> +extern BOOLEAN   m5LevelPagingNeeded;
> 
>  ///
>  /// The mode of the CPU at the time an SMI occurs
> @@ -682,7 +682,6 @@ SmmBlockingStartupThisAp (
> 
>  **/
>  EFI_STATUS
> -EFIAPI
>  SmmSetMemoryAttributes (
>IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
>IN  UINT64Length,
> @@ -712,7 +711,6 @@ SmmSetMemoryAttributes (
> 
>  **/
>  EFI_STATUS
> -EFIAPI
>  SmmClearMemoryAttributes (
>IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
>IN  UINT64Length,
> @@ -957,22 +955,12 @@ SetPageTableAttributes (
>VOID
>);
> 
> -/**
> -  Get page table base address and the depth of the page table.
> -
> -  @param[out] BasePage table base address.
> -  @param[out] FiveLevels  TRUE means 5 level paging. FALSE means 4 level
> paging.
> -**/
> -VOID
> -GetPageTable (
> -  OUT UINTN*Base,

Re: [edk2-devel] [edk2-platforms: PATCH] Modify processor _UID ordering by CPU default fused in MADT

[Ni, Ray]

Jack, the patch is merged.

> -Original Message-
> From: Lin, JackX 
> Sent: Wednesday, August 10, 2022 12:32 PM
> To: Ni, Ray ; Sinha, Ankit 
> Cc: Chiu, Chasel ; Dong, Eric ;
> Yao, Jiewen ; Chaganty, Rangasai V
> ; devel@edk2.groups.io; Kuo, Donald
> ; Kumar, Chandana C
> ; Palakshareddy, Lavanya C
> ; Palakshareddy, Lavanya C
> 
> Subject: RE: [edk2-platforms: PATCH] Modify processor _UID ordering by
> CPU default fused in MADT
> 
> Hi Ray,
> 
> The latest patch is sent in the code review mail, and I also attach one here,
> thank you.
> 
> Best regards
> Jack
> 
> -Original Message-
> From: Lin, JackX
> Sent: Wednesday, August 10, 2022 11:51 AM
> To: Ni, Ray ; Sinha, Ankit 
> Cc: Chiu, Chasel ; Dong, Eric ;
> Yao, Jiewen ; Chaganty, Rangasai V
> ; devel@edk2.groups.io; Kuo, Donald
> ; Kumar, Chandana C
> ; Palakshareddy, Lavanya C
> ; Palakshareddy, Lavanya C
> 
> Subject: RE: [edk2-platforms: PATCH] Modify processor _UID ordering by
> CPU default fused in MADT
> 
> Hi Ray,
> 
> I know this patch, and the thread 2 and 3 are added by my request for a
> reason on that time.
> I will re-sent the code patch.
> Thank you.
> 
> Jack
> 
> -Original Message-
> From: Ni, Ray 
> Sent: Wednesday, August 10, 2022 11:48 AM
> To: Lin, JackX ; Sinha, Ankit 
> Cc: Chiu, Chasel ; Dong, Eric ;
> Yao, Jiewen ; Chaganty, Rangasai V
> ; devel@edk2.groups.io; Kuo, Donald
> ; Kumar, Chandana C
> ; Palakshareddy, Lavanya C
> ; Palakshareddy, Lavanya C
> 
> Subject: RE: [edk2-platforms: PATCH] Modify processor _UID ordering by
> CPU default fused in MADT
> 
> Jack,
> Your patch cannot be merged to trunk because Ankit just did some change in
> the same C file, in below commit.
> * MinPlatformPkg/AcpiTables: Add additional thread mapping in MADT
> 
> Ankit,
> It seems your patch is to add support for thread #2 and #3. Jack's patch is to
> remove the additional sorting that put secondary threads after first threads.
> Do you see an issue that we remove the thread sorting logic?
> 
> Thanks,
> Ray
> 
> > -Original Message-
> > From: Lin, JackX 
> > Sent: Monday, August 8, 2022 4:21 PM
> > To: devel@edk2.groups.io
> > Cc: Lin, JackX ; Lin, JackX
> > ; Chiu, Chasel ; Dong,
> > Eric ; Yao, Jiewen ; Ni,
> > Ray ; Chaganty, Rangasai V
> > ; Kuo, Donald ;
> > Kumar, Chandana C ; Palakshareddy;
> > Palakshareddy, Lavanya C 
> > Subject: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU
> > default fused in MADT
> >
> > BIOS should not reordering cpu processor_uid
> >
> > Signed-off-by: JackX Lin 
> > Cc: Chasel Chiu 
> > Cc: Dong Eric 
> > Cc: Jiewen Yao 
> > Cc: Ray Ni 
> > Cc: Rangasai V Chaganty 
> > Cc: Donald Kuo 
> > Cc: Chandana C Kumar 
> > Cc: Palakshareddy, Lavanya C 
> > Cc: JackX Lin 
> > ---
> >  Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 174
> > +++-
> --
> > --
> > 
> > --
> >  1 file changed, 39 insertions(+), 135 deletions(-)
> >
> > diff --git
> > a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > index c7e87cbd7d..176e422e81 100644
> > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > @@ -57,38 +57,9 @@ BOOLEAN mForceX2ApicId;
> >  BOOLEAN mX2ApicEnabled;
> >
> >  EFI_MP_SERVICES_PROTOCOL*mMpService;
> > -BOOLEAN mCpuOrderSorted;
> > -EFI_CPU_ID_ORDER_MAP*mCpuApicIdOrderTable = NULL;
> >  UINTN   mNumberOfCpus = 0;
> >  UINTN   mNumberOfEnabledCPUs = 0;
> >
> > -
> > -/**
> > -  The function is called by PerformQuickSort to compare int values.
> > -
> > -  @param[in] LeftThe pointer to first buffer.
> > -  @param[in] Right   The pointer to second buffer.
> > -
> > -  @return -1 Buffer1 is less than Buffer2.
> > -  @return  1 Buffer1 is greater than Buffer2.
> > -
> > -**/
> > -INTN
> > -EFIAPI
> > -ApicIdCompareFunction (
> > -  IN CONST VOID *Left,
> > -  IN CONST VOID *Right
> > -  )
> > -{
> > -  UINT32  LeftApicId;
> > -  UINT32  RightApicId;
> > -
> > -  LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
> > -  RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;
> > -
> > -  return (LeftApicId > RightApicId)? 1 : (-1); -}
> > -
> >  /**
> >Print Cpu Apic ID Table
> >
> > @@ -116,7 +87,8 @@ DebugDisplayReOrderTable (  EFI_STATUS
> > AppendCpuMapTableEntry (
> >  IN VOID   *ApicPtr,
> > -IN UINT32 LocalApicCounter
> > +IN UINT32 LocalApicCounter,
> > +IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
> >)
> >  {
> >EFI_STATUSStatus;
> > @@ -131,9 +103,9 @@ AppendCpuMapTableEntry 

Re: [edk2-devel] [edk2-platforms: PATCH] Modify processor _UID ordering by CPU default fused in MADT

[Ni, Ray]

Thanks!
Reviewed-by: Ray Ni 



> -Original Message-
> From: Lin, JackX 
> Sent: Wednesday, August 10, 2022 12:29 PM
> To: devel@edk2.groups.io
> Cc: Lin, JackX ; Lin, JackX ; Chiu,
> Chasel ; Dong, Eric ; Yao,
> Jiewen ; Ni, Ray ; Chaganty,
> Rangasai V ; Kuo, Donald
> ; Kumar, Chandana C
> ; Palakshareddy; Palakshareddy, Lavanya C
> 
> Subject: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU
> default fused in MADT
> 
> BIOS should not reordering cpu processor_uid
> 
> Signed-off-by: JackX Lin 
> Cc: Chasel Chiu 
> Cc: Dong Eric 
> Cc: Jiewen Yao 
> Cc: Ray Ni 
> Cc: Rangasai V Chaganty 
> Cc: Donald Kuo 
> Cc: Chandana C Kumar 
> Cc: Palakshareddy, Lavanya C 
> Cc: JackX Lin 
> ---
>  Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 183
> --
> --
> ---
>  1 file changed, 40 insertions(+), 143 deletions(-)
> 
> diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> index 5a282e7c18..f134c8a58f 100644
> --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> @@ -57,38 +57,9 @@ BOOLEAN mForceX2ApicId;
>  BOOLEAN mX2ApicEnabled;
> 
>  EFI_MP_SERVICES_PROTOCOL*mMpService;
> -BOOLEAN mCpuOrderSorted;
> -EFI_CPU_ID_ORDER_MAP*mCpuApicIdOrderTable = NULL;
>  UINTN   mNumberOfCpus = 0;
>  UINTN   mNumberOfEnabledCPUs = 0;
> 
> -
> -/**
> -  The function is called by PerformQuickSort to compare int values.
> -
> -  @param[in] LeftThe pointer to first buffer.
> -  @param[in] Right   The pointer to second buffer.
> -
> -  @return -1 Buffer1 is less than Buffer2.
> -  @return  1 Buffer1 is greater than Buffer2.
> -
> -**/
> -INTN
> -EFIAPI
> -ApicIdCompareFunction (
> -  IN CONST VOID *Left,
> -  IN CONST VOID *Right
> -  )
> -{
> -  UINT32  LeftApicId;
> -  UINT32  RightApicId;
> -
> -  LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
> -  RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;
> -
> -  return (LeftApicId > RightApicId)? 1 : (-1);
> -}
> -
>  /**
>Print Cpu Apic ID Table
> 
> @@ -116,7 +87,8 @@ DebugDisplayReOrderTable (
>  EFI_STATUS
>  AppendCpuMapTableEntry (
>  IN VOID   *ApicPtr,
> -IN UINT32 LocalApicCounter
> +IN UINT32 LocalApicCounter,
> +IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
>)
>  {
>EFI_STATUSStatus;
> @@ -131,9 +103,9 @@ AppendCpuMapTableEntry (
> 
>if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
>  if(!mX2ApicEnabled) {
> -  LocalApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalApicPtr->ApicId   =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalApicPtr->AcpiProcessorUid =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalApicPtr->ApicId   =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalApicPtr->AcpiProcessorUid =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>LocalApicPtr->Flags= 0;
>LocalApicPtr->ApicId   = 0xFF;
> @@ -142,9 +114,9 @@ AppendCpuMapTableEntry (
>  }
>} else if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
>  if(mX2ApicEnabled) {
> -  LocalX2ApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalX2ApicPtr->X2ApicId =
> mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalX2ApicPtr->AcpiProcessorUid =
> mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalX2ApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalX2ApicPtr->X2ApicId =
> CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalX2ApicPtr->AcpiProcessorUid =
> CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>LocalX2ApicPtr->Flags= 0;
>LocalX2ApicPtr->X2ApicId = (UINT32)-1;
> @@ -159,32 +131,25 @@ AppendCpuMapTableEntry (
> 
>  }
> 
> +/**
> +  Collect all processors information and create a Cpu Apic Id table.
> +
> +  @param[in]  CpuApicIdOrderTable   Buffer to store information of Cpu.
> +**/
>  EFI_STATUS
> -SortCpuLocalApicInTable (
> -  VOID
> +CreateCpuLocalApicInTable (
> +  IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
>)
>  {
>EFI_STATUSStatus;
>EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;
>UINT32  

[edk2-devel] [Patch 1/1] MdePkg/Library/UefiDevicePathLib: Add back StandaloneMm INF file

[Michael D Kinney]

REF: https://github.com/tianocore/edk2/pull/3130

The above PR removed UefiDevicePathLibStandaloneMm.inf, which is
a non-backwards compatible change and does not provide time for
downstream platforms to use the UefiDevicePathLibBase.inf.

Add UefiDevicePathLibStandaloneMm.inf back, but add comments that
it is deprecated and that UefiDevicePathLibBase.inf should be used
instead.

Cc: Liming Gao  [lgao4]
Cc: Zhiguang Liu  [LiuZhiguang001]
Cc: Mateusz Albecki 
Cc: Yanbo Huang 
Signed-off-by: Michael D Kinney 
---
 .../UefiDevicePathLibStandaloneMm.inf | 78 +++
 MdePkg/MdePkg.dsc |  1 +
 2 files changed, 79 insertions(+)
 create mode 100644 
MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf

diff --git a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf 
b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
new file mode 100644
index ..97db485e23f8
--- /dev/null
+++ b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
@@ -0,0 +1,78 @@
+## @file
+# Instance of Device Path Library based on Memory Allocation Library.
+#
+# Device Path Library that layers on top of the Memory Allocation Library.
+#
+# This library instances is deprecated and should no longer be used.  Ue
+# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf instead.
+#
+# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) Microsoft Corporation.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = UefiDevicePathLibStandaloneMm
+  MODULE_UNI_FILE= UefiDevicePathLib.uni
+  FILE_GUID  = 7B60A2BC-9259-48A8-8279-971412EECAB3
+  MODULE_TYPE= BASE
+  PI_SPECIFICATION_VERSION   = 0x00010032
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = DevicePathLib
+
+
+#
+#  VALID_ARCHITECTURES   = IA32 X64 EBC
+#
+
+[Sources]
+  DevicePathUtilities.c
+  DevicePathUtilitiesBase.c
+  DevicePathToText.c
+  DevicePathFromText.c
+  UefiDevicePathLib.c
+  UefiDevicePathLib.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  BaseLib
+  MemoryAllocationLib
+  DebugLib
+  BaseMemoryLib
+  PcdLib
+  PrintLib
+
+[Guids]
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiVTUTF8Guid
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiVT100Guid
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiVT100PlusGuid
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiPcAnsiGuid
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiUartDevicePathGuid
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiSasDevicePathGuid
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiVirtualDiskGuid
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiVirtualCdGuid
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiPersistentVirtualDiskGuid
+  ## SOMETIMES_CONSUMES  ## GUID
+  gEfiPersistentVirtualCdGuid
+
+[Protocols]
+  gEfiDevicePathProtocolGuid## SOMETIMES_CONSUMES
+  gEfiDebugPortProtocolGuid ## UNDEFINED
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdMaximumDevicePathNodeCount## 
SOMETIMES_CONSUMES
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index 9daee93523e5..cc1ac196a931 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -112,6 +112,7 @@ [Components]
   MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
   MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
   MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf
+  MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
   
MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf
   
MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
   MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-- 
2.37.1.windows.1



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Re: [edk2-devel] [edk2-platforms: PATCH] Modify processor _UID ordering by CPU default fused in MADT

[JackX Lin]

Hi Ray,

The latest patch is sent in the code review mail, and I also attach one here, 
thank you.

Best regards
Jack

-Original Message-
From: Lin, JackX 
Sent: Wednesday, August 10, 2022 11:51 AM
To: Ni, Ray ; Sinha, Ankit 
Cc: Chiu, Chasel ; Dong, Eric ; 
Yao, Jiewen ; Chaganty, Rangasai V 
; devel@edk2.groups.io; Kuo, Donald 
; Kumar, Chandana C ; 
Palakshareddy, Lavanya C ; Palakshareddy, 
Lavanya C 
Subject: RE: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU 
default fused in MADT

Hi Ray,

I know this patch, and the thread 2 and 3 are added by my request for a reason 
on that time.
I will re-sent the code patch.
Thank you.

Jack

-Original Message-
From: Ni, Ray 
Sent: Wednesday, August 10, 2022 11:48 AM
To: Lin, JackX ; Sinha, Ankit 
Cc: Chiu, Chasel ; Dong, Eric ; 
Yao, Jiewen ; Chaganty, Rangasai V 
; devel@edk2.groups.io; Kuo, Donald 
; Kumar, Chandana C ; 
Palakshareddy, Lavanya C ; Palakshareddy, 
Lavanya C 
Subject: RE: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU 
default fused in MADT

Jack,
Your patch cannot be merged to trunk because Ankit just did some change in the 
same C file, in below commit.
* MinPlatformPkg/AcpiTables: Add additional thread mapping in MADT

Ankit,
It seems your patch is to add support for thread #2 and #3. Jack's patch is to 
remove the additional sorting that put secondary threads after first threads.
Do you see an issue that we remove the thread sorting logic?

Thanks,
Ray

> -Original Message-
> From: Lin, JackX 
> Sent: Monday, August 8, 2022 4:21 PM
> To: devel@edk2.groups.io
> Cc: Lin, JackX ; Lin, JackX 
> ; Chiu, Chasel ; Dong, 
> Eric ; Yao, Jiewen ; Ni, 
> Ray ; Chaganty, Rangasai V 
> ; Kuo, Donald ; 
> Kumar, Chandana C ; Palakshareddy; 
> Palakshareddy, Lavanya C 
> Subject: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU 
> default fused in MADT
> 
> BIOS should not reordering cpu processor_uid
> 
> Signed-off-by: JackX Lin 
> Cc: Chasel Chiu 
> Cc: Dong Eric 
> Cc: Jiewen Yao 
> Cc: Ray Ni 
> Cc: Rangasai V Chaganty 
> Cc: Donald Kuo 
> Cc: Chandana C Kumar 
> Cc: Palakshareddy, Lavanya C 
> Cc: JackX Lin 
> ---
>  Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 174
> +++---
> --
> 
> --
>  1 file changed, 39 insertions(+), 135 deletions(-)
> 
> diff --git
> a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> index c7e87cbd7d..176e422e81 100644
> --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> @@ -57,38 +57,9 @@ BOOLEAN mForceX2ApicId;
>  BOOLEAN mX2ApicEnabled;
> 
>  EFI_MP_SERVICES_PROTOCOL*mMpService;
> -BOOLEAN mCpuOrderSorted;
> -EFI_CPU_ID_ORDER_MAP*mCpuApicIdOrderTable = NULL;
>  UINTN   mNumberOfCpus = 0;
>  UINTN   mNumberOfEnabledCPUs = 0;
> 
> -
> -/**
> -  The function is called by PerformQuickSort to compare int values.
> -
> -  @param[in] LeftThe pointer to first buffer.
> -  @param[in] Right   The pointer to second buffer.
> -
> -  @return -1 Buffer1 is less than Buffer2.
> -  @return  1 Buffer1 is greater than Buffer2.
> -
> -**/
> -INTN
> -EFIAPI
> -ApicIdCompareFunction (
> -  IN CONST VOID *Left,
> -  IN CONST VOID *Right
> -  )
> -{
> -  UINT32  LeftApicId;
> -  UINT32  RightApicId;
> -
> -  LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
> -  RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;
> -
> -  return (LeftApicId > RightApicId)? 1 : (-1); -}
> -
>  /**
>Print Cpu Apic ID Table
> 
> @@ -116,7 +87,8 @@ DebugDisplayReOrderTable (  EFI_STATUS 
> AppendCpuMapTableEntry (
>  IN VOID   *ApicPtr,
> -IN UINT32 LocalApicCounter
> +IN UINT32 LocalApicCounter,
> +IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
>)
>  {
>EFI_STATUSStatus;
> @@ -131,9 +103,9 @@ AppendCpuMapTableEntry (
> 
>if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
>  if(!mX2ApicEnabled) {
> -  LocalApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalApicPtr->ApicId   =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalApicPtr->AcpiProcessorUid =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalApicPtr->ApicId   =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalApicPtr->AcpiProcessorUid =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>

[edk2-devel] [edk2-platforms: PATCH] Modify processor _UID ordering by CPU default fused in MADT

[JackX Lin]

BIOS should not reordering cpu processor_uid

Signed-off-by: JackX Lin 
Cc: Chasel Chiu 
Cc: Dong Eric 
Cc: Jiewen Yao 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
Cc: Donald Kuo 
Cc: Chandana C Kumar 
Cc: Palakshareddy, Lavanya C 
Cc: JackX Lin 
---
 Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 183 
---
 1 file changed, 40 insertions(+), 143 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c 
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 5a282e7c18..f134c8a58f 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -57,38 +57,9 @@ BOOLEAN mForceX2ApicId;
 BOOLEAN mX2ApicEnabled;
 
 EFI_MP_SERVICES_PROTOCOL*mMpService;
-BOOLEAN mCpuOrderSorted;
-EFI_CPU_ID_ORDER_MAP*mCpuApicIdOrderTable = NULL;
 UINTN   mNumberOfCpus = 0;
 UINTN   mNumberOfEnabledCPUs = 0;
 
-
-/**
-  The function is called by PerformQuickSort to compare int values.
-
-  @param[in] LeftThe pointer to first buffer.
-  @param[in] Right   The pointer to second buffer.
-
-  @return -1 Buffer1 is less than Buffer2.
-  @return  1 Buffer1 is greater than Buffer2.
-
-**/
-INTN
-EFIAPI
-ApicIdCompareFunction (
-  IN CONST VOID *Left,
-  IN CONST VOID *Right
-  )
-{
-  UINT32  LeftApicId;
-  UINT32  RightApicId;
-
-  LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
-  RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;
-
-  return (LeftApicId > RightApicId)? 1 : (-1);
-}
-
 /**
   Print Cpu Apic ID Table
 
@@ -116,7 +87,8 @@ DebugDisplayReOrderTable (
 EFI_STATUS
 AppendCpuMapTableEntry (
 IN VOID   *ApicPtr,
-IN UINT32 LocalApicCounter
+IN UINT32 LocalApicCounter,
+IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable 
   )
 {
   EFI_STATUSStatus;
@@ -131,9 +103,9 @@ AppendCpuMapTableEntry (
 
   if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
 if(!mX2ApicEnabled) {
-  LocalApicPtr->Flags= 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
-  LocalApicPtr->ApicId   = 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
-  LocalApicPtr->AcpiProcessorUid = 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
+  LocalApicPtr->Flags= 
(UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
+  LocalApicPtr->ApicId   = 
(UINT8)CpuApicIdOrderTable[LocalApicCounter].ApicId;
+  LocalApicPtr->AcpiProcessorUid = 
(UINT8)CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
 } else {
   LocalApicPtr->Flags= 0;
   LocalApicPtr->ApicId   = 0xFF;
@@ -142,9 +114,9 @@ AppendCpuMapTableEntry (
 }
   } else if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
 if(mX2ApicEnabled) {
-  LocalX2ApicPtr->Flags= 
(UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
-  LocalX2ApicPtr->X2ApicId = 
mCpuApicIdOrderTable[LocalApicCounter].ApicId;
-  LocalX2ApicPtr->AcpiProcessorUid = 
mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
+  LocalX2ApicPtr->Flags= 
(UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
+  LocalX2ApicPtr->X2ApicId = 
CpuApicIdOrderTable[LocalApicCounter].ApicId;
+  LocalX2ApicPtr->AcpiProcessorUid = 
CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
 } else {
   LocalX2ApicPtr->Flags= 0;
   LocalX2ApicPtr->X2ApicId = (UINT32)-1;
@@ -159,32 +131,25 @@ AppendCpuMapTableEntry (
 
 }
 
+/**
+  Collect all processors information and create a Cpu Apic Id table.
+
+  @param[in]  CpuApicIdOrderTable   Buffer to store information of Cpu.
+**/
 EFI_STATUS
-SortCpuLocalApicInTable (
-  VOID
+CreateCpuLocalApicInTable (
+  IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
   )
 {
   EFI_STATUSStatus;
   EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;
   UINT32Index;
   UINT32CurrProcessor;
-  UINT32BspApicId;
-  EFI_CPU_ID_ORDER_MAP  TempVal;
   EFI_CPU_ID_ORDER_MAP  *CpuIdMapPtr;
-  UINT32CoreThreadMask;
-  EFI_CPU_ID_ORDER_MAP  *TempCpuApicIdOrderTable;
   UINT32Socket;
 
-  Index  = 0;
   Status = EFI_SUCCESS;
 
-  if (mCpuOrderSorted) {
-return Status;
-  }
-
-  TempCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof 
(EFI_CPU_ID_ORDER_MAP));
-  CoreThreadMask = (UINT32) 

Re: [edk2-devel] [PATCH] MdePkg/UefiDevicePathLib: reback the DevicePathUtilitiesStandaloneMm

[Michael D Kinney]

Hi Liming,

I will prepare a patch for review that follows your suggestion.

Thanks,

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of gaoliming via 
> groups.io
> Sent: Sunday, August 7, 2022 10:25 PM
> To: devel@edk2.groups.io; Kinney, Michael D ; 
> Huang, Yanbo 
> Cc: Liu, Zhiguang ; Bi, Dandan 
> Subject: 回复: [edk2-devel] [PATCH] MdePkg/UefiDevicePathLib: reback the 
> DevicePathUtilitiesStandaloneMm
> 
> Mike:
>   In original thread, I don't receive the objection to change the library INF 
> file name. So, I merge original patch.
> 
>   Now, the downstream break is found. If you think 
> DevicePathUtilitiesStandaloneMm is required, I would suggest to add it for
> long term to keep the compatibility.
> 
> Yanbo:
>   You only need to add new DevicePathUtilitiesStandaloneMm.inf. Its content 
> is same to UefiDevicePathLibBase.inf.
> 
> Thanks
> Liming
> > -邮件原件-
> > 发件人: devel@edk2.groups.io  代表 Michael D
> > Kinney
> > 发送时间: 2022年8月5日 23:38
> > 收件人: devel@edk2.groups.io; Gao, Liming ;
> > Huang, Yanbo ; Kinney, Michael D
> > 
> > 抄送: Liu, Zhiguang ; Bi, Dandan
> > 
> > 主题: Re: [edk2-devel] [PATCH] MdePkg/UefiDevicePathLib: reback the
> > DevicePathUtilitiesStandaloneMm
> >
> > Liming,
> >
> > Adding a new INF that is type BASE was my original suggestion.  Not the
> > name change.
> >
> > In that thread, I suggested we get input from MM owners before changing the
> > name.
> >
> > If there are many downstream platforms that are breaking from the name
> > change,
> > then we should add the old INF back to provide time for all platform to 
> > update
> > to
> > use the new INF name.
> >
> > Mike
> >
> > > -Original Message-
> > > From: devel@edk2.groups.io  On Behalf Of
> > gaoliming via groups.io
> > > Sent: Thursday, August 4, 2022 11:11 PM
> > > To: Huang, Yanbo ; devel@edk2.groups.io
> > > Cc: Kinney, Michael D ; Liu, Zhiguang
> > ; Bi, Dandan 
> > > Subject: 回复: [edk2-devel] [PATCH] MdePkg/UefiDevicePathLib: reback
> > the DevicePathUtilitiesStandaloneMm
> > >
> > > Yanbo:
> > >   If this patch is temporarily added, you can handle it in your downstream
> > code base.
> > >
> > >   If you request to add DevicePathUtilitiesStandaloneMm for long term
> > compatibility, this topic has been discussed in
> > > https://edk2.groups.io/g/devel/message/91799.
> > >
> > > Thanks
> > > Liming
> > > > -邮件原件-
> > > > 发件人: Huang, Yanbo 
> > > > 发送时间: 2022年8月5日 13:34
> > > > 收件人: Gao, Liming ;
> > devel@edk2.groups.io
> > > > 抄送: Kinney, Michael D ; Liu, Zhiguang
> > > > ; Bi, Dandan 
> > > > 主题: RE: [edk2-devel] [PATCH] MdePkg/UefiDevicePathLib: reback the
> > > > DevicePathUtilitiesStandaloneMm
> > > >
> > > > Hi Liming,
> > > >
> > > > You mentioned patch rename the DevicePathUtilitiesStandaloneMm to
> > > > UefiDevicePathLibBase, but there are some consumer in intel platform 
> > > > still
> > > > use the DevicePathUtilitiesStandaloneMm, so downstream will failed in CI
> > > > because it cannot find DevicePathUtilitiesStandaloneMm. So the
> > > > DevicePathUtilitiesStandaloneMm and UefiDevicePathLibBase must exist
> > at
> > > > the same time for a period of time. After downstream finished and
> > platform
> > > > change to use UefiDevicePathLibBase, then
> > > > DevicePathUtilitiesStandaloneMm can be deleted.
> > > >
> > > > Best Regards,
> > > > Yanbo Huang
> > > >
> > > > -Original Message-
> > > > From: gaoliming 
> > > > Sent: Friday, August 5, 2022 11:16 AM
> > > > To: devel@edk2.groups.io; Huang, Yanbo 
> > > > Cc: Kinney, Michael D ; Liu, Zhiguang
> > > > 
> > > > Subject: 回复: [edk2-devel] [PATCH] MdePkg/UefiDevicePathLib: reback
> > the
> > > > DevicePathUtilitiesStandaloneMm
> > > >
> > > > Yanbo:
> > > >   Previous change has been reviewed and merged. Please see the detail
> > > > https://edk2.groups.io/g/devel/message/91799
> > > >
> > > > Thanks
> > > > Liming
> > > > > -邮件原件-
> > > > > 发件人: devel@edk2.groups.io  代表 Huang,
> > > > Yanbo
> > > > > 发送时间: 2022年8月5日 10:42
> > > > > 收件人: devel@edk2.groups.io
> > > > > 抄送: Yanbo Huang ; Michael D Kinney
> > > > > ; Liming Gao
> > ;
> > > > > Zhiguang Liu 
> > > > > 主题: [edk2-devel] [PATCH] MdePkg/UefiDevicePathLib: reback the
> > > > > DevicePathUtilitiesStandaloneMm
> > > > >
> > > > > From: Yanbo Huang 
> > > > >
> > > > > reback the DevicePathUtilitiesStandaloneMm to unblock the
> > downstream
> > > > > sync
> > > > >
> > > > > Signed-off-by: Yanbo Huang 
> > > > > CC: Michael D Kinney 
> > > > > CC: Liming Gao 
> > > > > CC: Zhiguang Liu 
> > > > >
> > > > > ---
> > > > >  .../DevicePathUtilitiesStandaloneMm.c | 39 ++
> > > > >  .../UefiDevicePathLibStandaloneMm.inf | 75
> > > > > +++
> > > > >  2 files changed, 114 insertions(+)
> > > > >  create mode 100644
> > > > > MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesStandaloneMm.c
> > > > >  create mode 100644
> > > > >
> > MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf

Re: [edk2-devel] [PATCH 0/2] Remove mInternalCr3 in PiSmmCpuDxeSmm

[duntan]

Hi Sean,

The patch set is a code refactoring and doesn't change any functionality.  The 
reason for this code refactoring is because:
1. In PiSmmCpuDxe driver entrypoint, this driver initializes smm page table 
which is different from Cr3 register. Currently, mInternalCr3 is used to pass 
address of page table which is different from Cr3 register.
 Now remove it and pass the page table base address from the root function 
to simplify the code logic.
2. Besides, current code logic will regard a RO range as shadow stack and set 
the dirty bit in corresponding page table entry if mInternalCr3 is not 0. This 
assumption may be confusing.
A new mIsShadowStack flag will be created to identify if it is a shadow 
stack  or not.

Thanks,
Dun
From: Sean Brogan 
Sent: Wednesday, August 10, 2022 11:21 AM
To: devel@edk2.groups.io; Tan, Dun 
Subject: Re: [edk2-devel] [PATCH 0/2] Remove mInternalCr3 in PiSmmCpuDxeSmm

Is there any documentation to why this change is important and what exactly was 
broken?

Thanks
Sean

From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> on behalf of duntan 
mailto:dun@intel.com>>
Sent: Tuesday, August 9, 2022 6:45:30 PM
To: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>>
Subject: [edk2-devel] [PATCH 0/2] Remove mInternalCr3 in PiSmmCpuDxeSmm

Add a new IsShadowStack flag in PiSmmCpuDxeSmm.
Remove mInternalCr3 in PiSmmCpuDxeSmm.

Dun Tan (2):
  UefiCpuPkg/PiSmmCpuDxeSmm: Add a new IsShadowStack flag
  UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm

 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  30 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h |  26 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 113 
+
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  73 
+++--
 4 files changed, 98 insertions(+), 144 deletions(-)

--
2.31.1.windows.1







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Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new IsShadowStack flag

[duntan]

Ok, I'll send the V2 patch set soon.

Thanks,
Dun

-Original Message-
From: Ni, Ray  
Sent: Wednesday, August 10, 2022 11:52 AM
To: devel@edk2.groups.io; Tan, Dun 
Cc: Dong, Eric ; Kumar, Rahul R 
Subject: RE: [edk2-devel] [PATCH 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new 
IsShadowStack flag

Dun,
Can you please update the commit message to explain it's a code refactoring and 
doesn't change any functionality? Also explain why such refactoring is needed.

IsShadowStack: the name doesn't follow EDKII coding style.
You need to use "mIsShadowStack".

Thanks,
Ray

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of duntan
> Sent: Wednesday, August 10, 2022 9:46 AM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; 
> Kumar, Rahul R 
> Subject: [edk2-devel] [PATCH 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new 
> IsShadowStack flag
> 
> Add a new IsShadowStack flag to identify whether current memory is 
> shadow stack. The dirty bit in page table entry for this memory will 
> be set if IsShadowStack is TRUE, instead of depending on mInternalCr3.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 8
> +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> index 1f7cc15727..b369c0c435 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> @@ -33,6 +33,7 @@ PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {  };
> 
>  UINTN  mInternalCr3;
> +UINTN  IsShadowStack = FALSE;
> 
>  /**
>Set the internal page table base address.
> @@ -249,7 +250,7 @@ ConvertPageEntryAttribute (
>if ((Attributes & EFI_MEMORY_RO) != 0) {
>  if (IsSet) {
>NewPageEntry &= ~(UINT64)IA32_PG_RW;
> -  if (mInternalCr3 != 0) {
> +  if (IsShadowStack) {
>  // Environment setup
>  // ReadOnly page need set Dirty bit for shadow stack
>  NewPageEntry |= IA32_PG_D;
> @@ -734,10 +735,11 @@ SetShadowStack (
>EFI_STATUS  Status;
> 
>SetPageTableBase (Cr3);
> -
> -  Status = SmmSetMemoryAttributes (BaseAddress, Length, 
> EFI_MEMORY_RO);
> +  IsShadowStack = TRUE;
> +  Status= SmmSetMemoryAttributes (BaseAddress, Length,
> EFI_MEMORY_RO);
> 
>SetPageTableBase (0);
> +  IsShadowStack = FALSE;
> 
>return Status;
>  }
> --
> 2.31.1.windows.1
> 
> 
> 
> 
> 



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Re: [edk2-devel] [edk2-platforms: PATCH] Modify processor _UID ordering by CPU default fused in MADT

[Ni, Ray]

Good to know. Thanks

> -Original Message-
> From: Lin, JackX 
> Sent: Wednesday, August 10, 2022 11:51 AM
> To: Ni, Ray ; Sinha, Ankit 
> Cc: Chiu, Chasel ; Dong, Eric ;
> Yao, Jiewen ; Chaganty, Rangasai V
> ; devel@edk2.groups.io; Kuo, Donald
> ; Kumar, Chandana C
> ; Palakshareddy, Lavanya C
> ; Palakshareddy, Lavanya C
> 
> Subject: RE: [edk2-platforms: PATCH] Modify processor _UID ordering by
> CPU default fused in MADT
> 
> Hi Ray,
> 
> I know this patch, and the thread 2 and 3 are added by my request for a
> reason on that time.
> I will re-sent the code patch.
> Thank you.
> 
> Jack
> 
> -Original Message-
> From: Ni, Ray 
> Sent: Wednesday, August 10, 2022 11:48 AM
> To: Lin, JackX ; Sinha, Ankit 
> Cc: Chiu, Chasel ; Dong, Eric ;
> Yao, Jiewen ; Chaganty, Rangasai V
> ; devel@edk2.groups.io; Kuo, Donald
> ; Kumar, Chandana C
> ; Palakshareddy, Lavanya C
> ; Palakshareddy, Lavanya C
> 
> Subject: RE: [edk2-platforms: PATCH] Modify processor _UID ordering by
> CPU default fused in MADT
> 
> Jack,
> Your patch cannot be merged to trunk because Ankit just did some change in
> the same C file, in below commit.
> * MinPlatformPkg/AcpiTables: Add additional thread mapping in MADT
> 
> Ankit,
> It seems your patch is to add support for thread #2 and #3. Jack's patch is to
> remove the additional sorting that put secondary threads after first threads.
> Do you see an issue that we remove the thread sorting logic?
> 
> Thanks,
> Ray
> 
> > -Original Message-
> > From: Lin, JackX 
> > Sent: Monday, August 8, 2022 4:21 PM
> > To: devel@edk2.groups.io
> > Cc: Lin, JackX ; Lin, JackX
> > ; Chiu, Chasel ; Dong,
> > Eric ; Yao, Jiewen ; Ni,
> > Ray ; Chaganty, Rangasai V
> > ; Kuo, Donald ;
> > Kumar, Chandana C ; Palakshareddy;
> > Palakshareddy, Lavanya C 
> > Subject: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU
> > default fused in MADT
> >
> > BIOS should not reordering cpu processor_uid
> >
> > Signed-off-by: JackX Lin 
> > Cc: Chasel Chiu 
> > Cc: Dong Eric 
> > Cc: Jiewen Yao 
> > Cc: Ray Ni 
> > Cc: Rangasai V Chaganty 
> > Cc: Donald Kuo 
> > Cc: Chandana C Kumar 
> > Cc: Palakshareddy, Lavanya C 
> > Cc: JackX Lin 
> > ---
> >  Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 174
> > +++-
> --
> > --
> > 
> > --
> >  1 file changed, 39 insertions(+), 135 deletions(-)
> >
> > diff --git
> > a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > index c7e87cbd7d..176e422e81 100644
> > --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> > @@ -57,38 +57,9 @@ BOOLEAN mForceX2ApicId;
> >  BOOLEAN mX2ApicEnabled;
> >
> >  EFI_MP_SERVICES_PROTOCOL*mMpService;
> > -BOOLEAN mCpuOrderSorted;
> > -EFI_CPU_ID_ORDER_MAP*mCpuApicIdOrderTable = NULL;
> >  UINTN   mNumberOfCpus = 0;
> >  UINTN   mNumberOfEnabledCPUs = 0;
> >
> > -
> > -/**
> > -  The function is called by PerformQuickSort to compare int values.
> > -
> > -  @param[in] LeftThe pointer to first buffer.
> > -  @param[in] Right   The pointer to second buffer.
> > -
> > -  @return -1 Buffer1 is less than Buffer2.
> > -  @return  1 Buffer1 is greater than Buffer2.
> > -
> > -**/
> > -INTN
> > -EFIAPI
> > -ApicIdCompareFunction (
> > -  IN CONST VOID *Left,
> > -  IN CONST VOID *Right
> > -  )
> > -{
> > -  UINT32  LeftApicId;
> > -  UINT32  RightApicId;
> > -
> > -  LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
> > -  RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;
> > -
> > -  return (LeftApicId > RightApicId)? 1 : (-1); -}
> > -
> >  /**
> >Print Cpu Apic ID Table
> >
> > @@ -116,7 +87,8 @@ DebugDisplayReOrderTable (  EFI_STATUS
> > AppendCpuMapTableEntry (
> >  IN VOID   *ApicPtr,
> > -IN UINT32 LocalApicCounter
> > +IN UINT32 LocalApicCounter,
> > +IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
> >)
> >  {
> >EFI_STATUSStatus;
> > @@ -131,9 +103,9 @@ AppendCpuMapTableEntry (
> >
> >if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
> >  if(!mX2ApicEnabled) {
> > -  LocalApicPtr->Flags=
> > (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> > -  LocalApicPtr->ApicId   =
> > (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> > -  LocalApicPtr->AcpiProcessorUid =
> > (UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> > +  LocalApicPtr->Flags=
> > (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> > +  LocalApicPtr->ApicId   =
> > 

Re: [edk2-devel] [PATCH 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new IsShadowStack flag

[Ni, Ray]

Dun,
Can you please update the commit message to explain it's a code refactoring and
doesn't change any functionality? Also explain why such refactoring is needed.

IsShadowStack: the name doesn't follow EDKII coding style.
You need to use "mIsShadowStack".

Thanks,
Ray

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of duntan
> Sent: Wednesday, August 10, 2022 9:46 AM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul R 
> Subject: [edk2-devel] [PATCH 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a
> new IsShadowStack flag
> 
> Add a new IsShadowStack flag to identify whether current memory is
> shadow stack. The dirty bit in page table entry for this memory will
> be set if IsShadowStack is TRUE, instead of depending on mInternalCr3.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 8
> +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> index 1f7cc15727..b369c0c435 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> @@ -33,6 +33,7 @@ PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {
>  };
> 
>  UINTN  mInternalCr3;
> +UINTN  IsShadowStack = FALSE;
> 
>  /**
>Set the internal page table base address.
> @@ -249,7 +250,7 @@ ConvertPageEntryAttribute (
>if ((Attributes & EFI_MEMORY_RO) != 0) {
>  if (IsSet) {
>NewPageEntry &= ~(UINT64)IA32_PG_RW;
> -  if (mInternalCr3 != 0) {
> +  if (IsShadowStack) {
>  // Environment setup
>  // ReadOnly page need set Dirty bit for shadow stack
>  NewPageEntry |= IA32_PG_D;
> @@ -734,10 +735,11 @@ SetShadowStack (
>EFI_STATUS  Status;
> 
>SetPageTableBase (Cr3);
> -
> -  Status = SmmSetMemoryAttributes (BaseAddress, Length,
> EFI_MEMORY_RO);
> +  IsShadowStack = TRUE;
> +  Status= SmmSetMemoryAttributes (BaseAddress, Length,
> EFI_MEMORY_RO);
> 
>SetPageTableBase (0);
> +  IsShadowStack = FALSE;
> 
>return Status;
>  }
> --
> 2.31.1.windows.1
> 
> 
> 
> 
> 



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Re: [edk2-devel] [edk2-platforms: PATCH] Modify processor _UID ordering by CPU default fused in MADT

[JackX Lin]

Hi Ray,

I know this patch, and the thread 2 and 3 are added by my request for a reason 
on that time.
I will re-sent the code patch.
Thank you.

Jack

-Original Message-
From: Ni, Ray  
Sent: Wednesday, August 10, 2022 11:48 AM
To: Lin, JackX ; Sinha, Ankit 
Cc: Chiu, Chasel ; Dong, Eric ; 
Yao, Jiewen ; Chaganty, Rangasai V 
; devel@edk2.groups.io; Kuo, Donald 
; Kumar, Chandana C ; 
Palakshareddy, Lavanya C ; Palakshareddy, 
Lavanya C 
Subject: RE: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU 
default fused in MADT

Jack,
Your patch cannot be merged to trunk because Ankit just did some change in the 
same C file, in below commit.
* MinPlatformPkg/AcpiTables: Add additional thread mapping in MADT

Ankit,
It seems your patch is to add support for thread #2 and #3. Jack's patch is to 
remove the additional sorting that put secondary threads after first threads.
Do you see an issue that we remove the thread sorting logic?

Thanks,
Ray

> -Original Message-
> From: Lin, JackX 
> Sent: Monday, August 8, 2022 4:21 PM
> To: devel@edk2.groups.io
> Cc: Lin, JackX ; Lin, JackX 
> ; Chiu, Chasel ; Dong, 
> Eric ; Yao, Jiewen ; Ni, 
> Ray ; Chaganty, Rangasai V 
> ; Kuo, Donald ; 
> Kumar, Chandana C ; Palakshareddy; 
> Palakshareddy, Lavanya C 
> Subject: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU 
> default fused in MADT
> 
> BIOS should not reordering cpu processor_uid
> 
> Signed-off-by: JackX Lin 
> Cc: Chasel Chiu 
> Cc: Dong Eric 
> Cc: Jiewen Yao 
> Cc: Ray Ni 
> Cc: Rangasai V Chaganty 
> Cc: Donald Kuo 
> Cc: Chandana C Kumar 
> Cc: Palakshareddy, Lavanya C 
> Cc: JackX Lin 
> ---
>  Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 174
> +++---
> --
> 
> --
>  1 file changed, 39 insertions(+), 135 deletions(-)
> 
> diff --git 
> a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> index c7e87cbd7d..176e422e81 100644
> --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> @@ -57,38 +57,9 @@ BOOLEAN mForceX2ApicId;
>  BOOLEAN mX2ApicEnabled;
> 
>  EFI_MP_SERVICES_PROTOCOL*mMpService;
> -BOOLEAN mCpuOrderSorted;
> -EFI_CPU_ID_ORDER_MAP*mCpuApicIdOrderTable = NULL;
>  UINTN   mNumberOfCpus = 0;
>  UINTN   mNumberOfEnabledCPUs = 0;
> 
> -
> -/**
> -  The function is called by PerformQuickSort to compare int values.
> -
> -  @param[in] LeftThe pointer to first buffer.
> -  @param[in] Right   The pointer to second buffer.
> -
> -  @return -1 Buffer1 is less than Buffer2.
> -  @return  1 Buffer1 is greater than Buffer2.
> -
> -**/
> -INTN
> -EFIAPI
> -ApicIdCompareFunction (
> -  IN CONST VOID *Left,
> -  IN CONST VOID *Right
> -  )
> -{
> -  UINT32  LeftApicId;
> -  UINT32  RightApicId;
> -
> -  LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
> -  RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;
> -
> -  return (LeftApicId > RightApicId)? 1 : (-1); -}
> -
>  /**
>Print Cpu Apic ID Table
> 
> @@ -116,7 +87,8 @@ DebugDisplayReOrderTable (  EFI_STATUS  
> AppendCpuMapTableEntry (
>  IN VOID   *ApicPtr,
> -IN UINT32 LocalApicCounter
> +IN UINT32 LocalApicCounter,
> +IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
>)
>  {
>EFI_STATUSStatus;
> @@ -131,9 +103,9 @@ AppendCpuMapTableEntry (
> 
>if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
>  if(!mX2ApicEnabled) {
> -  LocalApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalApicPtr->ApicId   =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalApicPtr->AcpiProcessorUid =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalApicPtr->ApicId   =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalApicPtr->AcpiProcessorUid =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>LocalApicPtr->Flags= 0;
>LocalApicPtr->ApicId   = 0xFF;
> @@ -142,9 +114,9 @@ AppendCpuMapTableEntry (
>  }
>} else if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
>  if(mX2ApicEnabled) {
> -  LocalX2ApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalX2ApicPtr->X2ApicId =
> mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalX2ApicPtr->AcpiProcessorUid =
> 

Re: [edk2-devel] [edk2-platforms: PATCH] Modify processor _UID ordering by CPU default fused in MADT

[Ni, Ray]

Jack,
Your patch cannot be merged to trunk because Ankit just did some change in the 
same C file, in below commit.
* MinPlatformPkg/AcpiTables: Add additional thread mapping in MADT

Ankit,
It seems your patch is to add support for thread #2 and #3. Jack's patch is to 
remove the additional sorting that put
secondary threads after first threads.
Do you see an issue that we remove the thread sorting logic?

Thanks,
Ray

> -Original Message-
> From: Lin, JackX 
> Sent: Monday, August 8, 2022 4:21 PM
> To: devel@edk2.groups.io
> Cc: Lin, JackX ; Lin, JackX ; Chiu,
> Chasel ; Dong, Eric ; Yao,
> Jiewen ; Ni, Ray ; Chaganty,
> Rangasai V ; Kuo, Donald
> ; Kumar, Chandana C
> ; Palakshareddy; Palakshareddy, Lavanya C
> 
> Subject: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU
> default fused in MADT
> 
> BIOS should not reordering cpu processor_uid
> 
> Signed-off-by: JackX Lin 
> Cc: Chasel Chiu 
> Cc: Dong Eric 
> Cc: Jiewen Yao 
> Cc: Ray Ni 
> Cc: Rangasai V Chaganty 
> Cc: Donald Kuo 
> Cc: Chandana C Kumar 
> Cc: Palakshareddy, Lavanya C 
> Cc: JackX Lin 
> ---
>  Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 174
> +++---
> --
> --
>  1 file changed, 39 insertions(+), 135 deletions(-)
> 
> diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> index c7e87cbd7d..176e422e81 100644
> --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> @@ -57,38 +57,9 @@ BOOLEAN mForceX2ApicId;
>  BOOLEAN mX2ApicEnabled;
> 
>  EFI_MP_SERVICES_PROTOCOL*mMpService;
> -BOOLEAN mCpuOrderSorted;
> -EFI_CPU_ID_ORDER_MAP*mCpuApicIdOrderTable = NULL;
>  UINTN   mNumberOfCpus = 0;
>  UINTN   mNumberOfEnabledCPUs = 0;
> 
> -
> -/**
> -  The function is called by PerformQuickSort to compare int values.
> -
> -  @param[in] LeftThe pointer to first buffer.
> -  @param[in] Right   The pointer to second buffer.
> -
> -  @return -1 Buffer1 is less than Buffer2.
> -  @return  1 Buffer1 is greater than Buffer2.
> -
> -**/
> -INTN
> -EFIAPI
> -ApicIdCompareFunction (
> -  IN CONST VOID *Left,
> -  IN CONST VOID *Right
> -  )
> -{
> -  UINT32  LeftApicId;
> -  UINT32  RightApicId;
> -
> -  LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
> -  RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;
> -
> -  return (LeftApicId > RightApicId)? 1 : (-1);
> -}
> -
>  /**
>Print Cpu Apic ID Table
> 
> @@ -116,7 +87,8 @@ DebugDisplayReOrderTable (
>  EFI_STATUS
>  AppendCpuMapTableEntry (
>  IN VOID   *ApicPtr,
> -IN UINT32 LocalApicCounter
> +IN UINT32 LocalApicCounter,
> +IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
>)
>  {
>EFI_STATUSStatus;
> @@ -131,9 +103,9 @@ AppendCpuMapTableEntry (
> 
>if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
>  if(!mX2ApicEnabled) {
> -  LocalApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalApicPtr->ApicId   =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalApicPtr->AcpiProcessorUid =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalApicPtr->ApicId   =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalApicPtr->AcpiProcessorUid =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>LocalApicPtr->Flags= 0;
>LocalApicPtr->ApicId   = 0xFF;
> @@ -142,9 +114,9 @@ AppendCpuMapTableEntry (
>  }
>} else if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
>  if(mX2ApicEnabled) {
> -  LocalX2ApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalX2ApicPtr->X2ApicId =
> mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalX2ApicPtr->AcpiProcessorUid =
> mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalX2ApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalX2ApicPtr->X2ApicId =
> CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalX2ApicPtr->AcpiProcessorUid =
> CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>LocalX2ApicPtr->Flags= 0;
>LocalX2ApicPtr->X2ApicId = (UINT32)-1;
> @@ -159,32 +131,25 @@ AppendCpuMapTableEntry (
> 
>  }
> 
> +/**
> +  Collect all processors information and create a Cpu Apic Id 

Re: [edk2-devel] [PATCH 0/2] Remove mInternalCr3 in PiSmmCpuDxeSmm

[Sean]

Is there any documentation to why this change is important and what exactly was 
broken?

Thanks
Sean

From: devel@edk2.groups.io  on behalf of duntan 

Sent: Tuesday, August 9, 2022 6:45:30 PM
To: devel@edk2.groups.io 
Subject: [edk2-devel] [PATCH 0/2] Remove mInternalCr3 in PiSmmCpuDxeSmm

Add a new IsShadowStack flag in PiSmmCpuDxeSmm.
Remove mInternalCr3 in PiSmmCpuDxeSmm.

Dun Tan (2):
  UefiCpuPkg/PiSmmCpuDxeSmm: Add a new IsShadowStack flag
  UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm

 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  30 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h |  26 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 113 
+
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  73 
+++--
 4 files changed, 98 insertions(+), 144 deletions(-)

--
2.31.1.windows.1








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[edk2-devel] [PATCH 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm

[duntan]

Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. Currently,
mInternalCr3 is used to pass address of pagetable which is different
from Cr3 register. Now remove it and pass the page table base address
from the root function to simplify the code logic.

Change-Id: I8f58158b94a01cf829f1b4fb2b8c763dcdda0662
Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
Signed-off-by: Dun Tan 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  30 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h |  26 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 107 
+--
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  73 
+++--
 4 files changed, 94 insertions(+), 142 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
index 8ec8790c05..97058a2810 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
@@ -28,26 +28,6 @@ EnableCet (
   VOID
   );
 
-/**
-  Get page table base address and the depth of the page table.
-
-  @param[out] BasePage table base address.
-  @param[out] FiveLevels  TRUE means 5 level paging. FALSE means 4 level 
paging.
-**/
-VOID
-GetPageTable (
-  OUT UINTN*Base,
-  OUT BOOLEAN  *FiveLevels OPTIONAL
-  )
-{
-  *Base = ((mInternalCr3 == 0) ?
-   (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :
-   mInternalCr3);
-  if (FiveLevels != NULL) {
-*FiveLevels = FALSE;
-  }
-}
-
 /**
   Create PageTable for SMM use.
 
@@ -297,10 +277,10 @@ SetPageTableAttributes (
 DEBUG ((DEBUG_INFO, "Start...\n"));
 PageTableSplitted = FALSE;
 
-GetPageTable (, NULL);
-L3PageTable = (UINT64 *)PageTableBase;
+PageTableBase = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
+L3PageTable   = (UINT64 *)PageTableBase;
 
-SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, 
EFI_MEMORY_RO, );
+SmmSetMemoryAttributesEx (PageTableBase, FALSE, 
(EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, );
 PageTableSplitted = (PageTableSplitted || IsSplitted);
 
 for (Index3 = 0; Index3 < 4; Index3++) {
@@ -309,7 +289,7 @@ SetPageTableAttributes (
 continue;
   }
 
-  SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, 
SIZE_4KB, EFI_MEMORY_RO, );
+  SmmSetMemoryAttributesEx (PageTableBase, FALSE, 
(EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, );
   PageTableSplitted = (PageTableSplitted || IsSplitted);
 
   for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
@@ -323,7 +303,7 @@ SetPageTableAttributes (
   continue;
 }
 
-SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, 
SIZE_4KB, EFI_MEMORY_RO, );
+SmmSetMemoryAttributesEx (PageTableBase, FALSE, 
(EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, );
 PageTableSplitted = (PageTableSplitted || IsSplitted);
   }
 }
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h 
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index dfeceec2aa..ef8bf5947d 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -264,7 +264,7 @@ extern UINTN mMaxNumberOfCpus;
 extern UINTN mNumberOfCpus;
 extern EFI_SMM_CPU_PROTOCOL  mSmmCpu;
 extern EFI_MM_MP_PROTOCOLmSmmMp;
-extern UINTN mInternalCr3;
+extern BOOLEAN   m5LevelPagingNeeded;
 
 ///
 /// The mode of the CPU at the time an SMI occurs
@@ -682,7 +682,6 @@ SmmBlockingStartupThisAp (
 
 **/
 EFI_STATUS
-EFIAPI
 SmmSetMemoryAttributes (
   IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
   IN  UINT64Length,
@@ -712,7 +711,6 @@ SmmSetMemoryAttributes (
 
 **/
 EFI_STATUS
-EFIAPI
 SmmClearMemoryAttributes (
   IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
   IN  UINT64Length,
@@ -957,22 +955,12 @@ SetPageTableAttributes (
   VOID
   );
 
-/**
-  Get page table base address and the depth of the page table.
-
-  @param[out] BasePage table base address.
-  @param[out] FiveLevels  TRUE means 5 level paging. FALSE means 4 level 
paging.
-**/
-VOID
-GetPageTable (
-  OUT UINTN*Base,
-  OUT BOOLEAN  *FiveLevels OPTIONAL
-  );
-
 /**
   This function sets the attributes for the memory region specified by 
BaseAddress and
   Length from their current attributes to the attributes specified by 
Attributes.
 
+  @param[in]   PageTableBaseThe page table base.
+  @param[in]   EnablePML5Paging If PML5 paging is enabled.
   @param[in]   BaseAddress  The physical address that is the start address 
of a memory region.
   @param[in]   Length   The size in bytes of the memory region.
   @param[in]   Attributes  

[edk2-devel] [PATCH 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new IsShadowStack flag

[duntan]

Add a new IsShadowStack flag to identify whether current memory is
shadow stack. The dirty bit in page table entry for this memory will
be set if IsShadowStack is TRUE, instead of depending on mInternalCr3.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Cc: Ray Ni 
Cc: Rahul Kumar 
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index 1f7cc15727..b369c0c435 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -33,6 +33,7 @@ PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {
 };
 
 UINTN  mInternalCr3;
+UINTN  IsShadowStack = FALSE;
 
 /**
   Set the internal page table base address.
@@ -249,7 +250,7 @@ ConvertPageEntryAttribute (
   if ((Attributes & EFI_MEMORY_RO) != 0) {
 if (IsSet) {
   NewPageEntry &= ~(UINT64)IA32_PG_RW;
-  if (mInternalCr3 != 0) {
+  if (IsShadowStack) {
 // Environment setup
 // ReadOnly page need set Dirty bit for shadow stack
 NewPageEntry |= IA32_PG_D;
@@ -734,10 +735,11 @@ SetShadowStack (
   EFI_STATUS  Status;
 
   SetPageTableBase (Cr3);
-
-  Status = SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
+  IsShadowStack = TRUE;
+  Status= SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
 
   SetPageTableBase (0);
+  IsShadowStack = FALSE;
 
   return Status;
 }
-- 
2.31.1.windows.1



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[edk2-devel] [PATCH 0/2] Remove mInternalCr3 in PiSmmCpuDxeSmm

[duntan]

Add a new IsShadowStack flag in PiSmmCpuDxeSmm.
Remove mInternalCr3 in PiSmmCpuDxeSmm.

Dun Tan (2):
  UefiCpuPkg/PiSmmCpuDxeSmm: Add a new IsShadowStack flag
  UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm

 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c   |  30 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h |  26 
+-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 113 
+
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c|  73 
+++--
 4 files changed, 98 insertions(+), 144 deletions(-)

-- 
2.31.1.windows.1



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[edk2-devel] [PATCH] MdeModulePkg/DxeIpl: Remove clearing CR0.WP when protecting pagetable

[duntan]

Remove clearing CR0.WP when marking the memory used for page table
to be read-only in the page table itself created by DxeIpl or
UefiPayloadEntry/UniversalPayloadEntry. This page table address is
written to Cr3 after these protection steps. Till this, the page
table is always RW.

Change-Id: Ibd65fb68ddfa3ea2931004d2d27b6023f457ab46
Signed-off-by: Dun Tan 
Cc: Dandan Bi 
Cc: Liming Gao 
Cc: Ray Ni 
---
 MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c| 7 +--
 UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c | 7 +--
 2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c 
b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index a451ca1604..18b121d768 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -626,12 +626,7 @@ EnablePageTableProtection (
   }
 
   //
-  // Disable write protection, because we need to mark page table to be write
-  // protected.
-  //
-  AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
-
-  //
+  // No need to clear CR0.WP since PageTableBase has't been written to CR3 yet.
   // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
   // remember original one in advance.
   //
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c 
b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index 74b667a62a..a586941352 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -622,12 +622,7 @@ EnablePageTableProtection (
   }
 
   //
-  // Disable write protection, because we need to mark page table to be write
-  // protected.
-  //
-  AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
-
-  //
+  // No need to clear CR0.WP since PageTableBase has't been written to CR3 yet.
   // SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
   // remember original one in advance.
   //
-- 
2.31.1.windows.1



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[edk2-devel] Event: TianoCore Bug Triage - APAC / NAMO - 08/09/2022 #cal-reminder

[Group Notification]

*Reminder: TianoCore Bug Triage - APAC / NAMO*

*When:*
08/09/2022
6:30pm to 7:30pm
(UTC-07:00) America/Los Angeles

*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTk1YzJhN2UtOGQwNi00NjY4LWEwMTktY2JiODRlYTY1NmY0%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%226e4ce4c4-1242-431b-9a51-92cd01a5df3c%22%7d

*Organizer:* Liming Gao gaolim...@byosoft.com.cn ( 
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 )

View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=1268262 )

*Description:*

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Re: [edk2-devel] [PATCH 0/4] IntelFsp2(Wrapper)Pkg: Support FSP 2.4 MultiPhase.

[Chiu, Chasel]

Thanks Nate for detail reviewing and all the good feedbacks!
I have applied all of them and sent a V2 patch series, please help to review 
again.


From: Desimone, Nathaniel L 
Sent: Thursday, August 4, 2022 5:51 PM
To: Chiu, Chasel ; devel@edk2.groups.io
Cc: Zeng, Star 
Subject: RE: [PATCH 0/4] IntelFsp2(Wrapper)Pkg: Support FSP 2.4 MultiPhase.

Hi Chasel,

I have a few comments for you.

First, we should have a platform provided LibraryClass for running code in 
between multi-phase actions. Right now you just have this comment in 
IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c:

//
// Platform handling can be added here to take care specific actions for 
each phase
// before returning control back to FSP.
//

I would like a new LibraryClass added: FspWrapperPlatformMultiPhaseLib

This would implement a single function:

VOID
EFIAPI
FspWrapperPlatformMultiPhaseHandler (
  IN UINT8 ComponentIndex,
  IN UINT32PhaseIndex
 );

Add an implementation of this in 
IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformMultiPhaseLibSample. That 
.inf will provide an implementation of FspWrapperPlatformMultiPhaseHandler() 
that doesn't do anything (just leave it empty).

Then, invoke FspWrapperPlatformMultiPhaseHandler() at the point where you have 
that comment above in FspWrapperMultiPhaseHandler().

The *BoardPkg can provide an SOC specific implementation. Typically the real 
*BoardPkg implementation will look something like this:

VOID
EFIAPI
FspWrapperPlatformMultiPhaseHandler (
  IN UINT8 ComponentIndex,
  IN UINT32PhaseIndex
 )
{
  switch (ComponentIndex) {
  case FspMultiPhaseMemInitApiIndex:
switch (PhaseIndex) {
  case 1:
PeiServicesInstallPpi (mSomePlatformSpecificNotifyPpi1);
  break;
}
break;
  case FspMultiPhaseSiInitApiIndex:
switch (PhaseIndex) {
  case 1:
PeiServicesInstallPpi (mSomePlatformSpecificNotifyPpi2);
  break;
}
break;
  }
}

The exact specifics would vary by SOC design and are out of scope for this 
patch series. But you do need to provide the base case of "do nothing" in 
IntelFsp2WrapperPkg.

Second, in 
IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c:

  case EnumFspVariableRequestSetVariable:
if (WriteVariableSupport) {
  Status = VariablePpi->SetVariable (
  VariablePpi,
  FspVariableRequestParams->VariableName,
  FspVariableRequestParams->VariableGuid,
  *FspVariableRequestParams->Attributes,
  (UINTN)*FspVariableRequestParams->DataSize,
  FspVariableRequestParams->Data
  );
} else {
  return EFI_UNSUPPORTED;
}

Instead of return EFI_UNSUPPORTED; it should be Status = EFI_UNSUPPORTED;. Same 
thing with EnumFspVariableRequestQueryVariableInfo.

Third, in FspWrapperVariableRequestHandler(), after you call 
EnumMultiPhaseCompleteVariableRequest you need to check if one of the 
FSP_STATUS_RESET_REQUIRED_* status codes is returned and if so invoke 
CallFspWrapperResetSystem().

Fourth, there is a bug in IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c:

FspWrapperVariableRequestHandler (, 
FspMultiPhaseMemInitApiIndex);

Should be this:

FspWrapperVariableRequestHandler (, 
FspMultiPhaseSiInitApiIndex);

Fifth, I noticed some spelling errors in 
IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c:

// Firstly querry variable request informaiton from FSP.

Should be:

// Get the variable request information from FSP.

And this:

  // Firstly querry FSP for how many phases supported.

Should be:

  // Query FSP for the number of phases supported.

Thanks,
Nate



-Original Message-
From: Chiu, Chasel mailto:chasel.c...@intel.com>>
Sent: Thursday, August 4, 2022 5:20 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel mailto:chasel.c...@intel.com>>; 
Desimone, Nathaniel L 
mailto:nathaniel.l.desim...@intel.com>>; Zeng, 
Star mailto:star.z...@intel.com>>
Subject: [PATCH 0/4] IntelFsp2(Wrapper)Pkg: Support FSP 2.4 MultiPhase.



REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916



Add FSP 2.4 MultiPhase interfaces and implementation.



Cc: Nate DeSimone 
mailto:nathaniel.l.desim...@intel.com>>

Cc: Star Zeng mailto:star.z...@intel.com>>

Signed-off-by: Chasel Chiu mailto:chasel.c...@intel.com>>



Chasel Chiu (4):

  IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface.

  IntelFsp2WrapperPkg: Add FSP 2.4 MultiPhase interface.

  IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.

  IntelFsp2WrapperPkg: Implement FSP 2.4 MultiPhase wrapper handlers.



IntelFsp2Pkg/FspSecCore/SecFsp.c
   |   4 

[edk2-devel] [PATCH v2 2/4] IntelFsp2WrapperPkg: Add FSP 2.4 MultiPhase interface.

[Chiu, Chasel]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916

Provide FSP 2.4 MultiPhase wrapper support library.

Cc: Nate DeSimone 
Cc: Star Zeng 
Signed-off-by: Chasel Chiu 
---
 
IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformMultiPhaseLibSample/FspWrapperPlatformMultiPhaseLibSample.c
   |  49 +
 
IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c
  | 355 
+++
 IntelFsp2WrapperPkg/Include/Library/FspWrapperMultiPhaseProcessLib.h   
 |  62 
++
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
 |  10 +-
 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dsc
 |   6 +-
 
IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformMultiPhaseLibSample/BaseFspWrapperPlatformMultiPhaseLibSample.inf
 |  37 +
 
IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/FspWrapperMultiPhaseProcessLib.inf
   |  48 
 7 files changed, 565 insertions(+), 2 deletions(-)

diff --git 
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformMultiPhaseLibSample/FspWrapperPlatformMultiPhaseLibSample.c
 
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformMultiPhaseLibSample/FspWrapperPlatformMultiPhaseLibSample.c
new file mode 100644
index 00..ef8819203d
--- /dev/null
+++ 
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformMultiPhaseLibSample/FspWrapperPlatformMultiPhaseLibSample.c
@@ -0,0 +1,49 @@
+/** @file
+  Support FSP MultiPhase process.
+
+  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+
+/**
+  FSP Wrapper Platform MultiPhase Handler
+
+  @param[in] FspHobListPtr- Pointer to FSP HobList (valid after FSP-M 
completed)
+  @param[in] ComponentIndex   - FSP Component which executing MultiPhase 
initialization.
+  @param[in] PhaseIndex   - Indicates current execution phase of FSP 
MultiPhase initialization.
+
+  @retval EFI_STATUSAlways return EFI_SUCCESS
+
+**/
+VOID
+EFIAPI
+FspWrapperPlatformMultiPhaseHandler (
+  IN OUT VOID  **FspHobListPtr,
+  IN UINT8 ComponentIndex,
+  IN UINT32PhaseIndex
+  )
+{
+  /* Example platform actions as below
+  switch (ComponentIndex) {
+  case FspMultiPhaseMemInitApiIndex:
+switch (PhaseIndex) {
+  case 1:
+PlatformAction1 ();
+  break;
+}
+break;
+  case FspMultiPhaseSiInitApiIndex:
+switch (PhaseIndex) {
+  case 1:
+PlatformAction2 ();
+  break;
+}
+break;
+  }
+  */
+}
diff --git 
a/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c
 
b/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c
new file mode 100644
index 00..c29a8277df
--- /dev/null
+++ 
b/IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c
@@ -0,0 +1,355 @@
+/** @file
+  Support FSP MultiPhase process.
+
+  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Execute 32-bit FSP API entry code.
+
+  @param[in] Function The 32bit code entry to be executed.
+  @param[in] Param1   The first parameter to pass to 32bit code.
+  @param[in] Param2   The second parameter to pass to 32bit code.
+
+  @return EFI_STATUS.
+**/
+EFI_STATUS
+Execute32BitCode (
+  IN UINT64  Function,
+  IN UINT64  Param1,
+  IN UINT64  Param2
+  );
+
+/**
+  Execute 64-bit FSP API entry code.
+
+  @param[in] Function The 64bit code entry to be executed.
+  @param[in] Param1   The first parameter to pass to 64bit code.
+  @param[in] Param2   The second parameter to pass to 64bit code.
+
+  @return EFI_STATUS.
+**/
+EFI_STATUS
+Execute64BitCode (
+  IN UINT64  Function,
+  IN UINT64  Param1,
+  IN UINT64  Param2
+  );
+
+/**
+  Call FspsMultiPhase API.
+
+  @param[in] FspsMultiPhaseParams - Parameters for MultiPhase API.
+  @param[in] FspHobListPtr- Pointer to FSP HobList (valid after FSP-M 
completed)
+  @param[in] ComponentIndex   - FSP Component which executing MultiPhase 
initialization.
+
+  

[edk2-devel] [PATCH v2 1/4] IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface.

[Chiu, Chasel]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916

Provide FSP 2.4 MultiPhase interface and scripts
support.

Cc: Nate DeSimone 
Cc: Star Zeng 
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c   | 184 

 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c |  30 
++
 IntelFsp2Pkg/Include/FspEas/FspApi.h   |  62 
--
 IntelFsp2Pkg/Include/FspGlobalData.h   |   5 -
 IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h|  54 
++
 IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h   |  19 
+++
 IntelFsp2Pkg/IntelFsp2Pkg.dec  |  12 
++--
 IntelFsp2Pkg/IntelFsp2Pkg.dsc  |   4 
 IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf |  50 
++
 IntelFsp2Pkg/Tools/SplitFspBin.py  |  48 
+---
 10 files changed, 440 insertions(+), 28 deletions(-)

diff --git a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c 
b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c
new file mode 100644
index 00..1ab355085b
--- /dev/null
+++ b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c
@@ -0,0 +1,184 @@
+/** @file
+  Null instance of Platform Sec Lib.
+
+  Copyright (c) 2022, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+EFI_STATUS
+EFIAPI
+FspMultiPhaseSwitchStack (
+  )
+{
+  SetFspApiReturnStatus (EFI_SUCCESS);
+  Pei2LoaderSwitchStack ();
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+FspVariableRequestSwitchStack (
+  IN FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS  *FspVariableRequestParams
+  )
+{
+  FSP_GLOBAL_DATA  *FspData;
+
+  FspData = GetFspGlobalDataPointer ();
+  if (((UINTN)FspData == 0) || ((UINTN)FspData == 0x)) {
+return EFI_UNSUPPORTED;
+  }
+
+  FspData->VariableRequestParameterPtr = (VOID *)FspVariableRequestParams;
+  SetFspApiReturnStatus (FSP_STATUS_VARIABLE_REQUEST);
+  Pei2LoaderSwitchStack ();
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function supports FspMultiPhase implementation.
+
+  @param[in]  ApiIdx   Internal index of the FSP API.
+  @param[in]  ApiParam Parameter of the FSP API.
+
+  @retval EFI_SUCCESS FSP execution was successful.
+  @retval EFI_INVALID_PARAMETER   Input parameters are invalid.
+  @retval EFI_UNSUPPORTED The FSP calling conditions were not met.
+  @retval EFI_DEVICE_ERRORFSP initialization failed.
+**/
+EFI_STATUS
+EFIAPI
+FspMultiPhaseWorker (
+  IN UINT32  ApiIdx,
+  IN VOID*ApiParam
+  )
+{
+  FSP_MULTI_PHASE_PARAMS   *FspMultiPhaseParams;
+  FSP_GLOBAL_DATA  *FspData;
+  FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS  *FspMultiPhaseGetNumber;
+  BOOLEAN  FspDataValid;
+  UINT32   NumberOfPhasesSupported;
+
+  FspDataValid = TRUE;
+  FspData  = GetFspGlobalDataPointer ();
+  if (((UINTN)FspData == 0) || ((UINTN)FspData == 0x)) {
+FspDataValid = FALSE;
+  }
+
+  //
+  // It is required that FspData->NumberOfPhases to be reset to 0 after
+  // current FSP component finished.
+  // The next component FspData->NumberOfPhases will only be re-initialized 
when FspData->NumberOfPhases = 0
+  //
+  if ((FspDataValid == TRUE) && (FspData->NumberOfPhases == 0)) {
+FspData->NumberOfPhases = PcdGet32 (PcdMultiPhaseNumberOfPhases);
+FspData->PhasesExecuted = 0;
+if (FspMultiPhasePlatformGetNumberOfPhases (ApiIdx, 
) == TRUE) {
+  //
+  // Platform has implemented runtime controling for 
NumberOfPhasesSupported
+  //
+  FspData->NumberOfPhases = NumberOfPhasesSupported;
+}
+  }
+
+  FspMultiPhaseParams = (FSP_MULTI_PHASE_PARAMS *)ApiParam;
+
+  if (FspDataValid == FALSE) {
+return EFI_DEVICE_ERROR;
+  } else {
+switch (FspMultiPhaseParams->MultiPhaseAction) {
+  case EnumMultiPhaseGetNumberOfPhases:
+if ((FspMultiPhaseParams->MultiPhaseParamPtr == NULL) || 
(FspMultiPhaseParams->PhaseIndex != 0)) {
+  return EFI_INVALID_PARAMETER;
+}
+
+FspMultiPhaseGetNumber = 
(FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS 
*)FspMultiPhaseParams->MultiPhaseParamPtr;
+FspMultiPhaseGetNumber->NumberOfPhases = 

[edk2-devel] [PATCH v2 3/4] IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.

[Chiu, Chasel]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916

Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM.
For backward compatibility, new INF are created for new modules.

Cc: Nate DeSimone 
Cc: Star Zeng 
Signed-off-by: Chasel Chiu 
---
 IntelFsp2Pkg/FspSecCore/SecFsp.c|   4 
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c  |   9 +
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf   |  75 
+++
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf   |  59 
+++
 IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm| 304 

 IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm| 101 
+
 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm |   3 +++
 IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm | 303 
+++
 IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm | 108 

 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm  |   3 +++
 10 files changed, 969 insertions(+)

diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index d9085ef51f..11be1f97ca 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -135,6 +135,10 @@ FspGlobalDataInit (
   PeiFspData->CoreStack = BootLoaderStack;
   PeiFspData->PerfIdx   = 2;
   PeiFspData->PerfSig   = FSP_PERFORMANCE_DATA_SIGNATURE;
+  //
+  // Cache FspHobList pointer passed by bootloader via ApiParameter2
+  //
+  PeiFspData->FspHobListPtr = (VOID **)GetFspApiParameter2 ();
 
   SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY);
 
diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c 
b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index 35d223a404..a44fbf2a50 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -69,8 +69,17 @@ FspApiCallingCheck (
 Status = EFI_UNSUPPORTED;
   } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, 
ApiParam))) {
 Status = EFI_INVALID_PARAMETER;
+  } else if (ApiIdx == FspSiliconInitApiIndex) {
+//
+// Reset MultiPhase NumberOfPhases to zero
+//
+FspData->NumberOfPhases = 0;
   }
 }
+  } else if (ApiIdx == FspMultiPhaseMemInitApiIndex) {
+if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS) || 
((UINTN)FspData == MAX_UINT32)) {
+  Status = EFI_UNSUPPORTED;
+}
   } else if (ApiIdx == FspSmmInitApiIndex) {
 //
 // FspSmmInitApiIndex check
diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
new file mode 100644
index 00..e93e176f15
--- /dev/null
+++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -0,0 +1,75 @@
+## @file
+#  Sec Core for FSP to support MultiPhase (SeparatePhase) MemInitialization.
+#
+#  Copyright (c) 2022, Intel Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = Fsp24SecCoreM
+  FILE_GUID  = C5BC0719-4A23-4F6E-94DA-05FB6A0DFA9C
+  MODULE_TYPE= SEC
+  VERSION_STRING = 1.0
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = IA32 X64
+#
+
+[Sources]
+  SecMain.c
+  SecMain.h
+  SecFsp.c
+  SecFsp.h
+  SecFspApiChk.c
+
+[Sources.IA32]
+  Ia32/Stack.nasm
+  Ia32/Fsp24ApiEntryM.nasm
+  Ia32/FspApiEntryCommon.nasm
+  Ia32/FspHelper.nasm
+  Ia32/ReadEsp.nasm
+
+[Sources.X64]
+  X64/Stack.nasm
+  X64/Fsp24ApiEntryM.nasm
+  X64/FspApiEntryCommon.nasm
+  X64/FspHelper.nasm
+  X64/ReadRsp.nasm
+
+[Binaries.Ia32]
+  RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
+
+[Packages]
+  MdePkg/MdePkg.dec
+  IntelFsp2Pkg/IntelFsp2Pkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseMemoryLib
+  DebugLib
+  BaseLib
+  PciCf8Lib
+  SerialPortLib
+  FspSwitchStackLib
+  FspCommonLib
+  FspSecPlatformLib
+  CpuLib
+  UefiCpuLib
+  FspMultiPhaseLib
+
+[Pcd]
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES
+  

[edk2-devel] [PATCH v2 0/4] IntelFsp2(Wrapper)Pkg: Support FSP 2.4 MultiPhase.

[Chiu, Chasel]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916

Add FSP 2.4 MultiPhase interfaces and implementation.

Cc: Nate DeSimone 
Cc: Star Zeng 
Signed-off-by: Chasel Chiu 

V2:
. Add FspMultiPhasePlatformGetNumberOfPhases() and
FspWrapperPlatformMultiPhaseHandler() to support
platform porting.

. Add FSP reset support in FspWrapperVariableRequestHandler()

. Fix bug that wrong parameter given when calling
FspWrapperVariableRequestHandler()

. Corrected code comments.

Chasel Chiu (4):
  IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface.
  IntelFsp2WrapperPkg: Add FSP 2.4 MultiPhase interface.
  IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.
  IntelFsp2WrapperPkg: Implement FSP 2.4 MultiPhase wrapper handlers.

 IntelFsp2Pkg/FspSecCore/SecFsp.c   
 |   4 
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c 
 |   9 +
 IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c   
 | 184 

 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c 
 |  30 ++
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c  
 |  33 +
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c  
 |  27 +--
 
IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformMultiPhaseLibSample/FspWrapperPlatformMultiPhaseLibSample.c
   |  49 +
 
IntelFsp2WrapperPkg/Library/FspWrapperMultiPhaseProcessLib/PeiFspWrapperMultiPhaseProcessLib.c
  | 355 
+++
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf  
 |  75 
+++
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf  
 |  59 
+++
 IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm   
 | 304 

 IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm   
 | 101 
+
 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm
 |   3 +++
 IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm
 | 303 
+++
 IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm
 | 108 

 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm 
 |   3 +++
 IntelFsp2Pkg/Include/FspEas/FspApi.h   
 |  62 
--
 IntelFsp2Pkg/Include/FspGlobalData.h   
 |   5 -
 IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h
 |  54 
++
 IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h   
 |  

[edk2-devel] [PATCH v2 4/4] IntelFsp2WrapperPkg: Implement FSP 2.4 MultiPhase wrapper handlers.

[Chiu, Chasel]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916

Implement MultiPhase wrapper handlers and only call to MultiPhase
handlers when FSP supports.

Cc: Nate DeSimone 
Cc: Star Zeng 
Signed-off-by: Chasel Chiu 
---
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c   | 33 
+
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c   | 27 
+--
 IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf |  1 +
 IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf |  3 ++-
 4 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index ac27524d08..ea206a7960 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -35,6 +36,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 extern EFI_GUID  gFspHobGuid;
 
@@ -119,25 +122,39 @@ PeiFspMemoryInit (
 
   TimeStampCounterStart = AsmReadTsc ();
   Status= CallFspMemoryInit (FspmUpdDataPtr, );
-  // Create hobs after memory initialization and not in temp RAM. Hence 
passing the recorded timestamp here
-  PERF_START_EX (, "EventRec", NULL, 
TimeStampCounterStart, FSP_STATUS_CODE_MEMORY_INIT | 
FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
-  PERF_END_EX (, "EventRec", NULL, 0, 
FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | 
FSP_STATUS_CODE_API_EXIT);
-  DEBUG ((DEBUG_INFO, "Total time spent executing FspMemoryInitApi: %d 
millisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - 
TimeStampCounterStart), 100)));
 
   //
   // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status
   //
   if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= 
FSP_STATUS_RESET_REQUIRED_8)) {
-DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status));
+DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset %r\n", Status));
 CallFspWrapperResetSystem (Status);
   }
 
-  if (EFI_ERROR (Status)) {
+  if ((Status != FSP_STATUS_VARIABLE_REQUEST) && EFI_ERROR (Status)) {
 DEBUG ((DEBUG_ERROR, "ERROR - Failed to execute FspMemoryInitApi(), Status 
= %r\n", Status));
+ASSERT_EFI_ERROR (Status);
   }
 
-  DEBUG ((DEBUG_INFO, "FspMemoryInit status: 0x%x\n", Status));
-  ASSERT_EFI_ERROR (Status);
+  DEBUG ((DEBUG_INFO, "FspMemoryInit status: %r\n", Status));
+  if (Status == FSP_STATUS_VARIABLE_REQUEST) {
+//
+// call to Variable request handler
+//
+FspWrapperVariableRequestHandler (, 
FspMultiPhaseMemInitApiIndex);
+  }
+
+  //
+  // See if MultiPhase process is required or not
+  //
+  FspWrapperMultiPhaseHandler (, FspMultiPhaseMemInitApiIndex);  
  // FspM MultiPhase
+
+  //
+  // Create hobs after memory initialization and not in temp RAM. Hence 
passing the recorded timestamp here
+  //
+  PERF_START_EX (, "EventRec", NULL, 
TimeStampCounterStart, FSP_STATUS_CODE_MEMORY_INIT | 
FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);
+  PERF_END_EX (, "EventRec", NULL, 0, 
FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | 
FSP_STATUS_CODE_API_EXIT);
+  DEBUG ((DEBUG_INFO, "Total time spent executing FspMemoryInitApi: %d 
millisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - 
TimeStampCounterStart), 100)));
 
   Status = TestFspMemoryInitApiOutput (FspmUpdDataPtr, );
   if (EFI_ERROR (Status)) {
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c 
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index ee48dd69d3..091ddb697a 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -36,6 +37,7 @@
 #include 
 #include 
 #include 
+#include 
 
 extern EFI_PEI_NOTIFY_DESCRIPTOR  mS3EndOfPeiNotifyDesc;
 extern EFI_GUID   gFspHobGuid;
@@ -318,23 +320,36 @@ PeiMemoryDiscoveredNotify (
   TimeStampCounterStart = AsmReadTsc ();
   PERF_START_EX (, "EventRec", NULL, 0, 
FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | 
FSP_STATUS_CODE_API_ENTRY);
   Status = CallFspSiliconInit ((VOID *)FspsUpdDataPtr);
-  PERF_END_EX (, "EventRec", NULL, 0, 
FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | 
FSP_STATUS_CODE_API_EXIT);
-  DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d 
millisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - 
TimeStampCounterStart), 100)));
 
   //
   // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status
   //
   if ((Status >= FSP_STATUS_RESET_REQUIRED_COLD) && (Status <= 
FSP_STATUS_RESET_REQUIRED_8)) {
-DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status));
+DEBUG ((DEBUG_INFO, 

Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: USB Redfish host interface is not supported

[Chang, Abner via groups.io]

Yes, please create the new patch set with the prefix [PATCH V2]. Also, use git 
move to move Redfish.h to Include\ to keep the commit history, this one could 
be the patch 3.

Thank you,
Abner

Get Outlook for Android

From: Igor Kulchytskyy 
Sent: Wednesday, August 10, 2022 3:21:46 AM
To: Chang, Abner ; devel@edk2.groups.io 

Cc: nickle.w...@hpe.com 
Subject: RE: [EXTERNAL] RE: [PATCH] RedfishPkg: RedfishDiscoverDxe: USB Redfish 
host interface is not supported

[CAUTION: External Email]

Hi Abner,
Thank you for your feedback.
I agree with you.
What should I do to change it?
Should I create a new patch?
Thank you,
Igor

-Original Message-
From: Chang, Abner 
Sent: Tuesday, August 09, 2022 3:35 AM
To: Igor Kulchytskyy ; devel@edk2.groups.io
Cc: nickle.w...@hpe.com
Subject: [EXTERNAL] RE: [PATCH] RedfishPkg: RedfishDiscoverDxe: USB Redfish 
host interface is not supported


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**

[AMD Official Use Only - General]

Hi Igor, my feedback is inline.

> -Original Message-
> From: Igor Kulchytskyy 
> Sent: Sunday, August 7, 2022 8:26 PM
> To: devel@edk2.groups.io
> Cc: Chang, Abner ; nickle.w...@hpe.com; Igor
> Kulchytskyy 
> Subject: [PATCH] RedfishPkg: RedfishDiscoverDxe: USB Redfish host
> interface is not supported
>
> [CAUTION: External Email]
>
> Host Interface details are discribed by the SMBIOS Type 42 table.
> The table is published by the RedfishHostInterfaceDxe driver.
> That driver supports PCI-E and USB host interface types.
> The table is consumed by the RedfishGetHostInterfaceProtocolData
> function in the RedfishDiscoverDxe driver.
> That function only supports PCI-E interface.
>
>
> Cc: Abner Chang 
> Cc: Nickle Wang 
> Signed-off-by: Igor Kulchytskyy 
> ---
>  RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c | 11
> --
> -
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git
> a/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> b/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> index d79750b..a3b977f 100644
> --- a/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> +++ b/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> @@ -65,10 +65,15 @@ RedfishGetHostInterfaceProtocolData (
>  RecordTmp   = (UINT8 *)Record + Offset;
>
>  //
> -// Check Device Type, only PCI/PCIe Network Interface v2 is supported
> now.
> +// Check Device Type, PCI/PCIe and USB Network Interface v2 is 
> supported.
>  //
> -if (*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_PCI_PCIE_V2) {
> -  ASSERT (SpecificDataLen == sizeof
> (PCI_OR_PCIE_INTERFACE_DEVICE_DESCRIPTOR_V2) + 1);
> +if ((*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_PCI_PCIE_V2) || (*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_USB_V2)) {
> +  if (*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_PCI_PCIE_V2){
> +  ASSERT (SpecificDataLen == sizeof
> (PCI_OR_PCIE_INTERFACE_DEVICE_DESCRIPTOR_V2) + 1);
> +  }
> +  if (*RecordTmp ==
> + REDFISH_HOST_INTERFACE_DEVICE_TYPE_USB_V2){
[Chang, Abner]
We can do if-else here because we only support two types of network device now.
Abner

> +  ASSERT (SpecificDataLen > sizeof
> (REDFISH_HOST_INTERFACE_DEVICE_TYPE_USB_V2) + 1);
> +  }
>*DeviceDescriptor = (REDFISH_INTERFACE_DATA *)RecordTmp;
>Offset= Offset + SpecificDataLen;
>RecordTmp = (UINT8 *)Record + Offset;
> --
> 2.6.1.windows.1
> -The information contained in this message may be confidential and
> proprietary to American Megatrends (AMI). This communication is
> intended to be read only by the individual or entity to whom it is
> addressed or by their designee. If the reader of this message is not
> the intended recipient, you are on notice that any distribution of
> this message, in any form, is strictly prohibited. Please promptly
> notify the sender by reply e-mail or by telephone at 770-246-8600, and then 
> delete or destroy all copies of the transmission.
-The information contained in this message may be confidential and proprietary 
to American Megatrends (AMI). This communication is intended to be read only by 
the individual or entity to whom it is addressed or by their designee. If the 
reader of this message is not the intended recipient, you are on notice that 
any distribution of this message, in any form, is strictly prohibited. Please 
promptly notify the sender by reply e-mail or by telephone at 770-246-8600, and 
then delete or destroy all copies of the transmission.


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Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: USB Redfish host interface is not supported

[Igor Kulchytskyy via groups.io]

Hi Abner,
Thank you for your feedback.
I agree with you.
What should I do to change it?
Should I create a new patch?
Thank you,
Igor

-Original Message-
From: Chang, Abner 
Sent: Tuesday, August 09, 2022 3:35 AM
To: Igor Kulchytskyy ; devel@edk2.groups.io
Cc: nickle.w...@hpe.com
Subject: [EXTERNAL] RE: [PATCH] RedfishPkg: RedfishDiscoverDxe: USB Redfish 
host interface is not supported


**CAUTION: The e-mail below is from an external source. Please exercise caution 
before opening attachments, clicking links, or following guidance.**

[AMD Official Use Only - General]

Hi Igor, my feedback is inline.

> -Original Message-
> From: Igor Kulchytskyy 
> Sent: Sunday, August 7, 2022 8:26 PM
> To: devel@edk2.groups.io
> Cc: Chang, Abner ; nickle.w...@hpe.com; Igor
> Kulchytskyy 
> Subject: [PATCH] RedfishPkg: RedfishDiscoverDxe: USB Redfish host
> interface is not supported
>
> [CAUTION: External Email]
>
> Host Interface details are discribed by the SMBIOS Type 42 table.
> The table is published by the RedfishHostInterfaceDxe driver.
> That driver supports PCI-E and USB host interface types.
> The table is consumed by the RedfishGetHostInterfaceProtocolData
> function in the RedfishDiscoverDxe driver.
> That function only supports PCI-E interface.
>
>
> Cc: Abner Chang 
> Cc: Nickle Wang 
> Signed-off-by: Igor Kulchytskyy 
> ---
>  RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c | 11
> --
> -
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git
> a/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> b/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> index d79750b..a3b977f 100644
> --- a/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> +++ b/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> @@ -65,10 +65,15 @@ RedfishGetHostInterfaceProtocolData (
>  RecordTmp   = (UINT8 *)Record + Offset;
>
>  //
> -// Check Device Type, only PCI/PCIe Network Interface v2 is supported
> now.
> +// Check Device Type, PCI/PCIe and USB Network Interface v2 is 
> supported.
>  //
> -if (*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_PCI_PCIE_V2) {
> -  ASSERT (SpecificDataLen == sizeof
> (PCI_OR_PCIE_INTERFACE_DEVICE_DESCRIPTOR_V2) + 1);
> +if ((*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_PCI_PCIE_V2) || (*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_USB_V2)) {
> +  if (*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_PCI_PCIE_V2){
> +  ASSERT (SpecificDataLen == sizeof
> (PCI_OR_PCIE_INTERFACE_DEVICE_DESCRIPTOR_V2) + 1);
> +  }
> +  if (*RecordTmp ==
> + REDFISH_HOST_INTERFACE_DEVICE_TYPE_USB_V2){
[Chang, Abner]
We can do if-else here because we only support two types of network device now.
Abner

> +  ASSERT (SpecificDataLen > sizeof
> (REDFISH_HOST_INTERFACE_DEVICE_TYPE_USB_V2) + 1);
> +  }
>*DeviceDescriptor = (REDFISH_INTERFACE_DATA *)RecordTmp;
>Offset= Offset + SpecificDataLen;
>RecordTmp = (UINT8 *)Record + Offset;
> --
> 2.6.1.windows.1
> -The information contained in this message may be confidential and
> proprietary to American Megatrends (AMI). This communication is
> intended to be read only by the individual or entity to whom it is
> addressed or by their designee. If the reader of this message is not
> the intended recipient, you are on notice that any distribution of
> this message, in any form, is strictly prohibited. Please promptly
> notify the sender by reply e-mail or by telephone at 770-246-8600, and then 
> delete or destroy all copies of the transmission.
-The information contained in this message may be confidential and proprietary 
to American Megatrends (AMI). This communication is intended to be read only by 
the individual or entity to whom it is addressed or by their designee. If the 
reader of this message is not the intended recipient, you are on notice that 
any distribution of this message, in any form, is strictly prohibited. Please 
promptly notify the sender by reply e-mail or by telephone at 770-246-8600, and 
then delete or destroy all copies of the transmission.


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Re: [edk2-devel] Building C static Library for UEFI

[Andrew Fish via groups.io]

Did you figure this out?

The per compiler flags come from BaseTools/Conf/tools_def.template. When you do 
the edksetup.sh it gets copied to Conf/tools_def.ttxt and that is what the 
build uses. The rules to generate makefiles come from 
BaseTools/Conf/build_rule.template[2] and gets copied to Conf/build_rule.txt

You can override the generic compiler flags via a [BuildOptions] section in an 
INF [3] of DSC [4]. 

[1] 
https://github.com/tianocore/edk2/blob/master/BaseTools/Conf/tools_def.template
[2] 
https://github.com/tianocore/edk2/blob/master/BaseTools/Conf/build_rule.template
[3] 
https://github.com/tianocore/edk2/blob/master/UnitTestFrameworkPkg/Library/CmockaLib/CmockaLib.inf#L28
 
[4] https://github.com/tianocore/edk2/blob/master/OvmfPkg/OvmfPkgX64.dsc#L111


Thanks,

Andrew Fish


> On Jul 30, 2022, at 7:25 AM, Ayush Singh  wrote:
> 
> Hello everyone. There are some tests in Rust std that statically link to a C 
> static library to check ffi. Since if Rust is ever used in edk2, it would 
> probably have to integrate with the existing C code. Thus, I thought rather 
> than ignoring these tests, I wanted to make them work.
> 
> What Rust cargo needs is a static C library (`.lib`) to link against. I was 
> not really able to find much about linking in UEFI applications. However, 
> from what I understand [1], edk2 already does do static link for C modules, 
> so it should technically be the same for Rust as well as long as a static 
> library can be generated from C code. I did look at the `build_rules` [2], 
> but I don't know where the flags are defined. I think following rules: 
> `C-Code-File` -> `Object-File` should technically create a static library, 
> but would it work with projects outside edk2? Also, it would be great if 
> someone can also help me with the flags that need to be supplied if it can.
> 
> 
> 
> Yours Sincerely
> 
> Ayush Singh
> 
> 
> 
> [1]: 
> https://edk2-docs.gitbook.io/edk-ii-build-specification/9_build_or_make_stage/95_dynamic_link
> 
> [2]: 
> https://github.com/tianocore/edk2/blob/e9150618ec91f79e70a1719ac8c198bee34a99be/BaseTools/Conf/build_rule.template
> 
> 



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[edk2-devel] Rust std for UEFI PR created

[Ayush Singh]

Hello everyone. This email is just a quick announcement for everyone 
interested in the GSoC project porting Rust std for UEFI. A Draft PR [1] 
has been created to upstream Rust project to get UEFI std work merged. 
Feel free to check out the PR and provide feedback.



Yours Sincerely,

Ayush Singh


[1]: https://github.com/rust-lang/rust/pull/100316



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Re: [edk2-devel] [PATCH v1 3/3] LogoFeaturePkg,BoardModulePkg: Set existing logo as BGRT

[Oram, Isaac W]

Comments should be wrapped with blank comment lines, so comments like
  // Determine BGRT display offsets
Should be
  //
  // Determine BGRT display offsets
  //
There are at least 4 instances to be corrected in Logo.c
And some in BoardBootManager.c

// MinPlatform has the FSP draw the logo.
Please make the comment more generic as it really could be implemented many 
ways and we wouldn't want to be overly specific here, for example if the 
features is used by a bootloader without FSP support.  There shouldn't be 
anything that ties this to FSP as far as I can see.

Please update the Readme.md removing JPEG comments and updating for new 
behaviors.

Please remove AspireVn7Dash572G use of PcdJpgEnable as this results in a build 
error for that board.

Otherwise, looks good to me.

Regards,
Isaac

-Original Message-
From: Benjamin Doron  
Sent: Monday, July 25, 2022 10:12 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Oram, Isaac W 
; Desimone, Nathaniel L 
; Sinha, Ankit ; Dong, 
Eric ; Bi, Dandan ; Gao, Liming 

Subject: [PATCH v1 3/3] LogoFeaturePkg,BoardModulePkg: Set existing logo as BGRT

In MinPlatform, FSP-S displays the logo to the user early. However, this means 
that no BGRT is written either. To reduce duplication in the flash image, a new 
LogoDxe will set this BMP as the BGRT buffer. The previous LogoDxe drivers 
here, along with a BootLogoEnableLogo() patch to BDS libraries, would begin 
displaying the Intel logo over the board FDF's choice - presently, these are 
the TianoCore logo.

Also begin using BootLogoUpdateProgress().

Tested on KabylakeOpenBoardPkg, the boot logo becomes also a BGRT logo.

A follow-up patch can be considered to set all platforms to use Intel's logo.

Cc: Sai Chaganty 
Cc: Isaac Oram 
Cc: Nate DeSimone 
Cc: Ankit Sinha 
Cc: Eric Dong 
Cc: Dandan Bi 
Cc: Liming Gao 
Signed-off-by: Benjamin Doron 
---
 Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc  
   |   8 -
 Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc
   |   6 +-
 Features/Intel/UserInterface/LogoFeaturePkg/Include/PostMemory.fdf 
   |   6 +-
 Features/Intel/UserInterface/LogoFeaturePkg/LogoDxe/JpegLogo.idf   
   |  10 --
 Features/Intel/UserInterface/LogoFeaturePkg/LogoDxe/JpegLogoDxe.inf
   |  52 --
 Features/Intel/UserInterface/LogoFeaturePkg/LogoDxe/Logo.c 
   | 183 +++-
 Features/Intel/UserInterface/LogoFeaturePkg/LogoDxe/Logo.idf   
   |  10 --
 Features/Intel/UserInterface/LogoFeaturePkg/LogoDxe/Logo.jpg   
   | Bin 9741 -> 0 bytes
 Features/Intel/UserInterface/LogoFeaturePkg/LogoDxe/LogoDxe.inf
   |  24 ++-
 Features/Intel/UserInterface/LogoFeaturePkg/LogoFeaturePkg.dec 
   |   2 +-
 Features/Intel/UserInterface/LogoFeaturePkg/LogoFeaturePkg.dsc 
   |   3 -
 Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c
   |   3 +-
 Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf  
   |   1 +
 Platform/Intel/BoardModulePkg/Library/BoardBootManagerLib/BoardBootManager.c   
   |  31 
 
Platform/Intel/BoardModulePkg/Library/BoardBootManagerLib/BoardBootManagerLib.inf
 |   5 +
 Platform/Intel/MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
   |   1 +
 16 files changed, 120 insertions(+), 225 deletions(-)

diff --git a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc 
b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
index 5365f0a1b844..da663f5c833f 100644
--- a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
+++ b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
@@ -77,11 +77,3 @@
   gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable  
|FALSE   gUserAuthFeaturePkgTokenSpaceGuid.PcdUseVersion1   
   |FALSE   
gVirtualKeyboardFeaturePkgTokenSpaceGuid.PcdVirtualKeyboardFeatureEnable  
|FALSE--#-# There seems to be some build parsing odd behavior that requires 
this PCD to be specified even though-# the *.fdf that consumes it is dependent 
on the feature flag.-# This section is to ensure that boards have these PCD 
instantiated.-#-[PcdsFeatureFlag]-  gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable  
|FALSEdiff --git 
a/Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc 
b/Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc
index 0acce1c7dfaf..3e990a84f8ec 100644
--- a/Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.dsc
+++ b/Features/Intel/UserInterface/LogoFeaturePkg/Include/LogoFeature.ds
+++ c
@@ -47,8 +47,4 @@
 # @todo: Change below line to [Components.$(DXE_ARCH)] after 
https://bugzilla.tianocore.org/show_bug.cgi?id=2308 #is completed. 
[Components.X64]-  !if gLogoFeaturePkgTokenSpaceGuid.PcdJpgEnable == TRUE-

Re: [edk2-devel] [PATCH v1 2/3] UserAuthFeaturePkg: Included DXE versions are mutually exclusive

[Benjamin Doron]

Hi Isaac,

>From memory, the primary difference between the versions of this module is
that v2 uses helper libraries to perform some of the functions in
UserAuthenticationDxePassword.c and the HII helpers in
UserAuthenticationDxe.c. There are other differences, at least including
the handler to challenge for the admin password that should be ported or
implemented for v2, but I think only one DXE module version is necessary to
be in the tree.

We can drop this commit and I can work on improving v2 and deprecating v1 -
as was my plan, because v2 needs to challenge for the password - but not at
the moment. Unless v1's implementation is preferred?

Sorry about the subject prefix. I see that patch 1/3 is in. I think I'll
work on 2/3 later and 3/3 separately.

Best regards,
Benjamin


On Mon, 8 Aug 2022 at 18:51, Oram, Isaac W  wrote:

> Benjamin,
>
> Can you update the readme with descriptions of the modules and their
> functionality?
> Can you comment the PcdUseVersion1 declaration in the DEC file?
> If you can think of a more descriptive name than "version 1", that would
> be better.
>
> Note that convention (maybe requirement) is to preface non-edk2 repo
> changes with the mailing list and repo info [edk2-devel][edk2-platforms] so
> that rules can filter more easily.  And multi-commit reviews should have a
> cover-letter enabled as well so you can provide an overview of the patch
> series.
> Here is the command I use: git format-patch -M --thread origin/master
> --cover-letter --subject-prefix="edk2-devel][edk2-platforms][PATCH V1"
>
> Regards,
> Isaac
>
> -Original Message-
> From: Benjamin Doron 
> Sent: Monday, July 25, 2022 10:12 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Oram, Isaac W <
> isaac.w.o...@intel.com>; Desimone, Nathaniel L <
> nathaniel.l.desim...@intel.com>; Sinha, Ankit ;
> Gao, Liming ; Bi, Dandan 
> Subject: [PATCH v1 2/3] UserAuthFeaturePkg: Included DXE versions are
> mutually exclusive
>
> Versions of the DXE module perform nearly identical functions, and are
> therefore mutually exclusive. Including both modules results in at least a
> duplicate HII package and an "already started" assert.
>
> Therefore, add a new PCD to determine which module will be included.
> However, now a second bug can be seen: version 2 does not challenge for
> the password. An RSC handler to hook UiApp entry is probably needed, as in
> version 1.
>
> Cc: Sai Chaganty 
> Cc: Isaac Oram 
> Cc: Nate DeSimone 
> Cc: Ankit Sinha 
> Cc: Liming Gao 
> Cc: Dandan Bi 
> Signed-off-by: Benjamin Doron 
> ---
>  Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
>   | 1 +
>  Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
>| 1 +
>  Features/Intel/UserInterface/UserAuthFeaturePkg/Include/PostMemory.fdf
>   | 9 ++---
>  Features/Intel/UserInterface/UserAuthFeaturePkg/Include/UserAuthFeature.dsc
> | 3 +++
>  Features/Intel/UserInterface/UserAuthFeaturePkg/UserAuthFeaturePkg.dec
>   | 3 ++-
>  5 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
> b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
> index 908fe4d1f7a9..8924dadcaa18 100644
> --- a/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
> +++ b/Features/Intel/AdvancedFeaturePkg/AdvancedFeaturePkg.dsc
> @@ -79,6 +79,7 @@
>#   gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable
>   |TRUE
>  gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable
> |TRUE+  gUserAuthFeaturePkgTokenSpaceGuid.PcdUseVersion1
>   |FALSE
>  gVirtualKeyboardFeaturePkgTokenSpaceGuid.PcdVirtualKeyboardFeatureEnable
> |TRUE  #diff --git
> a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> index d59e3e61b9b9..5365f0a1b844 100644
> --- a/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> +++ b/Features/Intel/AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
> @@ -75,6 +75,7 @@
> gLogoFeaturePkgTokenSpaceGuid.PcdLogoFeatureEnable
> |FALSE
>  gUserAuthFeaturePkgTokenSpaceGuid.PcdUserAuthenticationFeatureEnable
> |FALSE+  gUserAuthFeaturePkgTokenSpaceGuid.PcdUseVersion1
> |FALSE
>  gVirtualKeyboardFeaturePkgTokenSpaceGuid.PcdVirtualKeyboardFeatureEnable
> |FALSE  #diff --git
> a/Features/Intel/UserInterface/UserAuthFeaturePkg/Include/PostMemory.fdf
> b/Features/Intel/UserInterface/UserAuthFeaturePkg/Include/PostMemory.fdf
> index 030dcbe763d8..827deb08de7e 100644
> ---
> a/Features/Intel/UserInterface/UserAuthFeaturePkg/Include/PostMemory.fdf
> +++ b/Features/Intel/UserInterface/UserAuthFeaturePkg/Include/PostMemory
> +++ .fdf
> @@ -7,6 +7,9 @@
>  # ## -INF
> UserAuthFeaturePkg/UserAuthenticationDxeSmm/UserAuthenticationDxe.inf-INF
> UserAuthFeaturePkg/UserAuthenticationDxeSmm/UserAuthentication2Dxe.inf-INF
> UserAuthFeaturePkg/UserAuthenticationDxeSmm/UserAuthenticationSmm.inf+!if
> 

[edk2-devel] [PATCH v2] MdeModulePkg: Update the SMBIOS version by UPL

[kasimx . liu]

From: KasimX Liu 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4013

For the SMBIOS version can be update by UPL,we create
the gUniversalPayloadSmbios3TableGuid HOB to store
the value then updated version.

Cc: Guo Dong 
Cc: Ray Ni 
Cc: James Lu 
Cc: Gua Guo 
Signed-off-by: KasimX Liu 
---
 MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c | 25 
 MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h | 12 +++---
 2 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c 
b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
index 81df59cd0f..7c1e2adc02 100644
--- a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
+++ b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.c
@@ -1447,7 +1447,9 @@ BOOLEAN
 IsValidSmbios20Table (
   IN  VOID   *TableEntry,
   OUT VOID   **TableAddress,
-  OUT UINTN  *TableMaximumSize
+  OUT UINTN  *TableMaximumSize,
+  OUT UINT8  *MajorVersion,
+  OUT UINT8  *MinorVersion
   )
 {
   UINT8 Checksum;
@@ -1478,6 +1480,8 @@ IsValidSmbios20Table (
   if (SmbiosTable->MajorVersion < 2) {
 return FALSE;
   }
+  *MajorVersion = SmbiosTable->MajorVersion;
+  *MinorVersion = SmbiosTable->MinorVersion;
 
   //
   // The whole struct check sum should be zero
@@ -1522,7 +1526,9 @@ BOOLEAN
 IsValidSmbios30Table (
   IN  VOID   *TableEntry,
   OUT VOID   **TableAddress,
-  OUT UINTN  *TableMaximumSize
+  OUT UINTN  *TableMaximumSize,
+  OUT UINT8  *MajorVersion,
+  OUT UINT8  *MinorVersion
   )
 {
   UINT8 Checksum;
@@ -1541,6 +1547,8 @@ IsValidSmbios30Table (
   if (SmbiosTable->MajorVersion < 3) {
 return FALSE;
   }
+  *MajorVersion = SmbiosTable->MajorVersion;
+  *MinorVersion = SmbiosTable->MinorVersion;
 
   //
   // The whole struct check sum should be zero
@@ -1575,7 +1583,9 @@ EFI_STATUS
 ParseAndAddExistingSmbiosTable (
   IN EFI_HANDLEImageHandle,
   IN SMBIOS_STRUCTURE_POINTER  Smbios,
-  IN UINTN Length
+  IN UINTN Length,
+  IN UINT8 MajorVersion,
+  IN UINT8 MinorVersion
   )
 {
   EFI_STATUSStatus;
@@ -1583,6 +1593,9 @@ ParseAndAddExistingSmbiosTable (
   EFI_SMBIOS_HANDLE SmbiosHandle;
   SMBIOS_STRUCTURE_POINTER  SmbiosEnd;
 
+  mPrivateData.Smbios.MajorVersion = MajorVersion;
+  mPrivateData.Smbios.MinorVersion = MinorVersion;
+
   SmbiosEnd.Raw = Smbios.Raw + Length;
 
   if ((Smbios.Raw >= SmbiosEnd.Raw) || (Smbios.Raw == NULL)) {
@@ -1692,6 +1705,8 @@ RetrieveSmbiosFromHob (
   UNIVERSAL_PAYLOAD_GENERIC_HEADER  *GenericHeader;
   VOID  *TableAddress;
   UINTN TableMaximumSize;
+  UINT8 MajorVersion;
+  UINT8 MinorVersion;
 
   Status = EFI_NOT_FOUND;
 
@@ -1709,9 +1724,9 @@ RetrieveSmbiosFromHob (
 //
 SmBiosTableAdress = (UNIVERSAL_PAYLOAD_SMBIOS_TABLE 
*)GET_GUID_HOB_DATA (GuidHob);
 if (GenericHeader->Length >= UNIVERSAL_PAYLOAD_SIZEOF_THROUGH_FIELD 
(UNIVERSAL_PAYLOAD_SMBIOS_TABLE, SmBiosEntryPoint)) {
-  if (mIsSmbiosTableValid[Index].IsValid ((VOID 
*)(UINTN)SmBiosTableAdress->SmBiosEntryPoint, , 
)) {
+  if (mIsSmbiosTableValid[Index].IsValid ((VOID 
*)(UINTN)SmBiosTableAdress->SmBiosEntryPoint, , 
,,)) {
 Smbios.Raw = TableAddress;
-Status = ParseAndAddExistingSmbiosTable (ImageHandle, Smbios, 
TableMaximumSize);
+Status = ParseAndAddExistingSmbiosTable (ImageHandle, Smbios, 
TableMaximumSize,MajorVersion,MinorVersion);
 if (EFI_ERROR (Status)) {
   DEBUG ((DEBUG_ERROR, "RetrieveSmbiosFromHob: Failed to parse 
preinstalled tables from Guid Hob\n"));
   Status = EFI_UNSUPPORTED;
diff --git a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h 
b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h
index 019798ea77..f1500beabd 100644
--- a/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h
+++ b/MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.h
@@ -136,7 +136,9 @@ BOOLEAN
 IsValidSmbios30Table (
   IN  VOID   *TableEntry,
   OUT VOID   **TableAddress,
-  OUT UINTN  *TableMaximumSize
+  OUT UINTN  *TableMaximumSize,
+  OUT UINT8  *MajorVersion,
+  OUT UINT8  *MinorVersion
   );
 
 /**
@@ -155,7 +157,9 @@ BOOLEAN
 IsValidSmbios20Table (
   IN  VOID   *TableEntry,
   OUT VOID   **TableAddress,
-  OUT UINTN  *TableMaximumSize
+  OUT UINTN  *TableMaximumSize,
+  OUT UINT8  *MajorVersion,
+  OUT UINT8  *MinorVersion
   );
 
 /**
@@ -174,7 +178,9 @@ BOOLEAN
 (*IS_SMBIOS_TABLE_VALID) (
   IN  VOID   *TableEntry,
   OUT VOID   **TableAddress,
-  OUT UINTN  *TableMaximumSize
+  OUT UINTN  *TableMaximumSize,
+  OUT UINT8  *MajorVersion,
+  OUT UINT8  *MinorVersion
   );
 typedef struct {
   EFI_GUID *Guid;
-- 
2.32.0.windows.2



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Re: [edk2-devel] 回复: [edk2-devel] [PATCH] MdePkg:Improved Smbios Type9 table and Smbios 3.5.0 spec changes

[Sainadh Nagolu via groups.io]

Updated PrintInfo.c from ShellPkg, Patch for the same is available in edk2 
maillist.( https://edk2.groups.io/g/devel/message/92250 )

Please help to review.

Thanks,
Sainadh.


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[edk2-devel] [PATCH] ShellPkg:Improved Smbios Type 9 table changes in PrintInfo.c

[Sainadh Nagolu via groups.io]

Since PeerGroups has a variable number of entries, new fields added after 
PeerGroups are defined in a extended structure. Done changes in PrintInfo.c to 
access those fields using SMBIOS_TABLE_TYPE9_EXTENDED structure from SmBios.h.

Signed-off-by: Sainadh Nagolu 

CC: Vasudevan Sambandan 
CC: Sundaresan S 

---
 .../SmbiosView/PrintInfo.c| 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c 
b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
index a0ee286c9a..e1acb1e288 100644
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
@@ -2,6 +2,7 @@
   Module for clarifying the content of the smbios structure element 
information.



   Copyright (c) 2005 - 2018, Intel Corporation. All rights reserved.

+  Copyright (c) 1985 - 2022, American Megatrends International LLC.

   (C) Copyright 2014 Hewlett-Packard Development Company, L.P.

   (C) Copyright 2015-2019 Hewlett Packard Enterprise Development LP

   SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -597,8 +598,9 @@ SmbiosPrintStructure (
 //

 case 9:

 {

-  MISC_SLOT_PEER_GROUP  *PeerGroupPtr;

-  UINT8 PeerGroupCount;

+  MISC_SLOT_PEER_GROUP *PeerGroupPtr;

+ SMBIOS_TABLE_TYPE9_EXTENDED  *Type9ExtendedStruct;

+  UINT8PeerGroupCount;



   PRINT_PENDING_STRING (Struct, Type9, SlotDesignation);

   DisplaySystemSlotType (Struct->Type9->SlotType, Option);

@@ -636,9 +638,12 @@ SmbiosPrintStructure (
 ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN 
(STR_SMBIOSVIEW_PRINTINFO_DATA_BUS_WIDTH), gShellDebug1HiiHandle, 
PeerGroupPtr[Index].DataBusWidth);

   }



-  DisplaySystemSlotHeight (Struct->Type9->SlotHeight, Option);

-  DisplaySystemSlotPhysicalWidth (Struct->Type9->SlotPhysicalWidth, 
Option);

-  DisplaySystemSlotInformation (Struct->Type9->SlotInformation, 
Option);

+  //Since PeerGroups has a variable number of entries, new fields 
added after PeerGroups are defined in

+  //a extended structure. Those fields can be referenced using 
SMBIOS_TABLE_TYPE9_EXTENDED structure.

+ Type9ExtendedStruct = 
(SMBIOS_TABLE_TYPE9_EXTENDED*)((UINT8*)PeerGroupPtr + (PeerGroupCount * 
sizeof(MISC_SLOT_PEER_GROUP)));

+ DisplaySystemSlotHeight (Type9ExtendedStruct->SlotHeight, 
Option);

+  DisplaySystemSlotPhysicalWidth 
(Type9ExtendedStruct->SlotPhysicalWidth, Option);

+  DisplaySystemSlotInformation (Type9ExtendedStruct->SlotInformation, 
Option);

 }

   }



--
2.36.0.windows.1
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[edk2-devel] [PATCH v8 3/4] Silicon/Phytium: Added fvb driver for flash

[Ling Jia]

From: Ling Jia 

The FlashFvbDxe provided the fvb protocol,
which requested by the flash operators.

Signed-off-by: Ling Jia 
---
 Platform/Phytium/DurianPkg/DurianPkg.dsc |1 +
 Platform/Phytium/DurianPkg/DurianPkg.fdf |2 +
 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf |   63 +
 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h   |  105 ++
 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c   | 1329 

 5 files changed, 1500 insertions(+)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc 
b/Platform/Phytium/DurianPkg/DurianPkg.dsc
index cc0d41855584..cedf7480a5d6 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -267,6 +267,7 @@ [Components.common]
   # NOR Flash driver
   #
   Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
+  Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
 
   #
   # Usb Support
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf 
b/Platform/Phytium/DurianPkg/DurianPkg.fdf
index fffbc5b19565..9e97f614ea8a 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -88,6 +88,7 @@ [FV.FvMain]
 INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
 INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
 INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
+INF Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
   }
 
   INF MdeModulePkg/Core/Dxe/DxeMain.inf
@@ -104,6 +105,7 @@ [FV.FvMain]
 
   INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
   INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
+  INF Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
 
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF 
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
diff --git 
a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf 
b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
new file mode 100755
index ..7e947e6e753d
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
@@ -0,0 +1,63 @@
+#/** @file
+#  Phytium NorFlash Fvb Drivers.
+#
+#  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+#  Copyright (C) 2022, Phytium Technology Co, Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION= 0x0001001b
+  BASE_NAME  = FlashFvbDxe
+  FILE_GUID  = b8923820-3e7c-11eb-b12c-17525e90ecc8
+  MODULE_TYPE= DXE_RUNTIME_DRIVER
+  VERSION_STRING = 0.1
+  ENTRY_POINT= FvbEntryPoint
+
+[Sources]
+  FlashFvbDxe.c
+  FlashFvbDxe.h
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  DxeServicesTableLib
+  HobLib
+  MemoryAllocationLib
+  UefiBootServicesTableLib
+  UefiRuntimeLib
+  UefiDriverEntryPoint
+  UefiRuntimeServicesTableLib
+
+[Guids]
+  gEfiAuthenticatedVariableGuid
+  gEfiEventVirtualAddressChangeGuid
+  gEfiSystemNvDataFvGuid
+  gEfiVariableGuid
+
+[Protocols]
+  gEfiDevicePathProtocolGuid
+  gEfiFirmwareVolumeBlockProtocolGuid
+  gSpiNorFlashProtocolGuid
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+
+
+[Depex]
+  TRUE
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h 
b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h
new file mode 100755
index ..19a32fa7ff9b
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h
@@ -0,0 +1,105 @@
+/** @file
+  Phytium NorFlash Fvb Drivers Header.
+
+  Copyright (C) 2022, Phytium Technology Co Ltd. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef FVB_FLASH_DXE_H_
+#define FVB_FLASH_DXE_H_
+
+#include 
+#include 
+#include 
+#include 
+
+#define GET_DATA_OFFSET(BaseAddr, Lba, LbaSize) ((BaseAddr) + (UINTN)((Lba) * 
(LbaSize)))
+#define FVB_FLASH_SIGNATURE   SIGNATURE_32('S', 'N', 'O', 
'R')
+#define INSTANCE_FROM_FVB_THIS(a) CR(a, FT_FVB_DEVICE, 
FvbProtocol, FVB_FLASH_SIGNATURE)
+
+typedef struct _FT_FVB_DEVICEFT_FVB_DEVICE;
+
+#define NOR_FLASH_ERASE_RETRY 10
+
+typedef struct {

[edk2-devel] [PATCH v8 4/4] Silicon/Phytium: Added runtime support to spi master

[Ling Jia]

From: Ling Jia 

Solved the problem of virtual address translation
in runtime access under OS.

Signed-off-by: Ling Jia 
---
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf |  5 ++
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h   |  2 +
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c   | 84 +---
 3 files changed, 80 insertions(+), 11 deletions(-)

diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf 
b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
index 21d75f268da4..0b23821c6523 100644
--- a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
@@ -27,18 +27,23 @@ [Packages]
 [LibraryClasses]
   BaseLib
   DebugLib
+  DxeServicesTableLib
   IoLib
   UefiLib
   UefiBootServicesTableLib
   UefiDriverEntryPoint
+  UefiRuntimeLib
+  UefiRuntimeServicesTableLib
 
 [Guids]
+  gEfiEventVirtualAddressChangeGuid
 
 [Protocols]
   gSpiMasterProtocolGuid
 
 [FixedPcd]
   gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize
 
 [Depex]
   TRUE
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h 
b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h
index 8795ea238d83..842d0c3d1861 100644
--- a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h
@@ -10,6 +10,8 @@
 #ifndef SPI_DXE_H_
 #define SPI_DXE_H_
 
+#include 
+#include 
 #include 
 
 #define SPI_MASTER_SIGNATURE SIGNATURE_32 ('M', 'S', 'P', 'I')
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c 
b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c
index 7602a3e0cd63..5358ff6090dd 100644
--- a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c
@@ -13,8 +13,9 @@
 #include 
 #include "SpiDxe.h"
 
-PHYT_SPI_MASTER *pSpiMasterInstance;
-static UINTN mSpiControlBase;
+STATIC EFI_EVENT  mSpiMasterVirtualAddrChangeEvent;
+STATIC UINTN  mSpiMasterControlBase;
+PHYT_SPI_MASTER   *mSpiMasterInstance;
 
 /**
   This function inited a spi driver.
@@ -66,7 +67,7 @@ SpiMasterSetConfig (
 Value = Config;
   }
 
-  SpiAddr = mSpiControlBase + RegAddr;
+  SpiAddr = mSpiMasterControlBase + RegAddr;
   MmioWrite32 (SpiAddr, Value);
 
   return EFI_SUCCESS;
@@ -99,7 +100,7 @@ SpiMasterGetConfig (
   SpiAddr = 0;
   Value   = 0;
 
-  SpiAddr = mSpiControlBase + RegAddr;
+  SpiAddr = mSpiMasterControlBase + RegAddr;
   Value = MmioRead32 (SpiAddr);
 
   if (CmdId != 0) {
@@ -157,6 +158,34 @@ SpiMasterInitProtocol (
   return EFI_SUCCESS;
 }
 
+/**
+  Fixup internal data so that EFI can be call in virtual mode.
+  Call the passed in Child Notify event and convert any pointers
+  in lib to virtual mode.
+
+  @param[in]Event   The Event that is being processed.
+
+  @param[in]Context Event Context.
+
+  @retval   None.
+
+**/
+STATIC
+VOID
+EFIAPI
+SpiMasterVirtualNotifyEvent (
+  IN EFI_EVENTEvent,
+  IN VOID *Context
+  )
+{
+  EfiConvertPointer (0x0, (VOID **)&(mSpiMasterControlBase));
+  EfiConvertPointer (0x0, (VOID 
**)&(mSpiMasterInstance->SpiMasterProtocol.SpiGetConfig));
+  EfiConvertPointer (0x0, (VOID 
**)&(mSpiMasterInstance->SpiMasterProtocol.SpiSetConfig));
+  EfiConvertPointer (0x0, (VOID **)&(mSpiMasterInstance->SpiMasterProtocol));
+  EfiConvertPointer (0x0, (VOID **)&(mSpiMasterInstance));
+
+  return;
+}
 
 /**
   This function is the entrypoint of the spi driver.
@@ -178,25 +207,58 @@ SpiMasterDrvEntryPoint (
   )
 {
   EFI_STATUS  Status;
+  UINTN   SpiMasterControlSize;
 
-  pSpiMasterInstance = AllocateRuntimeZeroPool (sizeof (PHYT_SPI_MASTER));
-  if (pSpiMasterInstance == NULL) {
+  mSpiMasterControlBase = FixedPcdGet64 (PcdSpiControllerBase);
+  SpiMasterControlSize = FixedPcdGet64 (PcdSpiControllerSize);
+
+  mSpiMasterInstance = AllocateRuntimeZeroPool (sizeof (PHYT_SPI_MASTER));
+  if (mSpiMasterInstance == NULL) {
 return EFI_OUT_OF_RESOURCES;
   }
 
-  mSpiControlBase = FixedPcdGet64 (PcdSpiControllerBase);
+  mSpiMasterControlBase = FixedPcdGet64 (PcdSpiControllerBase);
 
-  SpiMasterInitProtocol (>SpiMasterProtocol);
+  SpiMasterInitProtocol (>SpiMasterProtocol);
 
-  pSpiMasterInstance->Signature = SPI_MASTER_SIGNATURE;
+  mSpiMasterInstance->Signature = SPI_MASTER_SIGNATURE;
 
   Status = gBS->InstallMultipleProtocolInterfaces (
-&(pSpiMasterInstance->Handle),
+&(mSpiMasterInstance->Handle),
 ,
-&(pSpiMasterInstance->SpiMasterProtocol),
+&(mSpiMasterInstance->SpiMasterProtocol),
 NULL
 );
   ASSERT_EFI_ERROR (Status);
 
+  //
+  // Declare the SPI Controller Space as EFI_MEMORY_RUNTIME
+  //
+  Status = gDS->AddMemorySpace (
+  EfiGcdMemoryTypeMemoryMappedIo,
+  (mSpiMasterControlBase >> EFI_PAGE_SHIFT) << EFI_PAGE_SHIFT, 

[edk2-devel] [PATCH v8 2/4] Silicon/Phytium: Added flash driver support for flash operation

[Ling Jia]

From: Ling Jia 

The SpiNorFlashDxe provided norflash initialization,
read-write, erase and other interfaces.

This is a special communication protocol for
FT-2000/4 chip.

Signed-off-by: Ling Jia 
---
 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec   |   1 +
 Platform/Phytium/DurianPkg/DurianPkg.dsc|  13 +
 Platform/Phytium/DurianPkg/DurianPkg.fdf|   6 +
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf   |  49 
+++
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h |  95 
+
 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h |  74 

 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c | 412 

 7 files changed, 650 insertions(+)

diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec 
b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
index 8427f32211f4..4c6c5c5f1118 100644
--- a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
@@ -49,3 +49,4 @@ [PcdsFixedAtBuild.common]
 
 [Protocols]
   gSpiMasterProtocolGuid = { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0x43, 
0x9d, 0x80, 0xdd, 0x0b, 0x7c}}
+  gSpiNorFlashProtocolGuid = { 0x00b4af42, 0xfbd0, 0x11ea, { 0x80, 0x3a, 0x27, 
0xea, 0x5e, 0x65, 0xe3, 0xf6}}
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc 
b/Platform/Phytium/DurianPkg/DurianPkg.dsc
index c1519070d616..cc0d41855584 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -100,6 +100,14 @@ [PcdsFixedAtBuild.common]
   # Stack Size
   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
 
+  #
+  # SPI Flash Control Register Base Address and Size
+  #
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x100
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x28014000
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x1000
+  gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x2800D000
   #
   # Designware PCI Root Complex
   #
@@ -255,6 +263,11 @@ [Components.common]
   #
   Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
 
+  #
+  # NOR Flash driver
+  #
+  Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
+
   #
   # Usb Support
   #
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf 
b/Platform/Phytium/DurianPkg/DurianPkg.fdf
index efb855c5da9e..fffbc5b19565 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -83,6 +83,11 @@ [FV.FvMain]
 
   APRIORI DXE {
 INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
+INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
   }
 
   INF MdeModulePkg/Core/Dxe/DxeMain.inf
@@ -98,6 +103,7 @@ [FV.FvMain]
   INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
 
   INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
+  INF Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
 
   INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
   INF 
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
diff --git 
a/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf 
b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
new file mode 100755
index ..94e7d0633467
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
@@ -0,0 +1,49 @@
+#/** @file
+#  Phytium NorFlash Drivers.
+#
+#  Copyright (C) 2022, Phytium Technology Co, Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION= 0x0001001b
+  BASE_NAME  = SpiNorFlashDxe
+  FILE_GUID  = f37ef706-187c-48fd-9102-ddbf86f551be
+  MODULE_TYPE= DXE_RUNTIME_DRIVER
+  VERSION_STRING = 1.0
+  ENTRY_POINT= NorFlashPlatformEntryPoint
+
+[Sources.common]
+  SpiNorFlashDxe.c
+  SpiNorFlashDxe.h
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  IoLib
+  UefiLib
+  UefiBootServicesTableLib
+  UefiRuntimeLib
+  UefiDriverEntryPoint
+  UefiRuntimeServicesTableLib
+
+[FixedPcd]
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize
+  gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase
+[Guids]
+  gEfiEventVirtualAddressChangeGuid
+
+[Protocols]
+  gSpiMasterProtocolGuid
+  gSpiNorFlashProtocolGuid
+
+ [Depex]
+  TRUE
diff --git 

[edk2-devel] [PATCH v8 1/4] Platform/Phytium: Solved problems during boot

[Ling Jia]

From: Ling Jia 

Solved the problem of lack of dependent Library
in PciHostBridgeDxe.

Solved the problem of missing boot management menu.

Signed-off-by: Ling Jia 
---
 Platform/Phytium/DurianPkg/DurianPkg.fdf | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf 
b/Platform/Phytium/DurianPkg/DurianPkg.fdf
index 2d4427e5eaa7..efb855c5da9e 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -142,6 +142,7 @@ [FV.FvMain]
   #
   # PCI Support
   #
+  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
   INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
   INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
 
@@ -204,6 +205,11 @@ [FV.FvMain]
   INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
   INF MdeModulePkg/Application/UiApp/UiApp.inf
 
+  #
+  #Setup
+  #
+  INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+
 [FV.FVMAIN_COMPACT]
 FvAlignment= 16
 ERASE_POLARITY = 1
-- 
2.25.1



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[edk2-devel] [PATCH v8 0/4] Improved supports for FT-2000/4 chip.

[Ling Jia]

Completed the flash driver and fvb driver,
solved the problems in boot process and
added runtime supports for flash operations
under OS.

The public git repository is :
https://github.com/jialing2020/edk2-platforms/tree/Phytium_Opensource_For_FT-2000/4_v8

Cc: Leif Lindholm 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Yiqi Shu 
Cc: Peng Xie 
Ling Jia (4):
  Platform/Phytium: Solved problems during boot
  Silicon/Phytium: Added flash driver support for flash operation
  Silicon/Phytium: Added fvb driver for flash
  Silicon/Phytium: Added runtime support to spi master

 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec  
  |1 +
 Platform/Phytium/DurianPkg/DurianPkg.dsc   
  |   14 +
 Platform/Phytium/DurianPkg/DurianPkg.fdf   
  |   14 +
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf  
  |5 +
 Silicon/Phytium/FT2000-4Pkg/Drivers/{SpiDxe/SpiDxe.inf => 
SpiNorFlashDxe/SpiNorFlashDxe.inf} |   27 +-
 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf   
  |   63 +
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h
  |2 +
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h
  |   95 ++
 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h 
  |  105 ++
 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h
  |   74 ++
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c
  |   84 +-
 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c
  |  412 ++
 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c 
  | 1329 
 13 files changed, 2203 insertions(+), 22 deletions(-)
 copy Silicon/Phytium/FT2000-4Pkg/Drivers/{SpiDxe/SpiDxe.inf => 
SpiNorFlashDxe/SpiNorFlashDxe.inf} (50%)
 mode change 100644 => 100755
 create mode 100755 
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
 create mode 100755 
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h
 create mode 100755 
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h
 create mode 100755 
Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h
 create mode 100755 
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c
 create mode 100755 
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c

-- 
2.25.1



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Re: [edk2-devel] [PATCH] ShellPkg/SmbiosView: Smbiosview tool is not show Extended Speed and Extended Configured Memory Speed in type 17.

[Gao, Zhichao]

Reviewed-by: Zhichao Gao 

Thanks,
Zhichao

> -Original Message-
> From: xueshengfeng 
> Sent: Saturday, August 6, 2022 10:02 AM
> To: devel@edk2.groups.io; Ni, Ray ; Gao, Zhichao
> 
> Cc: Gao, Liming ; Xue, ShengfengX
> 
> Subject: [PATCH] ShellPkg/SmbiosView: Smbiosview tool is not show
> Extended Speed and Extended Configured Memory Speed in type 17.
> 
> From: Shengfengx Xue 
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4014
> 
> if Configured Memory Speed is 65,535 MT/s or greater, and the actual speed
> is stored in the Extended Configured Memory Speed field. but current
> Smbiosview have no this logic.
> 
> Signed-off-by: Shengfengx Xue 
> ---
>  .../UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c| 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git
> a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
> b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
> index a0ee286c9a..0ab9f5063a 100644
> ---
> a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
> +++
> b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
> @@ -878,6 +878,11 @@ SmbiosPrintStructure (
>  }
>}
> 
> +  if (AE_SMBIOS_VERSION (0x3, 0x3) && (Struct->Hdr->Length > 0x54)) {
> +PRINT_STRUCT_VALUE_H (Struct, Type17, ExtendedSpeed);
> +PRINT_STRUCT_VALUE_H (Struct, Type17,
> ExtendedConfiguredMemorySpeed);
> +  }
> +
>break;
> 
>  //
> --
> 2.26.2.windows.1
> 



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Re: [edk2-devel] [edk2][PATCH V4 1/1] ArmPlatformPkg/PrePeiCore: Invoke constructors for SEC phase

[Rohit Mathew]

Hi,

Could anyone please let me know if there are any more comments on this patch? 
Saw that we have moved into soft freeze for edk2 and wanted to add that we had 
one round of review on the patch.

Regards,
Rohit

> -Original Message-
> From: Sami Mujawar 
> Sent: 25 July 2022 12:12
> To: Rohit Mathew ; devel@edk2.groups.io
> Cc: Ard Biesheuvel ; Rebecca Cran
> ; Pierre Gondois ; Thomas
> Abraham ; nd 
> Subject: Re: [edk2][PATCH V4 1/1] ArmPlatformPkg/PrePeiCore: Invoke
> constructors for SEC phase
> 
> Hi Rohit,
> 
> This patch looks good to me.
> 
> Reviewed-by: Sami Mujawar 
> 
> Regards,
> 
> Sami Mujawar
> 
> On 22/07/2022 06:02 pm, Rohit Mathew wrote:
> > On platforms that do not have the serial console port pre-initialized
> > prior to the SEC phase and due to the absence of a call to
> > "SerialPortInitialize", this results in missing debug logs. So, call
> > the auto-generated "ProcessLibraryConstructorList" function from SEC
> > phase to have all the dependent library constructors called (this
> > includes a call to "SerialPortInitialize").
> >
> > Signed-off-by: Rohit Mathew 
> > ---
> >   ArmPlatformPkg/PrePeiCore/PrePeiCore.h | 12 +++-
> >   ArmPlatformPkg/PrePeiCore/PrePeiCore.c |  6 +-
> >   2 files changed, 16 insertions(+), 2 deletions(-)
> >
> > Changes since V1:
> > - Rebased on top of latest master branch.
> > - Addressed comments from Ard.
> >
> > Changes since V2:
> > - Rebased on top of latest master branch.
> >
> > Changes since V3:
> > - Addressed comments from Sami.
> >
> > Link to github branch for the patch -
> > https://github.com/rohit-arm/edk2/tree/sec_constructor_issue
> >
> > diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
> > b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
> > index 0345dd7bdd2a..c1e13e23e11e 100644
> > --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
> > +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
> > @@ -1,7 +1,7 @@
> >   /** @file
> > Main file supporting the transition to PEI Core in Normal World
> > for Versatile Express
> >
> > -  Copyright (c) 2011, ARM Limited. All rights reserved.
> > +  Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > @@ -73,4 +73,14 @@ PeiCommonExceptionEntry (
> > IN UINTN   LR
> > );
> >
> > +/*
> > + * Autogenerated function that calls the library constructors for all
> > +of the
> > + * module's dependent libraries.
> > + */
> > +VOID
> > +EFIAPI
> > +ProcessLibraryConstructorList (
> > +  VOID
> > +  );
> > +
> >   #endif
> > diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> > b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> > index 6dd9bcdea24f..9c4b25df953d 100644
> > --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> > +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
> > @@ -1,7 +1,7 @@
> >   /** @file
> > Main file supporting the transition to PEI Core in Normal World
> > for Versatile Express
> >
> > -  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> > +  Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
> >
> > SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> > @@ -90,6 +90,10 @@ CEntryPoint (
> >
> > // If not primary Jump to Secondary Main
> > if (ArmPlatformIsPrimaryCore (MpId)) {
> > +// Invoke "ProcessLibraryConstructorList" to have all library 
> > constructors
> > +// called.
> > +ProcessLibraryConstructorList ();
> > +
> >   // Initialize the Debug Agent for Source Level Debugging
> >   InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
> >   SaveAndSetDebugTimerInterrupt (TRUE);


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Re: [edk2-devel] [PATCH v3 4/6] DynamicTablesPkg: DynamicTableManagerDxe: Added check for installed tables

[Sami Mujawar]

Hi Kun,

Please find my response inline marked [SAMI].

Regards,

Sami Mujawar

On 09/08/2022, 00:44, "Kun Qin"  wrote:

Hi Sami,

Thank you for taking time testing this change!

I have a question about one comment you have for this specific patch 
inline (marked with [KQ]).
Could you please provide more details?

I also responded to your other comments, please let me know if the 
proposed change makes
sense to you. Looking forward to your reply.

Thanks,
Kun

On 8/8/2022 8:39 AM, Sami Mujawar wrote:
> Hi Kun,
>
> Please find my response inline marked [SAMI].
>
> Regards,
>
> Sami Mujawar
>
> On 08/08/2022 02:05 pm, Sami Mujawar wrote:
>> Hi Kun,
>>
>> Thank you for this patch.
>>
>> Please find my response inline marked [SAMI].
>>
>> Regards,
>>
>> Sami Mujawar
>>
>> On 31/07/2022 06:37 am, Kun Qin wrote:
>>> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3997
>>>
>>> This change added an extra step to allow check for installed ACPI 
>>> tables.
>>>
>>> For FADT, MADT, GTDT, DSDT, DBG2 and SPCR tables, either 
>>> pre-installed or
>>> supplied through AcpiTableInfo can be accepted.
>>>
>>> An extra check for FADT ACPI table existence during installation 
>>> step is
>>> also added.
>>>
>>> Cc: Sami Mujawar 
>>> Cc: Alexei Fedorov 
>>>
>>> Co-authored-by: Joe Lopez 
>>> Signed-off-by: Kun Qin 
>>> Reviewed-by: Pierre Gondois 
>>> ---
>>>
>>> Notes:
>>>  v2:
>>>  - Function description updates [Sami]
>>>  - Refactorized the table verification [Pierre]
>>>   v3:
>>>  - Added descriptions for new structures [Pierre]
>>>  - Added check for SDT protocol PCD before using it [Pierre]
>>>
>>> 
DynamicTablesPkg/Drivers/DynamicTableManagerDxe/DynamicTableManagerDxe.c 
>>> | 214 
>>> 
DynamicTablesPkg/Drivers/DynamicTableManagerDxe/DynamicTableManagerDxe.inf 
>>> |   4 +
>>>   2 files changed, 138 insertions(+), 80 deletions(-)
>>>
>>> diff --git 
>>> 
a/DynamicTablesPkg/Drivers/DynamicTableManagerDxe/DynamicTableManagerDxe.c 
>>> 
b/DynamicTablesPkg/Drivers/DynamicTableManagerDxe/DynamicTableManagerDxe.c 
>>>
>>> index ed62299f9bbd..7f3deef08a66 100644
>>> --- 
>>> 
a/DynamicTablesPkg/Drivers/DynamicTableManagerDxe/DynamicTableManagerDxe.c
>>> +++ 
>>> 
b/DynamicTablesPkg/Drivers/DynamicTableManagerDxe/DynamicTableManagerDxe.c
>>> @@ -10,6 +10,7 @@
>>>   #include 
>>>
>>>   #include 
>>>
>>>   #include 
>>>
>>> +#include 
>>>
>>>   #include 
>>>
>>>
>>>   // Module specific include files.
>>>
>>> @@ -22,6 +23,58 @@
>>>   #include 
>>>
>>>   #include 
>>>
>>>
>>> +///
>>>
>>> +/// Bit definitions for acceptable ACPI table presence formats.
>>>
>>> +/// Currently only ACPI tables present in the ACPI info list and
>>>
>>> +/// already installed will count towards "Table Present" during
>>>
>>> +/// verification routine.
>>>
>>> +///
>>>
>>> +#define ACPI_TABLE_PRESENT_INFO_LIST  BIT0
>>>
>>> +#define ACPI_TABLE_PRESENT_INSTALLED  BIT1
>>>
>>> +
>>>
>>> +///
>>>
>>> +/// Order of ACPI table being verified during presence inspection.
>>>
>>> +///
>>>
>>> +#define ACPI_TABLE_VERIFY_FADT   0
>>>
>>> +#define ACPI_TABLE_VERIFY_MADT   1
>>>
>>> +#define ACPI_TABLE_VERIFY_GTDT   2
>>>
>>> +#define ACPI_TABLE_VERIFY_DSDT   3
>>>
>>> +#define ACPI_TABLE_VERIFY_DBG2   4
>>>
>>> +#define ACPI_TABLE_VERIFY_SPCR   5
>>>
>>> +#define ACPI_TABLE_VERIFY_COUNT  6
>>>
>>> +
>>>
>>> +///
>>>
>>> +/// Private data structure to verify the presence of mandatory
>>>
>>> +/// or optional ACPI tables.
>>>
>>> +///
>>>
>>> +typedef struct {
>>>
>>> +  /// ESTD ID for the ACPI table of interest.
>>>
>>> +  ESTD_ACPI_TABLE_IDEstdTableId;
>>>
>>> +  /// Standard UINT32 ACPI signature.
>>>
>>> +  UINT32AcpiTableSignature;
>>>
>>> +  /// 4 character ACPI table name (the 5th char8 is for null 
>>> terminator).
>>>
>>> +  CHAR8 AcpiTableName[sizeof (UINT32) + 1];
>>>
>>> +  /// Indicator on whether the ACPI table is required.
>>>
>>> +  BOOLEAN   IsMandatory;
>>>
>>> +  /// Formats of verified presences, as defined by 
>>> ACPI_TABLE_PRESENT_*
>>>
>>> +  /// This field should be initialized to 0 and will be populated 
>>> during
>>>
>>> +  /// verification routine.
>>>
>>> +  UINT16Presence;
>>>
>>> +} ACPI_TABLE_PRESENCE_INFO;
>>>
>>> +
>>>
   

Re: [edk2-devel] [PATCH 1/2] CloudHv/arm: add PeiMemInfoLib

[Jianyong Wu]

Hi Sami,

Thanks for review. All the comments are Ok for me. Just one inline reply:

+

+struct CloudHvMemNodeInfo CloudHvMemNode[CLOUDHV_MAX_MEM_NODE_NUM];

+

+RETURN_STATUS

+EFIAPI

+CloudHvVirtMemInfoPeiLibConstructor (

+  VOID

+  )

+{

+  VOID   *DeviceTreeBase;

+  EFI_RESOURCE_ATTRIBUTE_TYPE  ResourceAttributes;

+  INT32  Node, Prev;

+  UINT64 CurBase, MemBase;

+  UINT64 CurSize;

+  CONST CHAR8*Type;

+  INT32  Len;

+  CONST UINT64   *RegProp;

+  RETURN_STATUS  PcdStatus;

+  UINT8  Index;

+

+  ZeroMem (CloudHvMemNode, sizeof(CloudHvMemNode[0]) * 
CLOUDHV_MAX_MEM_NODE_NUM);
[SAMI] Will sizeof (CloudHvMemNode) should be sufficient above? Also, can you 
run uncrustify on your patches, please?

[Jong] The local uncrustify test environment is not ready. But I think “sizeof” 
here is OK, as this struct contains only two u64 variables, thus no padding 
here.

Thanks
Jianyong



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Re: [edk2-devel] [PATCH 3/3] UefiPayloadPkg: Hook up MICROSOFT_RECOMMENDED macro

[Sean Rhodes]

Hi Guo

Yes, that's fine with me.

This single patch can be disregarded then.

Thank you

Sean

On Tue, 9 Aug 2022, 06:29 Dong, Guo,  wrote:

>
> Hi Sean,
> How about directly setting the PCD in the build command line instead of
> adding a MACRO?
> Prefer not adding new MACRO if we could avoid it.
>
> Thanks,
> Guo
> -Original Message-
> From: Sean Rhodes 
> Sent: Friday, August 5, 2022 12:53 AM
> To: devel@edk2.groups.io
> Cc: Rhodes, Sean ; Dong, Guo ;
> Ni, Ray 
> Subject: [PATCH 3/3] UefiPayloadPkg: Hook up MICROSOFT_RECOMMENDED macro
>
> Hook up MICROSOFT_RECOMMENDED macro to PcdFollowMicrosoftRecommended.
>
> Cc: Guo Dong 
> Cc: Ray Ni 
> Signed-off-by: Sean Rhodes 
> ---
>  UefiPayloadPkg/UefiPayloadPkg.dsc | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc
> b/UefiPayloadPkg/UefiPayloadPkg.dsc
> index 91cd78dbf1..b3ed0f6a2e 100644
> --- a/UefiPayloadPkg/UefiPayloadPkg.dsc
> +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
> @@ -43,6 +43,7 @@
>DEFINE SD_MMC_TIMEOUT   = 100
>
>DEFINE USE_CBMEM_FOR_CONSOLE= FALSE
>
>DEFINE BOOTSPLASH_IMAGE = FALSE
>
> +  DEFINE MICROSOFT_RECOMMENDED= FALSE
>
>
>
>#
>
># NULL:NullMemoryTestDxe
>
> @@ -440,6 +441,7 @@
>
>
>
>  
> gUefiPayloadPkgTokenSpaceGuid.PcdDispatchModuleAbove4GMemory|$(ABOVE_4G_MEMORY)
>
>
>  gUefiPayloadPkgTokenSpaceGuid.PcdBootManagerEscape|$(BOOT_MANAGER_ESCAPE)
>
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdFollowMicrosoftRecommended|$(MICROSOFT_RECOMMENDED)
>
>
>
>gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|180
>
>
>
> --
> 2.34.1
>
>


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Re: [edk2-devel] [edk2-platforms: PATCH] Modify processor _UID ordering by CPU default fused in MADT

[Donald Kuo]

Thanks Jack

Looks good. Reviewed.

-Original Message-
From: Ni, Ray  
Sent: Tuesday, August 9, 2022 3:13 PM
To: Lin, JackX ; devel@edk2.groups.io
Cc: Chiu, Chasel ; Dong, Eric ; 
Yao, Jiewen ; Chaganty, Rangasai V 
; Kuo, Donald ; Kumar, 
Chandana C ; Palakshareddy, Lavanya C 
; Palakshareddy, Lavanya C 

Subject: RE: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU 
default fused in MADT

Reviewed-by: Ray Ni 

> -Original Message-
> From: Lin, JackX 
> Sent: Monday, August 8, 2022 4:21 PM
> To: devel@edk2.groups.io
> Cc: Lin, JackX ; Lin, JackX 
> ; Chiu, Chasel ; Dong, 
> Eric ; Yao, Jiewen ; Ni, 
> Ray ; Chaganty, Rangasai V 
> ; Kuo, Donald ; 
> Kumar, Chandana C ; Palakshareddy; 
> Palakshareddy, Lavanya C 
> Subject: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU 
> default fused in MADT
> 
> BIOS should not reordering cpu processor_uid
> 
> Signed-off-by: JackX Lin 
> Cc: Chasel Chiu 
> Cc: Dong Eric 
> Cc: Jiewen Yao 
> Cc: Ray Ni 
> Cc: Rangasai V Chaganty 
> Cc: Donald Kuo 
> Cc: Chandana C Kumar 
> Cc: Palakshareddy, Lavanya C 
> Cc: JackX Lin 
> ---
>  Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 174
> +++---
> --
> 
> --
>  1 file changed, 39 insertions(+), 135 deletions(-)
> 
> diff --git 
> a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> index c7e87cbd7d..176e422e81 100644
> --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> @@ -57,38 +57,9 @@ BOOLEAN mForceX2ApicId;
>  BOOLEAN mX2ApicEnabled;
> 
>  EFI_MP_SERVICES_PROTOCOL*mMpService;
> -BOOLEAN mCpuOrderSorted;
> -EFI_CPU_ID_ORDER_MAP*mCpuApicIdOrderTable = NULL;
>  UINTN   mNumberOfCpus = 0;
>  UINTN   mNumberOfEnabledCPUs = 0;
> 
> -
> -/**
> -  The function is called by PerformQuickSort to compare int values.
> -
> -  @param[in] LeftThe pointer to first buffer.
> -  @param[in] Right   The pointer to second buffer.
> -
> -  @return -1 Buffer1 is less than Buffer2.
> -  @return  1 Buffer1 is greater than Buffer2.
> -
> -**/
> -INTN
> -EFIAPI
> -ApicIdCompareFunction (
> -  IN CONST VOID *Left,
> -  IN CONST VOID *Right
> -  )
> -{
> -  UINT32  LeftApicId;
> -  UINT32  RightApicId;
> -
> -  LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
> -  RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;
> -
> -  return (LeftApicId > RightApicId)? 1 : (-1); -}
> -
>  /**
>Print Cpu Apic ID Table
> 
> @@ -116,7 +87,8 @@ DebugDisplayReOrderTable (  EFI_STATUS  
> AppendCpuMapTableEntry (
>  IN VOID   *ApicPtr,
> -IN UINT32 LocalApicCounter
> +IN UINT32 LocalApicCounter,
> +IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
>)
>  {
>EFI_STATUSStatus;
> @@ -131,9 +103,9 @@ AppendCpuMapTableEntry (
> 
>if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
>  if(!mX2ApicEnabled) {
> -  LocalApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalApicPtr->ApicId   =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalApicPtr->AcpiProcessorUid =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalApicPtr->ApicId   =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalApicPtr->AcpiProcessorUid =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>LocalApicPtr->Flags= 0;
>LocalApicPtr->ApicId   = 0xFF;
> @@ -142,9 +114,9 @@ AppendCpuMapTableEntry (
>  }
>} else if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
>  if(mX2ApicEnabled) {
> -  LocalX2ApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalX2ApicPtr->X2ApicId =
> mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalX2ApicPtr->AcpiProcessorUid =
> mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalX2ApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalX2ApicPtr->X2ApicId =
> CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalX2ApicPtr->AcpiProcessorUid =
> CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>LocalX2ApicPtr->Flags= 0;
>LocalX2ApicPtr->X2ApicId = (UINT32)-1;
> @@ -159,32 +131,25 @@ AppendCpuMapTableEntry (
> 
>  }
> 
> +/**
> +  Collect all processors information 

Re: [edk2-devel] [PATCH] RedfishPkg: RedfishDiscoverDxe: USB Redfish host interface is not supported

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Hi Igor, my feedback is inline.

> -Original Message-
> From: Igor Kulchytskyy 
> Sent: Sunday, August 7, 2022 8:26 PM
> To: devel@edk2.groups.io
> Cc: Chang, Abner ; nickle.w...@hpe.com; Igor
> Kulchytskyy 
> Subject: [PATCH] RedfishPkg: RedfishDiscoverDxe: USB Redfish host interface is
> not supported
> 
> [CAUTION: External Email]
> 
> Host Interface details are discribed by the SMBIOS Type 42 table.
> The table is published by the RedfishHostInterfaceDxe driver.
> That driver supports PCI-E and USB host interface types.
> The table is consumed by the RedfishGetHostInterfaceProtocolData function in
> the RedfishDiscoverDxe driver.
> That function only supports PCI-E interface.
> 
> 
> Cc: Abner Chang 
> Cc: Nickle Wang 
> Signed-off-by: Igor Kulchytskyy 
> ---
>  RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c | 11 --
> -
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> b/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> index d79750b..a3b977f 100644
> --- a/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> +++ b/RedfishPkg/RedfishDiscoverDxe/RedfishSmbiosHostInterface.c
> @@ -65,10 +65,15 @@ RedfishGetHostInterfaceProtocolData (
>  RecordTmp   = (UINT8 *)Record + Offset;
> 
>  //
> -// Check Device Type, only PCI/PCIe Network Interface v2 is supported
> now.
> +// Check Device Type, PCI/PCIe and USB Network Interface v2 is 
> supported.
>  //
> -if (*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_PCI_PCIE_V2) {
> -  ASSERT (SpecificDataLen == sizeof
> (PCI_OR_PCIE_INTERFACE_DEVICE_DESCRIPTOR_V2) + 1);
> +if ((*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_PCI_PCIE_V2) || (*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_USB_V2)) {
> +  if (*RecordTmp ==
> REDFISH_HOST_INTERFACE_DEVICE_TYPE_PCI_PCIE_V2){
> +  ASSERT (SpecificDataLen == sizeof
> (PCI_OR_PCIE_INTERFACE_DEVICE_DESCRIPTOR_V2) + 1);
> +  }
> +  if (*RecordTmp == REDFISH_HOST_INTERFACE_DEVICE_TYPE_USB_V2){
[Chang, Abner] 
We can do if-else here because we only support two types of network device now.
Abner

> +  ASSERT (SpecificDataLen > sizeof
> (REDFISH_HOST_INTERFACE_DEVICE_TYPE_USB_V2) + 1);
> +  }
>*DeviceDescriptor = (REDFISH_INTERFACE_DATA *)RecordTmp;
>Offset= Offset + SpecificDataLen;
>RecordTmp = (UINT8 *)Record + Offset;
> --
> 2.6.1.windows.1
> -The information contained in this message may be confidential and proprietary
> to American Megatrends (AMI). This communication is intended to be read only
> by the individual or entity to whom it is addressed or by their designee. If 
> the
> reader of this message is not the intended recipient, you are on notice that 
> any
> distribution of this message, in any form, is strictly prohibited. Please 
> promptly
> notify the sender by reply e-mail or by telephone at 770-246-8600, and then
> delete or destroy all copies of the transmission.


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Re: [edk2-devel] [edk2-platforms: PATCH] Modify processor _UID ordering by CPU default fused in MADT

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: Lin, JackX 
> Sent: Monday, August 8, 2022 4:21 PM
> To: devel@edk2.groups.io
> Cc: Lin, JackX ; Lin, JackX ; Chiu,
> Chasel ; Dong, Eric ; Yao,
> Jiewen ; Ni, Ray ; Chaganty,
> Rangasai V ; Kuo, Donald
> ; Kumar, Chandana C
> ; Palakshareddy; Palakshareddy, Lavanya C
> 
> Subject: [edk2-platforms: PATCH] Modify processor _UID ordering by CPU
> default fused in MADT
> 
> BIOS should not reordering cpu processor_uid
> 
> Signed-off-by: JackX Lin 
> Cc: Chasel Chiu 
> Cc: Dong Eric 
> Cc: Jiewen Yao 
> Cc: Ray Ni 
> Cc: Rangasai V Chaganty 
> Cc: Donald Kuo 
> Cc: Chandana C Kumar 
> Cc: Palakshareddy, Lavanya C 
> Cc: JackX Lin 
> ---
>  Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 174
> +++---
> --
> --
>  1 file changed, 39 insertions(+), 135 deletions(-)
> 
> diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> index c7e87cbd7d..176e422e81 100644
> --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> @@ -57,38 +57,9 @@ BOOLEAN mForceX2ApicId;
>  BOOLEAN mX2ApicEnabled;
> 
>  EFI_MP_SERVICES_PROTOCOL*mMpService;
> -BOOLEAN mCpuOrderSorted;
> -EFI_CPU_ID_ORDER_MAP*mCpuApicIdOrderTable = NULL;
>  UINTN   mNumberOfCpus = 0;
>  UINTN   mNumberOfEnabledCPUs = 0;
> 
> -
> -/**
> -  The function is called by PerformQuickSort to compare int values.
> -
> -  @param[in] LeftThe pointer to first buffer.
> -  @param[in] Right   The pointer to second buffer.
> -
> -  @return -1 Buffer1 is less than Buffer2.
> -  @return  1 Buffer1 is greater than Buffer2.
> -
> -**/
> -INTN
> -EFIAPI
> -ApicIdCompareFunction (
> -  IN CONST VOID *Left,
> -  IN CONST VOID *Right
> -  )
> -{
> -  UINT32  LeftApicId;
> -  UINT32  RightApicId;
> -
> -  LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
> -  RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;
> -
> -  return (LeftApicId > RightApicId)? 1 : (-1);
> -}
> -
>  /**
>Print Cpu Apic ID Table
> 
> @@ -116,7 +87,8 @@ DebugDisplayReOrderTable (
>  EFI_STATUS
>  AppendCpuMapTableEntry (
>  IN VOID   *ApicPtr,
> -IN UINT32 LocalApicCounter
> +IN UINT32 LocalApicCounter,
> +IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
>)
>  {
>EFI_STATUSStatus;
> @@ -131,9 +103,9 @@ AppendCpuMapTableEntry (
> 
>if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
>  if(!mX2ApicEnabled) {
> -  LocalApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalApicPtr->ApicId   =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalApicPtr->AcpiProcessorUid =
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalApicPtr->ApicId   =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalApicPtr->AcpiProcessorUid =
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>LocalApicPtr->Flags= 0;
>LocalApicPtr->ApicId   = 0xFF;
> @@ -142,9 +114,9 @@ AppendCpuMapTableEntry (
>  }
>} else if(Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
>  if(mX2ApicEnabled) {
> -  LocalX2ApicPtr->Flags=
> (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
> -  LocalX2ApicPtr->X2ApicId =
> mCpuApicIdOrderTable[LocalApicCounter].ApicId;
> -  LocalX2ApicPtr->AcpiProcessorUid =
> mCpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
> +  LocalX2ApicPtr->Flags=
> (UINT8)CpuApicIdOrderTable[LocalApicCounter].Flags;
> +  LocalX2ApicPtr->X2ApicId =
> CpuApicIdOrderTable[LocalApicCounter].ApicId;
> +  LocalX2ApicPtr->AcpiProcessorUid =
> CpuApicIdOrderTable[LocalApicCounter].AcpiProcessorUid;
>  } else {
>LocalX2ApicPtr->Flags= 0;
>LocalX2ApicPtr->X2ApicId = (UINT32)-1;
> @@ -159,32 +131,25 @@ AppendCpuMapTableEntry (
> 
>  }
> 
> +/**
> +  Collect all processors information and create a Cpu Apic Id table.
> +
> +  @param[in]  CpuApicIdOrderTable   Buffer to store information of Cpu.
> +**/
>  EFI_STATUS
> -SortCpuLocalApicInTable (
> -  VOID
> +CreateCpuLocalApicInTable (
> +  IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
>)
>  {
>EFI_STATUSStatus;
>EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;
>UINT32  

[edk2-devel] [PATCH v1 1/1] ShellPkg: Adds Local APIC parser to AcpiView

[Abdul Lateef Attar via groups.io]

Parse Type 0 or Local APIC structure.
Also parse the Local APIC Flags as bitfields.

Cc: Ray Ni 
Cc: Zhichao Gao 
Signed-off-by: Abdul Lateef Attar 
---
 ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c | 74 
++--
 1 file changed, 67 insertions(+), 7 deletions(-)

diff --git 
a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c 
b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c
index aaa68c99f514..41edcb9ffd1d 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c
@@ -2,6 +2,7 @@
   MADT table parser

 

   Copyright (c) 2016 - 2020, ARM Limited. All rights reserved.

+  Copyright (c) 2022, AMD Incorporated. All rights reserved.

   SPDX-License-Identifier: BSD-2-Clause-Patent

 

   @par Reference(s):

@@ -206,17 +207,65 @@ STATIC CONST ACPI_PARSER  InterruptSourceOverride[] = {
   { L"Flags",   2, 8, L"0x%x", NULL, NULL, NULL, NULL }

 };

 

+STATIC CONST ACPI_PARSER  LocalApicFlags[] = {

+  { L"Enabled",1,  0, L"%d", NULL, NULL, NULL, NULL },

+  { L"Online Capable", 1,  1, L"%d", NULL, NULL, NULL, NULL },

+  { L"Reserved",   30, 2, L"%d", NULL, NULL, NULL, NULL }

+};

+

+/**

+  This function traces Bit Flags fields.

+  If no format string is specified the Format must be NULL.

+

+  @param [in] Format  Optional format string for tracing the data.

+  @param [in] Ptr Pointer to the start of the buffer.

+**/

+VOID

+EFIAPI

+DumpLocalApicBitFlags (

+  IN CONST CHAR16  *Format OPTIONAL,

+  IN UINT8 *Ptr

+  )

+{

+  if (Format != NULL) {

+Print (Format, *(UINT32 *)Ptr);

+return;

+  }

+

+  Print (L"0x%X\n", *(UINT32 *)Ptr);

+  ParseAcpiBitFields (

+TRUE,

+2,

+NULL,

+Ptr,

+4,

+PARSER_PARAMS (LocalApicFlags)

+);

+}

+

+/**

+   An ACPI_PARSER array describing the Processor Local APIC Structure.

+ **/

+STATIC CONST ACPI_PARSER  ProcessorLocalApic[] = {

+  { L"Type",   1, 0, L"0x%x", NULL,  NULL, NULL, 
NULL },

+  { L"Length", 1, 1, L"%d",   NULL,  NULL, NULL, 
NULL },

+

+  { L"ACPI Processor UID", 1, 2, L"0x%x", NULL,  NULL, NULL, 
NULL },

+  { L"APIC ID",1, 3, L"0x%x", NULL,  NULL, NULL, 
NULL },

+  { L"Flags",  4, 4, NULL,DumpLocalApicBitFlags, NULL, NULL, 
NULL }

+};

+

 /**

   An ACPI_PARSER array describing the Processor Local x2APIC Structure.

 **/

 STATIC CONST ACPI_PARSER  ProcessorLocalX2Apic[] = {

-  { L"Type",   1, 0,  L"0x%x", NULL, NULL, NULL, NULL },

-  { L"Length", 1, 1,  L"%d",   NULL, NULL, NULL, NULL },

-  { L"Reserved",   2, 2,  L"0x%x", NULL, NULL, NULL, NULL },

+  { L"Type",   1, 0,  L"0x%x", NULL,  NULL, NULL, 
NULL },

+  { L"Length", 1, 1,  L"%d",   NULL,  NULL, NULL, 
NULL },

+  { L"Reserved",   2, 2,  L"0x%x", NULL,  NULL, NULL, 
NULL },

 

-  { L"X2APIC ID",  4, 4,  L"0x%x", NULL, NULL, NULL, NULL },

-  { L"Flags",  4, 8,  L"0x%x", NULL, NULL, NULL, NULL },

-  { L"ACPI Processor UID", 4, 12, L"0x%x", NULL, NULL, NULL, NULL }

+  { L"X2APIC ID",  4, 4,  L"0x%x", NULL,  NULL, NULL, 
NULL },

+  { L"Flags",  4, 8,  NULL,DumpLocalApicBitFlags, NULL, NULL, 
NULL },

+  { L"ACPI Processor UID", 4, 12, L"0x%x", NULL,  NULL, NULL, 
NULL }

 };

 

 /**

@@ -441,7 +490,18 @@ ParseAcpiMadt (
   );

 break;

   }

-

+  case EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC:

+  {

+ParseAcpi (

+  TRUE,

+  2,

+  "PROCESSOR LOCAL APIC",

+  InterruptContollerPtr,

+  *MadtInterruptControllerLength,

+  PARSER_PARAMS (ProcessorLocalApic)

+  );

+break;

+  }

   case EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC:

   {

 ParseAcpi (

-- 
2.25.1



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[edk2-devel] [PATCH v1 0/1] ShellPkg: Adds Local APIC parser to AcpiView

[Abdul Lateef Attar via groups.io]

Parse Type 0 or Local APIC structure.
Also parse the Local APIC Flags as bitfields.

Cc: Ray Ni 
Cc: Zhichao Gao 

Abdul Lateef Attar (1):
  ShellPkg: Adds Local APIC parser to AcpiView

 ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Madt/MadtParser.c | 74 
++--
 1 file changed, 67 insertions(+), 7 deletions(-)

-- 
2.25.1



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