Re: [edk2-devel] [PATCH 3/3] CryptoPkg: Add new Tls APIs to DXE and protocol

[Li, Yi]

Thanks, next patch set will fix it.

-Original Message-
From: Kinney, Michael D  
Sent: Friday, September 30, 2022 1:09 PM
To: devel@edk2.groups.io; Li, Yi1 ; Kinney, Michael D 

Cc: Yao, Jiewen ; Wang, Jian J ; 
Lu, Xiaoyu1 ; Jiang, Guomin 
Subject: RE: [edk2-devel] [PATCH 3/3] CryptoPkg: Add new Tls APIs to DXE and 
protocol

I see one issue with adding new bits to the crypto services structured PCD.

Comment below.

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Li, Yi
> Sent: Sunday, September 25, 2022 11:27 PM
> To: devel@edk2.groups.io
> Cc: Li, Yi1 ; Yao, Jiewen ; 
> Wang, Jian J ; Lu, Xiaoyu1 
> ; Jiang, Guomin 
> Subject: [edk2-devel] [PATCH 3/3] CryptoPkg: Add new Tls APIs to DXE 
> and protocol
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3892
> 
> The implementation provides new Tls library functions for Crypto EFI 
> Driver and Protocol.
> 
> Cc: Jiewen Yao 
> Cc: Jian J Wang 
> Cc: Xiaoyu Lu 
> Cc: Guomin Jiang 
> Signed-off-by: Yi Li 
> ---
>  CryptoPkg/Driver/Crypto.c | 155 +-
>  .../Pcd/PcdCryptoServiceFamilyEnable.h|   5 +
>  .../BaseCryptLibOnProtocolPpi/CryptLib.c  | 146 -
>  CryptoPkg/Private/Protocol/Crypto.h   | 136 ++-
>  4 files changed, 435 insertions(+), 7 deletions(-)
> 
> diff --git a/CryptoPkg/Driver/Crypto.c b/CryptoPkg/Driver/Crypto.c 
> index 7a8266aaba..f1ff77855c 100644
> --- a/CryptoPkg/Driver/Crypto.c
> +++ b/CryptoPkg/Driver/Crypto.c
> @@ -4238,6 +4238,28 @@ CryptoServiceTlsWrite (
>return CALL_BASECRYPTLIB (Tls.Services.Write, TlsWrite, (Tls, 
> Buffer, BufferSize), 0);  }
> 
> +/**
> +  Shutdown a TLS connection.
> +
> +  Shutdown the TLS connection without releasing the resources, 
> + meaning a new  connection can be started without calling TlsNew() 
> + and without setting  certificates etc.
> +
> +  @param[in]   TlsPointer to the TLS object to shutdown.
> +
> +  @retval EFI_SUCCESS The TLS is shutdown successfully.
> +  @retval EFI_INVALID_PARAMETER   Tls is NULL.
> +  @retval EFI_PROTOCOL_ERROR  Some other error occurred.
> +**/
> +EFI_STATUS
> +EFIAPI
> +CryptoServiceTlsShutdown (
> +  IN VOID  *Tls
> +  )
> +{
> +  return CALL_BASECRYPTLIB (Tls.Services.Shutdown, TlsShutdown, 
> +(Tls), EFI_UNSUPPORTED); }
> +
>  /**
>Set a new TLS/SSL method for a particular TLS object.
> 
> @@ -4463,11 +4485,41 @@ CryptoServiceTlsSetHostPublicCert (
>  /**
>Adds the local private key to the specified TLS object.
> 
> -  This function adds the local private key (PEM-encoded RSA or PKCS#8 
> private
> +  This function adds the local private key (DER-encoded or 
> + PEM-encoded or PKCS#8 private
> +  key) into the specified TLS object for TLS negotiation.
> +
> +  @param[in]  Tls Pointer to the TLS object.
> +  @param[in]  DataPointer to the data buffer of a DER-encoded or 
> PEM-encoded
> +  or PKCS#8 private key.
> +  @param[in]  DataSizeThe size of data buffer in bytes.
> +  @param[in]  PasswordPointer to NULL-terminated private key password, 
> set it to NULL
> +  if private key not encrypted.
> +
> +  @retval  EFI_SUCCESS The operation succeeded.
> +  @retval  EFI_UNSUPPORTED This function is not supported.
> +  @retval  EFI_ABORTED Invalid private key data.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CryptoServiceTlsSetHostPrivateKeyEx (
> +  IN VOID   *Tls,
> +  IN VOID   *Data,
> +  IN UINTN  DataSize,
> +  IN VOID   *Password  OPTIONAL
> +  )
> +{
> +  return CALL_BASECRYPTLIB (TlsSet.Services.HostPrivateKeyEx, 
> +TlsSetHostPrivateKeyEx, (Tls, Data, DataSize, Password),
> EFI_UNSUPPORTED);
> +}
> +
> +/**
> +  Adds the local private key to the specified TLS object.
> +
> +  This function adds the local private key (DER-encoded or 
> + PEM-encoded or PKCS#8 private
>key) into the specified TLS object for TLS negotiation.
> 
>@param[in]  Tls Pointer to the TLS object.
> -  @param[in]  DataPointer to the data buffer of a PEM-encoded RSA
> +  @param[in]  DataPointer to the data buffer of a DER-encoded or 
> PEM-encoded
>or PKCS#8 private key.
>@param[in]  DataSizeThe size of data buffer in bytes.
> 
> @@ -4511,6 +4563,59 @@ CryptoServiceTlsSetCertRevocationList (
>return CALL_BASECRYPTLIB (TlsSet.Services.CertRevocationList, 
> TlsSetCertRevocationList, (Data, DataSize), EFI_UNSUPPORTED);  }
> 
> +/**
> +  Set the signature algorithm list to used by the TLS object.
> +
> +  This function sets the signature algorithms for use by a specified TLS 
> object.
> +
> +  @param[in]  TlsPointer to a TLS object.
> +  @param[in]  Data   Array of UINT8 of signature algorithms. The 
> array consists of
> + pairs of the hash algorithm and the 
> signature algorithm as defined
> + 

Re: [edk2-devel] [PATCH 3/3] CryptoPkg: Add new Tls APIs to DXE and protocol

[Michael D Kinney]

I see one issue with adding new bits to the crypto services structured PCD.

Comment below.

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Li, Yi
> Sent: Sunday, September 25, 2022 11:27 PM
> To: devel@edk2.groups.io
> Cc: Li, Yi1 ; Yao, Jiewen ; Wang, 
> Jian J ; Lu, Xiaoyu1
> ; Jiang, Guomin 
> Subject: [edk2-devel] [PATCH 3/3] CryptoPkg: Add new Tls APIs to DXE and 
> protocol
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3892
> 
> The implementation provides new Tls library functions
> for Crypto EFI Driver and Protocol.
> 
> Cc: Jiewen Yao 
> Cc: Jian J Wang 
> Cc: Xiaoyu Lu 
> Cc: Guomin Jiang 
> Signed-off-by: Yi Li 
> ---
>  CryptoPkg/Driver/Crypto.c | 155 +-
>  .../Pcd/PcdCryptoServiceFamilyEnable.h|   5 +
>  .../BaseCryptLibOnProtocolPpi/CryptLib.c  | 146 -
>  CryptoPkg/Private/Protocol/Crypto.h   | 136 ++-
>  4 files changed, 435 insertions(+), 7 deletions(-)
> 
> diff --git a/CryptoPkg/Driver/Crypto.c b/CryptoPkg/Driver/Crypto.c
> index 7a8266aaba..f1ff77855c 100644
> --- a/CryptoPkg/Driver/Crypto.c
> +++ b/CryptoPkg/Driver/Crypto.c
> @@ -4238,6 +4238,28 @@ CryptoServiceTlsWrite (
>return CALL_BASECRYPTLIB (Tls.Services.Write, TlsWrite, (Tls, Buffer, 
> BufferSize), 0);
>  }
> 
> +/**
> +  Shutdown a TLS connection.
> +
> +  Shutdown the TLS connection without releasing the resources, meaning a new
> +  connection can be started without calling TlsNew() and without setting
> +  certificates etc.
> +
> +  @param[in]   TlsPointer to the TLS object to shutdown.
> +
> +  @retval EFI_SUCCESS The TLS is shutdown successfully.
> +  @retval EFI_INVALID_PARAMETER   Tls is NULL.
> +  @retval EFI_PROTOCOL_ERROR  Some other error occurred.
> +**/
> +EFI_STATUS
> +EFIAPI
> +CryptoServiceTlsShutdown (
> +  IN VOID  *Tls
> +  )
> +{
> +  return CALL_BASECRYPTLIB (Tls.Services.Shutdown, TlsShutdown, (Tls), 
> EFI_UNSUPPORTED);
> +}
> +
>  /**
>Set a new TLS/SSL method for a particular TLS object.
> 
> @@ -4463,11 +4485,41 @@ CryptoServiceTlsSetHostPublicCert (
>  /**
>Adds the local private key to the specified TLS object.
> 
> -  This function adds the local private key (PEM-encoded RSA or PKCS#8 private
> +  This function adds the local private key (DER-encoded or PEM-encoded or 
> PKCS#8 private
> +  key) into the specified TLS object for TLS negotiation.
> +
> +  @param[in]  Tls Pointer to the TLS object.
> +  @param[in]  DataPointer to the data buffer of a DER-encoded or 
> PEM-encoded
> +  or PKCS#8 private key.
> +  @param[in]  DataSizeThe size of data buffer in bytes.
> +  @param[in]  PasswordPointer to NULL-terminated private key password, 
> set it to NULL
> +  if private key not encrypted.
> +
> +  @retval  EFI_SUCCESS The operation succeeded.
> +  @retval  EFI_UNSUPPORTED This function is not supported.
> +  @retval  EFI_ABORTED Invalid private key data.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +CryptoServiceTlsSetHostPrivateKeyEx (
> +  IN VOID   *Tls,
> +  IN VOID   *Data,
> +  IN UINTN  DataSize,
> +  IN VOID   *Password  OPTIONAL
> +  )
> +{
> +  return CALL_BASECRYPTLIB (TlsSet.Services.HostPrivateKeyEx, 
> TlsSetHostPrivateKeyEx, (Tls, Data, DataSize, Password),
> EFI_UNSUPPORTED);
> +}
> +
> +/**
> +  Adds the local private key to the specified TLS object.
> +
> +  This function adds the local private key (DER-encoded or PEM-encoded or 
> PKCS#8 private
>key) into the specified TLS object for TLS negotiation.
> 
>@param[in]  Tls Pointer to the TLS object.
> -  @param[in]  DataPointer to the data buffer of a PEM-encoded RSA
> +  @param[in]  DataPointer to the data buffer of a DER-encoded or 
> PEM-encoded
>or PKCS#8 private key.
>@param[in]  DataSizeThe size of data buffer in bytes.
> 
> @@ -4511,6 +4563,59 @@ CryptoServiceTlsSetCertRevocationList (
>return CALL_BASECRYPTLIB (TlsSet.Services.CertRevocationList, 
> TlsSetCertRevocationList, (Data, DataSize), EFI_UNSUPPORTED);
>  }
> 
> +/**
> +  Set the signature algorithm list to used by the TLS object.
> +
> +  This function sets the signature algorithms for use by a specified TLS 
> object.
> +
> +  @param[in]  TlsPointer to a TLS object.
> +  @param[in]  Data   Array of UINT8 of signature algorithms. The 
> array consists of
> + pairs of the hash algorithm and the 
> signature algorithm as defined
> + in RFC 5246
> +  @param[in]  DataSize   The length the SignatureAlgoList. Must be 
> divisible by 2.
> +
> +  @retval  EFI_SUCCESS   The signature algorithm list was set 
> successfully.
> +  @retval  EFI_INVALID_PARAMETER The parameters are invalid.
> +  @retval  EFI_UNSUPPORTED   No supported TLS 

Re: [edk2-devel] [PATCH 0/3] CryptoPkg: Extend Tls library

[Li, Yi]

Hi All,
Any comment about this patch set? Thanks very much.

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Li, Yi
Sent: Monday, September 26, 2022 2:27 PM
To: devel@edk2.groups.io
Cc: Li, Yi1 ; Yao, Jiewen ; Wang, Jian 
J ; Lu, Xiaoyu1 ; Jiang, Guomin 

Subject: [edk2-devel] [PATCH 0/3] CryptoPkg: Extend Tls library

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3892

Review PR: https://github.com/tianocore/edk2/pull/3400
This patch sequence is used to extend Tls library, which are wrapped over 
OpenSSL. The implementation provides library functions for EFI DXE dirver and 
Protocol.

All APIs passed unit test and fuzzing test, detail as:
1. Unit test:
New Tls APIs tested on Intel platform as part of WIFI WPA3 feature.
2. Fuzzing test:
Various Fuzz Testing are employed across the all introduced APIs, and the test 
is used AFL (2.52b) and Libfuzzer (clang+llvm-11.0.0) as the fuzzer, based on 
HBFA.
Fuzzing Pass Rate is 100%;
The Code Coverage of new APIs is 91%.
All test case show in:
https://github.com/liyi77/edk2-staging/tree/HBFA/HBFA/UefiHostFuzzTestCasePkg/TestCase/CryptoPkg

Tested-by: Yi Li 
Cc: Jiewen Yao 
Cc: Jian J Wang 
Cc: Xiaoyu Lu 
Cc: Guomin Jiang 

Signed-off-by: Yi Li 

*** BLURB HERE ***

Yi Li (3):
  MdePkg: Add Tls configuration related define
  CryptoPkg: Extend Tls function library
  CryptoPkg: Add new Tls APIs to DXE and protocol

 CryptoPkg/Driver/Crypto.c | 155 ++-
 CryptoPkg/Include/Library/TlsLib.h| 126 +-
 .../Pcd/PcdCryptoServiceFamilyEnable.h|   5 +
 .../BaseCryptLibOnProtocolPpi/CryptLib.c  | 146 ++-
 CryptoPkg/Library/TlsLib/InternalTlsLib.h |   4 +
 CryptoPkg/Library/TlsLib/TlsConfig.c  | 413 --
 CryptoPkg/Library/TlsLib/TlsProcess.c |  32 ++
 CryptoPkg/Library/TlsLibNull/TlsConfigNull.c  | 123 +-  
CryptoPkg/Library/TlsLibNull/TlsProcessNull.c |  23 +
 CryptoPkg/Private/Protocol/Crypto.h   | 136 +-
 MdePkg/Include/IndustryStandard/Tls1.h| 110 +++--
 11 files changed, 1200 insertions(+), 73 deletions(-)

--
2.31.1.windows.1








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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: Handle InitialVFs=0 case for SR-IOV

[Ni, Ray]

Reviewed-by: Ray Ni 

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Foster Nong
> Sent: Thursday, September 29, 2022 5:20 PM
> To: devel@edk2.groups.io
> Cc: Nong, Foster 
> Subject: [edk2-devel] [PATCH 1/1] MdeModulePkg: Handle InitialVFs=0 case for 
> SR-IOV
> 
> Per the section 3.3.5 SR-IOV spec v1.1, InitialVFs (0ch).
> InitialVFs indicates to SR-PCIM the number of VFs that are initially 
> associated with the PF.
> The minimum value of InitialVFs is 0.
> 
> Below code is used to calculate SR-IOV reserved bus number,
> if InitialVFs =0, it maybe calculate the wrong bus number in this case.
>   LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride
> 
> we can fix it with below code:
>  if (PciIoDevice->InitialVFs == 0) {
>  PciIoDevice->ReservedBusNum = 0;
> } else {
> PFRid  = EFI_PCI_RID (Bus, Device, Func);
>  LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
> //
> // Calculate ReservedBusNum for this PF
> //
> PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
> //
>  // Calculate ReservedBusNum for this PF
> //
>  PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 
> 1);
> }
> 
> https://bugzilla.tianocore.org/show_bug.cgi?id=4069
> 
> Signed-off-by: Foster Nong 
> ---
>  .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> index 509f828b621d..eb250f6f7b62 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> @@ -2416,13 +2416,17 @@ CreatePciIoDevice (
>//
>// Calculate LastVF
>//
> -  PFRid  = EFI_PCI_RID (Bus, Device, Func);
> -  LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * 
> VFStride;
> +  if (PciIoDevice->InitialVFs == 0) {
> +PciIoDevice->ReservedBusNum = 0;
> +  } else {
> +PFRid  = EFI_PCI_RID (Bus, Device, Func);
> +LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * 
> VFStride;
> 
> -  //
> -  // Calculate ReservedBusNum for this PF
> -  //
> -  PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - 
> Bus + 1);
> +//
> +// Calculate ReservedBusNum for this PF
> +//
> +PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - 
> Bus + 1);
> +  }
> 
>DEBUG ((
>  DEBUG_INFO,
> --
> 2.37.1.windows.1
> 
> 
> 
> 
> 



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回复: [edk2-devel] [PATCH v5 3/3] .azurepipelines: Install code coverage tool

[gaoliming via groups.io]

Gua:
  Should the change in HostBasedUnitTestRunner.py be combined into the patch
2? 

Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io  代表 Guo, Gua
> 发送时间: 2022年9月30日 9:56
> 收件人: devel@edk2.groups.io
> 抄送: Gua Guo ; Sean Brogan
> ; Bret Barkelew
> ; Michael D Kinney
> ; Liming Gao 
> 主题: [edk2-devel] [PATCH v5 3/3] .azurepipelines: Install code coverage
tool
> 
> From: Gua Guo 
> 
> For Windows add below tool for code coverage
> 1. OpenCppCoverage: parsing pdb file to generate coverage
> data
> 2. pycobertura: show up html format data for coverage data
> 
> For Linux add below tool for code coverage
> 1. lcov: parsing gcda gcno file to generate coverage data
> 2. lcov-cobertura: convert coverage data to cobertura format
> 3. pycobertura: show up html format data for coverage data
> 
> Cc: Sean Brogan 
> Cc: Bret Barkelew 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Signed-off-by: Gua Guo 
> ---
>  .azurepipelines/Ubuntu-GCC5.yml  |  5 -
>  .azurepipelines/Windows-VS2019.yml   |  5 +
>  .azurepipelines/templates/pr-gate-build-job.yml  |  2 ++
>  .azurepipelines/templates/pr-gate-steps.yml  |  5 +
>  .../HostBasedUnitTestRunner.py   | 12
> ++--
>  pip-requirements.txt |  3 +++
>  6 files changed, 25 insertions(+), 7 deletions(-)
> 
> diff --git a/.azurepipelines/Ubuntu-GCC5.yml
> b/.azurepipelines/Ubuntu-GCC5.yml
> index 3760c6efe1..9d53528063 100644
> --- a/.azurepipelines/Ubuntu-GCC5.yml
> +++ b/.azurepipelines/Ubuntu-GCC5.yml
> @@ -18,4 +18,7 @@ jobs:
>  tool_chain_tag: 'GCC5'
> 
>  vm_image: 'ubuntu-latest'
> 
>  arch_list: "IA32,X64,ARM,AARCH64,RISCV64"
> 
> -
> 
> +extra_install_step:
> 
> +- bash: sudo apt-get install -y lcov
> 
> +  displayName: Install Code Coverage Tools
> 
> +  condition: and(gt(variables.pkg_count, 0), succeeded())
> 
> diff --git a/.azurepipelines/Windows-VS2019.yml
> b/.azurepipelines/Windows-VS2019.yml
> index e4bd4b1d22..c07e5bb434 100644
> --- a/.azurepipelines/Windows-VS2019.yml
> +++ b/.azurepipelines/Windows-VS2019.yml
> @@ -18,3 +18,8 @@ jobs:
>  tool_chain_tag: 'VS2019'
> 
>  vm_image: 'windows-2019'
> 
>  arch_list: "IA32,X64"
> 
> +extra_install_step:
> 
> +- powershell: choco install opencppcoverage; Write-Host
> "##vso[task.prependpath]C:\Program Files\OpenCppCoverage"
> 
> +  displayName: Install Code Coverage Tool
> 
> +  condition: and(gt(variables.pkg_count, 0), succeeded())
> 
> +
> 
> diff --git a/.azurepipelines/templates/pr-gate-build-job.yml
> b/.azurepipelines/templates/pr-gate-build-job.yml
> index 0e4ad019bf..0162ea97cb 100644
> --- a/.azurepipelines/templates/pr-gate-build-job.yml
> +++ b/.azurepipelines/templates/pr-gate-build-job.yml
> @@ -12,6 +12,7 @@ parameters:
>tool_chain_tag: ''
> 
>vm_image: ''
> 
>arch_list: ''
> 
> +  extra_install_step: []
> 
> 
> 
>  # Build step
> 
>  jobs:
> 
> @@ -70,3 +71,4 @@ jobs:
>build_pkgs: $(Build.Pkgs)
> 
>build_targets: $(Build.Targets)
> 
>build_archs: ${{ parameters.arch_list }}
> 
> +  extra_install_step: ${{ parameters.extra_install_step }}
> 
> diff --git a/.azurepipelines/templates/pr-gate-steps.yml
> b/.azurepipelines/templates/pr-gate-steps.yml
> index cb431e53fc..0568941399 100644
> --- a/.azurepipelines/templates/pr-gate-steps.yml
> +++ b/.azurepipelines/templates/pr-gate-steps.yml
> @@ -12,6 +12,7 @@ parameters:
>build_pkgs: ''
> 
>build_targets: ''
> 
>build_archs: ''
> 
> +  extra_install_step: []
> 
> 
> 
>  steps:
> 
>  - checkout: self
> 
> @@ -37,6 +38,8 @@ steps:
>displayName: fetch target branch
> 
>condition: eq(variables['Build.Reason'], 'PullRequest')
> 
> 
> 
> +- ${{ parameters.extra_install_step }}
> 
> +
> 
>  # trim the package list if this is a PR
> 
>  - task: CmdLine@1
> 
>displayName: Check if ${{ parameters.build_pkgs }} need testing
> 
> @@ -125,6 +128,8 @@ steps:
>TestSuites.xml
> 
>**/BUILD_TOOLS_REPORT.html
> 
>**/OVERRIDELOG.TXT
> 
> +  coverage.xml
> 
> +  coverage.html
> 
>  flattenFolders: true
> 
>condition: succeededOrFailed()
> 
> 
> 
> diff --git
> a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
> b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
> index d92de236dc..c2821cde7d 100644
> ---
> a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
> +++
> b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
> @@ -194,7 +194,7 @@ class HostBasedUnitTestRunner(IUefiBuildPlugin):
>  buildOutputBase =
> thebuilder.env.GetValue("BUILD_OUTPUT_BASE")
> 
>  testList = glob.glob(os.path.join(buildOutputBase,
> "**","*Test*.exe"), recursive=True)
> 
>  workspace = thebuilder.env.GetValue("WORKSPACE")
> 
> -
> 
> +workspace = (workspace + os.sep) if workspace[-1] != os.sep else
> workspace
> 

Re: [edk2-devel] [RFC] Adoption of CodeQL in edk2

[Ni, Ray]

Multiplication result converted to larger type · Code scanning alert #66 · 
tianocore/edk2 
(github.com)
Michael, I do not think above issue is a real issue. Will them be required to 
fix before enabling te CodeQL?

From: devel@edk2.groups.io  On Behalf Of Michael D Kinney
Sent: Friday, September 30, 2022 9:03 AM
To: devel@edk2.groups.io; mikub...@linux.microsoft.com; Kinney, Michael D 

Subject: Re: [edk2-devel] [RFC] Adoption of CodeQL in edk2

I just want to reiterate.  If there are no concerns or objections raised by Oct 
4, then the
CodeQL static analysis will be phased into use in the edk2 repo and there will 
be code
changes made to address the issues identified by COdeQL and all future code 
changes
after a CodeQL check is enabled will be blocked until the CodeQL CI checks pass.

This will impact all future code changes and all developers will have to learn 
how to
interpret CodeQL reports and fix issues.

Thanks,

Mike

From: devel@edk2.groups.io 
mailto:devel@edk2.groups.io>> On Behalf Of Michael Kubacki
Sent: Thursday, September 29, 2022 5:05 PM
To: Michael Kubacki 
mailto:mikub...@linux.microsoft.com>>; 
devel@edk2.groups.io
Subject: Re: [edk2-devel] [RFC] Adoption of CodeQL in edk2

If there's any further feedback on this RFC, please respond by Tuesday, October 
4th. We plan to start implementing the changes later in the week.

Thanks,
Michael



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回复: [edk2-devel] [PATCH] MdeModulePkg VariablePei: Add Variable state check when find variable in IndexTable.

[gaoliming via groups.io]

Jiading:

 Hob Variable Store Info IndexTable is NULL. So, this logic doesn’t work for 
HOB variable store. NV Variable Store Info has IndexTable. When its IndexTable 
is initialized, its IndexTable will only record the variable with VAR_ADDED 
attribute. Because NV Variable Data is not changed in PEI phase, this check is 
not required by NV variable. 

 

Thanks

Liming

发件人: devel@edk2.groups.io  代表 Jiading Zhang
发送时间: 2022年9月28日 11:05
收件人: devel@edk2.groups.io
主题: [edk2-devel] [PATCH] MdeModulePkg VariablePei: Add Variable state check 
when find variable in IndexTable.

 

When read a variable in PEI, it will find it first in the HOB, then find in 
variable store. When find in variable store, it will check the variable state, 
but find in HOB, it doesn't check the state, so if the variable was changed, it 
will find the obsolete variable in the HOB.

 

Signed-off-by: jdzhang mailto:jdzh...@kunluntech.com.cn> >

---

 MdeModulePkg/Universal/Variable/Pei/Variable.c | 12 +++-

 1 file changed, 7 insertions(+), 5 deletions(-)

 

diff --git a/MdeModulePkg/Universal/Variable/Pei/Variable.c 
b/MdeModulePkg/Universal/Variable/Pei/Variable.c

index 26a4c73b45..dffbd8cdb1 100644

--- a/MdeModulePkg/Universal/Variable/Pei/Variable.c

+++ b/MdeModulePkg/Universal/Variable/Pei/Variable.c

@@ -866,11 +866,13 @@ FindVariableEx (

   Offset  += IndexTable->Index[Index];

   MaxIndex = (VARIABLE_HEADER *)((UINT8 *)IndexTable->StartPtr + Offset);

   GetVariableHeader (StoreInfo, MaxIndex, );

-  if (CompareWithValidVariable (StoreInfo, MaxIndex, VariableHeader, 
VariableName, VendorGuid, PtrTrack) == EFI_SUCCESS) {

-if (VariableHeader->State == (VAR_IN_DELETED_TRANSITION & VAR_ADDED)) {

-  InDeletedVariable = PtrTrack->CurrPtr;

-} else {

-  return EFI_SUCCESS;

+  if ((VariableHeader->State == VAR_ADDED) || (VariableHeader->State == 
(VAR_IN_DELETED_TRANSITION & VAR_ADDED))) {

+if (CompareWithValidVariable (StoreInfo, MaxIndex, VariableHeader, 
VariableName, VendorGuid, PtrTrack) == EFI_SUCCESS) {

+  if (VariableHeader->State == (VAR_IN_DELETED_TRANSITION & 
VAR_ADDED)) {

+InDeletedVariable = PtrTrack->CurrPtr;

+  } else {

+return EFI_SUCCESS;

+  }

 }

   }

 }

-- 

2.20.1.windows.1

 





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Re: [edk2-devel] [PATCH v5 0/3] Add code coverage support for GCC

[Guo, Gua]

@Kinney, Michael D and @Sean 
Brogan



The PR is for the patch.

https://github.com/tianocore/edk2/pull/3349



CI/CD support ready done. Coverage Data can get on Build/coverage.html. Have 
any concern, please also share for me.



Thanks,

Gua

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Guo, Gua
Sent: Friday, September 30, 2022 9:56 AM
To: devel@edk2.groups.io
Cc: Guo, Gua 
Subject: [edk2-devel] [PATCH v5 0/3] Add code coverage support for GCC



From: Gua Guo mailto:gua@intel.com>>



V1: Add coverage option for GCC

V2: Add ReadMe.md for how to generate coverage report

V3: Add VS2019 and GCC code coverage support

V4: Add VS2019 and GCC Azure CI/CD support

V5: Fix some typo and some flow issue



Gua Guo (3):

  UnitTestFrameworkPkg: Add code coverage support for GCC

  BaseTools/Plugin: Add coverage support for Unit Test

  .azurepipelines: Install code coverage tool



.azurepipelines/Ubuntu-GCC5.yml   |   5 +-

.azurepipelines/Windows-VS2019.yml|   5 +

.../templates/pr-gate-build-job.yml   |   2 +

.azurepipelines/templates/pr-gate-steps.yml   |   5 +

.../HostBasedUnitTestRunner.py| 119 ++

UnitTestFrameworkPkg/ReadMe.md|  37 +-

.../UnitTestFrameworkPkg.ci.yaml  |   2 +

.../UnitTestFrameworkPkgHost.dsc.inc  |   3 +-

pip-requirements.txt  |   3 +

9 files changed, 176 insertions(+), 5 deletions(-)



--

2.31.1.windows.1














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[edk2-devel] [PATCH v5 3/3] .azurepipelines: Install code coverage tool

[Guo, Gua]

From: Gua Guo 

For Windows add below tool for code coverage
1. OpenCppCoverage: parsing pdb file to generate coverage
data
2. pycobertura: show up html format data for coverage data

For Linux add below tool for code coverage
1. lcov: parsing gcda gcno file to generate coverage data
2. lcov-cobertura: convert coverage data to cobertura format
3. pycobertura: show up html format data for coverage data

Cc: Sean Brogan 
Cc: Bret Barkelew 
Cc: Michael D Kinney 
Cc: Liming Gao 
Signed-off-by: Gua Guo 
---
 .azurepipelines/Ubuntu-GCC5.yml  |  5 -
 .azurepipelines/Windows-VS2019.yml   |  5 +
 .azurepipelines/templates/pr-gate-build-job.yml  |  2 ++
 .azurepipelines/templates/pr-gate-steps.yml  |  5 +
 .../HostBasedUnitTestRunner.py   | 12 ++--
 pip-requirements.txt |  3 +++
 6 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/.azurepipelines/Ubuntu-GCC5.yml b/.azurepipelines/Ubuntu-GCC5.yml
index 3760c6efe1..9d53528063 100644
--- a/.azurepipelines/Ubuntu-GCC5.yml
+++ b/.azurepipelines/Ubuntu-GCC5.yml
@@ -18,4 +18,7 @@ jobs:
 tool_chain_tag: 'GCC5'
 vm_image: 'ubuntu-latest'
 arch_list: "IA32,X64,ARM,AARCH64,RISCV64"
-
+extra_install_step:
+- bash: sudo apt-get install -y lcov
+  displayName: Install Code Coverage Tools
+  condition: and(gt(variables.pkg_count, 0), succeeded())
diff --git a/.azurepipelines/Windows-VS2019.yml 
b/.azurepipelines/Windows-VS2019.yml
index e4bd4b1d22..c07e5bb434 100644
--- a/.azurepipelines/Windows-VS2019.yml
+++ b/.azurepipelines/Windows-VS2019.yml
@@ -18,3 +18,8 @@ jobs:
 tool_chain_tag: 'VS2019'
 vm_image: 'windows-2019'
 arch_list: "IA32,X64"
+extra_install_step:
+- powershell: choco install opencppcoverage; Write-Host 
"##vso[task.prependpath]C:\Program Files\OpenCppCoverage"
+  displayName: Install Code Coverage Tool
+  condition: and(gt(variables.pkg_count, 0), succeeded())
+
diff --git a/.azurepipelines/templates/pr-gate-build-job.yml 
b/.azurepipelines/templates/pr-gate-build-job.yml
index 0e4ad019bf..0162ea97cb 100644
--- a/.azurepipelines/templates/pr-gate-build-job.yml
+++ b/.azurepipelines/templates/pr-gate-build-job.yml
@@ -12,6 +12,7 @@ parameters:
   tool_chain_tag: ''
   vm_image: ''
   arch_list: ''
+  extra_install_step: []
 
 # Build step
 jobs:
@@ -70,3 +71,4 @@ jobs:
   build_pkgs: $(Build.Pkgs)
   build_targets: $(Build.Targets)
   build_archs: ${{ parameters.arch_list }}
+  extra_install_step: ${{ parameters.extra_install_step }}
diff --git a/.azurepipelines/templates/pr-gate-steps.yml 
b/.azurepipelines/templates/pr-gate-steps.yml
index cb431e53fc..0568941399 100644
--- a/.azurepipelines/templates/pr-gate-steps.yml
+++ b/.azurepipelines/templates/pr-gate-steps.yml
@@ -12,6 +12,7 @@ parameters:
   build_pkgs: ''
   build_targets: ''
   build_archs: ''
+  extra_install_step: []
 
 steps:
 - checkout: self
@@ -37,6 +38,8 @@ steps:
   displayName: fetch target branch
   condition: eq(variables['Build.Reason'], 'PullRequest')
 
+- ${{ parameters.extra_install_step }}
+
 # trim the package list if this is a PR
 - task: CmdLine@1
   displayName: Check if ${{ parameters.build_pkgs }} need testing
@@ -125,6 +128,8 @@ steps:
   TestSuites.xml
   **/BUILD_TOOLS_REPORT.html
   **/OVERRIDELOG.TXT
+  coverage.xml
+  coverage.html
 flattenFolders: true
   condition: succeededOrFailed()
 
diff --git 
a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py 
b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
index d92de236dc..c2821cde7d 100644
--- a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
+++ b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
@@ -194,7 +194,7 @@ class HostBasedUnitTestRunner(IUefiBuildPlugin):
 buildOutputBase = thebuilder.env.GetValue("BUILD_OUTPUT_BASE")
 testList = glob.glob(os.path.join(buildOutputBase, "**","*Test*.exe"), 
recursive=True)
 workspace = thebuilder.env.GetValue("WORKSPACE")
-
+workspace = (workspace + os.sep) if workspace[-1] != os.sep else 
workspace
 # Generate coverage file
 coverageFile = ""
 for testFile in testList:
@@ -204,13 +204,14 @@ class HostBasedUnitTestRunner(IUefiBuildPlugin):
 logging.error("UnitTest Coverage: Failed to collect coverage 
data.")
 return 1
 
+DiskName = workspace[:workspace.find (":\\") + 2]
 # Generate and HTML file if requested.by each package
-ret = RunCmd("OpenCppCoverage", f"--export_type 
cobertura:{buildOutputBase}/coverage.xml --working_dir={workspace}/Build 
{coverageFile}")
+ret = RunCmd("OpenCppCoverage", f"--export_type 
cobertura:{buildOutputBase}/coverage.xml --working_dir={workspace}Build 
{coverageFile}")
 if(ret != 0):
 logging.error("UnitTest Coverage: 

[edk2-devel] [PATCH v5 2/3] BaseTools/Plugin: Add coverage support for Unit Test

[Guo, Gua]

From: Gua Guo 

For GCC, use lcov to generate Unit Test code coverage
report

For VS2019, use OpenCppCoverage to generate code
coverage report

Cc: Bob Feng 
Cc: Bret Barkelew 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Sean Brogan 
Signed-off-by: Gua Guo 
---
 .../HostBasedUnitTestRunner.py| 119 ++
 1 file changed, 119 insertions(+)

diff --git 
a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py 
b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
index c1eeaf2625..d92de236dc 100644
--- a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
+++ b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
@@ -112,4 +112,123 @@ class HostBasedUnitTestRunner(IUefiBuildPlugin):
 "  %s - %s" % 
(case.attrib['name'], result.text))
 failure_count += 1
 
+if thebuilder.env.GetValue("TOOL_CHAIN_TAG") == "GCC5":
+self.gen_code_coverage_gcc(thebuilder)
+elif thebuilder.env.GetValue("TOOL_CHAIN_TAG") == "VS2019":
+self.gen_code_coverage_msvc(thebuilder)
+else:
+logging.info("Skipping code coverage. Only supported on GCC.")
+
 return failure_count
+
+def gen_code_coverage_gcc(self, thebuilder):
+logging.info("Generating UnitTest code coverage")
+
+buildOutputBase = thebuilder.env.GetValue("BUILD_OUTPUT_BASE")
+workspace = thebuilder.env.GetValue("WORKSPACE")
+
+# Generate base code coverage for all source files
+ret = RunCmd("lcov", f"--no-external --capture --initial --directory 
{buildOutputBase} --output-file {buildOutputBase}/cov-base.info --rc 
lcov_branch_coverage=1")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to build initial coverage 
data.")
+return 1
+
+# Coverage data for tested files only
+ret = RunCmd("lcov", f"--capture --directory {buildOutputBase}/ 
--output-file {buildOutputBase}/coverage-test.info --rc lcov_branch_coverage=1")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to build coverage data 
for tested files.")
+return 1
+
+# Aggregate all coverage data
+ret = RunCmd("lcov", f"--add-tracefile {buildOutputBase}/cov-base.info 
--add-tracefile {buildOutputBase}/coverage-test.info --output-file 
{buildOutputBase}/total-coverage.info --rc lcov_branch_coverage=1")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to aggregate coverage 
data.")
+return 1
+
+# Generate coverage XML
+ret = RunCmd("lcov_cobertura",f"{buildOutputBase}/total-coverage.info 
-o {buildOutputBase}/compare.xml")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to generate coverage 
XML.")
+return 1
+
+# Filter out auto-generated and test code
+ret = RunCmd("lcov_cobertura",f"{buildOutputBase}/total-coverage.info 
--excludes ^.*UnitTest\|^.*MU\|^.*Mock\|^.*DEBUG -o 
{buildOutputBase}/coverage.xml")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed generate filtered 
coverage XML.")
+return 1
+
+# Generate all coverage file
+testCoverageList = glob.glob 
(f"{workspace}/Build/**/total-coverage.info", recursive=True)
+
+coverageFile = ""
+for testCoverage in testCoverageList:
+coverageFile += " --add-tracefile " + testCoverage
+ret = RunCmd("lcov", f"{coverageFile} --output-file 
{workspace}/Build/all-coverage.info --rc lcov_branch_coverage=1")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed generate all coverage 
file.")
+return 1
+
+# Generate and HTML file if requested.by each package
+ret = RunCmd("pycobertura", f"show --format html --output 
{buildOutputBase}/coverage.html {buildOutputBase}/coverage.xml --source 
{workspace}")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to generate HTML in 
single package..")
+
+# Generate and HTML file if requested.for all package
+if os.path.isfile(f"{workspace}/Build/coverage.xml"):
+os.remove(f"{workspace}/Build/coverage.xml")
+ret = RunCmd("lcov_cobertura",f"{workspace}/Build/all-coverage.info 
--excludes ^.*UnitTest\|^.*MU\|^.*Mock\|^.*DEBUG -o 
{workspace}/Build/coverage.xml")
+
+if os.path.isfile(f"{workspace}/Build/coverage.html"):
+os.remove(f"{workspace}/Build/coverage.html")
+ret = RunCmd("pycobertura", f"show --format html --output 
{workspace}/Build/coverage.html {workspace}/Build/coverage.xml --source 
{workspace}")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to generate HTML.")
+
+return 0
+
+
+def gen_code_coverage_msvc(self, thebuilder):
+

[edk2-devel] [PATCH v5 1/3] UnitTestFrameworkPkg: Add code coverage support for GCC

[Guo, Gua]

From: Gua Guo 

In order to collect code coverage after running executable
file, generate *.gcda and *.gcno file that require by lcov tool
to generate code coverage report.

Cc: Michael D Kinney 
Cc: Sean Brogan 
Cc: Bret Barkelew 
Cc: Michael Kubacki 
Signed-off-by: Gua Guo 
---
 UnitTestFrameworkPkg/ReadMe.md| 37 +--
 .../UnitTestFrameworkPkg.ci.yaml  |  2 +
 .../UnitTestFrameworkPkgHost.dsc.inc  |  3 +-
 3 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/UnitTestFrameworkPkg/ReadMe.md b/UnitTestFrameworkPkg/ReadMe.md
index e696412cb3..c00e2411f8 100644
--- a/UnitTestFrameworkPkg/ReadMe.md
+++ b/UnitTestFrameworkPkg/ReadMe.md
@@ -60,7 +60,7 @@ you should be good to go.
 
 See this example in 'SampleUnitTestUefiShell.inf'...
 
-```
+```inf
 [Packages]
   MdePkg/MdePkg.dec
 
@@ -75,7 +75,7 @@ See this example in 'SampleUnitTestUefiShell.inf'...
 Also, if you want you test to automatically be picked up by the Test Runner 
plugin, you will need
 to make sure that the module `BASE_NAME` contains the word `Test`...
 
-```
+```inf
 [Defines]
   BASE_NAME  = SampleUnitTestUefiShell
 ```
@@ -361,7 +361,7 @@ RUNNING TEST SUITE: Int Safe Conversions Test Suite
 ```
 
 You can also, if you are so inclined, read the output from the exact instance 
of the test that was run during
-`stuart_ci_build`. The ouput file can be found on a path that looks like:
+`stuart_ci_build`. The output file can be found on a path that looks like:
 
 `Build//HostTest//...result.xml`
 
@@ -399,6 +399,37 @@ CMOCKA_XML_FILE=
 
 This mode is used by the test running plugin to aggregate the results for CI 
test status reporting in the web view.
 
+### Code Coverage
+
+Host based Unit Tests will automatically enable coverage data.
+
+For Windows, This is primarily leverage for pipeline builds, but this can be 
leveraged locally using the
+OpenCppCoverage windows tool, and pycobertura is used to covert this coverage 
data to a human readable HTML
+file. These tools must be installed to parse code coverage.
+
+- Windows Prerequisite
+  ```bash
+  Download and install https://github.com/OpenCppCoverage/OpenCppCoverage/tags
+  python -m pip install --upgrade -r ./pip-requirements.txt
+  stuart_ci_build -c .pytool/CISettings.py  -t NOOPT TOOL_CHAIN_TAG=VS2019 -p 
MdeModulePkg
+  Open Build/coverage.html
+  ```
+
+
+For Linux, This is primarily leveraged for pipeline builds, but this can be 
leveraged locally using the
+lcov linux tool, and parsed using the lcov_cobertura python tool. pycobertura 
is used to
+covert this coverage data to a human readable HTML file. These tools must be 
installed
+to parse code coverage.
+
+- Linux Prerequisite
+  ```bash
+  sudo apt-get install -y lcov
+  python -m pip install --upgrade -r ./pip-requirements.txt
+  stuart_ci_build -c .pytool/CISettings.py  -t NOOPT TOOL_CHAIN_TAG=GCC5 -p 
MdeModulePkg
+  Open Build/coverage.html
+  ```
+
+
 ### Important Note
 
 This works on both Windows and Linux, but is currently limited to x64 
architectures. Working on getting others, but we
diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml 
b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml
index 77d51e1348..f68882e1cf 100644
--- a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml
+++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml
@@ -90,6 +90,8 @@
 "pytools",
 "NOFAILURE",
 "cmockery",
+"cobertura",
+"pycobertura",
 "DHAVE", # build flag for cmocka in the INF
 "corthon",  # Contact GitHub account in Readme
 "mdkinney", # Contact GitHub account in Readme
diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc 
b/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc
index 4dd8d4ac67..ca46b8513a 100644
--- a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc
+++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc
@@ -25,7 +25,8 @@
   GCC:*_*_*_CC_FLAGS   = -D UNIT_TESTING_DEBUG=1
   XCODE:*_*_*_CC_FLAGS = -D UNIT_TESTING_DEBUG=1
 !endif
-
+  GCC:*_GCC5_*_CC_FLAGS = --coverage
+  GCC:*_GCC5_*_DLINK_FLAGS = --coverage
 [BuildOptions.common.EDKII.HOST_APPLICATION]
   #
   # MSFT
-- 
2.31.1.windows.1



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[edk2-devel] [PATCH v5 0/3] Add code coverage support for GCC

[Guo, Gua]

From: Gua Guo 

V1: Add coverage option for GCC
V2: Add ReadMe.md for how to generate coverage report
V3: Add VS2019 and GCC code coverage support
V4: Add VS2019 and GCC Azure CI/CD support
V5: Fix some typo and some flow issue

Gua Guo (3):
  UnitTestFrameworkPkg: Add code coverage support for GCC
  BaseTools/Plugin: Add coverage support for Unit Test
  .azurepipelines: Install code coverage tool

 .azurepipelines/Ubuntu-GCC5.yml   |   5 +-
 .azurepipelines/Windows-VS2019.yml|   5 +
 .../templates/pr-gate-build-job.yml   |   2 +
 .azurepipelines/templates/pr-gate-steps.yml   |   5 +
 .../HostBasedUnitTestRunner.py| 119 ++
 UnitTestFrameworkPkg/ReadMe.md|  37 +-
 .../UnitTestFrameworkPkg.ci.yaml  |   2 +
 .../UnitTestFrameworkPkgHost.dsc.inc  |   3 +-
 pip-requirements.txt  |   3 +
 9 files changed, 176 insertions(+), 5 deletions(-)

-- 
2.31.1.windows.1



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[edk2-devel] [PATCH 3/3] .azurepipelines: Install code coverage tool

[Guo, Gua]

From: Gua Guo 

For Windows add below tool for code coverage
1. OpenCppCoverage: parsing pdb file to generate coverage
data
2. pycobertura: show up html format data for coverage data

For Linux add below tool for code coverage
1. lcov: parsing gcda gcno file to generate coverage data
2. lcov-cobertura: convert coverage data to cobertura format
3. pycobertura: show up html format data for coverage data

Cc: Sean Brogan 
Cc: Bret Barkelew 
Cc: Michael D Kinney 
Cc: Liming Gao 
Signed-off-by: Gua Guo 
---
 .azurepipelines/Ubuntu-GCC5.yml  |  5 -
 .azurepipelines/Windows-VS2019.yml   |  5 +
 .azurepipelines/templates/pr-gate-build-job.yml  |  2 ++
 .azurepipelines/templates/pr-gate-steps.yml  |  5 +
 .../HostBasedUnitTestRunner.py   | 12 ++--
 pip-requirements.txt |  3 +++
 6 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/.azurepipelines/Ubuntu-GCC5.yml b/.azurepipelines/Ubuntu-GCC5.yml
index 3760c6efe1..9d53528063 100644
--- a/.azurepipelines/Ubuntu-GCC5.yml
+++ b/.azurepipelines/Ubuntu-GCC5.yml
@@ -18,4 +18,7 @@ jobs:
 tool_chain_tag: 'GCC5'
 vm_image: 'ubuntu-latest'
 arch_list: "IA32,X64,ARM,AARCH64,RISCV64"
-
+extra_install_step:
+- bash: sudo apt-get install -y lcov
+  displayName: Install Code Coverage Tools
+  condition: and(gt(variables.pkg_count, 0), succeeded())
diff --git a/.azurepipelines/Windows-VS2019.yml 
b/.azurepipelines/Windows-VS2019.yml
index e4bd4b1d22..c07e5bb434 100644
--- a/.azurepipelines/Windows-VS2019.yml
+++ b/.azurepipelines/Windows-VS2019.yml
@@ -18,3 +18,8 @@ jobs:
 tool_chain_tag: 'VS2019'
 vm_image: 'windows-2019'
 arch_list: "IA32,X64"
+extra_install_step:
+- powershell: choco install opencppcoverage; Write-Host 
"##vso[task.prependpath]C:\Program Files\OpenCppCoverage"
+  displayName: Install Code Coverage Tool
+  condition: and(gt(variables.pkg_count, 0), succeeded())
+
diff --git a/.azurepipelines/templates/pr-gate-build-job.yml 
b/.azurepipelines/templates/pr-gate-build-job.yml
index 0e4ad019bf..0162ea97cb 100644
--- a/.azurepipelines/templates/pr-gate-build-job.yml
+++ b/.azurepipelines/templates/pr-gate-build-job.yml
@@ -12,6 +12,7 @@ parameters:
   tool_chain_tag: ''
   vm_image: ''
   arch_list: ''
+  extra_install_step: []
 
 # Build step
 jobs:
@@ -70,3 +71,4 @@ jobs:
   build_pkgs: $(Build.Pkgs)
   build_targets: $(Build.Targets)
   build_archs: ${{ parameters.arch_list }}
+  extra_install_step: ${{ parameters.extra_install_step }}
diff --git a/.azurepipelines/templates/pr-gate-steps.yml 
b/.azurepipelines/templates/pr-gate-steps.yml
index cb431e53fc..0568941399 100644
--- a/.azurepipelines/templates/pr-gate-steps.yml
+++ b/.azurepipelines/templates/pr-gate-steps.yml
@@ -12,6 +12,7 @@ parameters:
   build_pkgs: ''
   build_targets: ''
   build_archs: ''
+  extra_install_step: []
 
 steps:
 - checkout: self
@@ -37,6 +38,8 @@ steps:
   displayName: fetch target branch
   condition: eq(variables['Build.Reason'], 'PullRequest')
 
+- ${{ parameters.extra_install_step }}
+
 # trim the package list if this is a PR
 - task: CmdLine@1
   displayName: Check if ${{ parameters.build_pkgs }} need testing
@@ -125,6 +128,8 @@ steps:
   TestSuites.xml
   **/BUILD_TOOLS_REPORT.html
   **/OVERRIDELOG.TXT
+  coverage.xml
+  coverage.html
 flattenFolders: true
   condition: succeededOrFailed()
 
diff --git 
a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py 
b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
index d92de236dc..c2821cde7d 100644
--- a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
+++ b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
@@ -194,7 +194,7 @@ class HostBasedUnitTestRunner(IUefiBuildPlugin):
 buildOutputBase = thebuilder.env.GetValue("BUILD_OUTPUT_BASE")
 testList = glob.glob(os.path.join(buildOutputBase, "**","*Test*.exe"), 
recursive=True)
 workspace = thebuilder.env.GetValue("WORKSPACE")
-
+workspace = (workspace + os.sep) if workspace[-1] != os.sep else 
workspace
 # Generate coverage file
 coverageFile = ""
 for testFile in testList:
@@ -204,13 +204,14 @@ class HostBasedUnitTestRunner(IUefiBuildPlugin):
 logging.error("UnitTest Coverage: Failed to collect coverage 
data.")
 return 1
 
+DiskName = workspace[:workspace.find (":\\") + 2]
 # Generate and HTML file if requested.by each package
-ret = RunCmd("OpenCppCoverage", f"--export_type 
cobertura:{buildOutputBase}/coverage.xml --working_dir={workspace}/Build 
{coverageFile}")
+ret = RunCmd("OpenCppCoverage", f"--export_type 
cobertura:{buildOutputBase}/coverage.xml --working_dir={workspace}Build 
{coverageFile}")
 if(ret != 0):
 logging.error("UnitTest Coverage: 

[edk2-devel] [PATCH 2/3] BaseTools/Plugin: Add coverage support for Unit Test

[Guo, Gua]

From: Gua Guo 

For GCC, use lcov to generate Unit Test code coverage
report

For VS2019, use OpenCppCoverage to generate code
coverage report

Cc: Bob Feng 
Cc: Bret Barkelew 
Cc: Liming Gao 
Cc: Michael D Kinney 
Cc: Sean Brogan 
Signed-off-by: Gua Guo 
---
 .../HostBasedUnitTestRunner.py| 119 ++
 1 file changed, 119 insertions(+)

diff --git 
a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py 
b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
index c1eeaf2625..d92de236dc 100644
--- a/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
+++ b/BaseTools/Plugin/HostBasedUnitTestRunner/HostBasedUnitTestRunner.py
@@ -112,4 +112,123 @@ class HostBasedUnitTestRunner(IUefiBuildPlugin):
 "  %s - %s" % 
(case.attrib['name'], result.text))
 failure_count += 1
 
+if thebuilder.env.GetValue("TOOL_CHAIN_TAG") == "GCC5":
+self.gen_code_coverage_gcc(thebuilder)
+elif thebuilder.env.GetValue("TOOL_CHAIN_TAG") == "VS2019":
+self.gen_code_coverage_msvc(thebuilder)
+else:
+logging.info("Skipping code coverage. Only supported on GCC.")
+
 return failure_count
+
+def gen_code_coverage_gcc(self, thebuilder):
+logging.info("Generating UnitTest code coverage")
+
+buildOutputBase = thebuilder.env.GetValue("BUILD_OUTPUT_BASE")
+workspace = thebuilder.env.GetValue("WORKSPACE")
+
+# Generate base code coverage for all source files
+ret = RunCmd("lcov", f"--no-external --capture --initial --directory 
{buildOutputBase} --output-file {buildOutputBase}/cov-base.info --rc 
lcov_branch_coverage=1")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to build initial coverage 
data.")
+return 1
+
+# Coverage data for tested files only
+ret = RunCmd("lcov", f"--capture --directory {buildOutputBase}/ 
--output-file {buildOutputBase}/coverage-test.info --rc lcov_branch_coverage=1")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to build coverage data 
for tested files.")
+return 1
+
+# Aggregate all coverage data
+ret = RunCmd("lcov", f"--add-tracefile {buildOutputBase}/cov-base.info 
--add-tracefile {buildOutputBase}/coverage-test.info --output-file 
{buildOutputBase}/total-coverage.info --rc lcov_branch_coverage=1")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to aggregate coverage 
data.")
+return 1
+
+# Generate coverage XML
+ret = RunCmd("lcov_cobertura",f"{buildOutputBase}/total-coverage.info 
-o {buildOutputBase}/compare.xml")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to generate coverage 
XML.")
+return 1
+
+# Filter out auto-generated and test code
+ret = RunCmd("lcov_cobertura",f"{buildOutputBase}/total-coverage.info 
--excludes ^.*UnitTest\|^.*MU\|^.*Mock\|^.*DEBUG -o 
{buildOutputBase}/coverage.xml")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed generate filtered 
coverage XML.")
+return 1
+
+# Generate all coverage file
+testCoverageList = glob.glob 
(f"{workspace}/Build/**/total-coverage.info", recursive=True)
+
+coverageFile = ""
+for testCoverage in testCoverageList:
+coverageFile += " --add-tracefile " + testCoverage
+ret = RunCmd("lcov", f"{coverageFile} --output-file 
{workspace}/Build/all-coverage.info --rc lcov_branch_coverage=1")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed generate all coverage 
file.")
+return 1
+
+# Generate and HTML file if requested.by each package
+ret = RunCmd("pycobertura", f"show --format html --output 
{buildOutputBase}/coverage.html {buildOutputBase}/coverage.xml --source 
{workspace}")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to generate HTML in 
single package..")
+
+# Generate and HTML file if requested.for all package
+if os.path.isfile(f"{workspace}/Build/coverage.xml"):
+os.remove(f"{workspace}/Build/coverage.xml")
+ret = RunCmd("lcov_cobertura",f"{workspace}/Build/all-coverage.info 
--excludes ^.*UnitTest\|^.*MU\|^.*Mock\|^.*DEBUG -o 
{workspace}/Build/coverage.xml")
+
+if os.path.isfile(f"{workspace}/Build/coverage.html"):
+os.remove(f"{workspace}/Build/coverage.html")
+ret = RunCmd("pycobertura", f"show --format html --output 
{workspace}/Build/coverage.html {workspace}/Build/coverage.xml --source 
{workspace}")
+if(ret != 0):
+logging.error("UnitTest Coverage: Failed to generate HTML.")
+
+return 0
+
+
+def gen_code_coverage_msvc(self, thebuilder):
+

[edk2-devel] [PATCH 1/3] UnitTestFrameworkPkg: Add code coverage support for GCC

[Guo, Gua]

From: Gua Guo 

In order to collect code coverage after running executable
file, generate *.gcda and *.gcno file that require by lcov tool
to generate code coverage report.

Cc: Michael D Kinney 
Cc: Sean Brogan 
Cc: Bret Barkelew 
Cc: Michael Kubacki 
Signed-off-by: Gua Guo 
---
 UnitTestFrameworkPkg/ReadMe.md| 37 +--
 .../UnitTestFrameworkPkg.ci.yaml  |  2 +
 .../UnitTestFrameworkPkgHost.dsc.inc  |  3 +-
 3 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/UnitTestFrameworkPkg/ReadMe.md b/UnitTestFrameworkPkg/ReadMe.md
index e696412cb3..c00e2411f8 100644
--- a/UnitTestFrameworkPkg/ReadMe.md
+++ b/UnitTestFrameworkPkg/ReadMe.md
@@ -60,7 +60,7 @@ you should be good to go.
 
 See this example in 'SampleUnitTestUefiShell.inf'...
 
-```
+```inf
 [Packages]
   MdePkg/MdePkg.dec
 
@@ -75,7 +75,7 @@ See this example in 'SampleUnitTestUefiShell.inf'...
 Also, if you want you test to automatically be picked up by the Test Runner 
plugin, you will need
 to make sure that the module `BASE_NAME` contains the word `Test`...
 
-```
+```inf
 [Defines]
   BASE_NAME  = SampleUnitTestUefiShell
 ```
@@ -361,7 +361,7 @@ RUNNING TEST SUITE: Int Safe Conversions Test Suite
 ```
 
 You can also, if you are so inclined, read the output from the exact instance 
of the test that was run during
-`stuart_ci_build`. The ouput file can be found on a path that looks like:
+`stuart_ci_build`. The output file can be found on a path that looks like:
 
 `Build//HostTest//...result.xml`
 
@@ -399,6 +399,37 @@ CMOCKA_XML_FILE=
 
 This mode is used by the test running plugin to aggregate the results for CI 
test status reporting in the web view.
 
+### Code Coverage
+
+Host based Unit Tests will automatically enable coverage data.
+
+For Windows, This is primarily leverage for pipeline builds, but this can be 
leveraged locally using the
+OpenCppCoverage windows tool, and pycobertura is used to covert this coverage 
data to a human readable HTML
+file. These tools must be installed to parse code coverage.
+
+- Windows Prerequisite
+  ```bash
+  Download and install https://github.com/OpenCppCoverage/OpenCppCoverage/tags
+  python -m pip install --upgrade -r ./pip-requirements.txt
+  stuart_ci_build -c .pytool/CISettings.py  -t NOOPT TOOL_CHAIN_TAG=VS2019 -p 
MdeModulePkg
+  Open Build/coverage.html
+  ```
+
+
+For Linux, This is primarily leveraged for pipeline builds, but this can be 
leveraged locally using the
+lcov linux tool, and parsed using the lcov_cobertura python tool. pycobertura 
is used to
+covert this coverage data to a human readable HTML file. These tools must be 
installed
+to parse code coverage.
+
+- Linux Prerequisite
+  ```bash
+  sudo apt-get install -y lcov
+  python -m pip install --upgrade -r ./pip-requirements.txt
+  stuart_ci_build -c .pytool/CISettings.py  -t NOOPT TOOL_CHAIN_TAG=GCC5 -p 
MdeModulePkg
+  Open Build/coverage.html
+  ```
+
+
 ### Important Note
 
 This works on both Windows and Linux, but is currently limited to x64 
architectures. Working on getting others, but we
diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml 
b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml
index 77d51e1348..f68882e1cf 100644
--- a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml
+++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.ci.yaml
@@ -90,6 +90,8 @@
 "pytools",
 "NOFAILURE",
 "cmockery",
+"cobertura",
+"pycobertura",
 "DHAVE", # build flag for cmocka in the INF
 "corthon",  # Contact GitHub account in Readme
 "mdkinney", # Contact GitHub account in Readme
diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc 
b/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc
index 4dd8d4ac67..ca46b8513a 100644
--- a/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc
+++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkgHost.dsc.inc
@@ -25,7 +25,8 @@
   GCC:*_*_*_CC_FLAGS   = -D UNIT_TESTING_DEBUG=1
   XCODE:*_*_*_CC_FLAGS = -D UNIT_TESTING_DEBUG=1
 !endif
-
+  GCC:*_GCC5_*_CC_FLAGS = --coverage
+  GCC:*_GCC5_*_DLINK_FLAGS = --coverage
 [BuildOptions.common.EDKII.HOST_APPLICATION]
   #
   # MSFT
-- 
2.31.1.windows.1



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[edk2-devel] [PATCH 0/3] Add code coverage support for GCC

[Guo, Gua]

From: Gua Guo 

V1: Add coverage option for GCC
V2: Add ReadMe.md for how to generate coverage report
V3: Add VS2019 and GCC code coverage support
V4: Add VS2019 and GCC Azure CI/CD support
V5: Fix some typo and some flow issue

Gua Guo (3):
  UnitTestFrameworkPkg: Add code coverage support for GCC
  BaseTools/Plugin: Add coverage support for Unit Test
  .azurepipelines: Install code coverage tool

 .azurepipelines/Ubuntu-GCC5.yml   |   5 +-
 .azurepipelines/Windows-VS2019.yml|   5 +
 .../templates/pr-gate-build-job.yml   |   2 +
 .azurepipelines/templates/pr-gate-steps.yml   |   5 +
 .../HostBasedUnitTestRunner.py| 119 ++
 UnitTestFrameworkPkg/ReadMe.md|  37 +-
 .../UnitTestFrameworkPkg.ci.yaml  |   2 +
 .../UnitTestFrameworkPkgHost.dsc.inc  |   3 +-
 pip-requirements.txt  |   3 +
 9 files changed, 176 insertions(+), 5 deletions(-)

-- 
2.31.1.windows.1



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回复: [edk2-devel] [PATCH v2] MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer

[gaoliming via groups.io]

Jeff: 
  I have no comments for this change. Acked-by: Liming Gao 


Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io  代表 Jeff Brasen
> via groups.io
> 发送时间: 2022年9月30日 0:20
> 收件人: Ard Biesheuvel ; devel@edk2.groups.io
> 抄送: hao.a...@intel.com; ray...@intel.com; quic_llind...@quicinc.com;
> ardb+tianoc...@kernel.org; jian.j.w...@intel.com; gaoliming
> 
> 主题: Re: [edk2-devel] [PATCH v2]
> MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer
> 
> MdeModulePkg maintainers, Any comments on this?
> 
> > -Original Message-
> > From: Ard Biesheuvel 
> > Sent: Wednesday, September 21, 2022 10:32 AM
> > To: devel@edk2.groups.io; Jeff Brasen 
> > Cc: hao.a...@intel.com; ray...@intel.com; quic_llind...@quicinc.com;
> > ardb+tianoc...@kernel.org
> > Subject: Re: [edk2-devel] [PATCH v2]
> > MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer
> >
> > External email: Use caution opening links or attachments
> >
> >
> > On Wed, 21 Sept 2022 at 18:27, Jeff Brasen via groups.io
> >  wrote:
> > >
> > > Anything else needed to get this merged?
> > >
> >
> > That is up to the MdeModulePkg maintainers.
> >
> > > > -Original Message-
> > > > From: Ard Biesheuvel 
> > > > Sent: Thursday, September 8, 2022 9:55 AM
> > > > To: Jeff Brasen 
> > > > Cc: devel@edk2.groups.io; hao.a...@intel.com; ray...@intel.com;
> > > > quic_llind...@quicinc.com; ardb+tianoc...@kernel.org
> > > > Subject: Re: [edk2-devel] [PATCH v2]
> > > > MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer
> > > >
> > > > External email: Use caution opening links or attachments
> > > >
> > > >
> > > > On Thu, 8 Sept 2022 at 17:39, Jeff Brasen  wrote:
> > > > >
> > > > >
> > > > >
> > > > > > -Original Message-
> > > > > > From: Ard Biesheuvel 
> > > > > > Sent: Monday, August 15, 2022 8:42 AM
> > > > > > To: devel@edk2.groups.io; Jeff Brasen 
> > > > > > Cc: hao.a...@intel.com; ray...@intel.com;
> > > > > > quic_llind...@quicinc.com;
> > > > > > ardb+tianoc...@kernel.org
> > > > > > Subject: Re: [edk2-devel] [PATCH v2]
> > > > > > MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial
> > > > > > FreeBuffer
> > > > > >
> > > > > > External email: Use caution opening links or attachments
> > > > > >
> > > > > >
> > > > > > On Fri, 5 Aug 2022 at 18:56, Jeff Brasen via groups.io
> > > > > >  wrote:
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > > -Original Message-
> > > > > > > > From: Ard Biesheuvel 
> > > > > > > > Sent: Tuesday, August 2, 2022 10:51 AM
> > > > > > > > To: Jeff Brasen 
> > > > > > > > Cc: devel@edk2.groups.io; hao.a...@intel.com;
> > > > > > > > ray...@intel.com; quic_llind...@quicinc.com;
> > > > > > > > ardb+tianoc...@kernel.org
> > > > > > > > Subject: Re: [PATCH v2]
> > MdeModulePkg/NonDiscoverablePciDeviceDxe:
> > > > > > > > Allow partial FreeBuffer
> > > > > > > >
> > > > > > > > External email: Use caution opening links or attachments
> > > > > > > >
> > > > > > > >
> > > > > > > > On Tue, 2 Aug 2022 at 17:32, Jeff Brasen 
> > wrote:
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > > -Original Message-
> > > > > > > > > > From: Ard Biesheuvel 
> > > > > > > > > > Sent: Friday, July 29, 2022 9:48 AM
> > > > > > > > > > To: Jeff Brasen 
> > > > > > > > > > Cc: devel@edk2.groups.io; hao.a...@intel.com;
> > > > > > > > > > ray...@intel.com; quic_llind...@quicinc.com;
> > > > > > > > > > ardb+tianoc...@kernel.org
> > > > > > > > > > Subject: Re: [PATCH v2]
> > > > MdeModulePkg/NonDiscoverablePciDeviceDxe:
> > > > > > > > > > Allow partial FreeBuffer
> > > > > > > > > >
> > > > > > > > > > External email: Use caution opening links or attachments
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > On Thu, 28 Jul 2022 at 13:25, Jeff Brasen
> > > > > > > > > > 
> > > > wrote:
> > > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > Adding Leif/Ard to CC incase they have any comments on
> > this patch.
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > This generally looks ok to me. I just wonder if it
> > > > > > > > > > wouldn't be simpler to reuse the existing allocation
> > > > > > > > > > descriptor if it is not being freed entirely. Given the
> > > > > > > > > > [presumably] the most common case is to allocate and
> > > > > > > > > > then free some pages at the end, lowering the page count
> > > > > > > > > > on the existing descriptor would cover most cases, and
> > > > > > > > > > we'd only need to allocate new ones if pages are being
> > > > > > > > > > freed at the start or in
> > > > > > > > the middle.
> > > > > > > > >
> > > > > > > > > There is often freeing at the beginning as well as this is
> > > > > > > > > being used to create
> > > > > > > > a 64K aligned section of memory in the case. So it over
> > > > > > > > allocates and the free's some at the beginning and the end.
> > > > > > > > I could probably make it detect and use that but figured
> > > > > > > > this code would 

Re: [edk2-devel] [RFC] Adoption of CodeQL in edk2

[Michael D Kinney]

I just want to reiterate.  If there are no concerns or objections raised by Oct 
4, then the
CodeQL static analysis will be phased into use in the edk2 repo and there will 
be code
changes made to address the issues identified by COdeQL and all future code 
changes
after a CodeQL check is enabled will be blocked until the CodeQL CI checks pass.

This will impact all future code changes and all developers will have to learn 
how to
interpret CodeQL reports and fix issues.

Thanks,

Mike

From: devel@edk2.groups.io  On Behalf Of Michael Kubacki
Sent: Thursday, September 29, 2022 5:05 PM
To: Michael Kubacki ; devel@edk2.groups.io
Subject: Re: [edk2-devel] [RFC] Adoption of CodeQL in edk2

If there's any further feedback on this RFC, please respond by Tuesday, October 
4th. We plan to start implementing the changes later in the week.

Thanks,
Michael



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Re: [edk2-devel] The principles of EDK2 module reconstruction for archs

[Chang, Abner via groups.io]

[AMD Official Use Only - General]



> -Original Message-
> From: Sunil V L 
> Sent: Thursday, September 29, 2022 11:22 PM
> To: Chang, Abner 
> Cc: devel@edk2.groups.io; ray...@intel.com; Kinney, Michael D
> ; lichao ; Kirkendall,
> Garrett ; Grimes, Paul
> ; He, Jiangang ; Attar,
> AbdulLateef (Abdul Lateef) ; Leif Lindholm
> ; Andrew Fish 
> Subject: Re: [edk2-devel] The principles of EDK2 module reconstruction for
> archs
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> On Thu, Sep 29, 2022 at 02:54:05PM +, Chang, Abner wrote:
> > [AMD Official Use Only - General]
> >
> > Hi Sunil,
> > One more thing other than the module reconstruction for archs before you
> sending patch to edk2:
> > Not sure how would you do on migrating the RISC-V code from edk2-
> platforms to edk2.  Did you make some other changes to the RISC-V CpuDxe
> on edk2-platform?
> > Please keep the files history and send the patch for the migration first.
> Then have the follow up patches for your changes if any and also add the
> Ventana license.
> >
> > Below branches could be the reference for this migration,
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> > ub.com%2Fchangab%2Fedk2%2Fcommits%2FRISC-V-MIGRATION-EDK2-
> PRdata=
> >
> 05%7C01%7CAbner.Chang%40amd.com%7Cb644f4b61bbd4e096c2308daa22e
> 6703%7C3
> >
> dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C638000617445410044%7C
> Unknown
> >
> %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha
> WwiLCJ
> >
> XVCI6Mn0%3D%7C3000%7C%7C%7Csdata=wRnI%2Br4Dunydf77gSClb
> 6ghHuY24Qs
> > LrZTiPqc7pP1I%3Dreserved=0
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> > ub.com%2Fchangab%2Fedk2-platforms%2Fcommits%2FRISC-V-
> MIGRATION-EDK2-PL
> >
> ATFORMdata=05%7C01%7CAbner.Chang%40amd.com%7Cb644f4b61b
> bd4e096c23
> >
> 08daa22e6703%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63800
> 0617445
> >
> 410044%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2
> luMzIiLCJ
> >
> BTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=5T2PHJOj
> %2Bk6Mmu
> > zNn0vsELm0raYiIDiI1X%2FekgZt6ls%3Dreserved=0
> >
> > Thanks Sunil.
> > Abner
> >
> Thanks Abner. Let me take a look at your branch.
> 
> We have some changes and are not migrating everything from edk2-
> platforms. But I am not sure whether we can maintain the commit history
> when we migrate from a different repo. I think this should be like a new
> review and all old RB tags which were for edk2-platforms need to be
> removed.
I was used tool to cherry pick from different repo to keep the history. Not 
sure if git command line can do this or not.

To treat it as a new file that includes HPE and Ventana copyrights is confusing 
because HPE didn't have the collaboration with Ventana on those source files. I 
think you would have some files that are modified by Ventana regarding the 
functionality and some files without any change; the copyright should be 
applied to the contribution of functionality but not the migration or build 
error fix for the migration. I am fine with having a new review process, 
however, I would suggest below steps for the files from edk2-platform if to 
keep history is difficult.

1. Migrate the code from edk2-platform and fix the build error on edk2. In the 
source file keep HPE copyright only. Mention the origin of the file in the 
commit message. Please do not add Ventana copyright to the source file at this 
moment.
2. Afterward, add Ventana copyright for the further updates. This makes the 
contribution clear.
3. Do not delete the one on edk2-platforms. I think we can mention the 
implementation is obsoleted in the Readme.md under RISC-V PlatformPkg and 
ProcessorPkg.

BTW, I can help on CpuDxe X86 migration.

Thanks
Abner
> 
> For ex:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Fchangab%2Fedk2%2Fcommit%2Feca5ff6bea66be94fd58421ba98c
> b54d1f4181a6data=05%7C01%7CAbner.Chang%40amd.com%7Cb644f4
> b61bbd4e096c2308daa22e6703%7C3dd8961fe4884e608e11a82d994e183d%7C
> 0%7C0%7C638000617445566273%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiM
> C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000
> %7C%7C%7Csdata=2TRD8pySU%2FIhz7ttFwdCHtPpl6JM0YSp%2BZjvo5
> %2FEEZ4%3Dreserved=0
> 
> IMO, RB tag should be removed and should be reviewed fresh when it is
> being added to edk2 repo.
> 
> Thanks
> Sunil


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Re: [edk2-devel] [RFC] Adoption of CodeQL in edk2

[Michael Kubacki]

If there's any further feedback on this RFC, please respond by Tuesday, October 
4th. We plan to start implementing the changes later in the week.

Thanks,
Michael


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[edk2-devel] Updated Event: TianoCore Community Meeting - APAC/NAMO #cal-invite

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[edk2-devel] Updated Event: TianoCore Community Meeting EMEA/NAMO #cal-invite

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 4ed7712e255d%22%2c%22Oid%22%3a%226e4ce4c4-1242-431b-9a51-92cd01a5df3c%22%
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[edk2-devel] [PATCH] DynamicTablesPkg:ACPI: SLIT Generator files

[Name via groups.io]

From: Swatisri Kantamsetti 

Added SLIT Generator and supporting files to
generate SLIT ACPI Table

Signed-off-by: Swatisri Kantamsetti 
---
 DynamicTablesPkg/DynamicTables.dsc.inc|   2 +
 DynamicTablesPkg/Include/AcpiTableGenerator.h |   1 +
 .../Include/ArmNameSpaceObjects.h |  12 +
 .../Arm/AcpiSlitLibArm/AcpiSlitLibArm.inf |  29 ++
 .../Acpi/Arm/AcpiSlitLibArm/SlitGenerator.c   | 326 ++
 MdePkg/Include/IndustryStandard/Slit.h|  39 +++
 6 files changed, 409 insertions(+)
 create mode 100644 
DynamicTablesPkg/Library/Acpi/Arm/AcpiSlitLibArm/AcpiSlitLibArm.inf
 create mode 100644 
DynamicTablesPkg/Library/Acpi/Arm/AcpiSlitLibArm/SlitGenerator.c
 create mode 100644 MdePkg/Include/IndustryStandard/Slit.h

diff --git a/DynamicTablesPkg/DynamicTables.dsc.inc 
b/DynamicTablesPkg/DynamicTables.dsc.inc
index 3d4fa0c4c4..c24fc1d719 100644
--- a/DynamicTablesPkg/DynamicTables.dsc.inc
+++ b/DynamicTablesPkg/DynamicTables.dsc.inc
@@ -31,6 +31,7 @@
   DynamicTablesPkg/Library/Acpi/Arm/AcpiMcfgLibArm/AcpiMcfgLibArm.inf
   DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/AcpiPpttLibArm.inf
   DynamicTablesPkg/Library/Acpi/Arm/AcpiRawLibArm/AcpiRawLibArm.inf
+  DynamicTablesPkg/Library/Acpi/Arm/AcpiSlitLibArm/AcpiSlitLibArm.inf
   DynamicTablesPkg/Library/Acpi/Arm/AcpiSpcrLibArm/AcpiSpcrLibArm.inf
   DynamicTablesPkg/Library/Acpi/Arm/AcpiSratLibArm/AcpiSratLibArm.inf
 
@@ -56,6 +57,7 @@
   NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/AcpiPpttLibArm.inf
   NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiRawLibArm/AcpiRawLibArm.inf
   NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSpcrLibArm/AcpiSpcrLibArm.inf
+  NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSlitLibArm/AcpiSlitLibArm.inf
   NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSratLibArm/AcpiSratLibArm.inf
 
   # AML Fixup
diff --git a/DynamicTablesPkg/Include/AcpiTableGenerator.h 
b/DynamicTablesPkg/Include/AcpiTableGenerator.h
index f962dbff57..82d0272031 100644
--- a/DynamicTablesPkg/Include/AcpiTableGenerator.h
+++ b/DynamicTablesPkg/Include/AcpiTableGenerator.h
@@ -93,6 +93,7 @@ typedef enum StdAcpiTableId {
   EStdAcpiTableIdMcfg,  ///< MCFG Generator
   EStdAcpiTableIdIort,  ///< IORT Generator
   EStdAcpiTableIdPptt,  ///< PPTT Generator
+  EStdAcpiTableIdSlit,  ///< SLIT Generator
   EStdAcpiTableIdSrat,  ///< SRAT Generator
   EStdAcpiTableIdSsdtSerialPort,///< SSDT Serial-Port Generator
   EStdAcpiTableIdSsdtCmn600,///< SSDT Cmn-600 Generator
diff --git a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h 
b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
index c66b441d53..aa3f464132 100644
--- a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
+++ b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
@@ -65,6 +65,7 @@ typedef enum ArmObjectID {
   EArmObjRmr,  ///< 40 - Reserved Memory Range Node
   EArmObjMemoryRangeDescriptor,///< 41 - Memory Range Descriptor
   EArmObjCpcInfo,  ///< 42 - Continuous Performance 
Control Info
+  EArmObjSystemLocalityInfo,   ///< 43 - Relative Distance Info
   EArmObjMax
 } EARM_OBJECT_ID;
 
@@ -1095,6 +1096,17 @@ typedef struct CmArmRmrDescriptor {
 */
 typedef AML_CPC_INFO CM_ARM_CPC_INFO;
 
+/** A structure that describes the System Locality Information
+
+  This information is used to optimize the system performance
+
+  ID: EArmObjSystemLocalityInfo
+*/
+typedef struct CmArmSystemLocalityInfo {
+  UINT64NumSystemLocalities;
+  UINT8 *Distance;
+} CM_ARM_SYSTEM_LOCALITY_INFO;
+
 #pragma pack()
 
 #endif // ARM_NAMESPACE_OBJECTS_H_
diff --git 
a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSlitLibArm/AcpiSlitLibArm.inf 
b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSlitLibArm/AcpiSlitLibArm.inf
new file mode 100644
index 00..ab0ffc9a39
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSlitLibArm/AcpiSlitLibArm.inf
@@ -0,0 +1,29 @@
+## @file
+#  SRAT Table Generator
+#
+#  Copyright (c) 2022, ARM Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+  INF_VERSION= 0x0001001B
+  BASE_NAME  = AcpiSlitLibArm
+  FILE_GUID  = 28e3f485-0c24-4376-8982-8e1febd791bc
+  VERSION_STRING = 1.0
+  MODULE_TYPE= DXE_DRIVER
+  LIBRARY_CLASS  = NULL|DXE_DRIVER
+  CONSTRUCTOR= AcpiSlitLibConstructor
+  DESTRUCTOR = AcpiSlitLibDestructor
+
+[Sources]
+  SlitGenerator.c
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  DynamicTablesPkg/DynamicTablesPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  BaseLib
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSlitLibArm/SlitGenerator.c 
b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSlitLibArm/SlitGenerator.c
new file mode 100644
index 00..1a232ce95c
--- /dev/null
+++ 

[edk2-devel] [PATCH v1 1/1] MiscBootServices: Stall_Func: Reduces the stall interval for Stall_Func

[Robert Wood via groups.io]

The Stall_Func test on the highest TPL causes issues with the disk IO by
blocking interrupts. This blocking can cause disk corruption through IO
timeouts. Since this doesn't seem to be the intent of the test this
revision reduces the stall interval from 10 seconds to 4 and adjusts the
delta tolerance in scale.

Signed-off-by: Robert Wood 

Cc: Samer El-Haj-Mahmoud 
---
 
uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestMain.h
 | 2 +-
 
uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestFunction.c
 | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestMain.h
 
b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestMain.h
index 9e98ec013c74..4f8eaa4c70ea 100644
--- 
a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestMain.h
+++ 
b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestMain.h
@@ -46,7 +46,7 @@ typedef struct _RESET_DATA {
  { 0xA6033499, 0xE4AF, 0x44f5, {0x9D, 0x16, 0x30, 0x78, 0xD8, 0x61, 0x32, 0x28 
}}

 

 #define TPL_ARRAY_SIZE 3

-#define MAX_SECOND_MARGIN 2

+#define MAX_SECOND_MARGIN 1

 

 //

 // Change size from TPL_ARRAY_SIZE to TPL_ARRAY_SIZE + 1

diff --git 
a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestFunction.c
 
b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestFunction.c
index ad72646bada2..f831ed6fbccc 100644
--- 
a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestFunction.c
+++ 
b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestFunction.c
@@ -827,7 +827,7 @@ BBTestStallInterfaceTest (
   StartTime = Epoch;
 OldTpl = gtBS->RaiseTPL (TplArray[Index]);

 Status = gtBS->Stall (

- 1000

+ 400

  );

 gtBS->RestoreTPL (OldTpl);

 if (gtRT->GetTime (, NULL) != EFI_SUCCESS)
-- 
2.38.0.rc1.362.ged0d419d3c-goog



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[edk2-devel] [PATCH v1 0/1] Update Stall_Func interval to avoid IO timeouts

[Robert Wood via groups.io]

These changes contain an adjustment to the duration of the stall command
to avoid disk corruption via IO timeouts.

Robert Wood (1):
  MiscBootServices: Stall_Func: Reduces the stall interval for
Stall_Func

 
uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestMain.h
 | 2 +-
 
uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MiscBootServices/BlackBoxTest/MiscBootServicesBBTestFunction.c
 | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Cc: Samer El-Haj-Mahmoud 

-- 
2.38.0.rc1.362.ged0d419d3c-goog



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[edk2-devel] [PATCH] ShellPkg: Changes to display Type 45 table in smbiosview and improved Type 3 table.

[Kalaivani Palanikumar via groups.io]

Add support in smbiosview command to display Type 45 table. There is a bug in 
Type 3 table which displays SystemEnclosureType as Undefined. As per Smbios 
spec, BIT7 in SMBIOS_TABLE_TYPE3.Type denotes whether chassis lock is present 
or not. But, currently BIT7 considered to display SystemEnclosureType.

Signed-off by: kalaivani P 

cc: Vasudevan S 
cc: Sundaresan S 
cc: Liming Gao 

---
 .../SmbiosView/PrintInfo.c|  28 +++
 .../SmbiosView/PrintInfo.h|  48 +
 .../SmbiosView/QueryTable.c   | 165 +-
 .../SmbiosView/SmbiosViewStrings.uni  |   7 +-
 4 files changed, 246 insertions(+), 2 deletions(-)

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c 
b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
index bf5306205b..2b2a18bdce 100644
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.c
@@ -1274,6 +1274,34 @@ SmbiosPrintStructure (
   DisplayProcessorArchitectureType 
(Struct->Type44->ProcessorSpecificBlock.ProcessorArchType, Option);

   break;



+//

+// Firmware Inventory Information (Type 45)

+//

+case 45:

+{

+UINT16  *AssociatedComponentHandles;

+

+PRINT_PENDING_STRING  (Struct, Type45, FirmwareComponentName);

+PRINT_PENDING_STRING  (Struct, Type45, FirmwareVersion);

+DisplayFirmwareVersionFormat (Struct->Type45->FirmwareVersionFormat, 
Option);

+PRINT_PENDING_STRING  (Struct, Type45, FirmwareId);

+DisplayFirmwareIdFormat (Struct->Type45->FirmwareIdFormat, Option);

+PRINT_PENDING_STRING  (Struct, Type45, ReleaseDate);

+PRINT_PENDING_STRING  (Struct, Type45, Manufacturer);

+PRINT_PENDING_STRING  (Struct, Type45, LowestSupportedVersion);

+PRINT_STRUCT_VALUE_LH (Struct, Type45, ImageSize);

+DisplayFirmwareCharacteristics (*(UINT16 
*)(UINTN)>Type45->Characteristics, Option);

+DisplayFirmwareStateInformation (Struct->Type45->State, Option);

+PRINT_STRUCT_VALUE_H (Struct, Type45, AssociatedComponentCount);

+

+AssociatedComponentHandles = (UINT16 *)((UINTN)Struct->Type45 + 
sizeof(SMBIOS_TABLE_TYPE45));

+for (Index = 0; Index < Struct->Type45->AssociatedComponentCount; 
Index++) {

+ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN 
(STR_SMBIOSVIEW_PRINTINFO_FW_INVENTORY_HANDLE), gShellDebug1HiiHandle, Index + 
1, AssociatedComponentHandles[Index]);

+}

+

+break;

+}

+

 //

 // Inactive (Type 126)

 //

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.h 
b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.h
index 8ecec693ad..43dbfcb94f 100644
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.h
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.h
@@ -3,6 +3,7 @@


   Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved.

   (C) Copyright 2017 - 2019 Hewlett Packard Enterprise Development LP

+  Copyright (c) 1985 - 2022, American Megatrends International LLC.

   SPDX-License-Identifier: BSD-2-Clause-Patent



 **/

@@ -439,4 +440,51 @@ DisplayProcessorArchitectureType (
   IN UINT8  Option

   );



+/**

+  Display Firmware Version Format (Type 45).

+

+  @param[in] KeyThe key of the structure.

+  @param[in] Option The optional information.

+**/

+VOID

+DisplayFirmwareVersionFormat (

+  IN UINT8  Key,

+  IN UINT8  Option

+  );

+

+/**

+  Display Firmware ID Format (Type 45)

+

+  @param[in] KeyThe key of the structure.

+  @param[in] Option The optional information.

+**/

+VOID

+DisplayFirmwareIdFormat (

+  IN UINT8  Key,

+  IN UINT8  Option

+  );

+

+/**

+  Display Firmware State Information (Type 45)

+

+  @param[in] KeyThe key of the structure.

+  @param[in] Option The optional information.

+**/

+VOID

+DisplayFirmwareStateInformation (

+  IN UINT8  Key,

+  IN UINT8  Option

+  );

+

+/**

+  Display Firmware Inventory Characteristics (Type 45)

+

+  @param[in] KeyThe key of the structure.

+  @param[in] Option The optional information.

+**/

+VOID

+DisplayFirmwareCharacteristics (

+  IN UINT16  Key,

+  IN UINT8   Option

+  );

 #endif

diff --git 
a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/QueryTable.c 
b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/QueryTable.c
index 2e62ae3a34..06b24b55cd 100644
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/QueryTable.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/QueryTable.c
@@ -4,6 +4,7 @@


   Copyright (c) 2005 - 2021, Intel Corporation. All rights reserved.

   (C) Copyright 2016-2019 Hewlett Packard Enterprise Development LP

+  Copyright (c) 1985 - 2022, American Megatrends 

[edk2-devel] [PATCH 1/1] MdeModulePkg: Handle InitialVFs=0 case for SR-IOV

[Foster Nong]

Per the section 3.3.5 SR-IOV spec v1.1, InitialVFs (0ch).
InitialVFs indicates to SR-PCIM the number of VFs that are initially associated 
with the PF.
The minimum value of InitialVFs is 0.

Below code is used to calculate SR-IOV reserved bus number,
if InitialVFs =0, it maybe calculate the wrong bus number in this case.
  LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride

we can fix it with below code:
 if (PciIoDevice->InitialVFs == 0) {
 PciIoDevice->ReservedBusNum = 0;
} else {
PFRid  = EFI_PCI_RID (Bus, Device, Func);
 LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
//
// Calculate ReservedBusNum for this PF
//
PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
//
 // Calculate ReservedBusNum for this PF
//
 PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
}

https://bugzilla.tianocore.org/show_bug.cgi?id=4069

Signed-off-by: Foster Nong 
---
 .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index 509f828b621d..eb250f6f7b62 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -2416,13 +2416,17 @@ CreatePciIoDevice (
   //
   // Calculate LastVF
   //
-  PFRid  = EFI_PCI_RID (Bus, Device, Func);
-  LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * 
VFStride;
+  if (PciIoDevice->InitialVFs == 0) {
+PciIoDevice->ReservedBusNum = 0;
+  } else {
+PFRid  = EFI_PCI_RID (Bus, Device, Func);
+LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * 
VFStride;
 
-  //
-  // Calculate ReservedBusNum for this PF
-  //
-  PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus 
+ 1);
+//
+// Calculate ReservedBusNum for this PF
+//
+PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - 
Bus + 1);
+  }
 
   DEBUG ((
 DEBUG_INFO,
-- 
2.37.1.windows.1



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Re: [edk2-devel] The principles of EDK2 module reconstruction for archs

[Attar, AbdulLateef (Abdul Lateef) via groups.io]

Hi Abner,
Looks good to me.
Reviewed-by:  Abdul Lateef Attar 

Thanks
AbduL

-Original Message-
From: Chang, Abner  
Sent: 28 September 2022 20:31
To: Sunil V L ; devel@edk2.groups.io; ray...@intel.com
Cc: Kinney, Michael D ; lichao 
; Kirkendall, Garrett ; Grimes, 
Paul ; He, Jiangang ; Attar, 
AbdulLateef (Abdul Lateef) ; Leif Lindholm 
; Andrew Fish 
Subject: RE: [edk2-devel] The principles of EDK2 module reconstruction for archs

[AMD Official Use Only - General]

I just had created PR to update edkII C coding standard spec for the file and 
directory naming. We can review and confirm this update first and then go back 
to the principles of EDK2 module reconstruction for archs.
Here is the PR:
https://github.com/tianocore-docs/edk2-CCodingStandardsSpecification/pull/2

The naming rule is mainly for the new module or new file IMO. Some existing 
module may not meet the guidelines mentioned in this spec. Thus we need the 
principles of EDK2 module reconstruction on the existing module to support 
other processor archs and not impacting the existing platforms (e.g. rename the 
INF file or directory to meet the guidelines).

Sunil, seems RISC-V CpuDxe meet the guideline. Please check it.
Just feel that having  CpuDxe.c to Riscv64 folder is not quite a best solution. 
I think at least we can abstract the protocol structure and protocol 
installation under CpuDxe\ and have the arch implementation under arch folder. 
We can discuss this later after we confirming the guideline and principles.

Thanks
Abner

> -Original Message-
> From: Sunil V L 
> Sent: Wednesday, September 28, 2022 3:34 PM
> To: devel@edk2.groups.io; ray...@intel.com
> Cc: Chang, Abner ; Kinney, Michael D 
> ; lichao ; Kirkendall, 
> Garrett ; Grimes, Paul 
> ; He, Jiangang ; Attar, 
> AbdulLateef (Abdul Lateef) ; Leif Lindholm 
> ; Andrew Fish 
> Subject: Re: [edk2-devel] The principles of EDK2 module reconstruction 
> for archs
> 
> Caution: This message originated from an External Source. Use proper 
> caution when opening attachments, clicking links, or responding.
> 
> 
> On Wed, Sep 28, 2022 at 03:33:45AM +, Ni, Ray wrote:
> Hi Ray,
> >
> >   1.  When a new arch's implementation is introduced to the existing
> module which was developed for the specific arch:
> >
> >   1.  The folder reconstruction:
> >
> >   *   Create arch folder for the existing arch implementation
> > [Ray] Do you move existing arch implementation to that arch folder? 
> > It will
> break existing platforms a lot.
> >
> >   *   Create the arch folder for the new introduced arch
> > [Ray] I agree. But if we don't create arch folder for existing arch
> implementation, the pkg layout will be a mess.
> >
> > [Ray] Hard for me to understand all the principles here. Maybe we 
> > review
> existing code including to-be-upstreamed code and decide how to go.
> >
> 
> Could you please take a look below changes which is trying to add 
> RISC-V support for CpuDxe?
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Ftianocore%2Fedk2-
> staging%2Fcommit%2Fbba1a11be47dd091734e185afbed73ea75708749
> data=05%7C01%7Cabner.chang%40amd.com%7Ca419e6a010d34fde464b08d
> aa123e080%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63799947
> 2732494527%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIj
> oiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csd
> ata=Vq6pJLnn8yJrJhFZn7LfLbZzrtpG4n1VLWgAil6J38U%3Dreserved=0
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Ftianocore%2Fedk2-
> staging%2Fcommit%2F7fccf92a97a6d0618a20f1060e78b3687906da
> ta=05%7C01%7Cabner.chang%40amd.com%7Ca419e6a010d34fde464b08daa1
> 23e080%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63799947273
> 2494527%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV
> 2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata
> =xFmvUv58vh4AUAM17Qy9G5jZWFZlK2Ozt3njpG1e8%2BY%3Dreserv
> ed=0
> 
> What do you suggest with above example?
> 
> 1) Common INF for all architectures - but modify INF alone, no X86 
> folder creation.
> 
> This is what I have done in the commit above. May be of least impact 
> to existing code since it is only INF change. But like you mentioned 
> this is bit weird that X86 files will remain in root folder directly 
> along with some common files.
> 
> 2) Common INF (CpuDxe.inf) + create arch folders X86, X64, IA32, 
> RiscV64 etc
> 
> IMO, this is probably the best approach. What would be the challenges 
> with this?
> 
> 3) Separate INF for arch like CpuDxe.inf for x86, CpuDxeRiscV64.inf for 
> RISC-V.
> 
> This again probably is not a good idea.
> 
> 4) If the module/library is specific to one arch (ex: SMM(X86), 
> SBI(RISC-V)), then create separate INF.
> 
> Thanks!
> Sunil


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[edk2-devel] [edk2-platforms PATCH 0/2] Platform/RaspberryPi: SyncPcie() fixes

[Adrien Thierry]

This patch series does a few fixes in the SyncPcie() function, more
specifically in the logic that deletes the pci node to prevent Linux from
resetting the XHCI controller.

Adrien Thierry (2):
  Platform/RaspberryPi: fix pci DT node address in SyncPcie()
  Platform/RaspberryPi: delete usb node instead of pci in SyncPcie()

 Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)


base-commit: e55f0527dde48a5f139c1b8f35acc4e6b59dd794
-- 
2.37.3



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[edk2-devel] [edk2-platforms PATCH 2/2] Platform/RaspberryPi: delete usb node instead of pci in SyncPcie()

[Adrien Thierry]

In SyncPcie(), the pci node is removed from the device tree to make sure
the XHCI controller is not reset by Linux in DT mode. However, we should
only remove the usb child node and not the whole pci node. Removing the
whole pci node prevents Linux to bypass XHCI handoff for the Raspberry
Pi 4 [1]. Moreover, removing the usb node seems to have been the
original intent according to the error messages shown if the node is not
detected.

[1] 
https://elixir.bootlin.com/linux/latest/source/drivers/usb/host/pci-quirks.c#L1258

Fixes: efff29cdcdb7 ("Platform/RaspberryPi: Always use non translating DMA in 
DT mode")
Signed-off-by: Adrien Thierry 
---
 Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c 
b/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c
index 55c9d185fc..26334e50b8 100644
--- a/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c
+++ b/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c
@@ -388,7 +388,7 @@ SyncPcie (
* triggering the mailbox by removing the node.
*/
 
-  Node = fdt_path_offset (mFdtImage, "/scb/pcie@7d50/pci@0,0");
+  Node = fdt_path_offset (mFdtImage, "/scb/pcie@7d50/pci@0,0/usb@0,0");
   if (Node < 0) {
 // This can happen on CM4/etc which doesn't have an onboard XHCI
 DEBUG ((DEBUG_INFO, "%a: failed to locate 
/scb/pcie@7d50/pci@0/usb@0\n", __FUNCTION__));
-- 
2.37.3



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[edk2-devel] [edk2-platforms PATCH 1/2] Platform/RaspberryPi: fix pci DT node address in SyncPcie()

[Adrien Thierry]

To make sure the XHCI controller does not get reset by Linux in DT mode,
we remove its pci parent node from the device tree. However, the pci
node address has been updated in the Raspberry Pi 4 device tree [1] and
no longer matches the one we are trying to remove in SyncPcie(). This
results in the XHCI controller actually being reset by Linux, which
leads to errors during USB initialization:

[3.563963] xhci_hcd :01:00.0: xHCI Host Controller
[3.569538] xhci_hcd :01:00.0: new USB bus registered, assigned bus 
number 1
[3.577452] xhci_hcd :01:00.0: hcc params 0x002841eb hci version 0x100 
quirks 0x04000890
[3.587725] xhci_hcd :01:00.0: xHCI Host Controller
[3.593115] xhci_hcd :01:00.0: new USB bus registered, assigned bus 
number 2
[3.600693] xhci_hcd :01:00.0: Host supports USB 3.0 SuperSpeed
[3.608106] hub 1-0:1.0: USB hub found
[3.612026] hub 1-0:1.0: 1 port detected
[3.616819] hub 2-0:1.0: USB hub found
[3.620726] hub 2-0:1.0: 4 ports detected
[3.875902] usb 1-1: new high-speed USB device number 2 using xhci_hcd
[4.008123] usb 1-1: device descriptor read/64, error -71
[4.256088] usb 1-1: device descriptor read/64, error -71
[4.495882] usb 1-1: new high-speed USB device number 3 using xhci_hcd
[4.628111] usb 1-1: device descriptor read/64, error -71
[4.872083] usb 1-1: device descriptor read/64, error -71
[5.407888] usb 1-1: new high-speed USB device number 4 using xhci_hcd
[6.023964] xhci_hcd :01:00.0: Setup ERROR: setup address command for 
slot 1.
[6.239977] xhci_hcd :01:00.0: Setup ERROR: setup address command for 
slot 1.

This patch updates the pci node address (and usb node address in the
error messages) to match those found in the RPi4 device tree.

[1] https://lore.kernel.org/all/20210831125843.1233488-1-nsaen...@redhat.com/

Fixes: efff29cdcdb7 ("Platform/RaspberryPi: Always use non translating DMA in 
DT mode")
Signed-off-by: Adrien Thierry 
---
 Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c 
b/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c
index e72d132b18..55c9d185fc 100644
--- a/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c
+++ b/Platform/RaspberryPi/Drivers/FdtDxe/FdtDxe.c
@@ -388,14 +388,14 @@ SyncPcie (
* triggering the mailbox by removing the node.
*/
 
-  Node = fdt_path_offset (mFdtImage, "/scb/pcie@7d50/pci@1,0");
+  Node = fdt_path_offset (mFdtImage, "/scb/pcie@7d50/pci@0,0");
   if (Node < 0) {
 // This can happen on CM4/etc which doesn't have an onboard XHCI
-DEBUG ((DEBUG_INFO, "%a: failed to locate 
/scb/pcie@7d50/pci@1/usb@1\n", __FUNCTION__));
+DEBUG ((DEBUG_INFO, "%a: failed to locate 
/scb/pcie@7d50/pci@0/usb@0\n", __FUNCTION__));
   } else {
 Retval = fdt_del_node (mFdtImage, Node);
 if (Retval != 0) {
-  DEBUG ((DEBUG_ERROR, "Failed to remove 
/scb/pcie@7d50/pci@1/usb@1\n"));
+  DEBUG ((DEBUG_ERROR, "Failed to remove 
/scb/pcie@7d50/pci@0/usb@0\n"));
   return EFI_NOT_FOUND;
 }
   }
-- 
2.37.3



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Re: [edk2-devel] [PATCH v4 3/6] OvmfPkg: set PcdEnableUnacceptedMemory to FALSE

[Dionna Glaze via groups.io]

> Generally, we tend to rely on the DEC default for new PCDs if we're
> not deviating from it.
> If there is no specific reason to deviate from this here, I think we
> can drop this patch.
>
> Or is this also needed to declare them as the right type? In that
> case, I think you can drop the hunks that touch non-CC platforms.
>

I probably did something wrong. Without this patch, the protocol patch
with PcdSetBoolS fails to build.

INFO - In file included from
/usr/local/google/home/dionnaglaze/gitrepos/edk2/Build/OvmfX64/DEBUG_GCC5/X64/MdeModulePkg/Core/Dxe/DxeMain/DEBUG/AutoGen.h:17,
INFO -  from :
INFO - 
/usr/local/google/home/dionnaglaze/gitrepos/edk2/MdeModulePkg/Core/Dxe/Mem/Page.c:
In function ‘CoreEnableUnacceptedMemory’:
INFO - 
/usr/local/google/home/dionnaglaze/gitrepos/edk2/MdePkg/Include/Library/PcdLib.h:549:40:
error: implicit declaration of function
‘_PCD_SET_MODE_BOOL_S_PcdAcceptAllUnacceptedMemory’
[-Werror=implicit-function-declaration]
INFO -   549 | #define PcdSetBoolS(TokenName, Value)
_PCD_SET_MODE_BOOL_S_##TokenName((Value))
INFO -   |^
INFO - 
/usr/local/google/home/dionnaglaze/gitrepos/edk2/MdeModulePkg/Core/Dxe/Mem/Page.c:2232:10:
note: in expansion of macro ‘PcdSetBoolS’
INFO -  2232 |   return PcdSetBoolS(PcdAcceptAllUnacceptedMemory, FALSE);
INFO -   |  ^~~
INFO - cc1: all warnings being treated as errors
INFO - make: *** [GNUmakefile:452:
/usr/local/google/home/dionnaglaze/gitrepos/edk2/Build/OvmfX64/DEBUG_GCC5/X64/MdeModulePkg/Core/Dxe/DxeMain/OUTPUT/Mem/Page.obj]
Error 1
INFO -

What's the right way to do this?

-- 
-Dionna Glaze, PhD (she/her)


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Re: [edk2-devel] [PATCH 1/2] ArmPkg: implement EFI_MP_SERVICES_PROTOCOL based on PSCI calls

[Kun Qin]

Hi Rebecca,

Thanks for sending this patch. I have a few questions inline "[KQ]". 
Could you please help me to

understand the patch better? Thanks in advance.

Regards,
Kun

On 8/29/2022 8:59 AM, Rebecca Cran wrote:

Add support for EFI_MP_SERVICES_PROTOCOL during the DXE phase under
AArch64.

PSCI_CPU_ON is called to power on the core, the supplied procedure is
executed and PSCI_CPU_OFF is called to power off the core.

Fixes contributed by Ard Biesheuvel.

Signed-off-by: Rebecca Cran 
---
  ArmPkg/ArmPkg.dsc|1 +
  ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf |   55 +
  ArmPkg/Drivers/ArmPsciMpServicesDxe/MpServicesInternal.h |  351 
  ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.c   | 1774 

  ArmPkg/Drivers/ArmPsciMpServicesDxe/MpFuncs.S|   57 +
  5 files changed, 2238 insertions(+)

diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
index 59fd8f295d4f..4716789402fc 100644
--- a/ArmPkg/ArmPkg.dsc
+++ b/ArmPkg/ArmPkg.dsc
@@ -125,6 +125,7 @@ [Components.common]
ArmPkg/Drivers/CpuPei/CpuPei.inf
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+  ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
  
diff --git a/ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf b/ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf

new file mode 100644
index ..2b109c72e0a0
--- /dev/null
+++ b/ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf
@@ -0,0 +1,55 @@
+## @file
+#  ARM MP services protocol driver
+#
+#  Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 1.27
+  BASE_NAME  = ArmPsciMpServicesDxe
+  FILE_GUID  = 007ab472-dc4a-4df8-a5c2-abb4a327278c
+  MODULE_TYPE= DXE_DRIVER
+  VERSION_STRING = 1.0
+
+  ENTRY_POINT= ArmPsciMpServicesDxeInitialize
+
+[Sources.Common]
+  ArmPsciMpServicesDxe.c
+  MpFuncs.S
+  MpServicesInternal.h
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+  ArmLib
+  ArmMmuLib
+  ArmSmcLib
+  BaseMemoryLib
+  CacheMaintenanceLib
+  DebugLib
+  HobLib
+  MemoryAllocationLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Protocols]
+  gEfiMpServiceProtocolGuid## PRODUCES
+  gEfiLoadedImageProtocolGuid  ## CONSUMES
+
+[Guids]
+  gArmMpCoreInfoGuid
+
+[Depex]
+  TRUE
+
+[BuildOptions]
+  GCC:*_*_*_CC_FLAGS = -mstrict-align
diff --git a/ArmPkg/Drivers/ArmPsciMpServicesDxe/MpServicesInternal.h 
b/ArmPkg/Drivers/ArmPsciMpServicesDxe/MpServicesInternal.h
new file mode 100644
index ..ee13816ef64c
--- /dev/null
+++ b/ArmPkg/Drivers/ArmPsciMpServicesDxe/MpServicesInternal.h
@@ -0,0 +1,351 @@
+/** @file
+
+Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+Portions copyright (c) 2011, Apple Inc. All rights reserved.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MP_SERVICES_INTERNAL_H_
+#define MP_SERVICES_INTERNAL_H_
+
+#include 
+#include 
+
+#include 
+#include 
+
+#define AP_STACK_SIZE  0x1000
+
+//
+// Internal Data Structures
+//
+
+//
+// AP state
+//
+// The state transitions for an AP when it process a procedure are:
+//  Idle > Ready > Busy > Idle
+//   [BSP]   [AP]   [AP]
+//
+typedef enum {
+  CpuStateIdle,
+  CpuStateReady,
+  CpuStateBlocked,
+  CpuStateBusy,
+  CpuStateFinished,
+  CpuStateDisabled
+} CPU_STATE;
+
+//
+// Define Individual Processor Data block.
+//
+typedef struct {
+  EFI_PROCESSOR_INFORMATIONInfo;
+  EFI_AP_PROCEDURE Procedure;
+  VOID *Parameter;
+  CPU_STATEState;
+  EFI_EVENTCheckThisAPEvent;
+  UINTNTimeout;
+  UINTNTimeTaken;
+  VOID *Ttbr0;
+  UINTNTcr;
+  UINTNMair;
+} CPU_AP_DATA;
+
+//
+// Define MP data block which consumes individual processor block.
+//
+typedef struct {
+  UINTN   NumberOfProcessors;
+  UINTN   NumberOfEnabledProcessors;
+  EFI_EVENT   CheckAllAPsEvent;
+  EFI_EVENT   WaitEvent;
+  UINTN   FinishCount;
+  UINTN   StartCount;
+  EFI_AP_PROCEDUREProcedure;
+  VOID*ProcedureArgument;
+  BOOLEAN SingleThread;
+  UINTN   StartedNumber;
+  CPU_AP_DATA *CpuData;
+  UINTN   Timeout;
+  UINTN   

Re: [edk2-devel] [PATCH v4 2/6] MdeModulePkg: Add PcdEnableUnacceptedMemory

[Dionna Glaze via groups.io]

> The name PcdEnableUnacceptedMemory is a bit confusing imho. Could we
> rename this to PcdAcceptAllUnacceptedMemory or something like that?
>

Will do. Is the protocol name EnableUnacceptedMemory still acceptable
now that it's setting an AcceptAllUnacceptedMemory value to FALSE?

-- 
-Dionna Glaze, PhD (she/her)


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Re: [edk2-devel] [PATCH v4 4/6] MdeModulePkg: DxeMain accepts all memory at EBS if needed

[Dionna Glaze via groups.io]

>
> Can you explain a bit more why this PCD is needed?
>

I'll expand the comment further, but essentially we need a bit in the
firmware to persist from a call into a protocol to the eventual call
to ExitBootServices. If we needed offline persistence, then we'd need
to standardize a new bit in the OsIndications variable. We don't so we
make due with a Pcd.


>
> I am not following the logic here 100%. As far as I can tell, if
> accepting all memory succeeded without errors, ExitBootServices()
> returns with EFI_SUCCESS, even though it has modified the memory map.
> This means the actual memory map is out of sync with the last
> GetMemoryMap() call performed by the OS loader before it called
> ExitBootServices(), and so it will still contain unaccepted memory,
> right?

Ah yes you're right, I missed that part. I'll change it to return
EFI_WARN_STALE_DATA if any memory region gets accepted, and force a
failure in DxeMain if the status is an error or that warning.

-- 
-Dionna Glaze, PhD (she/her)


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Re: [edk2-devel] [PATCH v5 09/21] MdePkg/BaseRngLib: Rename ArmReadIdIsar0() to ArmGetFeatRng()

[Leif Lindholm]

On 2022-09-29 09:21, Pierre Gondois wrote:



On 9/28/22 19:10, Leif Lindholm wrote:

On 2022-09-19 12:21, pierre.gond...@arm.com wrote:

From: Pierre Gondois 

The MdePkg must be self contained and not have external dependencies.
ArmReadIdIsar0() is defined in MdePkg/Library/BaseRngLib and is
limited to the scope of this library.

  >

The same function will be required to check the FEAT_AES and FEAT_RNG
extensions in other libraries. As this function is Arm specific, it
cannot be added to a library interface in MdePkg. It should be part of
ArmPkg/ArmLib.


Ultimately, ArmPkg has no justification for existing. It is a legacy of
ARM support being added as a prototype, bolted onto the side of the rest
of EDK2. Over time, it needs to be integrated into MdePkg, UefiCpuPkg,
and possibly MdeModulePkg.

It makes sense to break the ID_ISAR0 read out into a separate library,
but we're not making the world a better place if we then hide random
direct-asm-accesses in various libraries. There are similar things in
other architectures - i.e. CPUID.

But I don't like this patch. I'd prefer to keep this code as-is until
the separate library has been added - in MdePkg - and we can switch
straight to that.


Ok, it is also possible to use RngGetBytes() to enable the 
PcdCpuRngSupportedAlgorithm,

so I'll do that and drop:
- ArmPkg/ArmLib: Add ArmHasRngExt()
- ArmPkg/ArmLib: Add ArmReadIdIsar0() helper


That works for me - thanks!

Just to understand how the ArmPkg should ideally be melded in other 
packages,
if I actually needed to add ArmReadIdIsar0() to library should it belong 
for instance

to:
   MdePkg/Include/Library/BaseLib.h
as some of the functions there allow to read intel extensions ?


I think it would make sense to create a separate ArchitectureFeatureLib 
(or somesuch) and move the x86 extension detection bits into that as 
well. But then I'm not an MdePkg maintainer. :)


Regards,

Leif


Regards,
Pierre



/
  Leif


To avoid having mutiple definitions/prototypes of ArmReadIdIsar0(),
and as BaseRngLib only requires to check the RNG capability bits,
rename the MdePkg/Library/BaseRngLib implementation to ArmGetFeatRng().

Signed-off-by: Pierre Gondois 
---
   .../AArch64/{ArmReadIdIsar0.S => ArmGetFeatRng.S} | 8 

   .../AArch64/{ArmReadIdIsar0.asm => ArmGetFeatRng.asm} | 8 


   MdePkg/Library/BaseRngLib/AArch64/ArmRng.h    | 2 +-
   MdePkg/Library/BaseRngLib/AArch64/Rndr.c  | 2 +-
   MdePkg/Library/BaseRngLib/BaseRngLib.inf  | 4 ++--
   5 files changed, 12 insertions(+), 12 deletions(-)
   rename MdePkg/Library/BaseRngLib/AArch64/{ArmReadIdIsar0.S => 
ArmGetFeatRng.S} (78%)
   rename MdePkg/Library/BaseRngLib/AArch64/{ArmReadIdIsar0.asm => 
ArmGetFeatRng.asm} (81%)


diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S 
b/MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.S

similarity index 78%
rename from MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S
rename to MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.S
index 82a00d362212..c42d60513077 100644
--- a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.S
@@ -1,6 +1,6 @@
   
#-- 


   #
-# ArmReadIdIsar0() for AArch64
+# ArmGetFeatRng() for AArch64
   #
   # Copyright (c) 2021, NUVIA Inc. All rights reserved.
   #
@@ -10,7 +10,7 @@
   .text
   .p2align 2
-GCC_ASM_EXPORT(ArmReadIdIsar0)
+GCC_ASM_EXPORT(ArmGetFeatRng)
   #/**
   #  Reads the ID_AA64ISAR0 Register.
@@ -20,11 +20,11 @@ GCC_ASM_EXPORT(ArmReadIdIsar0)
   #**/
   #UINT64
   #EFIAPI
-#ArmReadIdIsar0 (
+#ArmGetFeatRng (
   #  VOID
   #  );
   #
-ASM_PFX(ArmReadIdIsar0):
+ASM_PFX(ArmGetFeatRng):
 mrs  x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register
 ret
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm 
b/MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.asm

similarity index 81%
rename from MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm
rename to MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.asm
index 1d9f9a808c0c..947adfcd2749 100644
--- a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.asm
@@ -1,6 +1,6 @@
   
;-- 


   ;
-; ArmReadIdIsar0() for AArch64
+; ArmGetFeatRng() for AArch64
   ;
   ; Copyright (c) 2021, NUVIA Inc. All rights reserved.
   ;
@@ -8,7 +8,7 @@
   ;
   
;-- 


-  EXPORT ArmReadIdIsar0
+  EXPORT ArmGetFeatRng
 AREA BaseLib_LowLevel, CODE, READONLY
   ;/**
@@ -19,11 +19,11 @@
   ;**/
   ;UINT64
   ;EFIAPI
-;ArmReadIdIsar0 (
+;ArmGetFeatRng (
   ;  VOID
   ;  );
   ;
-ArmReadIdIsar0
+ArmGetFeatRng
 mrs  x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register
 ret
diff --git 

Re: [edk2-devel] [PATCH v5 09/21] MdePkg/BaseRngLib: Rename ArmReadIdIsar0() to ArmGetFeatRng()

[PierreGondois]

On 9/28/22 19:10, Leif Lindholm wrote:

On 2022-09-19 12:21, pierre.gond...@arm.com wrote:

From: Pierre Gondois 

The MdePkg must be self contained and not have external dependencies.
ArmReadIdIsar0() is defined in MdePkg/Library/BaseRngLib and is
limited to the scope of this library.

  >

The same function will be required to check the FEAT_AES and FEAT_RNG
extensions in other libraries. As this function is Arm specific, it
cannot be added to a library interface in MdePkg. It should be part of
ArmPkg/ArmLib.


Ultimately, ArmPkg has no justification for existing. It is a legacy of
ARM support being added as a prototype, bolted onto the side of the rest
of EDK2. Over time, it needs to be integrated into MdePkg, UefiCpuPkg,
and possibly MdeModulePkg.

It makes sense to break the ID_ISAR0 read out into a separate library,
but we're not making the world a better place if we then hide random
direct-asm-accesses in various libraries. There are similar things in
other architectures - i.e. CPUID.

But I don't like this patch. I'd prefer to keep this code as-is until
the separate library has been added - in MdePkg - and we can switch
straight to that.


Ok, it is also possible to use RngGetBytes() to enable the 
PcdCpuRngSupportedAlgorithm,
so I'll do that and drop:
- ArmPkg/ArmLib: Add ArmHasRngExt()
- ArmPkg/ArmLib: Add ArmReadIdIsar0() helper

Just to understand how the ArmPkg should ideally be melded in other packages,
if I actually needed to add ArmReadIdIsar0() to library should it belong for 
instance
to:
  MdePkg/Include/Library/BaseLib.h
as some of the functions there allow to read intel extensions ?

Regards,
Pierre



/
  Leif


To avoid having mutiple definitions/prototypes of ArmReadIdIsar0(),
and as BaseRngLib only requires to check the RNG capability bits,
rename the MdePkg/Library/BaseRngLib implementation to ArmGetFeatRng().

Signed-off-by: Pierre Gondois 
---
   .../AArch64/{ArmReadIdIsar0.S => ArmGetFeatRng.S} | 8 
   .../AArch64/{ArmReadIdIsar0.asm => ArmGetFeatRng.asm} | 8 
   MdePkg/Library/BaseRngLib/AArch64/ArmRng.h| 2 +-
   MdePkg/Library/BaseRngLib/AArch64/Rndr.c  | 2 +-
   MdePkg/Library/BaseRngLib/BaseRngLib.inf  | 4 ++--
   5 files changed, 12 insertions(+), 12 deletions(-)
   rename MdePkg/Library/BaseRngLib/AArch64/{ArmReadIdIsar0.S => 
ArmGetFeatRng.S} (78%)
   rename MdePkg/Library/BaseRngLib/AArch64/{ArmReadIdIsar0.asm => 
ArmGetFeatRng.asm} (81%)

diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S 
b/MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.S
similarity index 78%
rename from MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S
rename to MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.S
index 82a00d362212..c42d60513077 100644
--- a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.S
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.S
@@ -1,6 +1,6 @@
   
#--
   #
-# ArmReadIdIsar0() for AArch64
+# ArmGetFeatRng() for AArch64
   #
   # Copyright (c) 2021, NUVIA Inc. All rights reserved.
   #
@@ -10,7 +10,7 @@
   
   .text

   .p2align 2
-GCC_ASM_EXPORT(ArmReadIdIsar0)
+GCC_ASM_EXPORT(ArmGetFeatRng)
   
   #/**

   #  Reads the ID_AA64ISAR0 Register.
@@ -20,11 +20,11 @@ GCC_ASM_EXPORT(ArmReadIdIsar0)
   #**/
   #UINT64
   #EFIAPI
-#ArmReadIdIsar0 (
+#ArmGetFeatRng (
   #  VOID
   #  );
   #
-ASM_PFX(ArmReadIdIsar0):
+ASM_PFX(ArmGetFeatRng):
 mrs  x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register
 ret
   
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm b/MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.asm

similarity index 81%
rename from MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm
rename to MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.asm
index 1d9f9a808c0c..947adfcd2749 100644
--- a/MdePkg/Library/BaseRngLib/AArch64/ArmReadIdIsar0.asm
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmGetFeatRng.asm
@@ -1,6 +1,6 @@
   
;--
   ;
-; ArmReadIdIsar0() for AArch64
+; ArmGetFeatRng() for AArch64
   ;
   ; Copyright (c) 2021, NUVIA Inc. All rights reserved.
   ;
@@ -8,7 +8,7 @@
   ;
   
;--
   
-  EXPORT ArmReadIdIsar0

+  EXPORT ArmGetFeatRng
 AREA BaseLib_LowLevel, CODE, READONLY
   
   ;/**

@@ -19,11 +19,11 @@
   ;**/
   ;UINT64
   ;EFIAPI
-;ArmReadIdIsar0 (
+;ArmGetFeatRng (
   ;  VOID
   ;  );
   ;
-ArmReadIdIsar0
+ArmGetFeatRng
 mrs  x0, id_aa64isar0_el1 // Read ID_AA64ISAR0 Register
 ret
   
diff --git a/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h

index 2d6ef48ab941..b35cba3c063a 100644
--- a/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h
+++ b/MdePkg/Library/BaseRngLib/AArch64/ArmRng.h
@@ -35,7 +35,7 @@ ArmRndr (
   **/
   UINT64
   EFIAPI
-ArmReadIdIsar0 (

Re: [edk2-devel] [PATCH v2] MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer

[Jeff Brasen via groups.io]

MdeModulePkg maintainers, Any comments on this?

> -Original Message-
> From: Ard Biesheuvel 
> Sent: Wednesday, September 21, 2022 10:32 AM
> To: devel@edk2.groups.io; Jeff Brasen 
> Cc: hao.a...@intel.com; ray...@intel.com; quic_llind...@quicinc.com;
> ardb+tianoc...@kernel.org
> Subject: Re: [edk2-devel] [PATCH v2]
> MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer
> 
> External email: Use caution opening links or attachments
> 
> 
> On Wed, 21 Sept 2022 at 18:27, Jeff Brasen via groups.io
>  wrote:
> >
> > Anything else needed to get this merged?
> >
> 
> That is up to the MdeModulePkg maintainers.
> 
> > > -Original Message-
> > > From: Ard Biesheuvel 
> > > Sent: Thursday, September 8, 2022 9:55 AM
> > > To: Jeff Brasen 
> > > Cc: devel@edk2.groups.io; hao.a...@intel.com; ray...@intel.com;
> > > quic_llind...@quicinc.com; ardb+tianoc...@kernel.org
> > > Subject: Re: [edk2-devel] [PATCH v2]
> > > MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial FreeBuffer
> > >
> > > External email: Use caution opening links or attachments
> > >
> > >
> > > On Thu, 8 Sept 2022 at 17:39, Jeff Brasen  wrote:
> > > >
> > > >
> > > >
> > > > > -Original Message-
> > > > > From: Ard Biesheuvel 
> > > > > Sent: Monday, August 15, 2022 8:42 AM
> > > > > To: devel@edk2.groups.io; Jeff Brasen 
> > > > > Cc: hao.a...@intel.com; ray...@intel.com;
> > > > > quic_llind...@quicinc.com;
> > > > > ardb+tianoc...@kernel.org
> > > > > Subject: Re: [edk2-devel] [PATCH v2]
> > > > > MdeModulePkg/NonDiscoverablePciDeviceDxe: Allow partial
> > > > > FreeBuffer
> > > > >
> > > > > External email: Use caution opening links or attachments
> > > > >
> > > > >
> > > > > On Fri, 5 Aug 2022 at 18:56, Jeff Brasen via groups.io
> > > > >  wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > > -Original Message-
> > > > > > > From: Ard Biesheuvel 
> > > > > > > Sent: Tuesday, August 2, 2022 10:51 AM
> > > > > > > To: Jeff Brasen 
> > > > > > > Cc: devel@edk2.groups.io; hao.a...@intel.com;
> > > > > > > ray...@intel.com; quic_llind...@quicinc.com;
> > > > > > > ardb+tianoc...@kernel.org
> > > > > > > Subject: Re: [PATCH v2]
> MdeModulePkg/NonDiscoverablePciDeviceDxe:
> > > > > > > Allow partial FreeBuffer
> > > > > > >
> > > > > > > External email: Use caution opening links or attachments
> > > > > > >
> > > > > > >
> > > > > > > On Tue, 2 Aug 2022 at 17:32, Jeff Brasen 
> wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > > -Original Message-
> > > > > > > > > From: Ard Biesheuvel 
> > > > > > > > > Sent: Friday, July 29, 2022 9:48 AM
> > > > > > > > > To: Jeff Brasen 
> > > > > > > > > Cc: devel@edk2.groups.io; hao.a...@intel.com;
> > > > > > > > > ray...@intel.com; quic_llind...@quicinc.com;
> > > > > > > > > ardb+tianoc...@kernel.org
> > > > > > > > > Subject: Re: [PATCH v2]
> > > MdeModulePkg/NonDiscoverablePciDeviceDxe:
> > > > > > > > > Allow partial FreeBuffer
> > > > > > > > >
> > > > > > > > > External email: Use caution opening links or attachments
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > On Thu, 28 Jul 2022 at 13:25, Jeff Brasen
> > > > > > > > > 
> > > wrote:
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > Adding Leif/Ard to CC incase they have any comments on
> this patch.
> > > > > > > > > >
> > > > > > > > >
> > > > > > > > > This generally looks ok to me. I just wonder if it
> > > > > > > > > wouldn't be simpler to reuse the existing allocation
> > > > > > > > > descriptor if it is not being freed entirely. Given the
> > > > > > > > > [presumably] the most common case is to allocate and
> > > > > > > > > then free some pages at the end, lowering the page count
> > > > > > > > > on the existing descriptor would cover most cases, and
> > > > > > > > > we'd only need to allocate new ones if pages are being
> > > > > > > > > freed at the start or in
> > > > > > > the middle.
> > > > > > > >
> > > > > > > > There is often freeing at the beginning as well as this is
> > > > > > > > being used to create
> > > > > > > a 64K aligned section of memory in the case. So it over
> > > > > > > allocates and the free's some at the beginning and the end.
> > > > > > > I could probably make it detect and use that but figured
> > > > > > > this code would support all cases and required less case specific
> detection.
> > > > > > > >
> > > > > > >
> > > > > > > Ah interesting. Would it help if the allocate routine
> > > > > > > aligned allocations to their size?
> > > > > >
> > > > > > The PciIo->AllocateBuffer function doesn't support passing the
> > > > > > request in so
> > > > > we would need to know that info beforehand. The current calling
> > > > > in the XHCI driver does a free at the beginning and then the end
> > > > > of the buffer so we could the existing allocation tracker but
> > > > > figured it would be better to correct the function just in case
> > > > > someone called it to free
> > > in the middle.
> > > > > >
> > > > >
> 

Re: [edk2-devel] The principles of EDK2 module reconstruction for archs

[Sunil V L]

On Thu, Sep 29, 2022 at 02:54:05PM +, Chang, Abner wrote:
> [AMD Official Use Only - General]
> 
> Hi Sunil,
> One more thing other than the module reconstruction for archs before you 
> sending patch to edk2:
> Not sure how would you do on migrating the RISC-V code from edk2-platforms to 
> edk2.  Did you make some other changes to the RISC-V CpuDxe on edk2-platform?
> Please keep the files history and send the patch for the migration first.  
> Then have the follow up patches for your changes if any and also add the 
> Ventana license.
> 
> Below branches could be the reference for this migration,
> https://github.com/changab/edk2/commits/RISC-V-MIGRATION-EDK2-PR
> https://github.com/changab/edk2-platforms/commits/RISC-V-MIGRATION-EDK2-PLATFORM
> 
> Thanks Sunil.
> Abner
> 
Thanks Abner. Let me take a look at your branch.

We have some changes and are not migrating everything from
edk2-platforms. But I am not sure whether we can maintain the commit
history when we migrate from a different repo. I think this should be like a 
new review and all old RB tags which were for edk2-platforms need to be removed.

For ex:
https://github.com/changab/edk2/commit/eca5ff6bea66be94fd58421ba98cb54d1f4181a6

IMO, RB tag should be removed and should be reviewed fresh when it is
being added to edk2 repo.

Thanks
Sunil


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Re: [edk2-devel] The principles of EDK2 module reconstruction for archs

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Hi Sunil,
One more thing other than the module reconstruction for archs before you 
sending patch to edk2:
Not sure how would you do on migrating the RISC-V code from edk2-platforms to 
edk2.  Did you make some other changes to the RISC-V CpuDxe on edk2-platform?
Please keep the files history and send the patch for the migration first.  Then 
have the follow up patches for your changes if any and also add the Ventana 
license.

Below branches could be the reference for this migration,
https://github.com/changab/edk2/commits/RISC-V-MIGRATION-EDK2-PR
https://github.com/changab/edk2-platforms/commits/RISC-V-MIGRATION-EDK2-PLATFORM

Thanks Sunil.
Abner

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Ni, Ray
> via groups.io
> Sent: Thursday, September 29, 2022 3:48 PM
> To: devel@edk2.groups.io; suni...@ventanamicro.com
> Cc: Chang, Abner ; Kinney, Michael D
> ; lichao ; Kirkendall,
> Garrett ; Grimes, Paul
> ; He, Jiangang ; Attar,
> AbdulLateef (Abdul Lateef) ; Leif Lindholm
> ; Andrew Fish 
> Subject: Re: [edk2-devel] The principles of EDK2 module reconstruction for
> archs
> 
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
> 
> 
> Sunil, I don't have concern with your changes.
> Perhaps you can also move all existing source files to X86 folder.
> 
> > -Original Message-
> > From: devel@edk2.groups.io  On Behalf Of Sunil V
> > L
> > Sent: Wednesday, September 28, 2022 3:34 PM
> > To: devel@edk2.groups.io; Ni, Ray 
> > Cc: abner.ch...@amd.com; Kinney, Michael D
> > ; lichao ; Kirkendall,
> > Garrett ; Grimes, Paul
> > ; He, Jiangang ; Attar,
> > AbdulLateef (Abdul Lateef) ; Leif Lindholm
> > ; Andrew Fish 
> > Subject: Re: [edk2-devel] The principles of EDK2 module reconstruction
> > for archs
> >
> > On Wed, Sep 28, 2022 at 03:33:45AM +, Ni, Ray wrote:
> > Hi Ray,
> > >
> > >   1.  When a new arch's implementation is introduced to the existing
> > module which was developed for the specific arch:
> > >
> > >   1.  The folder reconstruction:
> > >
> > >   *   Create arch folder for the existing arch implementation
> > > [Ray] Do you move existing arch implementation to that arch folder?
> > > It will
> > break existing platforms a lot.
> > >
> > >   *   Create the arch folder for the new introduced arch
> > > [Ray] I agree. But if we don't create arch folder for existing arch
> > implementation, the pkg layout will be a mess.
> > >
> > > [Ray] Hard for me to understand all the principles here. Maybe we
> > > review
> > existing code including to-be-upstreamed code and decide how to go.
> > >
> >
> > Could you please take a look below changes which is trying to add
> > RISC-V support for CpuDxe?
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> > ub.com%2Ftianocore%2Fedk2-
> data=05%7C01%7Cabner.chang%40amd.com%7C
> >
> 84150fde7ae94437a06908daa1eee77a%7C3dd8961fe4884e608e11a82d994e18
> 3d%7C
> >
> 0%7C0%7C638000344717043181%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiM
> C4wLjAwMDA
> >
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&
> amp;sd
> >
> ata=P0QZ8%2B3IxaTnoEJPYOn3SgDLGhLZohPna53RoX6o2sc%3Dreserv
> ed=0
> > staging/commit/bba1a11be47dd091734e185afbed73ea75708749
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> > ub.com%2Ftianocore%2Fedk2-
> data=05%7C01%7Cabner.chang%40amd.com%7C
> >
> 84150fde7ae94437a06908daa1eee77a%7C3dd8961fe4884e608e11a82d994e18
> 3d%7C
> >
> 0%7C0%7C638000344717043181%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiM
> C4wLjAwMDA
> >
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&
> amp;sd
> >
> ata=P0QZ8%2B3IxaTnoEJPYOn3SgDLGhLZohPna53RoX6o2sc%3Dreserv
> ed=0
> > staging/commit/7fccf92a97a6d0618a20f1060e78b3687906
> >
> > What do you suggest with above example?
> >
> > 1) Common INF for all architectures - but modify INF alone, no X86
> > folder creation.
> >
> > This is what I have done in the commit above. May be of least impact
> > to existing code since it is only INF change. But like you mentioned
> > this is bit weird that X86 files will remain in root folder directly
> > along with some common files.
> >
> > 2) Common INF (CpuDxe.inf) + create arch folders X86, X64, IA32,
> > RiscV64 etc
> >
> > IMO, this is probably the best approach. What would be the challenges
> > with this?
> >
> > 3) Separate INF for arch like CpuDxe.inf for x86, CpuDxeRiscV64.inf
> > for RISC-V.
> >
> > This again probably is not a good idea.
> >
> > 4) If the module/library is specific to one arch (ex: SMM(X86),
> > SBI(RISC-V)), then create separate INF.
> >
> > Thanks!
> > Sunil
> >
> >
> >
> >
> >
> 
> 
> 
> 
> 


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[edk2-devel] [PATCH 2/4] OvmfPkg/PlatformInitLib: detect physical address space

[Gerd Hoffmann]

Try detect physical address space, when successful use it.
Otherwise go continue using the current guesswork code path.

Signed-off-by: Gerd Hoffmann 
---
 OvmfPkg/Library/PlatformInitLib/MemDetect.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c 
b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
index 143a01ceb01e..16ecbfadc30c 100644
--- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
+++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
@@ -761,6 +761,19 @@ PlatformAddressWidthInitialization (
 FirstNonAddress = PlatformGetFirstNonAddress (PlatformInfoHob);
   }
 
+  PlatformAddressWidthFromCpuid (PlatformInfoHob, TRUE);
+  if (PlatformInfoHob->PhysMemAddressWidth != 0) {
+// physical address width is known
+PlatformInfoHob->FirstNonAddress = FirstNonAddress;
+return;
+  }
+
+  //
+  // physical address width is NOT known
+  //   -> do some guess work, mostly based on installed memory
+  //   -> try be conservstibe to stay below the guaranteed minimum of
+  //  36 phys bits (aka 64 GB).
+  //
   PhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
 
   //
-- 
2.37.3



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[edk2-devel] [PATCH 0/4] OvmfPkg: make better use of physical address space.

[Gerd Hoffmann]

For historical reasons ovmf is quite conservative on address space
usage, to play safe and avoid using more than 36 physical address bits
(the guaranteed minimum) if possible.  With devices (specifically GPUs)
becoming larger and larger pci memory bars this becomes increasingly
problematic.

This patch series address that by trying to figure what the physical
address space size is (which is a bit tricky, see patch #1 for details).
If that worked scale up the 64-bit mmio window and also pcie bridge
windows dynamically with the available address space.

Gerd Hoffmann (4):
  OvmfPkg/PlatformInitLib: qemu cpuid physbits detection
  OvmfPkg/PlatformInitLib: detect physical address space
  OvmfPkg/PlatformInitLib: dynamic mmio window size
  OvmfPkg/PciHotPlugInitDxe: reserve more mmio space

 OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf |   1 +
 OvmfPkg/Library/PlatformInitLib/MemDetect.c  | 143 ---
 OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c   |  13 ++
 3 files changed, 139 insertions(+), 18 deletions(-)

-- 
2.37.3



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[edk2-devel] [PATCH 4/4] OvmfPkg/PciHotPlugInitDxe: reserve more mmio space

[Gerd Hoffmann]

In case the 64-bit pci mmio window is larger than the default size
of 32G be generous and hand out larger chunks of address space for
prefetchable mmio bridge windows.

Signed-off-by: Gerd Hoffmann 
---
 OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf |  1 +
 OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c   | 13 +
 2 files changed, 14 insertions(+)

diff --git a/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf 
b/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
index 78b95faa7a7a..f56b1de6fd92 100644
--- a/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
+++ b/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.inf
@@ -40,6 +40,7 @@ [Protocols]
 
 [Pcd]
   gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId ## CONSUMES
+  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size  ## CONSUMES
 
 [Depex]
   TRUE
diff --git a/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c 
b/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c
index c122855b735d..08ea5b57bc18 100644
--- a/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c
+++ b/OvmfPkg/PciHotPlugInitDxe/PciHotPlugInit.c
@@ -744,12 +744,25 @@ GetResourcePadding (
 //
 // Request defaults.
 //
+UINT64  Pci64Size = PcdGet64 (PcdPciMmio64Size);
+
+// non-prefetchable
 SetMmioPadding (
   --FirstResource,
   FALSE,
   TRUE,
   (UINTN)HighBitSetRoundUp32 (SIZE_2MB)
   );
+
+// prefetchable
+if (Pci64Size > SIZE_32GB) {
+  SetMmioPadding (
+--FirstResource,
+TRUE,
+FALSE,
+(UINTN)HighBitSetRoundUp64 (RShiftU64 (Pci64Size, 8))
+);
+}
   }
 
   //
-- 
2.37.3



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[edk2-devel] [PATCH 3/4] OvmfPkg/PlatformInitLib: dynamic mmio window size

[Gerd Hoffmann]

In case we have a reliable PhysMemAddressWidth use that to dynamically
size the 64bit address window.  Allocate 1/8 of the physical address
space and place the window at the upper end of the address space.

Signed-off-by: Gerd Hoffmann 
---
 OvmfPkg/Library/PlatformInitLib/MemDetect.c | 28 +
 1 file changed, 28 insertions(+)

diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c 
b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
index 16ecbfadc30c..ae217d0242ed 100644
--- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
+++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
@@ -604,6 +604,33 @@ PlatformAddressWidthFromCpuid (
   }
 }
 
+VOID
+EFIAPI
+PlatformDynamicMmioWindow (
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  )
+{
+  UINT64  AddrSpace, MmioSpace;
+
+  AddrSpace = LShiftU64 (1, PlatformInfoHob->PhysMemAddressWidth);
+  MmioSpace = LShiftU64 (1, PlatformInfoHob->PhysMemAddressWidth - 3);
+
+  if ((PlatformInfoHob->PcdPciMmio64Size < MmioSpace) &&
+  (PlatformInfoHob->PcdPciMmio64Base + MmioSpace < AddrSpace))
+  {
+DEBUG ((DEBUG_INFO, "%a: using dynamic mmio window\n", __func__));
+DEBUG ((DEBUG_INFO, "%a:   Addr Space 0x%Lx (%Ld GB)\n", __func__, 
AddrSpace, RShiftU64 (AddrSpace, 30)));
+DEBUG ((DEBUG_INFO, "%a:   MMIO Space 0x%Lx (%Ld GB)\n", __func__, 
MmioSpace, RShiftU64 (MmioSpace, 30)));
+PlatformInfoHob->PcdPciMmio64Size = MmioSpace;
+PlatformInfoHob->PcdPciMmio64Base = AddrSpace - MmioSpace;
+  } else {
+DEBUG ((DEBUG_INFO, "%a: using classic mmio window\n", __func__));
+  }
+
+  DEBUG ((DEBUG_INFO, "%a:   Pci64 Base 0x%Lx\n", __func__, 
PlatformInfoHob->PcdPciMmio64Base));
+  DEBUG ((DEBUG_INFO, "%a:   Pci64 Size 0x%Lx\n", __func__, 
PlatformInfoHob->PcdPciMmio64Size));
+}
+
 /**
   Iterate over the PCI host bridges resources information optionally provided
   in fw-cfg and find the highest address contained in the PCI MMIO windows. If
@@ -765,6 +792,7 @@ PlatformAddressWidthInitialization (
   if (PlatformInfoHob->PhysMemAddressWidth != 0) {
 // physical address width is known
 PlatformInfoHob->FirstNonAddress = FirstNonAddress;
+PlatformDynamicMmioWindow (PlatformInfoHob);
 return;
   }
 
-- 
2.37.3



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[edk2-devel] [PATCH 1/4] OvmfPkg/PlatformInitLib: qemu cpuid physbits detection

[Gerd Hoffmann]

Add some qemu specific quirks to PlatformAddressWidthFromCpuid()
to figure whenever the PhysBits value returned by CPUID is
something real we can work with or not.

See the source code comment for details on the logic.

Also apply some limits to the address space we are going to use:
 * Place a hard cap at 47 PhysBits (128 TB) to avoid using addresses
   which require 5-level paging support.
 * Cap at 40 PhysBits (1 TB) in case the CPU has no support for
   gigabyte pages, to avoid excessive amounts of pages being
   used for page tables.

Signed-off-by: Gerd Hoffmann 
---
 OvmfPkg/Library/PlatformInitLib/MemDetect.c | 102 
 1 file changed, 84 insertions(+), 18 deletions(-)

diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c 
b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
index d1a4f4b20791..143a01ceb01e 100644
--- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c
+++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c
@@ -503,39 +503,105 @@ PlatformGetFirstNonAddress (
 }
 
 /*
- * Use CPUID to figure physical address width.  Does *not* work
- * reliable on qemu.  For historical reasons qemu returns phys-bits=40
- * even in case the host machine supports less than that.
- *
- * qemu has a cpu property (host-phys-bits={on,off}) to change that
- * and make sure guest phys-bits are not larger than host phys-bits.,
- * but it is off by default.  Exception: microvm machine type
- * hard-wires that property to on.
+ * Use CPUID to figure physical address width.
+ *
+ * Does *not* work reliable on qemu.  For historical reasons qemu
+ * returns phys-bits=40 by default even in case the host machine
+ * supports less than that.
+ *
+ * So we apply the following rules (which can be enabled/disabled
+ * using the QemuQuirk parameter) to figure whenever we can work with
+ * the returned physical address width or not:
+ *
+ *   (1) If it is 41 or higher consider it valid.
+ *   (2) If it is 40 or lower consider it valid in case it matches a
+ *   known-good value for the CPU vendor, which is:
+ * ->  36 or 39 for Intel
+ * ->  40 for AMD
+ *   (3) Otherwise consider it invalid.
+ *
+ * Recommendation: Run qemu with host-phys-bits=on.  That will make
+ * sure guest phys-bits is not larger than host phys-bits.  Some
+ * distro builds do that by default.
  */
 VOID
 EFIAPI
 PlatformAddressWidthFromCpuid (
-  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob,
+  IN BOOLEANQemuQuirk
   )
 {
-  UINT32  RegEax;
+  UINT32   RegEax, RegEbx, RegEcx, RegEdx, Max;
+  UINT8PhysBits;
+  CHAR8Signature[13] = { 0 };
+  BOOLEAN  Valid = FALSE;
+  BOOLEAN  Page1GSupport = FALSE;
 
-  AsmCpuid (0x8000, , NULL, NULL, NULL);
-  if (RegEax >= 0x8008) {
+  AsmCpuid (0x8000, , , , );
+  *(UINT32 *)(Signature + 0) = RegEbx;
+  *(UINT32 *)(Signature + 4) = RegEdx;
+  *(UINT32 *)(Signature + 8) = RegEcx;
+  Max= RegEax;
+
+  if (Max >= 0x8001) {
+AsmCpuid (0x8001, NULL, NULL, NULL, );
+if ((RegEdx & BIT26) != 0) {
+  Page1GSupport = TRUE;
+}
+  }
+
+  if (Max >= 0x8008) {
 AsmCpuid (0x8008, , NULL, NULL, NULL);
-PlatformInfoHob->PhysMemAddressWidth = (UINT8)RegEax;
+PhysBits = (UINT8)RegEax;
   } else {
-PlatformInfoHob->PhysMemAddressWidth = 36;
+PhysBits = 36;
   }
 
-  PlatformInfoHob->FirstNonAddress = LShiftU64 (1, 
PlatformInfoHob->PhysMemAddressWidth);
+  if (!QemuQuirk) {
+Valid = TRUE;
+  } else if (PhysBits >= 41) {
+Valid = TRUE;
+  } else if (AsciiStrCmp (Signature, "GenuineIntel") == 0) {
+if ((PhysBits == 36) || (PhysBits == 39)) {
+  Valid = TRUE;
+}
+  } else if (AsciiStrCmp (Signature, "AuthenticAMD") == 0) {
+if (PhysBits == 40) {
+  Valid = TRUE;
+}
+  }
 
   DEBUG ((
 DEBUG_INFO,
-"%a: cpuid: phys-bits is %d\n",
+"%a: Signature: '%a', PhysBits: %d, QemuQuirk: %a, Valid: %a\n",
 __FUNCTION__,
-PlatformInfoHob->PhysMemAddressWidth
+Signature,
+PhysBits,
+QemuQuirk ? "On" : "Off",
+Valid ? "Yes" : "No"
 ));
+
+  if (Valid) {
+if (PhysBits > 47) {
+  /*
+   * Avoid 5-level paging altogether for now, which limits
+   * PhysBits to 48.  Also avoid using address bit 48, due to sign
+   * extension we can't identity-map these addresses (and lots of
+   * places in edk2 assume we have everything identity-mapped).
+   * So the actual limit is 47.
+   */
+  DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 47 (avoid 5-level paging)\n", 
__func__));
+  PhysBits = 47;
+}
+
+if (!Page1GSupport && (PhysBits > 40)) {
+  DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 40 (no 1G pages 
available)\n", __func__));
+  PhysBits = 40;
+}
+
+PlatformInfoHob->PhysMemAddressWidth = PhysBits;
+PlatformInfoHob->FirstNonAddress = LShiftU64 (1, 
PlatformInfoHob->PhysMemAddressWidth);
+  }
 }
 
 /**
@@ -672,7 +738,7 @@ 

Re: [edk2-devel] [Patch V2] UefiCpuPkg/CpuExceptionHandlerLib: Code optimization to allow bigger stack

[Chang, Abner via groups.io]

[AMD Official Use Only - General]

Not the maintainer or reviewer, however Reviewed-by: Abner Chang 


> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of duntan via
> groups.io
> Sent: Thursday, September 29, 2022 5:07 PM
> To: devel@edk2.groups.io
> Cc: Eric Dong ; Ray Ni ; Rahul Kumar
> 
> Subject: [edk2-devel] [Patch V2] UefiCpuPkg/CpuExceptionHandlerLib: Code
> optimization to allow bigger stack
> 
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
> 
> 
> This commit is a code optimization to allow bigger seperate stack size in
> ArchSetupExceptionStack. In previous code logic, CPU_STACK_ALIGNMENT
> bytes will be wasted if StackTop is already CPU_STACK_ALIGNMENT aligned.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Reviewed-by: Ray Ni 
> Cc: Rahul Kumar 
> ---
>  UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c | 5
> -
> UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c  | 5
> -
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> index 8c398ebc5b..c30ece1dc9 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandle
> +++ r.c
> @@ -215,7 +215,10 @@ ArchSetupExceptionStack (
>// Fixup exception task descriptor and task-state segment
>//
>AsmGetTssTemplateMap ();
> -  StackTop = StackTop - CPU_STACK_ALIGNMENT;
> +  //
> +  // Plus 1 byte is for compact stack layout in case StackTop is already 
> aligned.
> +  //
> +  StackTop = StackTop - CPU_STACK_ALIGNMENT + 1;
>StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
>IdtTable = (IA32_IDT_GATE_DESCRIPTOR  *)Idtr.Base;
>for (Index = 0; Index < CPU_STACK_SWITCH_EXCEPTION_NUMBER; ++Index)
> { diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> index 80e9f08e5b..4e85880ed4 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler
> +++ .c
> @@ -223,7 +223,10 @@ ArchSetupExceptionStack (
>// Fixup exception task descriptor and task-state segment
>//
>ZeroMem (Tss, sizeof (*Tss));
> -  StackTop = StackTop - CPU_STACK_ALIGNMENT;
> +  //
> +  // Plus 1 byte is for compact stack layout in case StackTop is already 
> aligned.
> +  //
> +  StackTop = StackTop - CPU_STACK_ALIGNMENT + 1;
>StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
>IdtTable = (IA32_IDT_GATE_DESCRIPTOR  *)Idtr.Base;
>for (Index = 0; Index < CPU_STACK_SWITCH_EXCEPTION_NUMBER; ++Index) {
> --
> 2.31.1.windows.1
> 
> 
> 
> 
> 


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[edk2-devel] [Patch V2] UefiCpuPkg/CpuExceptionHandlerLib: Code optimization to allow bigger stack

[duntan]

This commit is a code optimization to allow bigger seperate stack size in
ArchSetupExceptionStack. In previous code logic, CPU_STACK_ALIGNMENT bytes
will be wasted if StackTop is already CPU_STACK_ALIGNMENT aligned.

Signed-off-by: Dun Tan 
Cc: Eric Dong 
Reviewed-by: Ray Ni 
Cc: Rahul Kumar 
---
 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c | 5 -
 UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c  | 5 -
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index 8c398ebc5b..c30ece1dc9 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -215,7 +215,10 @@ ArchSetupExceptionStack (
   // Fixup exception task descriptor and task-state segment
   //
   AsmGetTssTemplateMap ();
-  StackTop = StackTop - CPU_STACK_ALIGNMENT;
+  //
+  // Plus 1 byte is for compact stack layout in case StackTop is already 
aligned.
+  //
+  StackTop = StackTop - CPU_STACK_ALIGNMENT + 1;
   StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
   IdtTable = (IA32_IDT_GATE_DESCRIPTOR  *)Idtr.Base;
   for (Index = 0; Index < CPU_STACK_SWITCH_EXCEPTION_NUMBER; ++Index) {
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index 80e9f08e5b..4e85880ed4 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -223,7 +223,10 @@ ArchSetupExceptionStack (
   // Fixup exception task descriptor and task-state segment
   //
   ZeroMem (Tss, sizeof (*Tss));
-  StackTop = StackTop - CPU_STACK_ALIGNMENT;
+  //
+  // Plus 1 byte is for compact stack layout in case StackTop is already 
aligned.
+  //
+  StackTop = StackTop - CPU_STACK_ALIGNMENT + 1;
   StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
   IdtTable = (IA32_IDT_GATE_DESCRIPTOR  *)Idtr.Base;
   for (Index = 0; Index < CPU_STACK_SWITCH_EXCEPTION_NUMBER; ++Index) {
-- 
2.31.1.windows.1



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Re: [edk2-devel] [PATCH] UefiCpuPkg/CpuExceptionHandlerLib: Code optimization to allow bigger stack

[duntan]

Hi Abner,

Thanks for the comments. I'll add comments on this code change to explain it in 
V2 patch.

Thanks,
Dun
-Original Message-
From: devel@edk2.groups.io  On Behalf Of Chang, Abner via 
groups.io
Sent: Thursday, September 29, 2022 9:05 AM
To: devel@edk2.groups.io; Tan, Dun 
Cc: Dong, Eric ; Ni, Ray ; Kumar, Rahul 
R 
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg/CpuExceptionHandlerLib: Code 
optimization to allow bigger stack

[AMD Official Use Only - General]



> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of duntan 
> via groups.io
> Sent: Wednesday, September 28, 2022 9:52 AM
> To: devel@edk2.groups.io
> Cc: Eric Dong ; Ray Ni ; Rahul 
> Kumar 
> Subject: [edk2-devel] [PATCH] UefiCpuPkg/CpuExceptionHandlerLib: Code 
> optimization to allow bigger stack
> 
> Caution: This message originated from an External Source. Use proper 
> caution when opening attachments, clicking links, or responding.
> 
> 
> This commit is a code optimization to allow bigger seperate stack size 
> in ArchSetupExceptionStack. In previous code logic, 
> CPU_STACK_ALIGNMENT bytes will be wasted if StackTop is already 
> CPU_STACK_ALIGNMENT aligned.
> 
> Signed-off-by: Dun Tan 
> Cc: Eric Dong 
> Cc: Ray Ni 
> Cc: Rahul Kumar 
> ---
>  UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c 
> |
> 2 +-
> UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c  
> |
> 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.
> c 
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.
> c
> index 8c398ebc5b..c8fa30a32f 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.
> c
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandle
> +++ r.c
> @@ -215,7 +215,7 @@ ArchSetupExceptionStack (
>// Fixup exception task descriptor and task-state segment
>//
>AsmGetTssTemplateMap ();
> -  StackTop = StackTop - CPU_STACK_ALIGNMENT;
> +  StackTop = StackTop - CPU_STACK_ALIGNMENT + 1;
Hi Dun,
Could you please add a comment on this change says the change is for the 
compact stack layout?
Thanks
Abner

>StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
>IdtTable = (IA32_IDT_GATE_DESCRIPTOR  *)Idtr.Base;
>for (Index = 0; Index < CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> ++Index) { diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> index 80e9f08e5b..74b2193cb0 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler
> +++ .c
> @@ -223,7 +223,7 @@ ArchSetupExceptionStack (
>// Fixup exception task descriptor and task-state segment
>//
>ZeroMem (Tss, sizeof (*Tss));
> -  StackTop = StackTop - CPU_STACK_ALIGNMENT;
> +  StackTop = StackTop - CPU_STACK_ALIGNMENT + 1;
>StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
>IdtTable = (IA32_IDT_GATE_DESCRIPTOR  *)Idtr.Base;
>for (Index = 0; Index < CPU_STACK_SWITCH_EXCEPTION_NUMBER;
> ++Index) {
> --
> 2.31.1.windows.1
> 
> 
> 
> 
> 







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Re: [edk2-devel] [PATCH] MdeModulePkg: Handle InitialVFs=0 case for SR-IOV

[Ni, Ray]

Foster,
Can you please include the SRIOV spec content in comments?

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Bob
> Feng
> Sent: Thursday, September 29, 2022 4:50 PM
> To: devel@edk2.groups.io
> Cc: Nong, Foster 
> Subject: [edk2-devel] [PATCH] MdeModulePkg: Handle InitialVFs=0 case for
> SR-IOV
> 
> From: Foster Nong 
> 
> Per SR-IOV spec,InitialVFs minimum is 0. Below code which use to calculate
> SR-IOV bus number,
> if InitialVFs =0, it maybe calculate the wrong bus number.
> 
> LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride
> we can fix it with below code:
>  if (PciIoDevice->InitialVFs == 0) {
>  PciIoDevice->ReservedBusNum = 0;
> } else {
> PFRid  = EFI_PCI_RID (Bus, Device, Func);
>  LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
> //
> // Calculate ReservedBusNum for this PF
> //
> PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) -
> Bus + 1);
> //
>  // Calculate ReservedBusNum for this PF
> //
>  PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) -
> Bus + 1);
> }
> 
> https://bugzilla.tianocore.org/show_bug.cgi?id=4069
> 
> Signed-off-by: Foster Nong 
> ---
>  .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> index 509f828b62..eb250f6f7b 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
> @@ -2416,13 +2416,17 @@ CreatePciIoDevice (
>//
>// Calculate LastVF
>//
> -  PFRid  = EFI_PCI_RID (Bus, Device, Func);
> -  LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * 
> VFStride;
> +  if (PciIoDevice->InitialVFs == 0) {
> +PciIoDevice->ReservedBusNum = 0;
> +  } else {
> +PFRid  = EFI_PCI_RID (Bus, Device, Func);
> +LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * 
> VFStride;
> 
> -  //
> -  // Calculate ReservedBusNum for this PF
> -  //
> -  PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID
> (LastVF) - Bus + 1);
> +//
> +// Calculate ReservedBusNum for this PF
> +//
> +PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID
> (LastVF) - Bus + 1);
> +  }
> 
>DEBUG ((
>  DEBUG_INFO,
> --
> 2.37.1.windows.1
> 
> 
> 
> 
> 



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[edk2-devel] [PATCH] MdeModulePkg: Handle InitialVFs=0 case for SR-IOV

[Bob Feng]

From: Foster Nong 

Per SR-IOV spec,InitialVFs minimum is 0. Below code which use to calculate 
SR-IOV bus number,
if InitialVFs =0, it maybe calculate the wrong bus number.

LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride
we can fix it with below code:
 if (PciIoDevice->InitialVFs == 0) {
 PciIoDevice->ReservedBusNum = 0;
} else {
PFRid  = EFI_PCI_RID (Bus, Device, Func);
 LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
//
// Calculate ReservedBusNum for this PF
//
PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
//
 // Calculate ReservedBusNum for this PF
//
 PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus + 1);
}

https://bugzilla.tianocore.org/show_bug.cgi?id=4069

Signed-off-by: Foster Nong 
---
 .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c 
b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index 509f828b62..eb250f6f7b 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -2416,13 +2416,17 @@ CreatePciIoDevice (
   //
   // Calculate LastVF
   //
-  PFRid  = EFI_PCI_RID (Bus, Device, Func);
-  LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * 
VFStride;
+  if (PciIoDevice->InitialVFs == 0) {
+PciIoDevice->ReservedBusNum = 0;
+  } else {
+PFRid  = EFI_PCI_RID (Bus, Device, Func);
+LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * 
VFStride;
 
-  //
-  // Calculate ReservedBusNum for this PF
-  //
-  PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - Bus 
+ 1);
+//
+// Calculate ReservedBusNum for this PF
+//
+PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) - 
Bus + 1);
+  }
 
   DEBUG ((
 DEBUG_INFO,
-- 
2.37.1.windows.1



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Re: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Enable ADM when change TTM

[Sheng Wei]

Hi Ray,
Could you help to review the merge the patch to the VTd driver in edkplatform 
branch ?
This patch is used to enable Abort DMA Mode(ADM) when change the TTM .
The comment from VTd spec is below.

 For implementations reporting Enhanced SRTP Support (ESRTPS) field as
 Clear in the Capability register, software must not modify this field while
 DMA remapping is active (TES=1 in Global Status register).

So, we will enable ADM while TE is disable.
Thank you
BR
Sheng Wei

> -Original Message-
> From: Huang, Jenny 
> Sent: 2022年9月29日 11:54
> To: devel@edk2.groups.io; Sheng, W 
> Cc: Ni, Ray ; Chaganty, Rangasai V
> ; Kowalewski, Robert
> 
> Subject: RE: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Enable ADM when
> change TTM
> 
> Reviewed-by: Jenny Huang 
> 
> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Sheng,
> W
> Sent: Monday, September 5, 2022 1:49 AM
> To: devel@edk2.groups.io
> Cc: Huang, Jenny ; Ni, Ray ;
> Chaganty, Rangasai V ; Kowalewski,
> Robert 
> Subject: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Enable ADM when change
> TTM
> 
> In Abort DMA Mode(ADM), hardware will abort all DMA operations without
> the need to set up a roottable. Enable Abort DMA Mode, when change
> Translation Table Mode(TTM)
> 
> Change-Id: I74207fe96ef7a57d89a355d40dfbdd36186f06c3
> Signed-off-by: Sheng Wei 
> Cc: Jenny Huang 
> Cc: Ray Ni 
> Cc: Rangasai V Chaganty 
> 
> Cc: Robert Kowalewski 
> ---
>  .../VTd/IntelVTdDmarPei/IntelVTdDmar.c| 157 +++-
>  .../Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf   |   1 +
>  .../Feature/VTd/IntelVTdDxe/VtdReg.c  | 169 +-
>  .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec |  12 +-
>  4 files changed, 245 insertions(+), 94 deletions(-)
> 
> diff --git
> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.
> c
> b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.
> c
> index b5b78f779..24beccd26 100644
> ---
> a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmar.
> c
> +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTd
> +++ Dmar.c
> @@ -361,6 +361,68 @@ InvalidateIOTLB (
>return EFI_SUCCESS;
> 
>  }
> 
> 
> 
> +/**
> 
> +  Clear Global Command Register Bits
> 
> +
> 
> +  @param[in] VtdUnitBaseAddress The base address of the VTd engine.
> 
> +  @param[in] BitMaskBit mask.
> 
> +**/
> 
> +VOID
> 
> +ClearGlobalCommandRegisterBits (
> 
> +  IN UINTN VtdUnitBaseAddress,
> 
> +  IN UINT32BitMask
> 
> +  )
> 
> +{
> 
> +  UINT32Reg32;
> 
> +  UINT32Status;
> 
> +  UINT32Command;
> 
> +
> 
> +  Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> 
> +  Status = (Reg32 & 0x96FF);   // Reset the one-shot bits
> 
> +  Command = (Status & (~BitMask));
> 
> +  MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);
> 
> +
> 
> +  DEBUG((DEBUG_INFO, "Clear GCMD_REG bits 0x%x.\n", BitMask));
> 
> +
> 
> +  //
> 
> +  // Poll on Status bit of Global status register to become zero
> 
> +  //
> 
> +  do {
> 
> +Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> 
> +  } while ((Reg32 & BitMask) == BitMask);
> 
> +}
> 
> +
> 
> +/**
> 
> +  Set Global Command Register Bits
> 
> +
> 
> +  @param[in] VtdUnitBaseAddress The base address of the VTd engine.
> 
> +  @param[in] BitMaskBit mask.
> 
> +**/
> 
> +VOID
> 
> +SetGlobalCommandRegisterBits (
> 
> +  IN UINTN VtdUnitBaseAddress,
> 
> +  IN UINT32BitMask
> 
> +  )
> 
> +{
> 
> +  UINT32Reg32;
> 
> +  UINT32Status;
> 
> +  UINT32Command;
> 
> +
> 
> +  Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> 
> +  Status = (Reg32 & 0x96FF);   // Reset the one-shot bits
> 
> +  Command = (Status | BitMask);
> 
> +  MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);
> 
> +
> 
> +  DEBUG((DEBUG_INFO, "Set GCMD_REG bits 0x%x.\n", BitMask));
> 
> +
> 
> +  //
> 
> +  // Poll on Status bit of Global status register to become not zero
> 
> +  //
> 
> +  do {
> 
> +Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> 
> +  } while ((Reg32 & BitMask) == 0);
> 
> +}
> 
> +
> 
>  /**
> 
>Enable DMAR translation in pre-mem phase.
> 
> 
> 
> @@ -383,13 +445,10 @@ EnableDmarPreMem (
>DEBUG ((DEBUG_INFO, "RTADDR_REG : 0x%016lx \n", RtaddrRegValue));
> 
>MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, RtaddrRegValue);
> 
> 
> 
> -  Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> 
> -  MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 |
> B_GMCD_REG_SRTP);
> 
> -
> 
>DEBUG ((DEBUG_INFO, "EnableDmarPreMem: waiting for RTPS bit to be
> set... \n"));
> 
> -  do {
> 
> -Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> 
> -  } while((Reg32 & B_GSTS_REG_RTPS) == 0);
> 
> +  SetGlobalCommandRegisterBits (VtdUnitBaseAddress,
> B_GMCD_REG_SRTP);
> 
> +
> 
> +  Reg32 = MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);
> 
>DEBUG ((DEBUG_INFO, "EnableDmarPreMem: R_GSTS_REG = 0x%x 

Re: [edk2-devel] The principles of EDK2 module reconstruction for archs

[Ni, Ray]

Sunil, I don't have concern with your changes.
Perhaps you can also move all existing source files to X86 folder.

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Sunil V L
> Sent: Wednesday, September 28, 2022 3:34 PM
> To: devel@edk2.groups.io; Ni, Ray 
> Cc: abner.ch...@amd.com; Kinney, Michael D
> ; lichao ; Kirkendall,
> Garrett ; Grimes, Paul
> ; He, Jiangang ; Attar,
> AbdulLateef (Abdul Lateef) ; Leif Lindholm
> ; Andrew Fish 
> Subject: Re: [edk2-devel] The principles of EDK2 module reconstruction for
> archs
> 
> On Wed, Sep 28, 2022 at 03:33:45AM +, Ni, Ray wrote:
> Hi Ray,
> >
> >   1.  When a new arch's implementation is introduced to the existing
> module which was developed for the specific arch:
> >
> >   1.  The folder reconstruction:
> >
> >   *   Create arch folder for the existing arch implementation
> > [Ray] Do you move existing arch implementation to that arch folder? It will
> break existing platforms a lot.
> >
> >   *   Create the arch folder for the new introduced arch
> > [Ray] I agree. But if we don't create arch folder for existing arch
> implementation, the pkg layout will be a mess.
> >
> > [Ray] Hard for me to understand all the principles here. Maybe we review
> existing code including to-be-upstreamed code and decide how to go.
> >
> 
> Could you please take a look below changes which is trying to add RISC-V
> support for CpuDxe?
> https://github.com/tianocore/edk2-
> staging/commit/bba1a11be47dd091734e185afbed73ea75708749
> https://github.com/tianocore/edk2-
> staging/commit/7fccf92a97a6d0618a20f1060e78b3687906
> 
> What do you suggest with above example?
> 
> 1) Common INF for all architectures - but modify INF alone, no X86
> folder creation.
> 
> This is what I have done in the commit above. May be of least impact to
> existing code
> since it is only INF change. But like you mentioned this is bit weird that X86
> files will
> remain in root folder directly along with some common files.
> 
> 2) Common INF (CpuDxe.inf) + create arch folders X86, X64, IA32, RiscV64 etc
> 
> IMO, this is probably the best approach. What would be the challenges
> with this?
> 
> 3) Separate INF for arch like CpuDxe.inf for x86, CpuDxeRiscV64.inf for
> RISC-V.
> 
> This again probably is not a good idea.
> 
> 4) If the module/library is specific to one arch (ex: SMM(X86),
> SBI(RISC-V)), then create separate INF.
> 
> Thanks!
> Sunil
> 
> 
> 
> 
> 



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Re: [edk2-devel] The principles of EDK2 module reconstruction for archs

[Ni, Ray]

Abner,
Comments in 
https://github.com/tianocore-docs/edk2-CCodingStandardsSpecification/pull/2#pullrequestreview-1124763311

We can discuss more in tomorrow's meeting.


> -Original Message-
> From: Attar, AbdulLateef (Abdul Lateef) 
> Sent: Thursday, September 29, 2022 3:11 PM
> To: Chang, Abner ; Sunil V L
> ; devel@edk2.groups.io; Ni, Ray
> 
> Cc: Kinney, Michael D ; lichao
> ; Kirkendall, Garrett ;
> Grimes, Paul ; He, Jiangang
> ; Leif Lindholm ;
> Andrew Fish 
> Subject: RE: [edk2-devel] The principles of EDK2 module reconstruction for
> archs
> 
> Hi Abner,
> Looks good to me.
> Reviewed-by:  Abdul Lateef Attar 
> 
> Thanks
> AbduL
> 
> -Original Message-
> From: Chang, Abner 
> Sent: 28 September 2022 20:31
> To: Sunil V L ; devel@edk2.groups.io;
> ray...@intel.com
> Cc: Kinney, Michael D ; lichao
> ; Kirkendall, Garrett ;
> Grimes, Paul ; He, Jiangang
> ; Attar, AbdulLateef (Abdul Lateef)
> ; Leif Lindholm ;
> Andrew Fish 
> Subject: RE: [edk2-devel] The principles of EDK2 module reconstruction for
> archs
> 
> [AMD Official Use Only - General]
> 
> I just had created PR to update edkII C coding standard spec for the file and
> directory naming. We can review and confirm this update first and then go
> back to the principles of EDK2 module reconstruction for archs.
> Here is the PR:
> https://github.com/tianocore-docs/edk2-
> CCodingStandardsSpecification/pull/2
> 
> The naming rule is mainly for the new module or new file IMO. Some existing
> module may not meet the guidelines mentioned in this spec. Thus we need
> the principles of EDK2 module reconstruction on the existing module to
> support other processor archs and not impacting the existing platforms (e.g.
> rename the INF file or directory to meet the guidelines).
> 
> Sunil, seems RISC-V CpuDxe meet the guideline. Please check it.
> Just feel that having  CpuDxe.c to Riscv64 folder is not quite a best 
> solution. I
> think at least we can abstract the protocol structure and protocol 
> installation
> under CpuDxe\ and have the arch implementation under arch folder. We can
> discuss this later after we confirming the guideline and principles.
> 
> Thanks
> Abner
> 
> > -Original Message-
> > From: Sunil V L 
> > Sent: Wednesday, September 28, 2022 3:34 PM
> > To: devel@edk2.groups.io; ray...@intel.com
> > Cc: Chang, Abner ; Kinney, Michael D
> > ; lichao ; Kirkendall,
> > Garrett ; Grimes, Paul
> > ; He, Jiangang ; Attar,
> > AbdulLateef (Abdul Lateef) ; Leif Lindholm
> > ; Andrew Fish 
> > Subject: Re: [edk2-devel] The principles of EDK2 module reconstruction
> > for archs
> >
> > Caution: This message originated from an External Source. Use proper
> > caution when opening attachments, clicking links, or responding.
> >
> >
> > On Wed, Sep 28, 2022 at 03:33:45AM +, Ni, Ray wrote:
> > Hi Ray,
> > >
> > >   1.  When a new arch's implementation is introduced to the existing
> > module which was developed for the specific arch:
> > >
> > >   1.  The folder reconstruction:
> > >
> > >   *   Create arch folder for the existing arch implementation
> > > [Ray] Do you move existing arch implementation to that arch folder?
> > > It will
> > break existing platforms a lot.
> > >
> > >   *   Create the arch folder for the new introduced arch
> > > [Ray] I agree. But if we don't create arch folder for existing arch
> > implementation, the pkg layout will be a mess.
> > >
> > > [Ray] Hard for me to understand all the principles here. Maybe we
> > > review
> > existing code including to-be-upstreamed code and decide how to go.
> > >
> >
> > Could you please take a look below changes which is trying to add
> > RISC-V support for CpuDxe?
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> > ub.com%2Ftianocore%2Fedk2-
> >
> staging%2Fcommit%2Fbba1a11be47dd091734e185afbed73ea75708749
> >
> data=05%7C01%7Cabner.chang%40amd.com%7Ca419e6a010d34fde464b08d
> >
> aa123e080%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63799947
> >
> 2732494527%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIj
> >
> oiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csd
> >
> ata=Vq6pJLnn8yJrJhFZn7LfLbZzrtpG4n1VLWgAil6J38U%3Dreserved=0
> >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> > ub.com%2Ftianocore%2Fedk2-
> >
> staging%2Fcommit%2F7fccf92a97a6d0618a20f1060e78b3687906da
> >
> ta=05%7C01%7Cabner.chang%40amd.com%7Ca419e6a010d34fde464b08daa1
> >
> 23e080%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63799947273
> >
> 2494527%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV
> >
> 2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata
> >
> =xFmvUv58vh4AUAM17Qy9G5jZWFZlK2Ozt3njpG1e8%2BY%3Dreserv
> > ed=0
> >
> > What do you suggest with above example?
> >
> > 1) Common INF for all architectures - but modify INF alone, no X86
> > folder creation.
> >
> > This is what I have done in the commit above. May be of least impact
> > to existing code since it is only INF change. But 

[edk2-devel] [edk2-platforms][PATCH V3 14/16] Platform/Loongson: Support Dxe

[xianglai]

Support Dxe for LoogArch.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Loongson/LoongArchQemuPkg/Loongson.dec|  14 +-
 .../Loongson/LoongArchQemuPkg/Loongson.dsc| 420 +-
 .../Loongson/LoongArchQemuPkg/Loongson.fdf| 243 ++
 .../LoongArchQemuPkg/Loongson.fdf.inc |  42 ++
 .../LoongArchQemuPkg/VarStore.fdf.inc |  64 +++
 5 files changed, 778 insertions(+), 5 deletions(-)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/VarStore.fdf.inc

diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
index 6a423f3ed6..5065f99042 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -18,7 +18,8 @@
 #   Comments are used for Keywords and Module Types.
 #
 # Supported Module Types:
-#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER
+#  DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
 #
 

 [Includes.common]
@@ -26,12 +27,20 @@
 
 [Guids]
   gLoongArchQemuPkgTokenSpaceGuid  = { 0x0e0383ce, 0x0151, 0x4d01, { 0x80, 
0x0e, 0x3f, 0xef, 0x8b, 0x27, 0x6d, 0x52 } }
+  gEfiLoongsonBootparamsTableGuid  = { 0x4660f721, 0x2ec5, 0x416a, { 0x89, 
0x9a, 0x43, 0x18, 0x02, 0x50, 0xa0, 0xc9 } }
+
+[Protocols]
 
 [PcdsFixedAtBuild, PcdsDynamic]
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvOffset|0x0|UINT64|0x0007
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvBase|0x0|UINT64|0x0008
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvSize|0x0|UINT32|0x0009
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecModuleBase|0x0|UINT64|0x000a
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecModuleSize|0x0|UINT32|0x000b
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashEventLogBase|0x0|UINT64|0x000c
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashEventLogSize|0x0|UINT32|0x000d
   gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreeBase|0x0|UINT64|0x0018
   gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreePadding|256|UINT32|0x0019
 
@@ -45,6 +54,8 @@
 [PcdsFixedAtBuild.LOONGARCH64]
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32|UINT8|0x0010
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0|UINT8|0x0011
+   
gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceSpaceStartAddress|0x1000|UINT32|0x0012
+   
gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceSpaceLength|0x8000|UINT32|0x0013
 
 [PcdsDynamic]
   gLoongArchQemuPkgTokenSpaceGuid.PcdRamSize|0x4000|UINT64|0x0041
@@ -56,3 +67,4 @@
   gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPmd|0x0|UINT64|0x0047
   gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPte|0x0|UINT64|0x0048
 
+[PcdsFeatureFlag]
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
index 1ca8cc09f7..74c83720b7 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -24,6 +24,25 @@
   FLASH_DEFINITION   = 
Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
   TTY_TERMINAL   = FALSE
 
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  DEFINE TTY_TERMINAL= FALSE
+  DEFINE SECURE_BOOT_ENABLE  = FALSE
+  DEFINE TPM2_ENABLE = FALSE
+  DEFINE TPM2_CONFIG_ENABLE  = FALSE
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_IP6_ENABLE  = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE= FALSE
+  DEFINE NETWORK_SNP_ENABLE  = FALSE
+  DEFINE NETWORK_TLS_ENABLE  = FALSE
+  DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS  = TRUE
+  DEFINE NETWORK_ISCSI_ENABLE= FALSE
+
+!include NetworkPkg/NetworkDefines.dsc.inc
 
 #
 # Defines for default states.  These can be changed on the command line.
@@ -37,16 +56,25 @@
   #
   GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
 
+!include NetworkPkg/NetworkBuildOptions.dsc.inc
 
 [BuildOptions.LOONGARCH64.EDKII.SEC]
   *_*_*_CC_FLAGS =
 
-#[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
-#  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
 
 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
   

[edk2-devel] [edk2-platforms][PATCH V3 15/16] Platform/Loongson: Add QemuFlashFvbServicesRuntimeDxe driver.

[xianglai]

This library provides flash read and write functionality
and supports writing variables to flash.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../QemuFlashFvbServicesRuntimeDxe/FvbInfo.c  |  115 ++
 .../FvbServicesRuntimeDxe.inf |   73 ++
 .../FwBlockService.c  | 1158 +
 .../FwBlockService.h  |  178 +++
 .../FwBlockServiceDxe.c   |  152 +++
 .../QemuFlash.c   |  251 
 .../QemuFlash.h   |   86 ++
 .../QemuFlashDxe.c|   21 +
 .../Loongson/LoongArchQemuPkg/Loongson.dsc|4 +-
 9 files changed, 2036 insertions(+), 2 deletions(-)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbInfo.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FwBlockService.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FwBlockService.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FwBlockServiceDxe.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/QemuFlash.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbInfo.c
 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbInfo.c
new file mode 100644
index 00..df772f72be
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbInfo.c
@@ -0,0 +1,115 @@
+/** @file
+  Defines data structure that is the volume header found.These data is intent
+  to decouple FVB driver with FV header.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The protocols, PPI and GUID definitions for this module
+//
+#include 
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+
+typedef struct {
+  UINT64FvLength;
+  EFI_FIRMWARE_VOLUME_HEADERFvbInfo;
+  //
+  // EFI_FV_BLOCK_MAP_ENTRYExtraBlockMap[n];//n=0
+  //
+  EFI_FV_BLOCK_MAP_ENTRYEnd[1];
+} EFI_FVB_MEDIA_INFO;
+
+EFI_FVB_MEDIA_INFO  mPlatformFvbMediaInfo[] = {
+  //
+  // System NvStorage FVB
+  //
+  {
+FixedPcdGet32 (PcdAllVarSize),
+{
+  {
+0,
+  },  // ZeroVector[16]
+  EFI_SYSTEM_NV_DATA_FV_GUID,
+  FixedPcdGet32 (PcdAllVarSize),
+  EFI_FVH_SIGNATURE,
+  EFI_FVB2_MEMORY_MAPPED |
+  EFI_FVB2_READ_ENABLED_CAP |
+  EFI_FVB2_READ_STATUS |
+  EFI_FVB2_WRITE_ENABLED_CAP |
+  EFI_FVB2_WRITE_STATUS |
+  EFI_FVB2_ERASE_POLARITY |
+  EFI_FVB2_ALIGNMENT_16,
+  sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+  0,  // CheckSum
+  0,  // ExtHeaderOffset
+  {
+0,
+  },  // Reserved[1]
+  2,  // Revision
+  {
+{
+  (FixedPcdGet32 (PcdAllVarSize))/
+  FixedPcdGet32 (PcdFlashBlockSize),
+  FixedPcdGet32 (PcdFlashBlockSize),
+}
+  } // BlockMap[1]
+},
+{
+  {
+0,
+0
+  }
+}  // End[1]
+  }
+};
+
+EFI_STATUS
+GetFvbInfo (
+  IN  UINT64  FvLength,
+  OUT EFI_FIRMWARE_VOLUME_HEADER  **FvbInfo
+  )
+{
+  STATIC BOOLEAN  Checksummed = FALSE;
+  UINTN   Index;
+
+  if (!Checksummed) {
+for (Index = 0;
+ Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+ Index += 1)
+{
+  UINT16  Checksum;
+  mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = 0;
+  Checksum  = CalculateCheckSum16 (
+(UINT16 
*)[Index].FvbInfo,
+
mPlatformFvbMediaInfo[Index].FvbInfo.HeaderLength
+);
+  mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = Checksum;
+}
+Checksummed = TRUE;
+  }
+
+  for (Index = 0;
+   Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+   Index += 1)
+  {
+if (mPlatformFvbMediaInfo[Index].FvLength == FvLength) {
+  *FvbInfo = [Index].FvbInfo;
+  return EFI_SUCCESS;
+}
+  }
+
+  return EFI_NOT_FOUND;
+}
diff --git 

[edk2-devel] [edk2-platforms][PATCH V3 16/16] Platform/Loongson: Support for saving variables to flash.

[xianglai]

Added the function of saving non-volatile variables.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 Platform/Loongson/LoongArchQemuPkg/Loongson.dec|  6 ++
 Platform/Loongson/LoongArchQemuPkg/Loongson.dsc|  2 +-
 Platform/Loongson/LoongArchQemuPkg/Loongson.fdf| 14 ++
 .../Loongson/LoongArchQemuPkg/Loongson.fdf.inc | 11 +++
 .../Loongson/LoongArchQemuPkg/VarStore.fdf.inc | 10 +-
 5 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
index 5065f99042..2fd80e7ea2 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -32,6 +32,8 @@
 [Protocols]
 
 [PcdsFixedAtBuild, PcdsDynamic]
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashFdBase|0x0|UINT64|0
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashBlockSize|0x0|UINT32|2
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvOffset|0x0|UINT64|0x0007
@@ -48,6 +50,10 @@
   gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x001d
   gLoongArchQemuPkgTokenSpaceGuid.PcdUefiRamTop|0x0|UINT64|0x001e
   gLoongArchQemuPkgTokenSpaceGuid.PcdRamRegionsBottom|0x0|UINT64|0x0022
+  
gLoongArchQemuPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT64|0x0024
+  gLoongArchQemuPkgTokenSpaceGuid.PcdAllVarSize|0x0|UINT32|0x0025
+  
gLoongArchQemuPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT64|0x0026
+  
gLoongArchQemuPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT64|0x0027
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvBase|0x0|UINT64|0x0028
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvSize|0x0|UINT32|0x0029
 
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
index 59beafb34f..46b326f0a5 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -444,7 +444,7 @@
   #
   # Variable
   #
-#  
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
+  
Platform/Loongson/LoongArchQemuPkg/Drivers/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
   OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.inf {
 
   PlatformFvbLib|OvmfPkg/Library/EmuVariableFvbLib/EmuVariableFvbLib.inf
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
index ba2942e455..12920a0833 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
@@ -31,6 +31,19 @@ 
gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvBase|gLoongArchQemuPkgTokenSpaceGui
 FV = FVMAIN_COMPACT
 
 !include VarStore.fdf.inc
+
+#
+[FD.QEMU_EFI_VARS]
+BaseAddress   = $(VARIABLE_BASE_ADDRESS)
+Size  = $(VAR_ALL_SIZE)
+ErasePolarity = 1
+BlockSize = $(BLOCK_SIZE)
+NumBlocks = $(VAR_ALL_BLOCKS)
+
+DEFINE VARIABLE_OFFSET = 0
+!include VarStore.fdf.inc
+DEFINE VARIABLE_OFFSET = 0x003a
+
 
#
 [FV.SECFV]
 FvNameGuid = 587d4265-5e71-41da-9c35-4258551f1e22
@@ -87,6 +100,7 @@ INF  MdeModulePkg/Core/Pei/PeiMain.inf
 INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
 INF  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 INF  Platform/Loongson/LoongArchQemuPkg/PlatformPei/PlatformPei.inf
+
 
#
 [FV.DXEFV]
 FvNameGuid = 5d19a5b3-130f-459b-a292-9270a9e6bc62
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc
index 964d69ed44..4b926a85ff 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc
@@ -34,6 +34,7 @@ DEFINE VAR_ALL_SIZE   = 0x6
 
 
 #Set Var Flash layout
+DEFINE VARIABLE_BASE_ADDRESS  = 0x1c3a
 DEFINE VARIABLE_SIZE  = 0x0001
 DEFINE VAR_ALL_BLOCKS = 0x60
 
@@ -53,11 +54,21 @@ DEFINE EVENT_LOG_OFFSET   = $(FWTWORKING_OFFSET) + 
$(FWTWORKING_SIZE)
 DEFINE EVENT_LOG_SIZE = 0x8000
 
 # Set Variable
+SET gLoongArchQemuPkgTokenSpaceGuid.PcdFlashFdBase = $(FD_BASE_ADDRESS)
+
+SET gLoongArchQemuPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase = 
$(FD_BASE_ADDRESS) + $(VARIABLE_OFFSET)
+SET gLoongArchQemuPkgTokenSpaceGuid.PcdAllVarSize = $(VAR_ALL_SIZE)
+
+SET 

[edk2-devel] [edk2-platforms][PATCH V3 13/16] Platform/Loongson: Add Reset System Lib.

[xianglai]

This library provides interfaces related to restart and shutdown.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../BaseResetSystemAcpiGed.c  | 155 ++
 .../BaseResetSystemAcpiGedLib.inf |  42 +++
 .../DxeResetSystemAcpiGed.c   | 270 ++
 .../DxeResetSystemAcpiGedLib.inf  |  47 +++
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.c   | 128 +
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.h   |  20 ++
 6 files changed, 662 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGedLib.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGed.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGedLib.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.h

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
 
b/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
new file mode 100644
index 00..a50672410b
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
@@ -0,0 +1,155 @@
+/** @file
+  Base ResetSystem library implementation.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include "ResetSystemAcpiGed.h"
+#include 
+
+/**
+  Get configuration item data by the firmware configuration file name.
+
+  @param[in]  Name - Name of file to look up.
+
+  @returnVOID*   The Pointer of Value of Firmware Configuration item 
read.
+
+**/
+VOID *
+GetFwCfgData(
+CONST CHAR8   *Name
+)
+{
+  FIRMWARE_CONFIG_ITEM FwCfgItem;
+  EFI_STATUS   Status;
+  UINTNFwCfgSize;
+  VOID *Data;
+
+  Status = QemuFwCfgFindFile (Name, , );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "%a %d read  %s error Status %d \n", __func__, 
__LINE__, Name, Status));
+return NULL;
+  }
+
+  Data = AllocatePool (FwCfgSize);
+  if (Data == NULL) {
+return NULL;
+  }
+
+  QemuFwCfgSelectItem (FwCfgItem);
+  QemuFwCfgReadBytes (FwCfgSize, Data);
+
+  return Data;
+}
+
+/**
+  Find the power manager related info from ACPI table
+
+
+  @retval RETURN_SUCCESS Successfully find out all the required 
information.
+  @retval RETURN_NOT_FOUND   Failed to find the required info.
+
+**/
+STATIC EFI_STATUS
+GetPowerManagerByParseAcpiInfo (VOID)
+{
+  EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE*Fadt = NULL;
+  EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp = NULL;
+  EFI_ACPI_DESCRIPTION_HEADER  *Xsdt = NULL;
+  EFI_ACPI_DESCRIPTION_HEADER  *Rsdt = NULL;
+  VOID *AcpiTables = NULL;
+  UINT32   *Entry32 = NULL;
+  UINTN Entry32Num;
+  UINT32   *Signature = NULL;
+  UINTN Idx;
+
+  Rsdp = GetFwCfgData ("etc/acpi/rsdp");
+  if (Rsdp == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/rsdp error \n", __func__, 
__LINE__));
+return RETURN_NOT_FOUND;
+  }
+
+  AcpiTables = GetFwCfgData ("etc/acpi/tables");
+  if (AcpiTables == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/tables error \n", __func__, 
__LINE__));
+FreePool (Rsdp);
+return RETURN_NOT_FOUND;
+  }
+
+  Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +  
Rsdp->RsdtAddress);
+  Entry32= (UINT32 *)(Rsdt + 1);
+  Entry32Num = (Rsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+  for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+  Fadt = (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+  DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));
+  goto Done;
+}
+  }
+
+
+  Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +  
Rsdp->XsdtAddress);
+  Entry32= (UINT32 *)(Xsdt + 1);
+  Entry32Num = (Xsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+  for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+  Fadt = (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+  DEBUG ((DEBUG_INFO, "Found Fadt in Xsdt\n"));
+  goto Done;

[edk2-devel] [edk2-platforms][PATCH V3 12/16] Platform/Loongson: Add Platform Boot Manager Lib.

[xianglai]

The Library provides Boot Manager interfaces.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../PlatformBootManagerLib/PlatformBm.c   | 760 ++
 .../PlatformBootManagerLib/PlatformBm.h   | 112 +++
 .../PlatformBootManagerLib.inf|  78 ++
 .../PlatformBootManagerLib/QemuKernel.c   |  81 ++
 4 files changed, 1031 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/QemuKernel.c

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
 
b/Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
new file mode 100644
index 00..f58c43fa89
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/PlatformBootManagerLib/PlatformBm.c
@@ -0,0 +1,760 @@
+/** @file
+  Implementation for PlatformBootManagerLib library class interfaces.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "PlatformBm.h"
+
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+//
+// VENDOR_DEVICE_PATH SerialDxe
+//
+{
+{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) 
},
+SERIAL_DXE_FILE_GUID
+},
+
+//
+// UART_DEVICE_PATH Uart
+//
+{
+{ MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+0,  // Reserved
+FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
+FixedPcdGet8 (PcdUartDefaultDataBits),  // DataBits
+FixedPcdGet8 (PcdUartDefaultParity),// Parity
+FixedPcdGet8 (PcdUartDefaultStopBits)   // StopBits
+  },
+
+  //
+  // VENDOR_DEFINED_DEVICE_PATH TermType
+  //
+  {
+{
+  MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,
+  DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)
+}
+//
+// Guid to be filled in dynamically
+//
+  },
+
+  //
+  // EFI_DEVICE_PATH_PROTOCOL End
+  //
+  {
+END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+  }
+};
+
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
+  //
+  // USB_CLASS_DEVICE_PATH Keyboard
+  //
+  {
+{
+  MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP,
+  DP_NODE_LEN (USB_CLASS_DEVICE_PATH)
+},
+0x, // VendorId: any
+0x, // ProductId: any
+3,  // DeviceClass: HID
+1,  // DeviceSubClass: boot
+1   // DeviceProtocol: keyboard
+  },
+
+  //
+  // EFI_DEVICE_PATH_PROTOCOL End
+  //
+  {
+END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE,
+DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL)
+  }
+};
+
+/**
+  Locate all handles that carry the specified protocol, filter them with a
+  callback function, and pass each handle that passes the filter to another
+  callback.
+
+  @param[in] ProtocolGuid  The protocol to look for.
+
+  @param[in] FilterThe filter function to pass each handle to. If this
+   parameter is NULL, then all handles are processed.
+
+  @param[in] Process   The callback function to pass each handle to that
+   clears the filter.
+**/
+VOID
+FilterAndProcess (
+  IN EFI_GUID  *ProtocolGuid,
+  IN FILTER_FUNCTION   Filter OPTIONAL,
+  IN CALLBACK_FUNCTION Process
+  )
+{
+  EFI_STATUS Status;
+  EFI_HANDLE *Handles;
+  UINTN  NoHandles;
+  UINTN  Idx;
+
+  Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,
+  NULL /* SearchKey */, , );
+  if (EFI_ERROR (Status)) {
+//
+// This is not an error, just an informative condition.
+//
+DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,
+  Status));
+return;
+  }
+
+  ASSERT (NoHandles > 0);
+  for (Idx = 0; Idx < NoHandles; ++Idx) {
+CHAR16*DevicePathText;
+STATIC CHAR16 Fallback[] = L"";
+
+//
+// The ConvertDevicePathToText () function handles NULL input 
transparently.
+//
+DevicePathText = ConvertDevicePathToText (
+   DevicePathFromHandle (Handles[Idx]),
+   FALSE, // DisplayOnly
+   FALSE  // AllowShortcuts
+   );
+if (DevicePathText == NULL) {
+  DevicePathText = Fallback;
+}
+
+if ((Filter == NULL)
+  || (Filter (Handles[Idx], DevicePathText)))
+{
+  Process (Handles[Idx], DevicePathText);
+}
+
+if (DevicePathText != 

[edk2-devel] [edk2-platforms][PATCH V3 09/16] Platform/Loongson: Add PciCpuIoDxe driver.

[xianglai]

Add PCI CpuIo protocol.there is no fix translation
offset between I/O port accesses and MMIO accesses.
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for IO access.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c   | 548 ++
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.h   | 219 +++
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf |  40 ++
 3 files changed, 807 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
new file mode 100644
index 00..f5154eea7a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -0,0 +1,548 @@
+/** @file
+  Produces the CPU I/O 2 Protocol.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "PciCpuIo2Dxe.h"
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE  mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  0, // EfiCpuIoWidthFifoUint8
+  0, // EfiCpuIoWidthFifoUint16
+  0, // EfiCpuIoWidthFifoUint32
+  0, // EfiCpuIoWidthFifoUint64
+  1, // EfiCpuIoWidthFillUint8
+  2, // EfiCpuIoWidthFillUint16
+  4, // EfiCpuIoWidthFillUint32
+  8  // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+  1, // EfiCpuIoWidthUint8
+  2, // EfiCpuIoWidthUint16
+  4, // EfiCpuIoWidthUint32
+  8, // EfiCpuIoWidthUint64
+  1, // EfiCpuIoWidthFifoUint8
+  2, // EfiCpuIoWidthFifoUint16
+  4, // EfiCpuIoWidthFifoUint32
+  8, // EfiCpuIoWidthFifoUint64
+  0, // EfiCpuIoWidthFillUint8
+  0, // EfiCpuIoWidthFillUint16
+  0, // EfiCpuIoWidthFillUint32
+  0  // EfiCpuIoWidthFillUint64
+};
+
+/**
+  Check parameters to a CPU I/O 2 Protocol service request.
+
+  The I/O operations are carried out exactly as requested. The caller is 
responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+  be handled by the driver.
+
+  @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port 
operation.
+  @param[in] Width  Signifies the width of the I/O or Memory operation.
+  @param[in] AddressThe base address of the I/O operation.
+  @param[in] Count  The number of I/O operations to perform. The 
number of
+bytes moved is Width size * Count, starting at 
Address.
+  @param[in] Buffer For read operations, the destination buffer to 
store the results.
+For write operations, the source buffer from which 
to write data.
+
+  @retval EFI_SUCCESSThe parameters for this request pass the 
checks.
+  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width.
+  @retval EFI_UNSUPPORTEDThe address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+EFI_STATUS
+CpuIoCheckParameter (
+  IN BOOLEANMmioOperation,
+  IN EFI_CPU_IO_PROTOCOL_WIDTH  Width,
+  IN UINT64 Address,
+  IN UINTN  Count,
+  IN VOID   *Buffer
+  )
+{
+  UINT64  MaxCount;
+  UINT64  Limit;
+
+  //
+  // Check to see if Buffer is NULL
+  //
+  if (Buffer == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // Check to see if Width is in the valid range
+  //
+  if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  //
+  // For FIFO type, the target address won't increase during the access,
+  // so treat Count as 1
+  //
+  if ((Width >= EfiCpuIoWidthFifoUint8)
+&& (Width <= EfiCpuIoWidthFifoUint64))
+  {
+Count = 1;
+  }
+
+  //
+  // Check to see if Width is in the valid range for I/O Port operations
+  //
+  Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+  if ((!MmioOperation)
+&& (Width == EfiCpuIoWidthUint64))
+  {
+return EFI_INVALID_PARAMETER;
+  }
+
+  

[edk2-devel] [edk2-platforms][PATCH V3 08/16] Platform/Loongson: Add CPU DXE driver.

[xianglai]

The driver produces EFI_CPU_ARCH_PROTOCOL,
Initialize the exception entry address.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c  | 382 ++
 .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h  | 151 +++
 .../Drivers/CpuDxe/CpuDxe.inf |  56 +++
 .../Drivers/CpuDxe/LoongArch64/Exception.c| 338 
 .../Drivers/CpuDxe/LoongArch64/Fpu.S  |  67 +++
 .../Drivers/CpuDxe/LoongArch64/LoongArch.S| 292 +
 6 files changed, 1286 insertions(+)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Exception.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Fpu.S
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/LoongArch.S

diff --git a/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
new file mode 100644
index 00..bff2bd0c0a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
@@ -0,0 +1,382 @@
+/** @file
+  CPU DXE Module to produce CPU ARCH Protocol
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "CpuDxe.h"
+
+BOOLEAN mInterruptState   = FALSE;
+
+/*
+  This function flushes the range of addresses from Start to Start+Length
+  from the processor's data cache. If Start is not aligned to a cache line
+  boundary, then the bytes before Start to the preceding cache line boundary
+  are also flushed. If Start+Length is not aligned to a cache line boundary,
+  then the bytes past Start+Length to the end of the next cache line boundary
+  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+  supported. If the data cache is fully coherent with all DMA operations, then
+  this function can just return EFI_SUCCESS. If the processor does not support
+  flushing a range of the data cache, then the entire data cache can be 
flushed.
+
+  @param  This The EFI_CPU_ARCH_PROTOCOL instance.
+  @param  StartThe beginning physical address to flush from the 
processor's data
+   cache.
+  @param  Length   The number of bytes to flush from the processor's 
data cache. This
+   function may flush more bytes than Length specifies 
depending upon
+   the granularity of the flush operation that the 
processor supports.
+  @param  FlushTypeSpecifies the type of flush operation to perform.
+
+  @retval EFI_SUCCESS   The address range from Start to Start+Length 
was flushed from
+the processor's data cache.
+  @retval EFI_UNSUPPORTEDT  The processor does not support the cache flush 
type specified
+by FlushType.
+  @retval EFI_DEVICE_ERROR  The address range from Start to Start+Length 
could not be flushed
+from the processor's data cache.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+  IN EFI_CPU_ARCH_PROTOCOL   *This,
+  IN EFI_PHYSICAL_ADDRESSStart,
+  IN UINT64  Length,
+  IN EFI_CPU_FLUSH_TYPE  FlushType
+  )
+{
+
+  switch (FlushType) {
+case EfiCpuFlushTypeWriteBack:
+  WriteBackDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+  break;
+case EfiCpuFlushTypeInvalidate:
+  InvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+  break;
+case EfiCpuFlushTypeWriteBackInvalidate:
+  WriteBackInvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+  break;
+default:
+  return EFI_INVALID_PARAMETER;
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function enables interrupt processing by the processor.
+
+  @param  This The EFI_CPU_ARCH_PROTOCOL instance.
+
+  @retval EFI_SUCCESS   Interrupts are enabled on the processor.
+  @retval EFI_DEVICE_ERROR  Interrupts could not be enabled on the 
processor.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+  IN EFI_CPU_ARCH_PROTOCOL  *This
+  )
+{
+  EnableInterrupts ();
+
+  mInterruptState  = TRUE;
+  return EFI_SUCCESS;
+}
+
+
+/**
+  This function disables interrupt processing by the processor.
+
+  @param  This The EFI_CPU_ARCH_PROTOCOL instance.
+
+  @retval EFI_SUCCESS   Interrupts are disabled on the processor.
+  @retval EFI_DEVICE_ERROR  Interrupts could not be disabled on 

[edk2-devel] [edk2-platforms][PATCH V3 10/16] Platform/Loongson: Add timer Dxe driver.

[xianglai]

This driver produces Timer Architectural Protocol,
Registers a timer interrupt and initializes the timer.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Drivers/StableTimerDxe/Timer.c| 405 ++
 .../Drivers/StableTimerDxe/Timer.h| 165 +++
 .../Drivers/StableTimerDxe/TimerDxe.inf   |  40 ++
 3 files changed, 610 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/TimerDxe.inf

diff --git a/Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c 
b/Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
new file mode 100644
index 00..68742551ec
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/StableTimerDxe/Timer.c
@@ -0,0 +1,405 @@
+/** @file
+  Timer Architectural Protocol as defined in the DXE CIS
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include "Library/Cpu.h"
+#include 
+#include 
+#include "Timer.h"
+#include 
+#include 
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLEmTimerHandle = NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL   mTimer = {
+  TimerDriverRegisterHandler,
+  TimerDriverSetTimerPeriod,
+  TimerDriverGetTimerPeriod,
+  TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+//
+// The current period of the timer interrupt
+//
+volatile UINT64   mTimerPeriod = 0;
+volatile UINT64   mTimerTicks = 0;
+
+//
+// Const frequence in Hz
+//
+extern UINT32 StableTimerFreq;
+
+/**
+  Sets the counter value for timer.
+
+  @param CountThe 16-bit counter value to program into stable timer.
+
+  @retval VOID
+**/
+VOID
+SetPitCount (
+  IN UINT64  Count
+  )
+{
+  if (Count <= 4) {
+return;
+  }
+
+  Count &= LOONGARCH_CSR_TMCFG_TIMEVAL;
+  Count |= LOONGARCH_CSR_TMCFG_EN | LOONGARCH_CSR_TMCFG_PERIOD;
+  LOONGARCH_CSR_WRITEQ (Count, LOONGARCH_CSR_TMCFG);
+}
+
+/**
+  Timer Interrupt Handler.
+
+  @param InterruptTypeThe type of interrupt that occurred
+  @param SystemContextA pointer to the system context when the interrupt 
occurred
+
+  @retval VOID
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+  IN EFI_EXCEPTION_TYPE   InterruptType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext
+  )
+{
+  EFI_TPL OriginalTPL;
+
+  OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+  //
+  // Clear interrupt.
+  //
+  LOONGARCH_CSR_WRITEQ (0x1, LOONGARCH_CSR_TINTCLR);
+
+  if (mTimerNotifyFunction != NULL) {
+//
+// @bug : This does not handle missed timer interrupts
+//
+mTimerNotifyFunction (mTimerPeriod);
+  }
+
+  gBS->RestoreTPL (OriginalTPL);
+}
+
+/**
+
+  This function registers the handler NotifyFunction so it is called every time
+  the timer interrupt fires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
+  returned.  If the CPU does not support registering a timer interrupt handler,
+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a 
handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not 
registered,
+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+  is returned.
+
+
+  @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param NotifyFunction   The function to call when a timer interrupt fires.  
This
+  function executes at TPL_HIGH_LEVEL.  The DXE Core 
will
+  register a handler for the timer interrupt, so it 
can know
+  how much time has passed.  This information is used 
to
+  signal timer based events.  NULL will unregister the 
handler.
+
+  @retvalEFI_SUCCESSThe timer handler was registered.
+  @retvalEFI_UNSUPPORTEDThe platform does not support timer 
interrupts.
+  @retvalEFI_ALREADY_STARTEDNotifyFunction is not NULL, and a 
handler is already
+registered.
+  @retval  

[edk2-devel] [edk2-platforms][PATCH V3 11/16] Platform/Loongson: Add RealTime Clock lib.

[xianglai]

This library provides interfaces such as
real-time clock initialization
to get time and setting time.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../LsRealTimeClockLib/LsRealTimeClock.h  |  41 +++
 .../LsRealTimeClockLib/LsRealTimeClockLib.c   | 343 ++
 .../LsRealTimeClockLib/LsRealTimeClockLib.inf |  41 +++
 3 files changed, 425 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.inf

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
 
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
new file mode 100644
index 00..c98881e5d0
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClock.h
@@ -0,0 +1,41 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Copyright (c) 2021, Loongson Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef LS_REAL_TIME_CLOCK_H_
+#define LS_REAL_TIME_CLOCK_H_
+
+#define TOY_WRITE0_REG0x24
+#define TOY_WRITE1_REG0x28
+#define TOY_READ0_REG 0x2c
+#define TOY_READ1_REG 0x30
+#define RTC_CTRL_REG  0x40
+
+/* TOY Enable bits */
+#define RTC_ENABLE_BIT(1UL << 13)
+#define TOY_ENABLE_BIT(1UL << 11)
+#define OSC_ENABLE_BIT(1UL << 8)
+
+/*
+ * shift bits and filed mask
+ */
+#define TOY_MON_MASK  0x3f
+#define TOY_DAY_MASK  0x1f
+#define TOY_HOUR_MASK 0x1f
+#define TOY_MIN_MASK  0x3f
+#define TOY_SEC_MASK  0x3f
+#define TOY_MSEC_MASK 0xf
+
+#define TOY_MON_SHIFT 26
+#define TOY_DAY_SHIFT 21
+#define TOY_HOUR_SHIFT16
+#define TOY_MIN_SHIFT 10
+#define TOY_SEC_SHIFT 4
+
+#endif //__LS_REAL_TIME_CLOCK_H__
diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
 
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
new file mode 100644
index 00..78420ddfab
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/LsRealTimeClockLib/LsRealTimeClockLib.c
@@ -0,0 +1,343 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Copyright (c) 2021, Loongson Limited. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "LsRealTimeClock.h"
+
+STATIC BOOLEANmInitialized = FALSE;
+STATIC EFI_EVENT  mRtcVirtualAddrChangeEvent;
+STATIC UINTN  mRtcBase = 0X100d0100;
+/*
+  Enable Real-time clock.
+
+  @param VOID
+
+  @retval  VOID
+ */
+VOID
+InitRtc (
+  VOID
+  )
+{
+ UINTN  Val;
+
+  if (!mInitialized) {
+/* enable rtc */
+Val  = MmioRead32 (mRtcBase + RTC_CTRL_REG);
+Val |= TOY_ENABLE_BIT | OSC_ENABLE_BIT;
+MmioWrite32 (mRtcBase + RTC_CTRL_REG, Val);
+mInitialized = TRUE;
+  }
+}
+
+/**
+  Returns the current time and date information, and the time-keeping 
capabilities
+  of the hardware platform.
+
+  @param  Time   A pointer to storage to receive a snapshot of 
the current time.
+  @param  Capabilities   An optional pointer to a buffer to receive 
the real time clock
+ device's capabilities.
+
+  @retval EFI_SUCCESSThe operation completed successfully.
+  @retval EFI_INVALID_PARAMETER  Time is NULL.
+  @retval EFI_DEVICE_ERROR   The time could not be retrieved due to 
hardware error.
+  @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an 
authentication failure.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+  OUT EFI_TIME*Time,
+  OUT EFI_TIME_CAPABILITIES   *Capabilities
+  )
+{
+  UINT32  Val;
+
+  // Ensure Time is a valid pointer
+  if (Time == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  InitRtc ();
+  Val = MmioRead32 (mRtcBase + TOY_READ1_REG);
+  Time->Year = Val + 1900;
+
+  Val = MmioRead32 (mRtcBase + TOY_READ0_REG);
+  Time->Month =  (Val >> TOY_MON_SHIFT) & TOY_MON_MASK;
+  Time->Day   =  (Val >> TOY_DAY_SHIFT) & TOY_DAY_MASK;
+  Time->Hour  =  (Val >> TOY_HOUR_SHIFT) & TOY_HOUR_MASK;
+  Time->Minute = (Val >> TOY_MIN_SHIFT) & TOY_MIN_MASK;
+  Time->Second = (Val >> TOY_SEC_SHIFT) & TOY_SEC_MASK;
+  Time->Nanosecond  = 0;
+  return EFI_SUCCESS;
+}
+
+
+/**
+  Sets the current local time and date information.
+
+  @param  Time  A pointer to the current time.
+
+  @retval EFI_SUCCESS   The 

[edk2-devel] [edk2-platforms][PATCH V3 06/16] Platform/Loongson: Add StableTimerLib.

[xianglai]

This library provides a delay interface and a timing interface.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Include/Library/StableTimer.h |  43 
 .../Library/StableTimerLib/Count.S|  35 +++
 .../Library/StableTimerLib/TimerLib.c | 242 ++
 .../Library/StableTimerLib/TimerLib.inf   |  28 ++
 4 files changed, 348 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.inf

diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
new file mode 100644
index 00..09a2d07404
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/StableTimer.h
@@ -0,0 +1,43 @@
+/** @file
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- Csr- Cpu Status Register
+- Calc   - Calculation
+- Freq   - frequency
+**/
+
+#ifndef STABLE_TIMER_H_
+#define STABLE_TIMER_H_
+#include "Library/Cpu.h"
+
+/**
+  Gets the timer count value.
+
+  @param[] VOID
+
+  @retval  timer count value.
+**/
+extern
+UINTN
+EFIAPI
+LoongArchReadTime (
+  VOID
+  );
+
+/**
+  Calculate the timer frequency.
+
+  @param[] VOID
+
+  @retval  Timer frequency.
+**/
+UINT32
+EFIAPI
+CalcConstFreq (
+  VOID
+  );
+#endif
diff --git a/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S 
b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
new file mode 100644
index 00..f22635712c
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/Count.S
@@ -0,0 +1,35 @@
+#--
+#
+# Count for LoongArch
+#
+# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#--
+
+#ifndef __ASSEMBLY__
+#define  __ASSEMBLY__
+#endif
+
+#include "Library/Cpu.h"
+#include "LoongArchAsmMacro.h"
+#
+# Set cpu interrupts
+# @param A0 The interrupt number
+#
+ASM_FUNC(CpuSetIP)
+csrrd   T0, LOONGARCH_CSR_ECFG
+or  T0, T0, A0
+csrwr   T0, LOONGARCH_CSR_ECFG
+jirlZERO, RA,0
+
+#
+#Gets the timer count value.
+#
+#@param[] VOID
+#
+#@retval  timer count value.
+ASM_FUNC(LoongArchReadTime)
+rdtime.d   A0, ZERO
+jirlZERO, RA,0
diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c 
b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
new file mode 100644
index 00..660a5d8b0b
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.c
@@ -0,0 +1,242 @@
+/** @file
+  Generic LoongArch implementation of TimerLib.h
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- Freq - Frequency
+- Csr  - Cpu Status Register
+- calc - calculate
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include "Library/StableTimer.h"
+#include "Library/Cpu.h"
+
+UINT32 StableTimerFreq = 0;
+
+/**
+  Calculate the timer frequency.
+
+  @param[] VOID
+
+  @retval  Timer frequency.
+**/
+UINT32
+EFIAPI
+CalcConstFreq (
+  VOID
+  )
+{
+  UINT32 Result;
+  UINT32 BaseFreq;
+  UINT32 ClockMultiplier;
+  UINT32 ClockDivide;
+
+  LOONGARCH_GET_CPUCFG (BaseFreq, LOONGARCH_CPUCFG4);
+  LOONGARCH_GET_CPUCFG (Result, LOONGARCH_CPUCFG5);
+  ClockMultiplier = Result & 0x;
+  ClockDivide = (Result >> 16) & 0x;
+
+  if ((!BaseFreq)
+|| (!ClockMultiplier)
+|| (!ClockDivide))
+  {
+return 0;
+  }
+  else {
+return (BaseFreq * ClockMultiplier / ClockDivide);
+  }
+}
+/**
+  Get the timer frequency.
+
+  @param[] VOID
+
+  @retval  Timer frequency.
+**/
+UINT32
+EFIAPI
+GetFreq (
+  VOID
+  )
+{
+  if (StableTimerFreq) {
+  } else {
+StableTimerFreq = CalcConstFreq ();
+  }
+
+  return StableTimerFreq;
+}
+
+/**
+  Stalls the CPU for at least the given number of microseconds.
+
+  Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+  @param  MicroSeconds  The minimum number of microseconds to delay.
+
+  @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+  IN  UINTN MicroSeconds
+  )
+{
+
+  UINTN Count;
+  UINTN Ticks;
+  UINTN Start;
+  UINTN End;
+
+  Count = GetFreq ();
+  Count = (Count * MicroSeconds) / 100;
+  Start = LoongArchReadTime ();
+  End = Start + Count;
+
+  do {
+Ticks = LoongArchReadTime 

[edk2-devel] [edk2-platforms][PATCH V3 01/16] Platform/Loongson: Add Serial Port library

[xianglai]

Serial Port library for LoongarchQemuPkg

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../LoongArchQemuPkg/Include/Library/Cpu.h| 387 +++
 .../Include/LoongArchQemuPlatform.h   |  97 +++
 .../Library/SerialPortLib/SerialPortLib.c | 612 ++
 .../Library/SerialPortLib/SerialPortLib.inf   |  36 ++
 4 files changed, 1132 insertions(+)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/LoongArchQemuPlatform.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/SerialPortLib/SerialPortLib.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/SerialPortLib/SerialPortLib.inf

diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h
new file mode 100644
index 00..8c3c21bd96
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/Cpu.h
@@ -0,0 +1,387 @@
+/** @file
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- EXC - Exception
+- INT - Interrupt
+- FPU - Floating Point Unit
+- CSR - CPU Status Register
+- READQ   - Read Quad Word
+**/
+#ifndef LOONGARCH_CPU_H_
+#define LOONGARCH_CPU_H_
+
+/* Exception types decoded by machdep exception decoder */
+#define EXC_INT 0   /* HW interrupt */
+#define EXC_TLBL1   /* TLB miss on a load */
+#define EXC_TLBS2   /* TLB miss on a store */
+#define EXC_TLBI3   /* TLB miss on a ifetch */
+#define EXC_TLBM4   /* TLB modified fault */
+#define EXC_TLBRI   5   /* TLB Read-Inhibit exception */
+#define EXC_TLBXI   6   /* TLB Execution-Inhibit exception 
*/
+#define EXC_TLBPE   7   /* TLB Privilege Error */
+#define EXC_ADE 8   /* Address Error */
+#define EXC_ALE 9   /* Unalign Access */
+#define EXC_OOB 10  /* Out of bounds */
+#define EXC_SYS 11  /* System call */
+#define EXC_BP  12  /* Breakpoint */
+#define EXC_INE 13  /* Inst. Not Exist */
+#define EXC_IPE 14  /* Inst. Privileged Error */
+#define EXC_FPDIS   15  /* FPU Disabled */
+#define EXC_LSXDIS  16  /* LSX Disabled */
+#define EXC_LASXDIS 17  /* LASX Disabled */
+#define EXC_FPE 18  /* Floating Point Exception */
+#define EXC_WATCH   19  /* Watch address reference */
+#define EXC_BAD 255 /* Undecodeable */
+
+#define COPY_SIGCODE// copy sigcode above user stack in exec
+#define ZERO$r0 /* wired zero */
+#define RA  $r1 /* return address */
+#define GP  $r2 /* global pointer - caller saved for 
PIC */
+#define SP  $r3 /* stack pointer */
+#define V0  $r4 /* return value - caller saved */
+#define V1  $r5
+#define A0  $r4 /* argument registers */
+#define A1  $r5
+#define A2  $r6
+#define A3  $r7
+#define A4  $r8 /* arg reg 64 bit; caller saved in 32 
bit */
+#define A5  $r9
+#define A6  $r10
+#define A7  $r11
+#define T0  $r12 /* caller saved */
+#define T1  $r13
+#define T2  $r14
+#define T3  $r15
+#define T4  $r16 /* callee saved */
+#define T5  $r17
+#define T6  $r18
+#define T7  $r19
+#define T8  $r20 /* caller saved */
+#define TP  $r21 /* TLS */
+#define FP  $r22 /* frame pointer */
+#define S0  $r23 /* callee saved */
+#define S1  $r24
+#define S2  $r25
+#define S3  $r26
+#define S4  $r27
+#define S5  $r28
+#define S6  $r29
+#define S7  $r30
+#define S8  $r31 /* callee saved */
+
+#define FCSR0   $r0
+
+//
+// Location of the saved registers relative to ZERO.
+// Usage is p->p_regs[XX].
+//
+#define RA_NUM  1
+#define GP_NUM  2
+#define SP_NUM   

[edk2-devel] [edk2-platforms][PATCH V3 07/16] Platform/Loongson: Support PEI phase.

[xianglai]

Platform PEI module for LoongArch platform initialization.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Loongson/LoongArchQemuPkg/Loongson.dec|  22 ++
 .../Loongson/LoongArchQemuPkg/Loongson.dsc|  65 -
 .../Loongson/LoongArchQemuPkg/Loongson.fdf|  51 
 .../LoongArchQemuPkg/PlatformPei/Fv.c |  61 
 .../LoongArchQemuPkg/PlatformPei/MemDetect.c  | 108 +++
 .../LoongArchQemuPkg/PlatformPei/Platform.c   | 264 ++
 .../LoongArchQemuPkg/PlatformPei/Platform.h   |  87 ++
 .../PlatformPei/PlatformPei.inf   |  71 +
 8 files changed, 728 insertions(+), 1 deletion(-)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/Fv.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/MemDetect.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/Platform.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/PlatformPei/Platform.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/PlatformPei/PlatformPei.inf

diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
index 8cfa63ee8a..6a423f3ed6 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -30,7 +30,29 @@
 [PcdsFixedAtBuild, PcdsDynamic]
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvBase|0x0|UINT64|0x0008
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashDxeFvSize|0x0|UINT32|0x0009
+  gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreeBase|0x0|UINT64|0x0018
+  gLoongArchQemuPkgTokenSpaceGuid.PcdDeviceTreePadding|256|UINT32|0x0019
+
   gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamBase|0|UINT64|0x001c
   gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x001d
+  gLoongArchQemuPkgTokenSpaceGuid.PcdUefiRamTop|0x0|UINT64|0x001e
+  gLoongArchQemuPkgTokenSpaceGuid.PcdRamRegionsBottom|0x0|UINT64|0x0022
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvBase|0x0|UINT64|0x0028
   gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvSize|0x0|UINT32|0x0029
+
+[PcdsFixedAtBuild.LOONGARCH64]
+   gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32|UINT8|0x0010
+   gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0|UINT8|0x0011
+
+[PcdsDynamic]
+  gLoongArchQemuPkgTokenSpaceGuid.PcdRamSize|0x4000|UINT64|0x0041
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFwCfgSelectorAddress|0x0|UINT64|0x0042
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFwCfgDataAddress|0x0|UINT64|0x0043
+  gLoongArchQemuPkgTokenSpaceGuid.PcdSwapPageDir|0x0|UINT64|0x0044
+  gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPgd|0x0|UINT64|0x0045
+  gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPud|0x0|UINT64|0x0046
+  gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPmd|0x0|UINT64|0x0047
+  gLoongArchQemuPkgTokenSpaceGuid.PcdInvalidPte|0x0|UINT64|0x0048
+
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
index 52ab11de9a..1ca8cc09f7 100644
--- a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -57,22 +57,58 @@
 
 [LibraryClasses.common]
   PcdLib   | 
MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  TimerLib | 
Platform/Loongson/LoongArchQemuPkg/Library/StableTimerLib/TimerLib.inf
   PrintLib | 
MdePkg/Library/BasePrintLib/BasePrintLib.inf
   BaseMemoryLib| 
MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
 
 
   BaseLib  | MdePkg/Library/BaseLib/BaseLib.inf
+  PerformanceLib   | 
MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
   PeCoffLib| 
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  CacheMaintenanceLib  | 
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  UefiDecompressLib| 
MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
   PeCoffGetEntryPointLib   | 
MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
   IoLib| 
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
   SerialPortLib| 
Platform/Loongson/LoongArchQemuPkg/Library/SerialPortLib/SerialPortLib.inf
   DebugPrintErrorLevelLib  | 
MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+  FdtLib   | EmbeddedPkg/Library/FdtLib/FdtLib.inf
   PeCoffExtraActionLib | 
MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
   DebugAgentLib| 
MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
 
   DebugLib | 

[edk2-devel] [edk2-platforms][PATCH V3 05/16] Platform/Loongson: Add MmuLib.

[xianglai]

Read the memory map information through the QemuFwCfg interface,
then build the page table through the memory map information,
and finally enable Mmu.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../LoongArchQemuPkg/Include/Library/MmuLib.h |  85 ++
 .../LoongArchQemuPkg/Library/MmuLib/Mmu.S |  35 +
 .../Library/MmuLib/MmuBaseLib.inf |  35 +
 .../Library/MmuLib/MmuBaseLibPei.inf  |  42 +
 .../Library/MmuLib/MmuLibCore.c   | 908 ++
 .../Library/MmuLib/MmuLibCore.h   |  39 +
 .../Library/MmuLib/MmuLibCorePei.c| 236 +
 .../LoongArchQemuPkg/Library/MmuLib/mmu.h | 104 ++
 .../LoongArchQemuPkg/Library/MmuLib/page.h| 267 +
 .../LoongArchQemuPkg/Library/MmuLib/pte.h |  57 ++
 10 files changed, 1808 insertions(+)
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuBaseLib.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuBaseLibPei.inf
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuLibCore.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuLibCore.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/MmuLibCorePei.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/mmu.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/page.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/pte.h

diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h
new file mode 100644
index 00..6c501eca07
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/MmuLib.h
@@ -0,0 +1,85 @@
+/** @file
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- EXC - execute
+**/
+#ifndef MMU_LIB_H_
+#define MMU_LIB_H_
+/**
+  write operation is performed Count times from the first element of Buffer.
+Convert EFI Attributes to Loongarch Attributes.
+  @param[in]  EfiAttributes Efi Attributes.
+
+  @retval  LoongArch Attributes.
+**/
+UINTN
+EfiAttributeToLoongArchAttribute (
+  IN UINTN  EfiAttributes
+  );
+
+/**
+  Finds the length and memory properties of the memory region corresponding to 
the specified base address.
+
+  @param[in]  BaseAddressTo find the base address of the memory region.
+  @param[in]  EndAddress To find the end address of the memory region.
+  @param[out]  RegionLengthThe length of the memory region found.
+  @param[out]  RegionAttributesProperties of the memory region found.
+
+  @retval  EFI_SUCCESSThe corresponding memory area was successfully found
+   EFI_NOT_FOUNDNo memory area found
+**/
+EFI_STATUS
+GetLoongArchMemoryRegion (
+  IN UINTN  BaseAddress,
+  IN UINTN  EndAddress,
+  OUTUINTN  *RegionLength,
+  OUTUINTN  *RegionAttributes
+  );
+
+/**
+  Sets the Attributes  of the specified memory region
+
+  @param[in]  BaseAddress  The base address of the memory region to set the 
Attributes.
+  @param[in]  Length   The length of the memory region to set the 
Attributes.
+  @param[in]  Attributes   The Attributes to be set.
+
+  @retval  EFI_SUCCESSThe Attributes was set successfully
+
+**/
+EFI_STATUS
+LoongArchSetMemoryAttributes (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINTN Length,
+  IN UINTN Attributes
+  );
+
+/**
+  Sets the non-executable Attributes for the specified memory region
+
+  @param[in]  BaseAddress  The base address of the memory region to set the 
Attributes.
+  @param[in]  Length   The length of the memory region to set the 
Attributes.
+
+  @retval  EFI_SUCCESSThe Attributes was set successfully
+**/
+EFI_STATUS
+LoongArchSetMemoryRegionNoExec (
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN  UINTNLength
+  );
+/**
+  Create a page table and initialize the MMU.
+
+  @param[] VOID
+
+  @retval  VOID
+**/
+VOID
+EFIAPI
+ConfigureMmu (
+  VOID
+  );
+#endif
diff --git a/Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S 
b/Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S
new file mode 100644
index 00..a697b54e65
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Library/MmuLib/Mmu.S
@@ -0,0 +1,35 @@
+#--
+#
+# LoongArch for LoongArch
+#
+# Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#-
+
+#ifndef _KERNEL
+#define _KERNEL
+#endif
+

[edk2-devel] [edk2-platforms][PATCH V3 02/16] Platform/Loongson: Support SEC And Add Readme.md

[xianglai]

Add SEC Code And Readme.md for LoongArchQemu

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li  
Signed-off-by: xianglai li 
---
 Maintainers.txt   |   4 +
 .../Include/LoongArchAsmMacro.h   |  23 +
 .../Loongson/LoongArchQemuPkg/Loongson.dec|  36 ++
 .../Loongson/LoongArchQemuPkg/Loongson.dsc| 131 +
 .../Loongson/LoongArchQemuPkg/Loongson.fdf|  53 ++
 .../LoongArchQemuPkg/Loongson.fdf.inc |  21 +
 Platform/Loongson/LoongArchQemuPkg/Readme.md  |  59 ++
 .../LoongArchQemuPkg/Sec/LoongArch64/Start.S  |  76 +++
 .../Loongson/LoongArchQemuPkg/Sec/SecMain.c   | 510 ++
 .../Loongson/LoongArchQemuPkg/Sec/SecMain.inf |  47 ++
 Readme.md |   9 +
 11 files changed, 969 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.dec
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.fdf
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Loongson.fdf.inc
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Readme.md
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Sec/LoongArch64/Start.S
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Sec/SecMain.c
 create mode 100644 Platform/Loongson/LoongArchQemuPkg/Sec/SecMain.inf

diff --git a/Maintainers.txt b/Maintainers.txt
index 700ca0af60..8921d6b4e1 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -329,6 +329,10 @@ M: Bob Feng 
 M: Liming Gao 
 R: Yuwei Chen 
 
+Loongson platforms
+F: Platform/Loongson/
+M: xianglai li 
+
 Marvell platforms and silicon
 F: Platform/Marvell/
 F: Platform/SolidRun/Armada80x0McBin/
diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
new file mode 100644
index 00..366d4308e8
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/LoongArchAsmMacro.h
@@ -0,0 +1,23 @@
+/** @file
+   LoongArch ASM macro definition.
+
+   Copyright (c) 2021, Loongson Limited. All rights reserved.
+
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ **/
+
+#ifndef LOONGARCH_ASM_MACRO_H_
+#define LOONGARCH_ASM_MACRO_H_
+
+#include 
+
+#define _ASM_FUNC(Name, Section)\
+  .global   Name  ; \
+  .section  #Section, "ax"; \
+  .type Name, %function   ; \
+  Name:
+
+#define ASM_FUNC(Name)_ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+
+#endif // __LOONGARCH_ASM_MACRO_H__
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dec 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
new file mode 100644
index 00..8cfa63ee8a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dec
@@ -0,0 +1,36 @@
+## @file
+#
+#  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION  = 0x00010005
+  PACKAGE_NAME   = LoongArchQemuPkg
+  PACKAGE_GUID   = b51d765a-41da-45fc-a537-de3ee785c0f6
+  PACKAGE_VERSION= 0.1
+
+
+#
+# Include Section - list of Include Paths that are provided by this package.
+#   Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER 
DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+
+[Includes.common]
+  Include# Root include for the package
+
+[Guids]
+  gLoongArchQemuPkgTokenSpaceGuid  = { 0x0e0383ce, 0x0151, 0x4d01, { 0x80, 
0x0e, 0x3f, 0xef, 0x8b, 0x27, 0x6d, 0x52 } }
+
+[PcdsFixedAtBuild, PcdsDynamic]
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvBase|0x0|UINT64|0x0003
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashPeiFvSize|0x0|UINT32|0x0004
+  gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamBase|0|UINT64|0x001c
+  gLoongArchQemuPkgTokenSpaceGuid.PcdSecPeiTempRamSize|0|UINT32|0x001d
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvBase|0x0|UINT64|0x0028
+  gLoongArchQemuPkgTokenSpaceGuid.PcdFlashSecFvSize|0x0|UINT32|0x0029
diff --git a/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc 
b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
new file mode 100644
index 00..52ab11de9a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Loongson.dsc
@@ -0,0 +1,131 @@
+## @file
+#
+#  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Defines Section - statements that 

[edk2-devel] [edk2-platforms][PATCH V3 04/16] Platform/Loongson: Add QemuFwCfgLib.

[xianglai]

QemuFwCfgLib for PEI phase.
This library obtains the QemuFWCfg base address by
directly parsing the fdt, and reads and writes the data
in the QemuFWCfg by operating on the QemuFWCfg base address.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../Include/IndustryStandard/QemuFwCfg.h  |  95 
 .../Include/Library/QemuFwCfgLib.h| 193 +++
 .../QemuFwCfgLib/QemuFwCfgLibInternal.h   |  64 +++
 .../Library/QemuFwCfgLib/QemuFwCfgPei.c   | 119 +
 .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.c| 477 ++
 .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf  |  44 ++
 6 files changed, 992 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgLibInternal.h
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
new file mode 100644
index 00..a028ca1124
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/IndustryStandard/QemuFwCfg.h
@@ -0,0 +1,95 @@
+/** @file
+  Macro and type definitions corresponding to the QEMU fw_cfg interface.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- FW - FireWare
+- CFG- Configure
+- FNAME- File Name
+- CTL- Contorl
+**/
+
+#ifndef QEMU_FW_CFG_H_
+#define QEMU_FW_CFG_H_
+
+#include 
+
+//
+// The size, in bytes, of names of firmware configuration files, including at
+// least one terminating NUL byte.
+//
+#define QEMU_FW_CFG_FNAME_SIZE  56
+
+//
+// If the following bit is set in the UINT32 fw_cfg revision / feature bitmap
+// -- read from key 0x0001 with the basic IO Port or MMIO method --, then the
+// DMA interface is available.
+//
+#define FW_CFG_F_DMA BIT1
+
+//
+// Macros for the FW_CFG_DMA_ACCESS.Control bitmap (in native encoding).
+//
+#define FW_CFG_DMA_CTL_ERROR BIT0
+#define FW_CFG_DMA_CTL_READ  BIT1
+#define FW_CFG_DMA_CTL_SKIP  BIT2
+#define FW_CFG_DMA_CTL_SELECTBIT3
+#define FW_CFG_DMA_CTL_WRITE BIT4
+
+//
+// The fw_cfg registers can be found at these IO Ports, on the IO-mapped
+// platforms (Ia32 and X64).
+//
+#define FW_CFG_IO_SELECTOR  0x510
+#define FW_CFG_IO_DATA  0x511
+#define FW_CFG_IO_DMA_ADDRESS   0x514
+
+//
+// Numerically defined keys.
+//
+typedef enum {
+  QemuFwCfgItemSignature= 0x,
+  QemuFwCfgItemInterfaceVersion = 0x0001,
+  QemuFwCfgItemSystemUuid   = 0x0002,
+  QemuFwCfgItemRamSize  = 0x0003,
+  QemuFwCfgItemGraphicsEnabled  = 0x0004,
+  QemuFwCfgItemSmpCpuCount  = 0x0005,
+  QemuFwCfgItemMachineId= 0x0006,
+  QemuFwCfgItemKernelAddress= 0x0007,
+  QemuFwCfgItemKernelSize   = 0x0008,
+  QemuFwCfgItemKernelCommandLine= 0x0009,
+  QemuFwCfgItemInitrdAddress= 0x000a,
+  QemuFwCfgItemInitrdSize   = 0x000b,
+  QemuFwCfgItemBootDevice   = 0x000c,
+  QemuFwCfgItemNumaData = 0x000d,
+  QemuFwCfgItemBootMenu = 0x000e,
+  QemuFwCfgItemMaximumCpuCount  = 0x000f,
+  QemuFwCfgItemKernelEntry  = 0x0010,
+  QemuFwCfgItemKernelData   = 0x0011,
+  QemuFwCfgItemInitrdData   = 0x0012,
+  QemuFwCfgItemCommandLineAddress   = 0x0013,
+  QemuFwCfgItemCommandLineSize  = 0x0014,
+  QemuFwCfgItemCommandLineData  = 0x0015,
+  QemuFwCfgItemKernelSetupAddress   = 0x0016,
+  QemuFwCfgItemKernelSetupSize  = 0x0017,
+  QemuFwCfgItemKernelSetupData  = 0x0018,
+  QemuFwCfgItemFileDir  = 0x0019,
+
+} FIRMWARE_CONFIG_ITEM;
+
+//
+// Communication structure for the DMA access method. All fields are encoded in
+// big endian.
+//
+#pragma pack (1)
+typedef struct {
+  UINT32 Control;
+  UINT32 Length;
+  UINT64 Address;
+} FW_CFG_DMA_ACCESS;
+#pragma pack ()
+
+#endif
diff --git a/Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h 
b/Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
new file mode 100644
index 00..6b42cf3073
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Include/Library/QemuFwCfgLib.h
@@ -0,0 +1,193 @@
+/** @file
+  QEMU/KVM Firmware Configuration access
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- FW or Fw 

[edk2-devel] [edk2-platforms][PATCH V3 00/16] Platform: Add Loongson support.

[xianglai]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

The uploaded code generates firmware to support Linux launching on the 
LoongArch platform under qemu,
So it will run in a virtual machine.

LoongArch is the general processor architecture of Loongson.
You can get the latest LoongArch documents or LoongArch tools at 
https://github.com/loongson/.

You can also view the code through the Loongson community.
The edk2 code in Loongson community:
https://github.com/loongson/edk2/tree/LoongArch
The edk2-platform code in Loonson community:
https://github.com/loongson/edk2-platforms
The qemu code in Loongson community:
https://gitlab.com/qemu-project/qemu.git
The LoongArch Documentation in Loongson community:
https://github.com/loongson/LoongArch-Documentation/tree/main/docs
The all patches at:
https://github.com/loongson/edk2-platforms/tree/devel-LoongArch-patch

v2 changes:
 - Remove the inline assembly from StableTimerLib.
 - troubleshoot TAB strings, convert TAB characters to spaces.
 - remove smm related code, loongarch has no smm mode.

v3 changes:
 - delete ExtractHandler related code.
 - Boot UEFI with low 256M memory.
 - Modify common interrupt handling.

xianglai li (16):
  Platform/Loongson: Add Serial Port library
  Platform/Loongson: Support SEC And Add Readme.md
  Platform/Loongson: Add PeiServicesTablePointerLib.
  Platform/Loongson: Add QemuFwCfgLib.
  Platform/Loongson: Add MmuLib.
  Platform/Loongson: Add StableTimerLib.
  Platform/Loongson: Support PEI phase.
  Platform/Loongson: Add CPU DXE driver.
  Platform/Loongson: Add PciCpuIoDxe driver.
  Platform/Loongson:  Add timer Dxe driver.
  Platform/Loongson: Add RealTime Clock lib.
  Platform/Loongson: Add Platform Boot Manager Lib.
  Platform/Loongson: Add Reset System Lib.
  Platform/Loongson: Support Dxe
  Platform/Loongson: Add QemuFlashFvbServicesRuntimeDxe driver.
  Platform/Loongson: Support for saving variables to flash.

 Maintainers.txt   |4 +
 .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c  |  382 ++
 .../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h  |  151 +++
 .../Drivers/CpuDxe/CpuDxe.inf |   56 +
 .../Drivers/CpuDxe/LoongArch64/Exception.c|  338 +
 .../Drivers/CpuDxe/LoongArch64/Fpu.S  |   67 +
 .../Drivers/CpuDxe/LoongArch64/LoongArch.S|  292 +
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c   |  548 
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.h   |  219 
 .../Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf |   40 +
 .../QemuFlashFvbServicesRuntimeDxe/FvbInfo.c  |  115 ++
 .../FvbServicesRuntimeDxe.inf |   73 ++
 .../FwBlockService.c  | 1158 +
 .../FwBlockService.h  |  178 +++
 .../FwBlockServiceDxe.c   |  152 +++
 .../QemuFlash.c   |  251 
 .../QemuFlash.h   |   86 ++
 .../QemuFlashDxe.c|   21 +
 .../Drivers/StableTimerDxe/Timer.c|  405 ++
 .../Drivers/StableTimerDxe/Timer.h|  165 +++
 .../Drivers/StableTimerDxe/TimerDxe.inf   |   40 +
 .../Include/IndustryStandard/QemuFwCfg.h  |   95 ++
 .../LoongArchQemuPkg/Include/Library/Cpu.h|  387 ++
 .../LoongArchQemuPkg/Include/Library/MmuLib.h |   85 ++
 .../Include/Library/QemuFwCfgLib.h|  193 +++
 .../Include/Library/StableTimer.h |   43 +
 .../Include/LoongArchAsmMacro.h   |   23 +
 .../Include/LoongArchQemuPlatform.h   |   97 ++
 .../LsRealTimeClockLib/LsRealTimeClock.h  |   41 +
 .../LsRealTimeClockLib/LsRealTimeClockLib.c   |  343 +
 .../LsRealTimeClockLib/LsRealTimeClockLib.inf |   41 +
 .../LoongArchQemuPkg/Library/MmuLib/Mmu.S |   35 +
 .../Library/MmuLib/MmuBaseLib.inf |   35 +
 .../Library/MmuLib/MmuBaseLibPei.inf  |   42 +
 .../Library/MmuLib/MmuLibCore.c   |  908 +
 .../Library/MmuLib/MmuLibCore.h   |   39 +
 .../Library/MmuLib/MmuLibCorePei.c|  236 
 .../LoongArchQemuPkg/Library/MmuLib/mmu.h |  104 ++
 .../LoongArchQemuPkg/Library/MmuLib/page.h|  267 
 .../LoongArchQemuPkg/Library/MmuLib/pte.h |   57 +
 .../PeiServicesTablePointer.c |   78 ++
 .../PeiServicesTablePointerLib.inf|   32 +
 .../PlatformBootManagerLib/PlatformBm.c   |  760 +++
 .../PlatformBootManagerLib/PlatformBm.h   |  112 ++
 .../PlatformBootManagerLib.inf|   78 ++
 .../PlatformBootManagerLib/QemuKernel.c   |   81 ++
 .../QemuFwCfgLib/QemuFwCfgLibInternal.h   |   64 +
 .../Library/QemuFwCfgLib/QemuFwCfgPei.c   |  119 ++
 .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.c|  477 +++
 .../Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf  |   44 +
 .../BaseResetSystemAcpiGed.c  |  155 +++
 .../BaseResetSystemAcpiGedLib.inf |   42 +
 .../DxeResetSystemAcpiGed.c   

[edk2-devel] [edk2-platforms][PATCH V3 03/16] Platform/Loongson: Add PeiServicesTablePointerLib.

[xianglai]

Use a register to save PeiServicesTable pointer,
This lib Provides PeiServicesTable pointer saving
and retrieval services.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054

Signed-off-by: xianglai li 
---
 .../PeiServicesTablePointer.c | 78 +++
 .../PeiServicesTablePointerLib.inf| 32 
 2 files changed, 110 insertions(+)
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
 create mode 100644 
Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf

diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
 
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
new file mode 100644
index 00..068960d4ce
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
@@ -0,0 +1,78 @@
+/** @file
+  PEI Services Table Pointer Library.
+
+  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include "Library/Cpu.h"
+
+/**
+  Caches a pointer PEI Services Table.
+
+  Caches the pointer to the PEI Services Table specified by 
PeiServicesTablePointer
+  in a platform specific manner.
+
+  If PeiServicesTablePointer is NULL, then ASSERT ().
+
+  @paramPeiServicesTablePointer   The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+  IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+  )
+{
+  LOONGARCH_CSR_WRITEQ ((UINTN)PeiServicesTablePointer, LOONGARCH_CSR_KS0);
+}
+
+/**
+  Retrieves the cached value of the PEI Services Table pointer.
+
+  Returns the cached value of the PEI Services Table pointer in a CPU specific 
manner
+  as specified in the CPU binding section of the Platform Initialization 
Pre-EFI
+  Initialization Core Interface Specification.
+
+  If the cached PEI Services Table pointer is NULL, then ASSERT ().
+
+  @return  The pointer to PeiServices.
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+  VOID
+  )
+{
+  UINTN  val;
+
+  LOONGARCH_CSR_READQ (val, LOONGARCH_CSR_KS0);
+  return (CONST EFI_PEI_SERVICES **)val;
+}
+
+/**
+Perform CPU specific actions required to migrate the PEI Services Table
+pointer from temporary RAM to permanent RAM.
+
+For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
+a dedicated CPU register.  This means that there is no memory storage
+associated with storing the PEI Services Table pointer, so no additional
+migration actions are required for Itanium or ARM CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+VOID
+)
+{
+  return;
+}
diff --git 
a/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
 
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
new file mode 100644
index 00..6fe76d1351
--- /dev/null
+++ 
b/Platform/Loongson/LoongArchQemuPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
@@ -0,0 +1,32 @@
+## @file
+#  PEI Services Table Pointer Library.
+#
+#  Copyright (c) 2021 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = PeiServicesTablePointerLib
+  FILE_GUID  = C3C9C4ED-EB8A-4548-BE1B-ABB0B6F35B1E
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PeiServicesTablePointerLib|PEIM PEI_CORE SEC
+
+#
+#  VALID_ARCHITECTURES   = LOONGARCH64
+#
+
+[Sources]
+  PeiServicesTablePointer.c
+
+[Packages]
+  Platform/Loongson/LoongArchQemuPkg/Loongson.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  DebugLib
+
+[Pcd]
+
-- 
2.31.1



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Re: [edk2-devel] [PATCH V4 00/10] Introduce Lazy-accept for Tdx guest

[Min Xu]

On September 22, 2022 1:25 PM, Min Xu wrote:
> 
> Hi, Liming/Jian/Zhiguang/Michael
> Can you help to review below patches for the lazy-accept feature? Because
> you're the maintainer/reviewer of the related modules.
> Any comment is welcome.
>
There is still no comments received since last notification. Can 
Liming/Jian/Zhiguang/Michael provide your review comments about the lazy-accept 
feature?
> 
> [PATCH V4 01/10] MdeModulePkg: Add PrePiHob.h
> https://edk2.groups.io/g/devel/message/93671
> 
> [PATCH V4 02/10] MdePkg: Increase EFI_RESOURCE_MAX_MEMORY_TYPE
> https://edk2.groups.io/g/devel/message/93672
> 
> [PATCH V4 04/10] MdePkg: Add UEFI Unaccepted memory definition
> https://edk2.groups.io/g/devel/message/93674
> 
> [PATCH V4 05/10] MdeModulePkg: Update Dxe to handle unaccepted
> memory type
> https://edk2.groups.io/g/devel/message/93675
> 
> [PATCH V4 08/10] MdePkg: The prototype definition of
> EdkiiMemoryAcceptProtocol
> https://edk2.groups.io/g/devel/message/93678
> 

Thanks much!
Min


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