date:20240311

Re: [edk2-devel] [PATCH V1 0/3] OvmfPkg: Update TDVMCALL to avoid leaking secrets to the VMM

2024-03-11 Thread Yao, Jiewen

Reviewed-by: Jiewen Yao 

> -Original Message-
> From: Xu, Min M 
> Sent: Tuesday, February 27, 2024 2:49 PM
> To: Sun, CepingX ; devel@edk2.groups.io
> Cc: Liming Gao ; Kinney, Michael D
> ; Aktas, Erdem ; James
> Bottomley ; Yao, Jiewen ; Tom
> Lendacky ; Michael Roth
> ; Gerd Hoffmann ; Yamahata,
> Isaku 
> Subject: RE: [PATCH V1 0/3] OvmfPkg: Update TDVMCALL to avoid leaking secrets
> to the VMM
> 
> Reviewed-by: Min Xu 
> 
> > -Original Message-
> > From: Sun, CepingX 
> > Sent: Tuesday, February 27, 2024 5:19 AM
> > To: devel@edk2.groups.io
> > Cc: Sun, CepingX ; Liming Gao
> > ; Kinney, Michael D
> > ; Aktas, Erdem ;
> > James Bottomley ; Yao, Jiewen
> > ; Xu, Min M ; Tom Lendacky
> > ; Michael Roth ;
> > Gerd Hoffmann ; Yamahata, Isaku
> > 
> > Subject: [PATCH V1 0/3] OvmfPkg: Update TDVMCALL to avoid leaking secrets
> > to the VMM
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4696
> >
> > According to section 2.4.1 of [GHCI] spec, RBP register is usually used as a
> > frame pointer according to the C language calling convention.
> > The software should not use RBP as an input/output parameter and should
> > clear BIT5 (RBP) in the GPR mask in RCX.
> >
> > Reference:
> > [GHCI]: TDX Guest-Host-Communication Interface v1.5
> > https://cdrdv2.intel.com/v1/dl/getContent/726792
> >
> >
> > Cc: Liming Gao 
> > Cc: Michael D Kinney 
> > Cc: Erdem Aktas 
> > Cc: James Bottomley 
> > Cc: Jiewen Yao 
> > Cc: Min Xu 
> > Cc: Tom Lendacky 
> > Cc: Michael Roth 
> > Cc: Gerd Hoffmann 
> > Cc: Isaku Yamahata 
> > Signed-off-by: Ceping Sun 
> >
> > Ceping Sun (3):
> >   MdePkg/BaseLib: Update TDVMCALL_EXPOSE_REGS_MASK
> >   OvmfPkg/CcExitLib: Update TDVMCALL_EXPOSE_REGS_MASK
> >   OvmfPkg/TdxDxe: Clear the registers before tdcall
> >
> >  MdePkg/Library/BaseLib/X64/TdVmcall.nasm  |  2 +-
> >  .../Library/CcExitLib/X64/TdVmcallCpuid.nasm  |  2 +-
> >  OvmfPkg/TdxDxe/X64/ApRunLoop.nasm | 30 ---
> >  3 files changed, 28 insertions(+), 6 deletions(-)
> >
> > --
> > 2.34.1



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Re: [edk2-devel] [staging/dynamictables-reorg PATCH v1 0/2] DynamicTablesPkg: Arch Common Namespace

2024-03-11 Thread Sunil V L

On Mon, Mar 11, 2024 at 07:35:28AM -0700, Sami Mujawar wrote:
> Hi Sunil,
> 
> > How do we plan creating further patches? I am fine with any approach you
> > suggest but don't want to duplicate effort. I think it would be helpful
> > to know whether someone is already working on it.
> [SAMI] I am working on a patch series that moves the common objects from Arm 
> Namespace to Arch Common Namespace.
> Pierre is going to create a patch series for the corresponding edk2-platforms 
> updates for FVP & Juno.
> I think once we have reviewed and merged those, we can start looking at 
> reorganising the files and directory structure.
> Once this is completed, I think the arch specific patches can start being 
> reviewed and merged.
>
Hi Sami,
Great!. Thanks!

-Sunil


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[edk2-devel] [PATCH 1/1] MdeModulePkg/XhciDxe: Reset endpoint while USB Transaction error

2024-03-11 Thread Xianglei Cai

https://bugzilla.tianocore.org/show_bug.cgi?id=4556

Based on XHCI spec 4.8.3, software should do the
reset endpoint while USB Transaction occur.
Also add the error code for USB Transaction error
since UEFI spec don't have the related definition.

Cc: Hao A Wu 
Cc: Ray Ni   
Cc: Liming Gao   
Cc: Jenny Huang  
Cc: More Shih

Signed-off-by: Xianglei Cai 
---
 MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c  |  2 +-
 MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c |  2 +-
 MdePkg/Include/Protocol/UsbIo.h  | 21 +++--
 3 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c 
b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
index f4e61d223c1b..63cc29b26536 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
@@ -825,7 +825,7 @@ XhcTransfer (
   *TransferResult = Urb->Result;
   *DataLength = Urb->Completed;
 
-  if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == 
EFI_USB_ERR_BABBLE)) {
+  if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == 
EFI_USB_ERR_BABBLE) || (*TransferResult == EFI_USB_ERR_TRANSACTION)) {
 ASSERT (Status == EFI_DEVICE_ERROR);
 RecoveryStatus = XhcRecoverHaltedEndpoint (Xhc, Urb);
 if (EFI_ERROR (RecoveryStatus)) {
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c 
b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 05528a478baf..e77852f62f10 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -1193,7 +1193,7 @@ XhcCheckUrbResult (
 goto EXIT;
 
   case TRB_COMPLETION_USB_TRANSACTION_ERROR:
-CheckedUrb->Result  |= EFI_USB_ERR_TIMEOUT;
+CheckedUrb->Result  |= EFI_USB_ERR_TRANSACTION;
 CheckedUrb->Finished = TRUE;
 DEBUG ((DEBUG_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! 
Completecode = %x\n", EvtTrb->Completecode));
 goto EXIT;
diff --git a/MdePkg/Include/Protocol/UsbIo.h b/MdePkg/Include/Protocol/UsbIo.h
index a780b4e07b44..211ef0c94156 100644
--- a/MdePkg/Include/Protocol/UsbIo.h
+++ b/MdePkg/Include/Protocol/UsbIo.h
@@ -50,16 +50,17 @@ typedef enum {
 //
 // USB Transfer Results
 //
-#define EFI_USB_NOERROR 0x00
-#define EFI_USB_ERR_NOTEXECUTE  0x01
-#define EFI_USB_ERR_STALL   0x02
-#define EFI_USB_ERR_BUFFER  0x04
-#define EFI_USB_ERR_BABBLE  0x08
-#define EFI_USB_ERR_NAK 0x10
-#define EFI_USB_ERR_CRC 0x20
-#define EFI_USB_ERR_TIMEOUT 0x40
-#define EFI_USB_ERR_BITSTUFF0x80
-#define EFI_USB_ERR_SYSTEM  0x100
+#define EFI_USB_NOERROR  0x00
+#define EFI_USB_ERR_NOTEXECUTE   0x01
+#define EFI_USB_ERR_STALL0x02
+#define EFI_USB_ERR_BUFFER   0x04
+#define EFI_USB_ERR_BABBLE   0x08
+#define EFI_USB_ERR_NAK  0x10
+#define EFI_USB_ERR_CRC  0x20
+#define EFI_USB_ERR_TIMEOUT  0x40
+#define EFI_USB_ERR_BITSTUFF 0x80
+#define EFI_USB_ERR_SYSTEM   0x100
+#define EFI_USB_ERR_TRANSACTION  0x200
 
 /**
   Async USB transfer callback routine.
-- 
2.42.0.windows.2



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[edk2-devel] [PATCH] AMD/AmdPlatformPkg: Update AMD Vangogh platform reference code

2024-03-11 Thread Zhai, MingXin (Duke) via groups.io

From: Duke Zhai 

BZ #:4728

1.Use HPET timer to replace 8254 timer
2.Fix Bug Microcode version cannot show correctly at BIOS setup
3.Enable capsule at linux build
4.Update FspWrapper UPD table for BIOS setup options

Cc: Ken Yao 
Cc: Igniculus Fu 
Reviewed-by: Abner Chang 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 .../BIOSImageDirectory32M.xml |  2 +-
 .../ChachaniBoardPkg/GenCapsule.bat   |  2 +-
 .../VanGoghBoard/ChachaniBoardPkg/Project.dsc |  2 -
 .../VanGoghBoard/ChachaniBoardPkg/Project.fdf |  3 +-
 .../VanGoghBoard/ChachaniBoardPkg/build.sh| 22 +-
 .../edk2/Fsp2WrapperPkg/Include/FspmUpd.h | 71 ++-
 .../FspWrapperPlatformLibSample.c | 29 
 7 files changed, 59 insertions(+), 72 deletions(-)

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
index 22af6623e2..585e12d487 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
@@ -57,7 +57,7 @@
 
 
 
-
+
 
   
 
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
index 7dca22a4e3..c55f561772 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
@@ -36,7 +36,7 @@ if not exist %WORKSPACE%\%BIOS_FILE_NAME% (
   goto ERROR
 )
 
- Setup OpenSSL Command Line Environment
+echo Setup OpenSSL Command Line Environment
 if not "%OPENSSL_PATH%" == "" (
   set OPENSSL_PATH_TEMP=%OPENSSL_PATH%
 )
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
index 510ce10c0c..20f06dd851 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
@@ -745,8 +745,6 @@
   MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
   FatPkg/EnhancedFatDxe/Fat.inf
   PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
-  OvmfPkg/8259InterruptControllerDxe/8259.inf
-  OvmfPkg/8254TimerDxe/8254Timer.inf
   
MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
   
MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf
 
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
index 5194a8c10d..0d844689b3 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
@@ -416,8 +416,7 @@ NumBlocks = 0x100
   # Platform
   #
   INF  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
-  INF  OvmfPkg/8259InterruptControllerDxe/8259.inf
-  INF  OvmfPkg/8254TimerDxe/8254Timer.inf
+  INF  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
 
   #
   # ACPI
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
index f4652e91c6..0984876ef2 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
@@ -1,3 +1,4 @@
+#!/bin/bash
 ## @file
 # Linux build script file to launch Chachani Board BIOS build
 #
@@ -22,6 +23,7 @@ export OemBoard=Chachani
 export PLATFORM_PATH=edk2-platforms/Platform/AMD/VanGoghBoard
 export BUILD_TYPE=RELEASE
 export TOOLCHAIN_TAG=CLANGPDB
+export OTA_CAPSULE_NAME=OTACAPSULE # You need to keep this name sync with 
PlatformCapsule.fdf
 #TRUE / FALSE
 export COMPRESS_FSP_REGION=TRUE
 export KEY_MODE=TK
@@ -35,16 +37,25 @@ export NASM_PREFIX=
 export GCC5_BIN=
 #CLANG_BIN shall end with a slash.
 export CLANG_BIN=
+#OPENSSL_PATH shall end with a slash.
+export OPENSSL_PATH=
 
 echo "Building for ${OemBoard} board, ${BUILD_TYPE} mode with 
${TOOLCHAIN_TAG}."
-echo "IASL: ${IASL_PREFIX}iasl, NASM: ${NASM_PREFIX}nasm, GCC: ${GCC5_BIN}gcc, 
CLANG:${CLANG_BIN}clang."
+echo "IASL: ${IASL_PREFIX}iasl, NASM: ${NASM_PREFIX}nasm, GCC: ${GCC5_BIN}gcc, 
CLANG:${CLANG_BIN}clang, OPENSSL:${OPENSSL_PATH}openssl."
 [[ ${COMPRESS_FSP_REGION} == "TRUE" ]] && echo "FSP will be built with 
compress support."
 # Env check
 echo_section "Checking compilation environment"
 [[ "${IASL_PREFIX}" == "" ]] && export IASL_PREFIX=$(dirname $(which iasl))/
 [[ "${NASM_PREFIX}" == "" ]] && export NASM_PREFIX=$(dirname $(which nasm))/
+[[ "${OPENSSL_PATH}" == "" ]] && export OPENSSL_PATH=$(dirname $(which 
openssl))/
 [[ -f ${IASL_PREFIX}iasl ]] || (echo "IASL not found! Please specify 
IASL_PREFIX!";exit -1)
-[[ -f ${IASL_PREFIX}nasm ]] || (echo "NASM not found! Please specify 
NASM_PREFIX!";exit -1)
+[[ -f ${NASM_PREFIX}nasm ]] || (echo "NASM not found! Please specify 
NASM_PREFIX!";exit -1)
+[[ -f ${OPENSSL_PATH}openssl ]] || (echo "OpenSSL not found! Please specify 
OPENSSL_PATH!";exit -1)
+

[edk2-devel] Event: TianoCore Bug Triage - APAC / NAMO - Tuesday, March 12, 2024 #cal-reminder

2024-03-11 Thread Group Notification

*Reminder: TianoCore Bug Triage - APAC / NAMO*

*When:*
Tuesday, March 12, 2024
6:30pm to 7:30pm
(UTC-07:00) America/Los Angeles

*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTk1YzJhN2UtOGQwNi00NjY4LWEwMTktY2JiODRlYTY1NmY0%40thread.v2/0?context=%7b%22Tid%22%3a%2246c98d88-e344-4ed4-8496-4ed7712e255d%22%2c%22Oid%22%3a%226e4ce4c4-1242-431b-9a51-92cd01a5df3c%22%7d

*Organizer:* Liming Gao gaolim...@byosoft.com.cn ( 
gaolim...@byosoft.com.cn?subject=Re:%20Event:%20TianoCore%20Bug%20Triage%20-%20APAC%20%2F%20NAMO
 )

View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=2159769 )

*Description:*

TianoCore Bug Triage - APAC / NAMO

Hosted by Liming Gao



Microsoft Teams meeting

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Re: [edk2-devel] Cancelled Event: Tools, CI, Code base construction meeting series - Monday, March 11, 2024 #cal-cancelled

2024-03-11 Thread Sean

Not enough content requested here Tools and CI Meeting - vNext - Date TBD · 
tianocore/edk2 · Discussion #5366 (github.com) ( 
https://github.com/tianocore/edk2/discussions/5366 )
Cancelling the meeting for the week.


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[edk2-devel] Cancelled Event: Tools, CI, Code base construction meeting series - Monday, March 11, 2024 #cal-cancelled

2024-03-11 Thread Group Notification

BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Groups.io Inc//Groups.io Calendar//EN
METHOD:CANCEL
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-PUBLISHED-TTL:PT1H
CALSCALE:GREGORIAN
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
LAST-MODIFIED:20231222T233358Z
TZURL:https://www.tzurl.org/zoneinfo-outlook/America/Los_Angeles
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ORGANIZER;CN=devel@edk2.groups.io Group;SENT-BY="mailto:devel@edk2.groups
 .io":mailto:devel@edk2.groups.io
DTSTART:20240311T233000Z
DTEND:20240312T003000Z
SUMMARY:Tools\, CI\, Code base construction meeting series
DESCRIPTION:TianoCore community\,\n\nMicrosoft and Intel will be hosting 
 a series of open meetings to discuss build\, CI\, tools\, and other relat
 ed topics. If you are interested\, have ideas/opinions please join us. Th
 ese meetings will be Monday 4:30pm Pacific Time on Microsoft Teams.\n\nMS
  Teams Link in following discussion:\n* https://github.com/tianocore/edk2
 /discussions/2614\n\nAnyone is welcome to join.\n\n* tianocore/edk2: EDK 
 II (github.com)\n* tianocore/edk2-basetools: EDK II BaseTools Python tool
 s as a PIP module (github.com) https://github.com/tianocore/edk2-basetool
 s\n* tianocore/edk2-pytool-extensions: Extensions to the edk2 build syste
 m allowing for a more robust and plugin based build system and tool execu
 tion environment (github.com) https://github.com/tianocore/edk2-pytool-ex
 tensions\n* tianocore/edk2-pytool-library: Python library package that su
 pports UEFI development (github.com) https://github.com/tianocore/edk2-py
 tool-library\n\nMS Teams Browser Clients\n* https://docs.microsoft.com/en
 -us/microsoftteams/get-clients?tabs=Windows#browser-client
LOCATION:https://teams.microsoft.com/l/meetup-join/19%3ameeting_ZDI2ZDg4N
 mMtMjI1My00MzI5LWFmYjAtMGQyNjUzNTBjZGYw%40thread.v2/0?context=%7b%22Tid%2
 2%3a%2272f988bf-86f1-41af-91ab-2d7cd011db47%22%2c%22Oid%22%3a%2223af6561-
 6e1c-450d-b917-d9d674eb3cb6%22%7d
SEQUENCE:1
STATUS:CANCELLED
END:VEVENT
END:VCALENDAR


invite.ics
Description: application/ics

[edk2-devel] Event: Tools, CI, Code base construction meeting series - Monday, March 11, 2024 #cal-reminder

2024-03-11 Thread Group Notification

*Reminder: Tools, CI, Code base construction meeting series*

*When:*
Monday, March 11, 2024
4:30pm to 5:30pm
(UTC-07:00) America/Los Angeles

*Where:*
https://teams.microsoft.com/l/meetup-join/19%3ameeting_ZDI2ZDg4NmMtMjI1My00MzI5LWFmYjAtMGQyNjUzNTBjZGYw%40thread.v2/0?context=%7b%22Tid%22%3a%2272f988bf-86f1-41af-91ab-2d7cd011db47%22%2c%22Oid%22%3a%2223af6561-6e1c-450d-b917-d9d674eb3cb6%22%7d

View Event ( https://edk2.groups.io/g/devel/viewevent?eventid=2159774 )

*Description:*

TianoCore community,

Microsoft and Intel will be hosting a series of open meetings to discuss build, 
CI, tools, and other related topics. If you are interested, have ideas/opinions 
please join us. These meetings will be Monday 4:30pm Pacific Time on Microsoft 
Teams.

MS Teams Link in following discussion: * 
https://github.com/tianocore/edk2/discussions/2614

Anyone is welcome to join.

* tianocore/edk2: EDK II (github.com)
* tianocore/edk2-basetools: EDK II BaseTools Python tools as a PIP module 
(github.com) https://github.com/tianocore/edk2-basetools
* tianocore/edk2-pytool-extensions: Extensions to the edk2 build system 
allowing for a more robust and plugin based build system and tool execution 
environment (github.com) https://github.com/tianocore/edk2-pytool-extensions
* tianocore/edk2-pytool-library: Python library package that supports UEFI 
development (github.com) https://github.com/tianocore/edk2-pytool-library

MS Teams Browser Clients * 
https://docs.microsoft.com/en-us/microsoftteams/get-clients?tabs=Windows#browser-client


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[edk2-devel] [PATCH v2 0/3] MdeModulePkg: ImagePropertiesRecordLib Fixes

2024-03-11 Thread Oliver Smith-Denny

ImagePropertiesRecordLib is currently creating Image Records that
are not accurate. It is setting the CodeSegmentSize to be the size
of the raw data in the image file, however, when the image is
loaded into memory, the raw data size is aligned to the
section alignment. This caused the memory attributes table to
have incorrect entries for systems, like ARM64, where the section
alignment is not 4k for all modules.

In fixing this, I noticed that MemoryProtection.c is using its own
version of image record creation where this logic was actually
correct. ImagePropertiesRecordLib was created to consolidate the
logic around creating and managing image records, so this patchset
also updates MemoryProtection.c to use ImagePropertiesRecordsLib
after making a few small adjustments to ensure the same functionality
is present.

This patchset was tested on ArmVirtQemu to ensure that all image
records were the same before and after this, other than fixing
the CodeSegmentSize.

v2:
- Align VirtualSize instead of SizeOfRawData

Github PR: https://github.com/tianocore/edk2/pull/5402

Cc: Liming Gao 
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Sami Mujawar 
Cc: Taylor Beebe 

Oliver Smith-Denny (3):
  MdeModulePkg: ImagePropertiesRecordLib: Use SectionAlignment for
CodeSize
  MdeModulePkg: ImagePropertiesRecordLib: Consolidate Usage
  MdeModulePkg: MemoryProtection: Use ImageRecordPropertiesLib

 MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c| 241 
+++-
 MdeModulePkg/Library/ImagePropertiesRecordLib/ImagePropertiesRecordLib.c |  86 
+--
 2 files changed, 94 insertions(+), 233 deletions(-)

-- 
2.40.1



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Re: [edk2-devel] [PATCH v4] IntelFsp2Pkg: Fsp 2.x Changes

2024-03-11 Thread Nate DeSimone

Hi Chinni,

Switching from TopOfCar to SizeOfFspMemory doesn't address my previous 
feedback. Please also give this patch a better title. Adding new FSP-T Arch 
UPDs or something like that. Look forward to a V5 patch.

Thanks,
Nate

-Original Message-
From: Duggapu, Chinni B  
Sent: Wednesday, February 28, 2024 12:30 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Desimone, Nathaniel L 
; Chiu, Chasel ; 
Duggapu, Chinni B 
Subject: [PATCH v4] IntelFsp2Pkg: Fsp 2.x Changes

Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty 
Cc: Nate DeSimone 
Cc: Chiu Chasel 
Cc: Duggapu Chinni B 


Signed-off-by: Duggapu Chinni B 
---
 IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf |  2 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf   |  2 +-
 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf   |  1 +
 .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm   |  1 -
 .../FspSecCore/Ia32/FspApiEntryM.nasm |  1 -
 .../FspSecCore/Ia32/FspApiEntryT.nasm | 70 ++---
 .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 11 +++
 IntelFsp2Pkg/FspSecCore/SecFsp.c  | 17 +++-
 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c|  4 +-
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 78 +++
 IntelFsp2Pkg/Include/FspEas/FspApi.h  |  5 +-
 .../Include/SaveRestoreSseAvxNasm.inc | 21 +
 IntelFsp2Pkg/IntelFsp2Pkg.dec |  5 ++
 .../SecRamInitData.c  |  3 +-
 14 files changed, 185 insertions(+), 36 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
index cb011f99f9..cf8cb2eda9 100644
--- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -63,11 +63,11 @@
 

 [Pcd]

   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES

-  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported  ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize## CONSUMES

+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES

 

 [Ppis]

   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES

diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 8029832235..717941c33f 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -62,11 +62,11 @@
 

 [Pcd]

   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES

-  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize   ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported  ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize## CONSUMES

+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES

 

 [Ppis]

   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES

diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
index e5a6eaa164..05c0d5f48b 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
@@ -51,6 +51,7 @@
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase  ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize  ## CONSUMES

   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES

+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress  ## CONSUMES

 

 [Ppis]

   gEfiTemporaryRamSupportPpiGuid  ## PRODUCES

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
index 15f8ecea83..5fa5c03569 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs

 ;

 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))

-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))

 extern   ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))

 extern   ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))

 

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm 
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index 61ab4612a3..861cce4d01 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -11,7 +11,6 @@
 ; Following are fixed PCDs

 ;

 extern   ASM_PFX(PcdGet32(PcdTemporaryRamBase))

-extern   ASM_PFX(PcdGet32(PcdTemporaryRamSize))

 extern

Re: [edk2-devel] [PATCH] Maintainers.txt: remove Laszlo's entries

2024-03-11 Thread Laszlo Ersek

On 3/11/24 18:49, Pedro Falcato wrote:
> On Mon, Mar 11, 2024 at 3:04 AM Ni, Ray  wrote:
>>
>> This is a good idea to have a CREDITS file in edk2 repo.
>>
>> Pedro, would you mind initiating one?
> 
> Laszlo told me (in private) that he doesn't want a CREDITS entry for
> him, git log is enough.
> 
> So unless you have other people in mind, let's drop the idea :)
> 
> (FWIW, the idea was to have more or less the CREDITS in Linux - once
> people drop out of MAINTAINERS, move them there)

I guess for recruiters, a CREDITS file *is* more approachable than
git-log. Not sure what purposes CREDITS is supposed to serve, in
general. Either way, if Linux already has CREDITS (with an established
process around it -- I didn't know!), then it's probably not a bad idea;
but as you say, I wouldn't want to be the sole entry in it!

Thanks!
Laszlo



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Re: [edk2-devel] [PATCH] Maintainers.txt: remove Laszlo's entries

2024-03-11 Thread Laszlo Ersek

On 3/11/24 11:29, Zeng, Star wrote:
> Thank you Laszlo.
> 
> Is ler...@redhat.com still reachable for now ? 

March 14th is my last day at Red Hat; my email access will be revoked on
that day.

Laszlo



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Re: [edk2-devel][PATCH v1 1/3] MdeModulePkg: ImagePropertiesRecordLib: Use SectionAlignment for CodeSize

2024-03-11 Thread Oliver Smith-Denny

On 3/4/2024 2:38 PM, Oliver Smith-Denny wrote:

On 3/4/2024 11:24 AM, Oliver Smith-Denny wrote:

On 3/4/2024 10:54 AM, Ard Biesheuvel wrote:

On Mon, 4 Mar 2024 at 18:49, Oliver Smith-Denny
wrote:

Hi Ard,

On 3/1/2024 3:58 AM, Ard Biesheuvel wrote:

Hi Oliver,

On Tue, 27 Feb 2024 at 21:27, Oliver Smith-Denny
wrote:

- ImageRecordCodeSection->CodeSegmentSize =
Section[Index].SizeOfRawData;
+ ImageRecordCodeSection->CodeSegmentSize = ALIGN_VALUE
(Section[Index].SizeOfRawData, SectionAlignment);

This should be the virtual size, not the file size, right?

Correct, SectionAlignment is the alignment of the image as loaded in
memory, so in the case of a DXE runtime driver on ARM64, it will be
64k.

No, I mean we should not be using SizeOfRawData here but VirtualSize.

I understand this is unlikely to make a difference in practice, but
VirtualSize may exceed SizeOfRawData by a wide margin, and we need the
whole region to be covered.

I see, yes I do believe VirtualSize could be used here instead. Two
things give me pause. One is that the PE spec states that SizeOfRawData
is rounded and VirtualSize is not, so that SizeOfRawData may be greater
than the VirtualSize in some cases (which seems incorrect).

The other is that the image loader partially uses VirtualSize when
loading:

https://github.com/tianocore/edk2/blob/918288ab5a7c3abe9c58d576ccc0ae32e2c7dea0/MdePkg/Library/BasePeCoffLib/BasePeCoff.c#L1399-L1400

However, when determining the size of a loaded image (and therefore the
number of pages to allocate) it will allocate an extra page:

https://github.com/tianocore/edk2/blob/918288ab5a7c3abe9c58d576ccc0ae32e2c7dea0/MdeModulePkg/Core/Dxe/Image/Image.c#L646-L652

as ImageSize here is:

https://github.com/tianocore/edk2/blob/918288ab5a7c3abe9c58d576ccc0ae32e2c7dea0/MdePkg/Library/BasePeCoffLib/BasePeCoff.c#L312

Which according to the spec, SizeOfImage is the size of the image as
loaded into memory and must be a multiple of section alignment.

So, reflecting on this, let me test with VirtualSize here, I think
that is the right value to use, the only time we would have a
SizeOfRawData that is greater than the VirtualSize would be if our
FileAlignment is greater than our SectionAlignment, which would be
a misconfiguration.

I do think the ImageLoader should also be fixed to only allocate
ImageSize number of pages (which should be the sum of the section
VirtualSizes + any headers that aren't included). Might as well not
waste an extra page for each image and then our image record code is
simpler as well (ensuring we are protecting the right pages).

I think this patch series should go in, as it is fixing an active bug,
but I will also take a look at the image loader creating the image
records and having a protocol it produces to retrieve the list, to
attempt to avoid issues like this in the future.

Surprisingly, I am seeing that the VirtualSize is not 64k aligned there.
I am looking deeper into GenFw to make sure it is correctly getting set
to align to SectionAlignment in the section headers. When I use dumpbin
to dump the headers, it shows each section having VirtualSize as 64k
aligned for a runtime image, but the same image doesn't show that in FW.

I'll do some digging here.

Following up on this:

Not surprisingly, different toolchains do different things here.

gcc obviously creates ELF files and ElfConvert*.c converts these to PE
images. However, when it does this, it always sets the section and file
alignment to the same value (I'm not as familiar with ELF images, I'm
not sure if there is the same concept as file vs section alignment).
GenFw could probably update this information to shrink the file
alignment, but that's a space optimization for gcc built binaries.

In ElfConvert.c, the VirtualSize does get set to the section aligned
value, which is what I would expect from the spec.

In MSVC PE images, VirtualSize is not section aligned and the
expectation appears to be that loaders will align the VirtualSize
to the section alignment. I am planning on reaching out to the MSVC
folks to learn why this is the case, is it intended, etc., as my
understanding is that the VirtualSize in the section headers should
be section aligned.

We are stuck with this for existing MSVC toolchains, however, so we
will need to align either the VirtualSize or SizeOfRawData to the
section alignment when we create the image records. I don't have a
preference between the two, they end up being the same when we align
them, so I can send a v2 with aligning the VirtualSize. This will be
a no-op on gcc built binaries and will set it to the correct value for
MSVC.

Thanks,
Oliver

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Re: [edk2-devel] [PATCH] Maintainers.txt: remove Laszlo's entries

2024-03-11 Thread Pedro Falcato

On Mon, Mar 11, 2024 at 3:04 AM Ni, Ray  wrote:
>
> This is a good idea to have a CREDITS file in edk2 repo.
>
> Pedro, would you mind initiating one?

Laszlo told me (in private) that he doesn't want a CREDITS entry for
him, git log is enough.

So unless you have other people in mind, let's drop the idea :)

(FWIW, the idea was to have more or less the CREDITS in Linux - once
people drop out of MAINTAINERS, move them there)

-- 
Pedro


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Re: [edk2-devel] [PATCH 0/3] Platform/ARM: Remove ArmVExpressLibSec and CTA15-A7 support

2024-03-11 Thread PierreGondois


Hello Sami, Leif,
Just a ping in case the patch-set was forgotten,

Regards,
Pierre

On 2/14/24 14:26, Ard Biesheuvel wrote:

On Wed, 14 Feb 2024 at 13:44,  wrote:


From: Pierre Gondois 

Following the discussion at:
https://edk2.groups.io/g/devel/message/115378

Remove:
- the ArmVExpressLibSec module, containing the last reference to
   ArmCortexA9.h
- CTA15-A7 platform support
- files/modules used by the CTA15-A7 platform.

Pierre Gondois (3):
   Platform/ARM: Remove ArmVExpressLibSec
   Platform/ARM: Remove CTA15-A7 platform support
   Platform/ARM: Remove CTA15-A7 support



Reviewed-by: Ard Biesheuvel 



  .../ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc  | 286 
  .../ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf  | 299 
  .../VExpressPkg/ArmVExpress-FVP-AArch64.dsc   |   3 -
  Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc  |   7 +-
  .../Drivers/Isp1761UsbDxe/Isp1761UsbDxe.c | 636 --
  .../Drivers/Isp1761UsbDxe/Isp1761UsbDxe.h | 123 
  .../Drivers/Isp1761UsbDxe/Isp1761UsbDxe.inf   |  46 --
  .../Include/Platform/CTA15-A7/ArmPlatform.h   | 148 
  .../ArmVExpressLibCTA15-A7/ArmVExpressLib.inf |  44 --
  .../Library/ArmVExpressLibCTA15-A7/CTA15-A7.c | 176 -
  .../ArmVExpressLibCTA15-A7/CTA15-A7Helper.S   |  75 ---
  .../ArmVExpressLibCTA15-A7/CTA15-A7Mem.c  | 172 -
  .../ArmVExpressLibRTSM/Arm/RTSMHelper.S   |  91 ---
  .../ArmVExpressLibRTSM/ArmVExpressLib.inf |   3 -
  .../ArmVExpressLibRTSM/ArmVExpressLibSec.inf  |  49 --
  15 files changed, 1 insertion(+), 2157 deletions(-)
  delete mode 100644 Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc
  delete mode 100644 Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf
  delete mode 100644 
Platform/ARM/VExpressPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.c
  delete mode 100644 
Platform/ARM/VExpressPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.h
  delete mode 100644 
Platform/ARM/VExpressPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.inf
  delete mode 100644 
Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h
  delete mode 100644 
Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf
  delete mode 100644 
Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c
  delete mode 100644 
Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S
  delete mode 100644 
Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c
  delete mode 100644 
Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.S
  delete mode 100644 
Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf

--
2.25.1




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Re: [edk2-devel] [PATCH 0/2] ArmPkg: Remove ArmCortexA[5x|9].h files

2024-03-11 Thread PierreGondois


Hello Sami, Leif,
Just a ping in case the patch-set was forgotten,

Regards,
Pierre

On 2/14/24 14:26, Ard Biesheuvel wrote:

On Wed, 14 Feb 2024 at 13:42, PierreGondois  wrote:


Following the discussion at:
https://edk2.groups.io/g/devel/message/115378
remove ArmCortexA5x.h and ArmCortexA9.h files.
A patch-set for the edk2-platforms repository will be posted
to remove the remaining references.

Pierre Gondois (2):
   ArmPkg: Remove ArmCortexA5x.h
   ArmPkg: Remove ArmCortexA9.h



Reviewed-by: Ard Biesheuvel 


  ArmPkg/Include/Chipset/ArmCortexA5x.h | 44 -
  ArmPkg/Include/Chipset/ArmCortexA9.h  | 57 ---
  2 files changed, 101 deletions(-)
  delete mode 100644 ArmPkg/Include/Chipset/ArmCortexA5x.h
  delete mode 100644 ArmPkg/Include/Chipset/ArmCortexA9.h

--
2.25.1




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Re: [edk2-devel] [RFC PATCH 1/1] ArmPkg,MdePkg: move ArmLib.h to MdePkg

2024-03-11 Thread PierreGondois





On 3/1/24 12:45, Leif Lindholm wrote:

Thank you.

OK, that's logically consistent.
So we'd need an ArmLibNull in MdePkg until ArmLib itself migrates there
(ideally subsumed into BaseLib).


From what Jiewen said, it doesn't seem that creating an ArmLibNull
in the MdePkg is necessary (unless I misunderstood).

I will send a follow-up patch to the RFC tomorrow. Along the RFC patch,
it should be sufficient to move ArmLib to the MdePkg,

Regards,
Pierre



But the dependency in .inf should still be able to be declared under
[LibraryClasses.AArch64, LibraryClasses.ARM]?

Regards,

Leif

On 2024-03-01 01:00, Yao, Jiewen wrote:

Sure.

When we say "dependency", what we really mean is the dependency in INF file, not 
"dependency" in DSC file.

  From package release perspective, only INF is the interface to other package.
The DSC is only the package internal stuff, you can create multiple DSCs or 
add/remove DSC freely.

Having "dependency" in DSC does not matter.
Having dependency in INF is something we should care about.

Thank you
Yao, Jiewen



-Original Message-
From: Leif Lindholm 
Sent: Tuesday, February 13, 2024 1:38 AM
To: Pierre Gondois ; devel@edk2.groups.io; Yao,
Jiewen 
Cc: Ard Biesheuvel ; Liming Gao
; Kinney, Michael D ;
Sami Mujawar ; Liu, Zhiguang

Subject: Re: [RFC PATCH 1/1] ArmPkg,MdePkg: move ArmLib.h to MdePkg

Jiewen, can you clarify what you said back in
https://edk2.groups.io/g/devel/message/111551
?

On 2024-02-12 17:24, Pierre Gondois wrote:

A ArmLibNull.inf library might also need to be created. If the
OpensslLibFullAccel.inf module will depend on the ArmLib library,
a Null implementation will be necessary for non-Arm architectures.


Can ArmLib be declared under a [LibraryClasses.AArch64,
LibraryClasses.ARM]? Have I forgotten something that we discussed back
in ... November?


   From [1], it seems the MdePkg/CryptoPkg should build without a dependency
on the ArmPkg. This is currently not really the case. cf. [2].

However, having a ArmLibNull implementation in the MdePkg would allow to
avoid going in this direction when providing libraries to CryptoPkg.dsc.

(Just in case, I think this ArmLibNull is a minor point.)


Well, sure, it is now.
Until we need a RiscV64LibNull, LoongarchLibNull, ...


[1] https://edk2.groups.io/g/devel/message/111545
[2]


https://github.com/tianocore/edk2/blob/8801c75b4d77c2e6e06b3ddc8560e0db
590f6342/CryptoPkg/CryptoPkg.dsc#L117





Otherwise I could apply and run the CryptoPkg/Arm native instructions
patchset on top of this patch.

---

As a side note, it also seems that:
- ArmPkg/Include/Chipset/ArmCortexA5x.h
      isn't used anymore in edk2/edk2-platorms
- ArmPkg/Include/Chipset/ArmCortexA9.h
      is barely used in edk2-platforms.
Maybe the files should have been removed/simplified as part of
- cffa7925a293 ("ArmPkg: remove ArmCpuLib header and implementations")
- a913ad02479d ("ArmPlatformPkg: remove ArmVExpressPkg")


I think you're right.
Well, ArmCortexA9.h is still *used*, but I can't imagine the Arm branch
of ArmVExpressLib has been build by anyone for some time. And surely the
inclusion of ArmVExpressLibSec in ArmVExpress-FVP-AArch64.dsc is
superfluous (such that that .inf can be deleted)?


The file could just be moved in the Library. I assume you/Sami/Ard
will know more on the usage of the library itself,


Sami?

/
   Leif








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Re: [edk2-devel] [PATCH] MdeModulePkg/Xhci: Skip another size round up for TRB address translation

2024-03-11 Thread Dat Mach via groups.io

Thank you all for your support. :)
-Dat

-Original Message-
From: Cheng, Gao  
Sent: Sunday, March 10, 2024 9:46 PM
To: Wu, Hao A ; Dat Mach ; gaoliming 
; devel@edk2.groups.io
Cc: Ni, Ray 
Subject: RE: [PATCH] MdeModulePkg/Xhci: Skip another size round up for TRB 
address translation

External email: Use caution opening links or attachments


Hi Dat,

Thanks for catching this corner case. The code change looks good to me.

Best Regards,
Gao

-Original Message-
From: Wu, Hao A 
Sent: Monday, March 11, 2024 11:27 AM
To: Dat Mach ; gaoliming ; 
devel@edk2.groups.io
Cc: Cheng, Gao ; Ni, Ray 
Subject: RE: [PATCH] MdeModulePkg/Xhci: Skip another size round up for TRB 
address translation

No additional comment from my side.

Best Regards,
Hao Wu

> -Original Message-
> From: Dat Mach 
> Sent: Saturday, March 9, 2024 7:33 AM
> To: gaoliming ; devel@edk2.groups.io
> Cc: Cheng, Gao ; Wu, Hao A ; 
> Ni, Ray 
> Subject: RE: [PATCH] MdeModulePkg/Xhci: Skip another size round up for 
> TRB address translation
>
> Hi Gao and Hao,
>
> Could you please take a look at my patch and see if anything I might 
> have missed?
>
> Thanks,
> Dat
>
> -Original Message-
> From: gaoliming 
> Sent: Monday, March 4, 2024 4:34 PM
> To: Dat Mach ; devel@edk2.groups.io
> Cc: gao.ch...@intel.com; hao.a...@intel.com; ray...@intel.com
> Subject: 回复: [PATCH] MdeModulePkg/Xhci: Skip another size round up for 
> TRB address translation
>
> External email: Use caution opening links or attachments
>
>
> This change looks good. Reviewed-by: Liming Gao 
> 
>
> Cheng and Hao:
>   Have you any comments for this patch?
>
> Thanks
> Liming
> > -邮件原件-
> > 发件人: Dat Mach 
> > 发送时间: 2024年2月26日 10:00
> > 收件人: devel@edk2.groups.io
> > 抄送: gao.ch...@intel.com; hao.a...@intel.com; ray...@intel.com; 
> > gaolim...@byosoft.com.cn; Dat Mach 
> > 主题: [PATCH] MdeModulePkg/Xhci: Skip another size round up for TRB 
> > address translation
> >
> > REF:https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%
> > 2F
> >
> bugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D4560=05%7C02%7Cd
> mach
> > %40nvidia.com%7C135326cf31634dbe703e08dc3cac0417%7C43083d1572
> 7340c1b7d
> >
> b39efd9ccc17a%7C0%7C0%7C638451956723393894%7CUnknown%7CTWFp
> bGZsb3d8eyJ
> >
> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> 7C0%7C
> > %7C%7C=JlpbOr0QHodUF7QDJZl5gY88maLemat4ktudCyDShMQ%3D
> =0
> >
> > Commit f36e1ec1f0a5fd3be84913e09181d7813444b620 had fixed the 
> > DXE_ASSERT caused by the TRB size round up from 16 to 64 for most 
> > cases.
> >
> > However, there is a remaining case that the TRB size is also rounded 
> > up during setting TR dequeue pointer that would trigger DXE_ASSERT.
> >
> > This patch sets the alignment flag to FALSE in 
> > XhcSetTrDequeuePointer to fix this issue as well.
> >
> > Signed-off-by: Dat Mach 
> > ---
> >  MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 2 +- 
> > MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 2 +-
> >  2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
> > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
> > index 05528a478b..5d735008ba 100644
> > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
> > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
> > @@ -3539,7 +3539,7 @@ XhcSetTrDequeuePointer (
> >// Send stop endpoint command to transit Endpoint from running to 
> > stop state
> >//
> >ZeroMem (, sizeof (CmdSetTRDeq));
> > -  PhyAddr  = UsbHcGetPciAddrForHostAddr (Xhc->MemPool,
> > Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE);
> > +  PhyAddr  = UsbHcGetPciAddrForHostAddr
> > (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof 
> > (CMD_SET_TR_DEQ_POINTER), FALSE);
> >CmdSetTRDeq.PtrLo= XHC_LOW_32BIT (PhyAddr) |
> > Urb->Ring->RingPCS;
> >CmdSetTRDeq.PtrHi= XHC_HIGH_32BIT (PhyAddr);
> >CmdSetTRDeq.CycleBit = 1;
> > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
> > b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
> > index 53272f62dd..c956e45907 100644
> > --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
> > +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
> > @@ -2526,7 +2526,7 @@ XhcPeiSetTrDequeuePointer (
> >// Send stop endpoint command to transit Endpoint from running to 
> > stop state
> >//
> >ZeroMem (, sizeof (CmdSetTRDeq));
> > -  PhyAddr  = UsbHcGetPciAddrForHostAddr (Xhc->MemPool,
> > Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE);
> > +  PhyAddr  = UsbHcGetPciAddrForHostAddr
> > (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof 
> > (CMD_SET_TR_DEQ_POINTER), FALSE);
> >CmdSetTRDeq.PtrLo= XHC_LOW_32BIT (PhyAddr) |
> > Urb->Ring->RingPCS;
> >CmdSetTRDeq.PtrHi= XHC_HIGH_32BIT (PhyAddr);
> >CmdSetTRDeq.CycleBit = 1;
> > --
> > 2.44.0.rc2
>
>



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Re: [edk2-devel] [PATCH V2] Pkg-Module: Silicon/Marvell

2024-03-11 Thread Marcin Wojtas

wt., 20 lut 2024 o 11:35 Gahan Saraiya  napisał(a):
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4689
>
> Bug 4689 - GetInfo() of Adapter Information Protocol
> should have a provision for IHV to return no data for
> UEFI Spec compliance 2.9 [mantis #1866]
>
> Cc: Marcin Wojtas 
> Cc: Leif Lindholm 
> Signed-off-by: Gahan Saraiya 
> ---
>  Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c 
> b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> index 5e463ac932..517b21940d 100644
> --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> @@ -1394,6 +1394,7 @@ Pp2DxeSnpInstall (
>
>@retval EFI_SUCCESSThe InformationType information was 
> retrieved.
>@retval EFI_UNSUPPORTEDThe InformationType is not known.
> +  @retval EFI_NOT_FOUND  Information is not available for the 
> requested information type.
>@retval EFI_DEVICE_ERROR   The device reported an error.
>@retval EFI_OUT_OF_RESOURCES   The request could not be completed due 
> to a lack of resources.
>@retval EFI_INVALID_PARAMETER  This is NULL.
> --
> 2.39.2.windows.1
>

Reviewed-by: Marcin Wojtas 

Thanks!


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Re: [edk2-devel] [edk2-platforms][PATCH v5 9/9] Platform/Sgi: Add CPPC support for RD-Fremont platform

2024-03-11 Thread levi.yun

Reviewed-by: levi.yun 


From: devel@edk2.groups.io  on behalf of Prabin CA via 
groups.io 
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 9/9] Platform/Sgi: Add CPPC 
support for RD-Fremont platform

Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set the
desired performance. In addition to this, RD-Fremont platform does not
support CPPC revision 1 and below. So update the _OSC method to let OSPM
know about this fact.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf |   1 +
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 162 

 2 files changed, 163 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
index 7556c1239116..fcaa3299c4ea 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -48,6 +48,7 @@ [FixedPcd]
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
   gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
   gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdOscCppcEnable
   gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
index f921eeb2d99e..9c7266c79285 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -11,6 +11,10 @@
 *   - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States
 *   - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1,
 * Idle management and Low Power Idle states
+*   - ACPI 6.5, Chapter 8, Section 8.4.6, Collaborative Processor Performance
+* Control
+*   - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.2,
+* Performance management and Collaborative Processor Performance Control
 *
 **/

@@ -43,6 +47,20 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
   Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
 }
   }
+
+  If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+/* CPPC revision 1 and below not supported */
+And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+
+  If (And (CAP0, OSC_CAP_CPPC2_SUPPORT)) {
+if (LEqual (FixedPcdGet32 (PcdOscCppcEnable), Zero)) {
+  And (CAP0, Not (OSC_CAP_CPPC2_SUPPORT), CAP0)
+  Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+}
+  }
+
 } Else {
   And (STS0, Not (OSC_STS_MASK), STS0)
   Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -116,6 +134,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 0)
 Name (_STA, 0xF)

+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200093000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (0)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -131,6 +158,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 1)
 Name (_STA, 0xF)

+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200293000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (1)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -146,6 +182,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 2)
 Name (_STA, 0xF)

+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200493000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (2)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -161,6 +206,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 3)
 Name (_STA, 0xF)

+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200693000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (3)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -176,6 +230,15 @@ DefinitionBlock

Re: [edk2-devel] [staging/dynamictables-reorg PATCH v1 0/2] DynamicTablesPkg: Arch Common Namespace

2024-03-11 Thread Sami Mujawar

Hi Sunil,

> How do we plan creating further patches? I am fine with any approach you
> suggest but don't want to duplicate effort. I think it would be helpful
> to know whether someone is already working on it.
[SAMI] I am working on a patch series that moves the common objects from Arm 
Namespace to Arch Common Namespace.
Pierre is going to create a patch series for the corresponding edk2-platforms 
updates for FVP & Juno.
I think once we have reviewed and merged those, we can start looking at 
reorganising the files and directory structure.
Once this is completed, I think the arch specific patches can start being 
reviewed and merged.
[/SAMI]

Regards,

Sami Mujawar

> Thanks!
> Sunil





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Re: [edk2-devel] [edk2-platforms][PATCH v5 7/9] Platform/Sgi: Extend SMBIOS support for RD-Fremont

2024-03-11 Thread levi.yun

Reviewed-by: levi.yun 


From: devel@edk2.groups.io  on behalf of Prabin CA via 
groups.io 
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 7/9] Platform/Sgi: Extend 
SMBIOS support for RD-Fremont

Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 
+
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 5 
-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 5 
-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 1 +
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 
++
 5 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h 
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 6fa39d407bc9..acfa45910aed 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -51,6 +51,10 @@
 #define RD_V2_PART_NUM0x7F2
 #define RD_V2_CONF_ID 0x1

+// RD-Fremont Platform Identification values
+#define RD_Fremont_PART_NUM   0x7EE
+#define RD_Fremont_CONF_ID0x1
+
 #define SGI_CONFIG_MASK   0x0F
 #define SGI_CONFIG_SHIFT  0x1C
 #define SGI_PART_NUM_MASK 0xFFF
@@ -90,6 +94,7 @@ typedef enum {
   RdN2Cfg1,
   RdN2Cfg2,
   RdV2,
+  RdFremont,
 } ARM_RD_PRODUCT_ID;

 // Arm ProductId look-up table
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index edf2a5f63c63..9c28b051ebc2 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -34,7 +34,8 @@
   "RdN2\0"  \
   "RdN2Cfg1\0"  \
   "RdN2Cfg2\0"  \
-  "RdV2\0"
+  "RdV2\0"  \
+  "RdFremont\0"

 typedef enum {
   ManufacturerName = 1,
@@ -74,6 +75,8 @@ STATIC GUID mSmbiosUid[] = {
   {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 
0x60}},
   /* Rd-V2 */
   {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 
0x45}},
+  /* Rd-Fremont*/
+  {0x904b28d6, 0x0662, 0x11ed, {0xb9, 0x39, 0x02, 0x42, 0xac, 0x12, 0x00, 
0x02}},
 };

 /* System information */
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index ee269f707714..c39c1553f6aa 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -44,6 +44,7 @@
   "Neoverse-N2\0"   \
   "Neoverse-N2\0"   \
   "Neoverse-V2\0"   \
+  "Neoverse-Poseidon\0" \
   "000-0\0" /* Serial number */ \
   "783-3\0" \
   "786-1\0" \
@@ -54,7 +55,8 @@
   "7B7-1\0" \
   "7B6-1\0" \
   "7B7-1\0" \
-  "7F2-1\0"
+  "7F2-1\0" \
+  "7EE-1\0"

 typedef enum {
   PartNumber = 1,
@@ -181,6 +183,7 @@ InstallType4ProcessorInformation (
   case RdN2:
   case RdN2Cfg1:
   case RdV2:
+  case RdFremont:
 mArmRdSmbiosType4.Base.CoreCount = CoreCount;
 mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
 mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index 4af72919a3f1..4cdea5b3b763 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -335,6 +335,7 @@ InstallType7CacheInformation (
 mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
 break;
   case RdV2:
+  case RdFremont:
 /* L1 instruction cache */

Re: [edk2-devel] [edk2-platforms][PATCH v5 8/9] Platform/Sgi: Low Power Idle States for RD-Fremont

2024-03-11 Thread levi.yun

Reviewed-by: levi.yun 


From: devel@edk2.groups.io  on behalf of Prabin CA via 
groups.io 
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 8/9] Platform/Sgi: Low Power 
Idle States for RD-Fremont

RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf |   1 +
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 154 

 2 files changed, 155 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
index 9d07001dec96..7556c1239116 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -48,6 +48,7 @@ [FixedPcd]
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
   gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
   gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
index 8812ea877f7a..f921eeb2d99e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -8,6 +8,9 @@
 * @par Specification Reference:
 *   - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description
 * Table (DSDT)
+*   - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States
+*   - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1,
+* Idle management and Low Power Idle states
 *
 **/

@@ -17,6 +20,93 @@
 DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
  EFI_ACPI_ARM_OEM_REVISION) {
   Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+
+  If (And (CAP0, OSC_CAP_PLAT_COORDINATED_LPI)) {
+if (LEqual (FixedPcdGet32 (PcdOscLpiEnable), Zero)) {
+  And (CAP0, Not (OSC_CAP_PLAT_COORDINATED_LPI), CAP0)
+  Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+}
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  0,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+0,// Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+0,// Residency Counter Frequency
+0,// No

Re: [edk2-devel] [edk2-platforms][PATCH v5 6/9] Platform/Sgi: Add initial support for RD-Fremont platform

2024-03-11 Thread levi.yun

Reviewed-by: levi.yun 


From: devel@edk2.groups.io  on behalf of Prabin CA via 
groups.io 
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 6/9] Platform/Sgi: Add initial 
support for RD-Fremont platform

The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM.
Add initial support for this platform by adding the required platform
build configuration files. This platform has considerable differences in
its memory map compared to its predecessors. So add a corresponding
memory map file as well to define the PCDs for its generation of
platforms.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc   | 71 
 Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc | 55 +++
 Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc | 10 +++
 3 files changed, 136 insertions(+)

diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc 
b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc
new file mode 100644
index ..06c3b37388c1
--- /dev/null
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc
@@ -0,0 +1,71 @@
+#
+#  Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[PcdsFixedAtBuild.common]
+  # System Peripherals
+  gArmSgiTokenSpaceGuid.PcdSmcCs0Base|0x0800
+  gArmSgiTokenSpaceGuid.PcdSmcCs1Base|0x06
+  gArmSgiTokenSpaceGuid.PcdSysPeriphBase|0x0C00
+  gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase|0x0C01
+
+  # SP804 dual timer
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x0C11
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x0001
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|216
+
+  # Virtio Disk
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x0C13
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x1
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt|184
+
+  # GPIO controller
+  gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D
+  gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
+  gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|168
+
+   # Ethernet
+  gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x0C15
+  gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|186
+
+  # PL031 RealTimeClock
+  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0C17
+
+  # Virtio P9
+  gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress|0x0C19
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x1
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|185
+
+  # PL370 - HDLCD1
+  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0EF6
+
+  # PL011 - Serial Debug UART
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0EF7
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt|179
+
+  # PL011 - Serial Terminal
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt|112
+
+  # System Memory (2GB - 128MB of Trusted DRAM at the top of the 32bit address 
space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7800
+
+  # SMMU
+  gArmSgiTokenSpaceGuid.PcdSmmuBase|0x28000
+  gArmSgiTokenSpaceGuid.PcdSmmuSize|0x400
+
+  # Non-Volatile variable storage
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x06
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x060140
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x060280
+
+  # Address bus width - 64TB address space
+  gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|46
+
+  # Timer & Watchdog interrupts
+  gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|109
+  gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|108
+  gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|110
+  gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|111
diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc 
b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc
new file mode 100644
index ..b52d2f59e15d
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc
@@ -0,0 +1,55 @@
+#
+#  Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME  = RdFremont
+  PLATFORM_GUID  = fd140b0f-4467-4314-aa69-cd0bd712e08e
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 0x0001001B
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= AARCH64
+  BUILD_TARGETS  = NOOPT|DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = Platform/ARM/SgiPkg/SgiPlatform.fdf
+  BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc
+  BUILD_NUMBER

Re: [edk2-devel] [edk2-platforms][PATCH v5 5/9] Platform/Sgi: Add ACPI tables for RD-Fremont platform

2024-03-11 Thread levi.yun

Reviewed-by: levi.yun 


From: devel@edk2.groups.io  on behalf of Prabin CA via 
groups.io 
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 5/9] Platform/Sgi: Add ACPI 
tables for RD-Fremont platform

From: Shriram K 

RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. In preparation for
adding support for this platform, add the initial set of ACPI tables and
reuse existing ACPI tables as applicable to boot a operating system on
this platform.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf |  73 
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 196 

 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 ++
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 +
 4 files changed, 574 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
new file mode 100644
index ..9d07001dec96
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -0,0 +1,73 @@
+## @file
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2024, Arm Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = RdFremontAcpiTables
+  FILE_GUID  = c712719a-0aaf-438c-9cdd-35ab4d60207d  # 
gArmSgiAcpiTablesGuid
+  MODULE_TYPE= USER_DEFINED
+  VERSION_STRING = 1.0
+
+[Sources]
+  Dbg2.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  RdFremont/Dsdt.asl
+  RdFremont/Madt.aslc
+  RdFremont/Pptt.aslc
+  Spcr.aslc
+  SsdtEvents.asl
+  SsdtRos.asl
+  SsdtRosVirtioP9.asl
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmPlatformTokenSpaceGuid.PcdClusterCount
+
+  gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
+  gArmSgiTokenSpaceGuid.PcdGpioController0Size
+  gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
+  gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
+  gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+  gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+  gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+  gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+  gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Size
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt
+  gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
+  gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
new file mode 100644
index ..8812ea877f7a
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -0,0 +1,196 @@
+/** @file
+*  Differentiated System Description Table Fields (DSDT)
+*
+*  Copyright (c) 2024, Arm Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+*   - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description
+* Table (DSDT)
+*
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+  Scope (_SB) {
+Device (CL00) {   // Cluster 0
+  Name (_HID, "ACPI0010")
+  Name (_UID, 0)
+
+  Device (CP00) { // Neoverse Poseidon core 0
+Name (_HID, "ACPI0007")
+Name (_UID, 0)
+Name (_STA, 0xF)
+  }
+}
+
+Device (CL01) {   // Cluster 1
+

Re: [edk2-devel] [edk2-platforms][PATCH v5 4/9] Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms

2024-03-11 Thread levi.yun

Reviewed-by: levi.yun 


From: devel@edk2.groups.io  on behalf of Prabin CA via 
groups.io 
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 4/9] Platform/Sgi: Introduce a 
flag to enable PCIe support for RD Platforms

Introducing a flag called PCIE_ENABLE, which can be set to TRUE or
FALSE from the respective .dsc files to enable or disable the
PCIe support. As not all reference design platforms have PCIe support
enabled, this flag is introduced.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatform.dec  |  1 +
 Platform/ARM/SgiPkg/SgiPlatform.dsc.inc  |  6 ++
 Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdV1/RdV1.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc|  4 +++-
 Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc|  4 +++-
 Platform/ARM/SgiPkg/SgiPlatform.fdf  |  4 +++-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf  |  5 -
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 19 
+++
 11 files changed, 43 insertions(+), 16 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec 
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 4087ff6cad2e..af7887e54126 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -31,6 +31,7 @@ [Guids.common]
 [PcdsFeatureFlag.common]
   gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x0001
   gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x0010
+  gArmSgiTokenSpaceGuid.PcdPcieEnable|FALSE|BOOLEAN|0x002E

 [PcdsFixedAtBuild]
   gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x0002
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc 
b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 1cfe07c7e4ed..1bf489ffeb39 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -103,6 +103,10 @@ [PcdsFeatureFlag.common]
   gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|FALSE

+!if $(PCIE_ENABLE) == TRUE
+  gArmSgiTokenSpaceGuid.PcdPcieEnable|TRUE
+!endif
+
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdVFPEnabled|1
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
@@ -330,6 +334,7 @@ [Components.common]
   # Virtio Network
   OvmfPkg/VirtioNetDxe/VirtioNet.inf

+!if $(PCIE_ENABLE) == TRUE
   #
   # Required by PCI
   #
@@ -343,6 +348,7 @@ [Components.common]
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
   }
+!endif

   #
   # AHCI Support
diff --git a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc 
b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
index 32d67d380814..c7463da5203e 100644
--- a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
+++ b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,6 +22,8 @@ [Defines]
   BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.fdf.inc
   BUILD_NUMBER   = 1

+  DEFINE PCIE_ENABLE = TRUE
+
 # include common definitions from SgiPlatform.dsc
 !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
 !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
diff --git a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc 
b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
index 6c9a64df054f..77efec9d9533 100644
--- a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
+++ b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,6 +22,8 @@ [Defines]
   BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.fdf.inc
   BUILD_NUMBER   = 1

+  DEFINE PCIE_ENABLE = TRUE
+
 # include common definitions from SgiPlatform.dsc
 !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
 !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
diff --git a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc 
b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
index 10e5bfa29b46..521d88925059 100644
--- a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
+++ b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,6 +22,8 @@ [Defines]
   BOARD_DXE_FV_COMPONENTS

Re: [edk2-devel] [edk2-platforms][PATCH v5 3/9] Platform/Sgi: Refactor system memory base and size definitions

2024-03-11 Thread levi.yun

Reviewed-by: levi.yun 


From: devel@edk2.groups.io  on behalf of Prabin CA via 
groups.io 
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 3/9] Platform/Sgi: Refactor 
system memory base and size definitions

In preparation of adding the next generation of reference design
platform that have different memory map, refactor the
PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the
common PCD definitions file into the various platform generation
specific memory map PCD definitions file.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc  | 8 +++-
 Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 8 +++-
 Platform/ARM/SgiPkg/SgiPlatform.dsc.inc   | 6 +-
 3 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc 
b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
index 0c577c42..eab43b23ec6d 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+#  Copyright (c) 2020 - 2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -67,3 +67,9 @@ [PcdsFixedAtBuild.common]
   gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D
   gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|136
+
+  # System Memory (1GB - 16MB of Trusted DRAM at the top of the
+  # 32bit address space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00
+
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc 
b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index de1d8ea24b89..35e27d42d5a2 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020 - 2023, Arm Limited. All rights reserved.
+#  Copyright (c) 2020 - 2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -75,3 +75,9 @@ [PcdsFixedAtBuild.common]

   # IO virtualization block
   gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0x108000
+
+  # System Memory (1GB - 16MB of Trusted DRAM at the top of the
+  # 32bit address space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00
+
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc 
b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 26ecd9ed59a7..1cfe07c7e4ed 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 #  (C) Copyright 2021 Hewlett Packard Enterprise Development LP
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -131,10 +131,6 @@ [PcdsFixedAtBuild.common]
   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4
   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0

-  # System Memory (1GB - 16MB of Trusted DRAM at the top of the 32bit address 
space)
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00
-
   # ACPI Table Version
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20

--
2.34.1



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Re: [edk2-devel] [edk2-platforms][PATCH v5 2/9] Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64

2024-03-11 Thread levi.yun

Reviewed-by: levi.yun 


From: devel@edk2.groups.io  on behalf of Prabin CA via 
groups.io 
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 2/9] Platform/Sgi: Update the 
datatype of PcdSmmuBase from u32 to u64

From: Vivek Gautam 

On RD-N2 and previous generation platforms, the base address was within
32-bit region. However, on upcoming platforms, the SMMUv3 base address
is beyond 32-bit address region. So, update the datatype of SMMUv3 base
PCD.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatform.dec  | 2 +-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec 
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 103dff8471a7..4087ff6cad2e 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -79,7 +79,7 @@ [PcdsFixedAtBuild]
   gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|0|UINT32|0x0014

   # SMMU
-  gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x001D
+  gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT64|0x001D
   gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x001E

   # GPIO Controller
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c 
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
index fa3cfbc730f6..62c212f3c5b0 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2018-2023, ARM Limited. All rights reserved.
+*  Copyright (c) 2018-2024, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -167,8 +167,8 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Attributes  = 
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

   // Sub System Peripherals - SMMU
-  VirtualMemoryTable[++Index].PhysicalBase  = FixedPcdGet32 (PcdSmmuBase);
-  VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdSmmuBase);
+  VirtualMemoryTable[++Index].PhysicalBase  = FixedPcdGet64 (PcdSmmuBase);
+  VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSmmuBase);
   VirtualMemoryTable[Index].Length  = FixedPcdGet32 (PcdSmmuSize);
   VirtualMemoryTable[Index].Attributes  = 
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

--
2.34.1



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Re: [edk2-devel] [edk2-platforms][PATCH v5 1/9] Platform/Sgi: Correct typo in defining CPPC performance limited register

2024-03-11 Thread levi.yun

Reviewed-by: levi.yun 

From: devel@edk2.groups.io  on behalf of Prabin CA via 
groups.io 
Sent: 11 March 2024 13:14
To: devel@edk2.groups.io
Cc: Ard Biesheuvel; Leif Lindholm; Sami Mujawar; Thomas Abraham
Subject: [edk2-devel] [edk2-platforms][PATCH v5 1/9] Platform/Sgi: Correct typo 
in defining CPPC performance limited register

The reference design platform currently lacks the CPPC (Collaborative
Processor Performance Control) performance limited register as defined
by the ACPI 6.x specification. There is a typo in the macro definition
where the 'fastchannel address of the performance limited register' is
mentioned instead of the 'performance limited register address'.
Correcting this typo. However, it's important to retain the reference to
the performance limited register in the macro for future use, as it will
prove useful once functionalities such as power metering devices are
enabled.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h 
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 033d398fdb63..3e24f569c95a 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -469,8 +469,7 @@ typedef struct {

 @param [in] DesiredPerfReg  Fastchannel address for desired performance
 register.
-@param [in] PerfLimitedReg  Fastchannel address for performance limited
-register.
+@param [in] PerfLimitedReg  Address for performance limited register.
 @param [in] GranularityMHz  Granularity of the performance scale.
 @param [in] HighestPerf Highest performance in linear scale.
 @param [in] NominalPerf Nominal performance in linear scale.
--
2.34.1

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Re: [edk2-devel] [PATCH v2 0/5] Platform/RaspberryPi: Various minor fixes

2024-03-11 Thread Ard Biesheuvel

On Wed, 17 Jan 2024 at 22:36, Jeremy Linton  wrote:
>
> This includes a change to always initialize the PL011 to the
> configured baud (which should be 115200 for the SBSA UART), which
> fixes linux's assumption that SBSA UARTs are pre-programmed for
> 115200. This in turn (re)enables the PL011 when the console is on the
> miniuart per the config.txt file.
>
> Also included is another spin with the DT/XHCI reset patch which puts
> removal of the DT node that causes linux to reset the XHCI controller,
> as well as an additional patch that updates the DT to match the PCIe
> MMIO window we have programmed. This cures much of the problem with
> the PCIe/XHCI configuration when booted in DT mode on linux.
>
> There is also a few menu visibility/section tweaks to assure ACPI/DT
> specific settings show up at the appropriate time.
>
> As well as a minor fix to work around a bogus compiler warning.
>
> v1->v2: Ard's review comments.
> Convert PCIe MMIO address to use the fixedPCDs defined elsewhere
> Hardcode 115200 for the SBSA UART
>
> Jeremy Linton (5):
>   Platform/RaspberryPi/DualSerialPortLib: Always configure the pl011
>   Silicon/Broadcom/BcmGenetDxe: Suppress some bogus compiler warnings
>   Platform/RaspberryPi: Cleanup menu visibility
>   Platform/RaspberryPi: Give the user control over the XHCI mailbox
>   Platform/RaspberryPi: Update PCIe MMIO window for DT
>

Pushed patches #2 - #5. Thanks.


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Re: [edk2-devel] [PATCH v2 4/4] DynamicTablesPkg: Adds ACPI SSDT HPET Table generator

2024-03-11 Thread PierreGondois


(follow-up)

On 3/11/24 15:16, Pierre Gondois wrote:

Hello Abdul,

On 3/4/24 16:43, Abdul Lateef Attar wrote:

From: Abdul Lateef Attar 

Adds generic ACPI SSDT HPET table generator library.
Register/Deregister HPET table.
Adds ACPI namespace object for HPET device.
Adds Address space for HPET device.

Cc: Sami Mujawar 
Cc: Pierre Gondois 
Signed-off-by: Abdul Lateef Attar `
---
   DynamicTablesPkg/DynamicTables.dsc.inc|   2 +
   DynamicTablesPkg/Include/AcpiTableGenerator.h |   2 +
   .../Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf  |  36 +++
   .../Acpi/AcpiSsdtHpetLib/SsdtHpetGenerator.c  | 266 ++
   4 files changed, 306 insertions(+)
   create mode 100644 
DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf
   create mode 100644 
DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/SsdtHpetGenerator.c

diff --git a/DynamicTablesPkg/DynamicTables.dsc.inc 
b/DynamicTablesPkg/DynamicTables.dsc.inc
index 477dc6b6a9..fc2ac5962e 100644
--- a/DynamicTablesPkg/DynamicTables.dsc.inc
+++ b/DynamicTablesPkg/DynamicTables.dsc.inc
@@ -36,6 +36,7 @@
 DynamicTablesPkg/Library/Acpi/AcpiFadtLib/AcpiFadtLib.inf
 DynamicTablesPkg/Library/Acpi/AcpiHpetLib/AcpiHpetLib.inf
 DynamicTablesPkg/Library/Acpi/AcpiWsmtLib/AcpiWsmtLib.inf
+  DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf


(note for later):
The HPET table seems to be intel specific actually,

and the WSMT is generic. So the tables might be built depending
on the ARCH.

Tables common to all ARCHs should be part of all the different
  DynamicTableFactoryDxe.inf
drivers, and ARCH specificat tables should not be in the
  [Components.common]
section. Sorry for not realizing the HPET table was not common
to all ARCHs earlier.


This section will change after the Arm/Arch common namespace update
and will have to be rebased. So I assume it can be left as is for now.

[snip]


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Re: [edk2-devel] [PATCH v2 4/4] DynamicTablesPkg: Adds ACPI SSDT HPET Table generator

2024-03-11 Thread PierreGondois


Hello Abdul,

On 3/4/24 16:43, Abdul Lateef Attar wrote:

From: Abdul Lateef Attar 

Adds generic ACPI SSDT HPET table generator library.
Register/Deregister HPET table.
Adds ACPI namespace object for HPET device.
Adds Address space for HPET device.

Cc: Sami Mujawar 
Cc: Pierre Gondois 
Signed-off-by: Abdul Lateef Attar `
---
  DynamicTablesPkg/DynamicTables.dsc.inc|   2 +
  DynamicTablesPkg/Include/AcpiTableGenerator.h |   2 +
  .../Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf  |  36 +++
  .../Acpi/AcpiSsdtHpetLib/SsdtHpetGenerator.c  | 266 ++
  4 files changed, 306 insertions(+)
  create mode 100644 
DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf
  create mode 100644 
DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/SsdtHpetGenerator.c

diff --git a/DynamicTablesPkg/DynamicTables.dsc.inc 
b/DynamicTablesPkg/DynamicTables.dsc.inc
index 477dc6b6a9..fc2ac5962e 100644
--- a/DynamicTablesPkg/DynamicTables.dsc.inc
+++ b/DynamicTablesPkg/DynamicTables.dsc.inc
@@ -36,6 +36,7 @@
DynamicTablesPkg/Library/Acpi/AcpiFadtLib/AcpiFadtLib.inf
DynamicTablesPkg/Library/Acpi/AcpiHpetLib/AcpiHpetLib.inf
DynamicTablesPkg/Library/Acpi/AcpiWsmtLib/AcpiWsmtLib.inf
+  DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf


(note for later):
The HPET table seems to be intel specific actually,

  
  [Components.IA32, Components.X64]

#
@@ -46,6 +47,7 @@
NULL|DynamicTablesPkg/Library/Acpi/AcpiFadtLib/AcpiFadtLib.inf
NULL|DynamicTablesPkg/Library/Acpi/AcpiHpetLib/AcpiHpetLib.inf
NULL|DynamicTablesPkg/Library/Acpi/AcpiWsmtLib/AcpiWsmtLib.inf
+  NULL|DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf
}
  
  [Components.ARM, Components.AARCH64]

diff --git a/DynamicTablesPkg/Include/AcpiTableGenerator.h 
b/DynamicTablesPkg/Include/AcpiTableGenerator.h
index a32ef46ecb..ef651aa2aa 100644
--- a/DynamicTablesPkg/Include/AcpiTableGenerator.h
+++ b/DynamicTablesPkg/Include/AcpiTableGenerator.h
@@ -1,6 +1,7 @@
  /** @file
  
Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.

+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
  
SPDX-License-Identifier: BSD-2-Clause-Patent
  
@@ -101,6 +102,7 @@ typedef enum StdAcpiTableId {

EStdAcpiTableIdPcct,  ///< PCCT Generator
EStdAcpiTableIdHpet,  ///< HPET Generator
EStdAcpiTableIdWsmt,  ///< WSMT Generator
+  EStdAcpiTableIdSsdtHpet,  ///< SSDT HPET Generator
EStdAcpiTableIdMax
  } ESTD_ACPI_TABLE_ID;
  
diff --git a/DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf b/DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf

new file mode 100644
index 00..7586b31adf
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf
@@ -0,0 +1,36 @@
+## @file
+#  SSDT HPET Table Generator
+#
+#  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+  INF_VERSION= 1.27
+  BASE_NAME  = AcpiSsdtHpetLib
+  FILE_GUID  = 85262912-AD7F-4EE0-8BB1-EE177275A54E
+  VERSION_STRING = 1.0
+  MODULE_TYPE= DXE_DRIVER
+  LIBRARY_CLASS  = NULL|DXE_DRIVER
+  CONSTRUCTOR= AcpiSsdtHpetLibConstructor
+  DESTRUCTOR = AcpiSsdtHpetLibDestructor
+
+[Sources]
+  SsdtHpetGenerator.c
+
+[Packages]
+  DynamicTablesPkg/DynamicTablesPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  PcAtChipsetPkg/PcAtChipsetPkg.dec
+
+[LibraryClasses]
+  AcpiHelperLib
+  AmlLib
+  BaseLib
+  DebugLib
+  PcdLib
+
+[Pcd]
+  gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress


Cf. [1], I think this should be removed along the dependency over the
PcAtChipsetPkg dependency.


diff --git a/DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/SsdtHpetGenerator.c 
b/DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/SsdtHpetGenerator.c
new file mode 100644
index 00..3d401204ae
--- /dev/null
+++ b/DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/SsdtHpetGenerator.c
@@ -0,0 +1,266 @@
+/** @file
+  SSDT HPET Table Generator
+
+  Copyright (c) 2017 - 2023, Arm Limited. All rights reserved.
+  Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Reference(s):
+  - ACPI 6.5 Specification, Aug 29, 2022


Is it possible to reference the HPET spec. with a link aswell if possible ?
Same comment for the other generators with their respective spec.


+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/** The Creator ID for the ACPI tables generated using
+  the standard ACPI table generators.
+*/
+#define TABLE_GENERATOR_CREATOR_ID_GENERIC  SIGNATURE_32('D', 'Y', 'N', 'T')
+
+/** This macro defines the HPET Table Generator revision.
+*/
+#define HPET_GENERATOR_REVISION  CREATE_REVISION (1, 0)


Is it possible to

Re: [edk2-devel] [PATCH v2 3/4] DynamicTablesPkg: Adds ACPI WSMT Table generator

2024-03-11 Thread PierreGondois


Hello Abdul,

On 3/4/24 16:43, Abdul Lateef Attar wrote:

From: Abdul Lateef Attar 

Adds generic ACPI WSMT table generator library.
Register/Deregister WSMT table.
Update the WSMT table during boot as per specification.

Cc: Sami Mujawar 
Cc: Pierre Gondois 
Signed-off-by: Abdul Lateef Attar 
---
  DynamicTablesPkg/DynamicTables.dsc.inc|   2 +
  DynamicTablesPkg/Include/AcpiTableGenerator.h |   1 +
  .../Include/ArchNameSpaceObjects.h|  10 +
  .../Library/Acpi/AcpiWsmtLib/AcpiWsmtLib.inf  |  30 +++
  .../Library/Acpi/AcpiWsmtLib/WsmtGenerator.c  | 230 ++
  5 files changed, 273 insertions(+)
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiWsmtLib/AcpiWsmtLib.inf
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiWsmtLib/WsmtGenerator.c



[snip]


+STATIC
+EFI_STATUS
+BuildWsmtTable (
+  IN  CONST ACPI_TABLE_GENERATOR  *CONST  This,
+  IN  CONST CM_STD_OBJ_ACPI_TABLE_INFO*CONST  AcpiTableInfo,
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  *CONST  CfgMgrProtocol,
+  OUT   EFI_ACPI_DESCRIPTION_HEADER  **CONST  Table
+  )
+{
+  EFI_STATUS Status;
+  CM_ARCH_WSMT_PROTECTION_FLAGS  *ProtectionFlags;
+
+  ASSERT (This != NULL);
+  ASSERT (AcpiTableInfo != NULL);
+  ASSERT (CfgMgrProtocol != NULL);
+  ASSERT (Table != NULL);
+  ASSERT (AcpiTableInfo->TableGeneratorId == This->GeneratorID);
+  ASSERT (AcpiTableInfo->AcpiTableSignature == This->AcpiTableSignature);
+
+  if ((AcpiTableInfo->AcpiTableRevision < This->MinAcpiTableRevision) ||
+  (AcpiTableInfo->AcpiTableRevision > This->AcpiTableRevision))
+  {
+DEBUG ((
+  DEBUG_ERROR,
+  "ERROR: WSMT: Requested table revision = %d, is not supported."
+  "Supported table revision: Minimum = %d, Maximum = %d\n",
+  AcpiTableInfo->AcpiTableRevision,
+  This->MinAcpiTableRevision,
+  This->AcpiTableRevision
+  ));
+return EFI_INVALID_PARAMETER;
+  }
+
+  *Table = NULL;
+
+  Status = AddAcpiHeader (
+ CfgMgrProtocol,
+ This,
+ (EFI_ACPI_DESCRIPTION_HEADER *),
+ AcpiTableInfo,
+ sizeof (EFI_ACPI_WSMT_TABLE)
+ );
+  if (EFI_ERROR (Status)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "ERROR: WSMT: Failed to add ACPI header. Status = %r\n",
+  Status
+  ));
+return Status;
+  }
+
+  Status = GetEArchObjWsmtProtectionFlags (
+ CfgMgrProtocol,
+ CM_NULL_TOKEN,
+ ,
+ NULL
+ );
+  if (EFI_ERROR (Status)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "ERROR: WSMT: Failed to get protection flags information." \
+  " Status = %r\n",
+  Status
+  ));
+  } else {
+mAcpiWsmt.ProtectionFlags = ProtectionFlags->ProtectionFlags;
+  }


It seems that EFI_WSMT_PROTECTION_FLAGS_COMM_BUFFER_NESTED_PTR_PROTECTION
bit can only be set if EFI_WSMT_PROTECTION_FLAGS_FIXED_COMM_BUFFERS
is set. Maybe this should be checked here.


+
+  *Table = (EFI_ACPI_DESCRIPTION_HEADER *)
+
+  return Status;
+}
+


Regards,
Pierre


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Re: [edk2-devel] [PATCH v2 2/4] DynamicTablesPkg: Adds ACPI HPET Table generator

2024-03-11 Thread PierreGondois


Hello Abdul,

On 3/4/24 16:43, Abdul Lateef Attar wrote:

From: Abdul Lateef Attar 

Adds generic ACPI HPET table generator library.
Register/Deregister HPET table.
Update the HPET table during boot as per specification.

Cc: Sami Mujawar 
Cc: Pierre Gondois 
Signed-off-by: Abdul Lateef Attar 
---
  DynamicTablesPkg/DynamicTables.dsc.inc|   2 +
  DynamicTablesPkg/DynamicTablesPkg.ci.yaml |   3 +-
  DynamicTablesPkg/Include/AcpiTableGenerator.h |   1 +
  .../Library/Acpi/AcpiHpetLib/AcpiHpetLib.inf  |  35 +++
  .../Library/Acpi/AcpiHpetLib/HpetGenerator.c  | 216 ++
  5 files changed, 256 insertions(+), 1 deletion(-)
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiHpetLib/AcpiHpetLib.inf
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiHpetLib/HpetGenerator.c

diff --git a/DynamicTablesPkg/DynamicTables.dsc.inc 
b/DynamicTablesPkg/DynamicTables.dsc.inc
index 92f3a138e4..b2ef36eb8a 100644
--- a/DynamicTablesPkg/DynamicTables.dsc.inc
+++ b/DynamicTablesPkg/DynamicTables.dsc.inc
@@ -34,6 +34,7 @@
# Generators
#
DynamicTablesPkg/Library/Acpi/AcpiFadtLib/AcpiFadtLib.inf
+  DynamicTablesPkg/Library/Acpi/AcpiHpetLib/AcpiHpetLib.inf
  
  [Components.IA32, Components.X64]

#
@@ -42,6 +43,7 @@
DynamicTablesPkg/Drivers/DynamicTableFactoryDxe/DynamicTableFactoryDxe.inf {
  
NULL|DynamicTablesPkg/Library/Acpi/AcpiFadtLib/AcpiFadtLib.inf
+  NULL|DynamicTablesPkg/Library/Acpi/AcpiHpetLib/AcpiHpetLib.inf
}
  
  [Components.ARM, Components.AARCH64]

diff --git a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml 
b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
index 1ad5540e24..cacdaa1df6 100644
--- a/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
+++ b/DynamicTablesPkg/DynamicTablesPkg.ci.yaml
@@ -53,7 +53,8 @@
  "EmbeddedPkg/EmbeddedPkg.dec",
  "DynamicTablesPkg/DynamicTablesPkg.dec",
  "MdeModulePkg/MdeModulePkg.dec",
-"MdePkg/MdePkg.dec"
+"MdePkg/MdePkg.dec",
+"PcAtChipsetPkg/PcAtChipsetPkg.dec"


Cf. the comment in:
   [PATCH v2 4/4] DynamicTablesPkg: Adds ACPI SSDT HPET Table generator
I think this depenency should be removed. A HPET CmObj should be created
instead.
Sorry for not saying this in the v1.

[snip]

Regards,
Pierre


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Re: [edk2-devel] [PATCH v2 0/4] DynamicTablesPkg V2: Adds generic FADT, HPET and WSMT table generators

2024-03-11 Thread PierreGondois


Hello Abdul,
I think the FADT patch will change too much with the modifications currently
ongoing on the Arm/Arch common namespace objects. So it might not be worth
reviewing it for now.

The other patches will also have to be rebased/modified, but with less
modifications,

Regards,
Pierre

On 3/4/24 16:43, Abdul Lateef Attar wrote:

From: Abdul Lateef Attar 

PR: https://github.com/tianocore/edk2/pull/5438

V2: delta changes
   Addressed review comments
   Adds ACPI HPET table to add HPET to ACPI namespace
V1:
Adds new space for ArchNameSpaceObjects.
Adds generic FADT table generator.
Adds generic HPET table generator.
Adds generic WSMT table generator.

Cc: Sami Mujawar 
Cc: Pierre Gondois 
Cc: Abdul Lateef Attar 


Abdul Lateef Attar (4):
   DynamicTablesPkg: Adds ACPI FADT Table generator
   DynamicTablesPkg: Adds ACPI HPET Table generator
   DynamicTablesPkg: Adds ACPI WSMT Table generator
   DynamicTablesPkg: Adds ACPI SSDT HPET Table generator

  DynamicTablesPkg/DynamicTables.dsc.inc|  16 +-
  DynamicTablesPkg/DynamicTablesPkg.ci.yaml |   7 +-
  DynamicTablesPkg/Include/AcpiTableGenerator.h |   4 +
  .../Include/ArchNameSpaceObjects.h| 227 ++
  .../Include/ConfigurationManagerObject.h  |   6 +
  .../Library/Acpi/AcpiFadtLib/AcpiFadtLib.inf  |  36 +
  .../Library/Acpi/AcpiFadtLib/Arm/FadtUpdate.c |  39 +
  .../Library/Acpi/AcpiFadtLib/FadtGenerator.c  | 747 ++
  .../Library/Acpi/AcpiFadtLib/FadtUpdate.h |  26 +
  .../Library/Acpi/AcpiFadtLib/X64/FadtUpdate.c |  32 +
  .../Library/Acpi/AcpiHpetLib/AcpiHpetLib.inf  |  35 +
  .../Library/Acpi/AcpiHpetLib/HpetGenerator.c  | 216 +
  .../Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf  |  36 +
  .../Acpi/AcpiSsdtHpetLib/SsdtHpetGenerator.c  | 266 +++
  .../Library/Acpi/AcpiWsmtLib/AcpiWsmtLib.inf  |  30 +
  .../Library/Acpi/AcpiWsmtLib/WsmtGenerator.c  | 230 ++
  16 files changed, 1950 insertions(+), 3 deletions(-)
  create mode 100644 DynamicTablesPkg/Include/ArchNameSpaceObjects.h
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiFadtLib/AcpiFadtLib.inf
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiFadtLib/Arm/FadtUpdate.c
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiFadtLib/FadtGenerator.c
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiFadtLib/FadtUpdate.h
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiFadtLib/X64/FadtUpdate.c
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiHpetLib/AcpiHpetLib.inf
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiHpetLib/HpetGenerator.c
  create mode 100644 
DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/AcpiSsdtHpetLib.inf
  create mode 100644 
DynamicTablesPkg/Library/Acpi/AcpiSsdtHpetLib/SsdtHpetGenerator.c
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiWsmtLib/AcpiWsmtLib.inf
  create mode 100644 DynamicTablesPkg/Library/Acpi/AcpiWsmtLib/WsmtGenerator.c




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Re: [edk2-devel] [PATCH v2 1/5] Platform/RaspberryPi/DualSerialPortLib: Always configure the pl011

2024-03-11 Thread Ard Biesheuvel

On Wed, 17 Jan 2024 at 22:36, Jeremy Linton  wrote:
>
> The rpi's config.txt controls which uart (pl011, or miniuart) is
> selected as the console. TFA and edk2 follow its lead, but if the
> miniuart is selected as the primary and the machine is booted in ACPI
> mode the baud/etc is never configured for the pl011. The linux kernel
> won't reconfigure it either as its listed as a "SBSA" uart, so it
> simply won't work.
>
> This re-enables BT on the pl011 in ACPI mode, and it somewhat starts
> to work again.
>
> Signed-off-by: Jeremy Linton 
> ---
>  .../DualSerialPortLib/DualSerialPortLib.c | 44 ---
>  1 file changed, 29 insertions(+), 15 deletions(-)
>
> diff --git 
> a/Platform/RaspberryPi/Library/DualSerialPortLib/DualSerialPortLib.c 
> b/Platform/RaspberryPi/Library/DualSerialPortLib/DualSerialPortLib.c
> index d2f983bf0a..09d3e33c00 100644
> --- a/Platform/RaspberryPi/Library/DualSerialPortLib/DualSerialPortLib.c
> +++ b/Platform/RaspberryPi/Library/DualSerialPortLib/DualSerialPortLib.c
> @@ -76,6 +76,8 @@ SerialPortInitialize (
>EFI_PARITY_TYPE Parity;
>UINT8   DataBits;
>EFI_STOP_BITS_TYPE  StopBits;
> +  RETURN_STATUS   Ret;
> +  UINTN   Timeout;
>
>//
>// First thing we need to do is determine which of PL011 or miniUART is 
> selected
> @@ -85,23 +87,34 @@ SerialPortInitialize (
>  UsePl011UartSet = TRUE;
>}
>
> -  if (UsePl011Uart) {
> -BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> +  // always init the pl011 on the RPi4, linux expects a SBSA uart to be at 
> 115200
> +  // this means we need to set the baud/etc even if we aren't using it as a 
> console
> +  if ((UsePl011Uart) || (RPI_MODEL == 4)) {
>  ReceiveFifoDepth = 0; // Use default FIFO depth
> +if (!UsePl011Uart)
> +{
> +  BaudRate = 115200;
> +}
> +else
> +{
> +  BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> +}
>  Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
>  DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
>  StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
>
> -return PL011UartInitializePort (
> - PL011_UART_REGISTER_BASE,
> - PL011UartClockGetFreq(),
> - ,
> - ,
> - ,
> - ,
> - 
> - );
> -  } else {
> +Ret = PL011UartInitializePort (
> +   PL011_UART_REGISTER_BASE,
> +   PL011UartClockGetFreq(),
> +   ,
> +   ,
> +   ,
> +   ,
> +   
> +   );
> +  }
> +
> +  if (!UsePl011Uart) {
>  SerialRegisterBase = MINI_UART_REGISTER_BASE;
>  Divisor = SerialPortGetDivisor (PcdGet32 (PcdSerialBaudRate));
>
> @@ -127,7 +140,8 @@ SerialPortInitialize (
>  // Wait for the serial port to be ready.
>  // Verify that both the transmit FIFO and the shift register are empty.
>  //
> -while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & 
> (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | 
> B_UART_LSR_TXRDY));
> +Timeout = 1000;
> +while (((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & 
> (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | 
> B_UART_LSR_TXRDY)) && (Timeout--));
>

Why is this necessary, and what does it have to do with the rest of the patch?

>  //
>  // Configure baud rate
> @@ -158,9 +172,9 @@ SerialPortInitialize (
>  // Put Modem Control Register(MCR) into its reset state of 0x00.
>  //
>  SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
> -
> -return RETURN_SUCCESS;
> +Ret = RETURN_SUCCESS;
>}
> +  return Ret;
>  }
>
>  /**
> --
> 2.43.0
>


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Re: [edk2-devel] [PATCH v2 3/4] StandaloneMmPkg: Support to unregister MMI handler inside MMI handler

2024-03-11 Thread Ard Biesheuvel

On Wed, 28 Feb 2024 at 03:28, Zhiguang Liu  wrote:
>
> To support unregister MMI handler inside MMI handler itself,
> get next node before MMI handler is executed, since LIST_ENTRY that
> Link points to may be freed if unregister MMI handler in MMI handler
> itself.
>
> Cc: Liming Gao 
> Cc: Jiaxin Wu 
> Cc: Ray Ni 
> Cc: Laszlo Ersek 
> Cc: Ard Biesheuvel 
> Cc: Sami Mujawar 
> Signed-off-by: Zhiguang Liu 
> ---
>  StandaloneMmPkg/Core/Mmi.c | 9 +++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>

Reviewed-by: Ard Biesheuvel 

> diff --git a/StandaloneMmPkg/Core/Mmi.c b/StandaloneMmPkg/Core/Mmi.c
> index 0de6fd17fc..c1a1d76e85 100644
> --- a/StandaloneMmPkg/Core/Mmi.c
> +++ b/StandaloneMmPkg/Core/Mmi.c
> @@ -154,9 +154,14 @@ MmiManage (
>  Head = >MmiHandlers;
>}
>
> -  for (Link = Head->ForwardLink; Link != Head; Link = Link->ForwardLink) {
> +  for (Link = Head->ForwardLink; Link != Head;) {
>  MmiHandler = CR (Link, MMI_HANDLER, Link, MMI_HANDLER_SIGNATURE);
> -
> +//
> +// To support unregister MMI handler inside MMI handler itself,
> +// get next node before handler is executed, since LIST_ENTRY that
> +// Link points to may be freed if unregister MMI handler.
> +//
> +Link   = Link->ForwardLink;
>  Status = MmiHandler->Handler (
> (EFI_HANDLE)MmiHandler,
> Context,
> --
> 2.31.1.windows.1
>
>
>
> 
>
>


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Re: [edk2-devel][PATCH v3 3/3] MdeModulePkg: DxeCore: Do Not Apply Guards to Unsupported Types

2024-03-11 Thread Ard Biesheuvel

On Sat, 9 Mar 2024 at 20:06, Oliver Smith-Denny
 wrote:
>
> Currently, there are multiple issues when page or pool guards are
> allocated for runtime memory regions that are aligned to
> non-EFI_PAGE_SIZE alignments. Multiple other issues have been fixed
> for these same systems (notably ARM64 which has a 64k runtime page
> allocation granularity) recently. The heap guard system is only built
> to support 4k guard pages and 4k alignment.
>
> Today, the address returned to a caller of AllocatePages will not be
> aligned correctly to the runtime page allocation granularity, because
> the heap guard system does not take non-4k alignment requirements into
> consideration.
>
> However, even with this bug fixed, the Memory Allocation Table cannot
> be produced and an OS with a larger than 4k page granularity will not
> have aligned memory regions because the guard pages are reported as
> part of the same memory allocation. So what would have been, on an
> ARM64 system, a 64k runtime memory allocation is actually a 72k
> memory allocation as tracked by the Page.c code because the guard
> pages are tracked as part of the same allocation. This is a core
> function of the current heap guard architecture.
>
> This could also be fixed with rearchitecting the heap guard system to
> respect alignment requirements and shift the guard pages inside of the
> outer rounded allocation or by having guard pages be the runtime
> granularity. Both of these approaches have issues. In the former case,
> we break UEFI spec 2.10 section 2.3.6 for AARCH64, which states that
> each 64k page for runtime memory regions may not have mixed memory
> attributes, which pushing the guard pages inside would create. In the
> latter case, an immense amount of memory is wasted to support such
> large guard pages, and with pool guard many systems could not support
> an additional 128k allocation for all runtime memory.
>
> The simpler and safer solution is to disallow page and pool guards for
> runtime memory allocations for systems that have a runtime granularity
> greater than the EFI_PAGE_SIZE (4k). The usefulness of such guards is
> limited, as OSes do not map guard pages today, so there is only boot
> time protection of these ranges. This also prevents other bugs from
> being exposed by using guards for regions that have a non-4k alignment
> requirement, as again, multiple have cropped up because the heap guard
> system was not built to support it.
>
> This patch adds both a static assert to ensure that either the runtime
> granularity is the EFI_PAGE_SIZE or that the PCD bits are not set to
> enable heap guard for runtime memory regions. It also adds a check in
> the page and pool allocation system to ensure that at runtime we are
> not allocating a runtime region and attempt to guard it (the PCDs are
> close to being removed in favor of dynamic heap guard configurations).
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4674
> Github PR: https://github.com/tianocore/edk2/pull/5382
>
> Cc: Leif Lindholm 
> Cc: Ard Biesheuvel 
> Cc: Sami Mujawar 
> Cc: Liming Gao 
>
> Signed-off-by: Oliver Smith-Denny 
> ---
>  MdeModulePkg/MdeModulePkg.dec | 10 ++
>  MdeModulePkg/Core/Dxe/Mem/HeapGuard.h | 14 ++
>  MdeModulePkg/Core/Dxe/Mem/Page.c  | 11 +++
>  MdeModulePkg/Core/Dxe/Mem/Pool.c  | 11 +++
>  4 files changed, 46 insertions(+)
>

Reviewed-by: Ard Biesheuvel 

> diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
> index a2cd83345f5b..a82dedc070df 100644
> --- a/MdeModulePkg/MdeModulePkg.dec
> +++ b/MdeModulePkg/MdeModulePkg.dec
> @@ -1027,6 +1027,11 @@ [PcdsFixedAtBuild]
># free pages for all of them. The page allocation for the type related to
># cleared bits keeps the same as ususal.
>#
> +  # The heap guard system only supports guarding EfiRuntimeServicesCode, 
> EfiRuntimeServicesData,
> +  # EfiReservedMemoryType, and EfiACPIMemoryNVS memory types for systems 
> that have
> +  # RUNTIME_PAGE_ALLOCATION_GRANULARITY == EFI_PAGE_SIZE. This is to 
> preserve alignment requirements
> +  # without extending the page guard size to very large granularities.
> +  #
># This PCD is only valid if BIT0 and/or BIT2 are set in 
> PcdHeapGuardPropertyMask.
>#
># Below is bit mask for this PCD: (Order is same as UEFI spec)
> @@ -1058,6 +1063,11 @@ [PcdsFixedAtBuild]
># if there's enough free memory for all of them. The pool allocation for 
> the
># type related to cleared bits keeps the same as ususal.
>#
> +  # The heap guard system only supports guarding EfiRuntimeServicesCode, 
> EfiRuntimeServicesData,
> +  # EfiReservedMemoryType, and EfiACPIMemoryNVS memory types for systems 
> that have
> +  # RUNTIME_PAGE_ALLOCATION_GRANULARITY == EFI_PAGE_SIZE. This is to 
> preserve alignment requirements
> +  # without extending the page guard size to very large granularities.
> +  #
># This PCD is only valid if BIT1 and/or BIT3 are set in 
>

Re: [edk2-devel] [PATCH 4/4][edk2-redfish-client] RedfishClientPkg: fix memory leak

2024-03-11 Thread Nickle Wang via groups.io




Reviewed-by: Nickle Wang 

Regards,
Nickle

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Mike
> Maslenkin via groups.io
> Sent: Sunday, March 10, 2024 6:42 PM
> To: devel@edk2.groups.io
> Cc: Mike Maslenkin ; Abner Chang
> ; Igor Kulchytskyy ; Nickle Wang
> 
> Subject: [edk2-devel] [PATCH 4/4][edk2-redfish-client] RedfishClientPkg: fix
> memory leak
> 
> External email: Use caution opening links or attachments
> 
> 
> The structure instance retunred by ToStructure() must be deallocated properly.
> 
> Cc: Abner Chang 
> Cc: Igor Kulchytskyy 
> Cc: Nickle Wang 
> Signed-off-by: Mike Maslenkin 
> ---
>  .../v1_5_0/RedfishResourceIdentifyLibComputerSystem.c| 9 ++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git
> a/RedfishClientPkg/Library/RedfishResourceIdentifyLibComputerSystem/v1_5_0/
> RedfishResourceIdentifyLibComputerSystem.c
> b/RedfishClientPkg/Library/RedfishResourceIdentifyLibComputerSystem/v1_5_0/
> RedfishResourceIdentifyLibComputerSystem.c
> index 29b4f525d5ff..2f177b8032cc 100644
> ---
> a/RedfishClientPkg/Library/RedfishResourceIdentifyLibComputerSystem/v1_5_0/
> RedfishResourceIdentifyLibComputerSystem.c
> +++ b/RedfishClientPkg/Library/RedfishResourceIdentifyLibComputerSystem/
> +++ v1_5_0/RedfishResourceIdentifyLibComputerSystem.c
> @@ -70,19 +70,20 @@ RedfishIdentifyResource (
>ComputerSystemCs = ComputerSystem->ComputerSystem;
> 
> 
> 
>if (IS_EMPTY_STRING (ComputerSystemCs->UUID)) {
> 
> -return FALSE;
> 
> +Status = EFI_NOT_FOUND;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>Status = AsciiStrToGuid (ComputerSystemCs->UUID, );
> 
>if (EFI_ERROR (Status)) {
> 
>  DEBUG ((DEBUG_ERROR, "%a, fail to get resource UUID: %r\n", __func__,
> Status));
> 
> -return FALSE;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>Status = NetLibGetSystemGuid ();
> 
>if (EFI_ERROR (Status)) {
> 
>  DEBUG ((DEBUG_ERROR, "%a, fail to get system UUID from SMBIOS: %r\n",
> __func__, Status));
> 
> -return FALSE;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>DEBUG ((REDFISH_DEBUG_TRACE, "%a, Identify: System: %g Resource: %g\n",
> __func__, , ));
> 
> @@ -92,6 +93,8 @@ RedfishIdentifyResource (
>  Status = EFI_UNSUPPORTED;
> 
>}
> 
> 
> 
> +ON_RELEASE:
> 
> +
> 
>mJsonStructProtocol->DestoryStructure (
> 
>   mJsonStructProtocol,
> 
>   (EFI_REST_JSON_STRUCTURE_HEADER *)ComputerSystem
> 
> --
> 2.32.0 (Apple Git-132)
> 
> 
> 
> -=-=-=-=-=-=
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Re: [edk2-devel] [PATCH 3/4][edk2-redfish-client] RedfishClientPkg: fix leak in provisioning properties functions

2024-03-11 Thread Nickle Wang via groups.io




Reviewed-by: Nickle Wang 

Regards,
Nickle

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Mike
> Maslenkin via groups.io
> Sent: Sunday, March 10, 2024 6:42 PM
> To: devel@edk2.groups.io
> Cc: Mike Maslenkin ; Abner Chang
> ; Igor Kulchytskyy ; Nickle Wang
> 
> Subject: [edk2-devel] [PATCH 3/4][edk2-redfish-client] RedfishClientPkg: fix 
> leak
> in provisioning properties functions
> 
> External email: Use caution opening links or attachments
> 
> 
> The structure instance retunred by ToStructure() must be deallocated properly.
> 
> Cc: Abner Chang 
> Cc: Igor Kulchytskyy 
> Cc: Nickle Wang 
> Signed-off-by: Mike Maslenkin 
> ---
>  .../v1_13_0/Common/ComputerSystemCommon.c | 25 +--
>  .../v1_5_0/Common/ComputerSystemCommon.c  | 25 +--
>  2 files changed, 36 insertions(+), 14 deletions(-)
> 
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.c
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.c
> index df22a1c90c46..4795e4d6c6eb 100644
> ---
> a/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSyst
> emCommon.c
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_13_0/Common/ComputerSy
> +++ stemCommon.c
> @@ -263,7 +263,7 @@ ProvisioningComputerSystemProperties (
>);
> 
>if (EFI_ERROR (Status)) {
> 
>  DEBUG ((DEBUG_ERROR, "%a: ToStructure failure: %r\n", __func__, Status));
> 
> -return Status;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>ComputerSystemCs = ComputerSystem->ComputerSystem;
> 
> @@ -365,7 +365,7 @@ ProvisioningComputerSystemProperties (
>   );
> 
>if (EFI_ERROR (Status)) {
> 
>  DEBUG ((DEBUG_ERROR, "%a: ToJson() failed: %r\n", __func__, Status));
> 
> -return Status;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>if (PropertyChanged) {
> 
> @@ -374,10 +374,14 @@ ProvisioningComputerSystemProperties (
>  if (EFI_ERROR (Status)) {
> 
>DEBUG ((DEBUG_ERROR, "%a: Fail to remove Redfish unchangeable
> properties from ResultJson.\n", __func__));
> 
>*ResultJson = NULL;
> 
> -  return Status;
> 
> +  goto ON_RELEASE;
> 
>  }
> 
>}
> 
> 
> 
> +  Status = EFI_SUCCESS;
> 
> +
> 
> +ON_RELEASE:
> 
> +
> 
>//
> 
>// Release resource.
> 
>//
> 
> @@ -393,10 +397,17 @@ ProvisioningComputerSystemProperties (
>  DestoryRedfishCharArray (ComputerSystemCsEmpty->Boot->BootOrder,
> ArraySize);
> 
>}
> 
> 
> 
> -  JsonStructProtocol->DestoryStructure (
> 
> -JsonStructProtocol,
> 
> -(EFI_REST_JSON_STRUCTURE_HEADER *)ComputerSystemEmpty
> 
> -);
> 
> +  if (ComputerSystemEmpty != NULL) {
> 
> +JsonStructProtocol->DestoryStructure (
> 
> +  JsonStructProtocol,
> 
> +  (EFI_REST_JSON_STRUCTURE_HEADER
> + *)ComputerSystemEmpty
> 
> +  );
> 
> +  }
> 
> +
> 
> +  if (EFI_ERROR (Status)) {
> 
> +return Status;
> 
> +  }
> 
> +
> 
>return (PropertyChanged ? EFI_SUCCESS : EFI_NOT_FOUND);
> 
>  }
> 
> 
> 
> diff --git
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSyste
> mCommon.c
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSyste
> mCommon.c
> index c383cad59029..2d257e01da2b 100644
> ---
> a/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSyste
> mCommon.c
> +++
> b/RedfishClientPkg/Features/ComputerSystem/v1_5_0/Common/ComputerSys
> +++ temCommon.c
> @@ -793,7 +793,7 @@ ProvisioningComputerSystemProperties (
>);
> 
>if (EFI_ERROR (Status)) {
> 
>  DEBUG ((DEBUG_ERROR, "%a: ToStructure failure: %r\n", __func__, Status));
> 
> -return Status;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>ComputerSystemCs = ComputerSystem->ComputerSystem;
> 
> @@ -1235,7 +1235,7 @@ ProvisioningComputerSystemProperties (
>   );
> 
>if (EFI_ERROR (Status)) {
> 
>  DEBUG ((DEBUG_ERROR, "%a: ToJson() failed: %r\n", __func__, Status));
> 
> -return Status;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>if (PropertyChanged) {
> 
> @@ -1244,10 +1244,14 @@ ProvisioningComputerSystemProperties (
>  if (EFI_ERROR (Status)) {
> 
>DEBUG ((DEBUG_ERROR, "%a: Fail to remove Redfish unchangeable
> properties from ResultJson.\n", __func__));
> 
>*ResultJson = NULL;
> 
> -  return Status;
> 
> +  goto ON_RELEASE;
> 
>  }
> 
>}
> 
> 
> 
> +  Status = EFI_SUCCESS;
> 
> +
> 
> +ON_RELEASE:
> 
> +
> 
>//
> 
>// Release resource.
> 
>//
> 
> @@ -1263,10 +1267,17 @@ ProvisioningComputerSystemProperties (
>  DestoryRedfishCharArray (ComputerSystemCsEmpty->Boot->BootOrder,
> ArraySize);
> 
>}
> 
> 
> 
> -  JsonStructProtocol->DestoryStructure (
> 
> -

Re: [edk2-devel] [PATCH 2/4][edk2-redfish-client] RedfishClientPkg: fix leak in provisioning properties functions

2024-03-11 Thread Nickle Wang via groups.io




Reviewed-by: Nickle Wang 

Regards,
Nickle

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Mike
> Maslenkin via groups.io
> Sent: Sunday, March 10, 2024 6:42 PM
> To: devel@edk2.groups.io
> Cc: Mike Maslenkin ; Abner Chang
> ; Igor Kulchytskyy ; Nickle Wang
> 
> Subject: [edk2-devel] [PATCH 2/4][edk2-redfish-client] RedfishClientPkg: fix 
> leak
> in provisioning properties functions
> 
> External email: Use caution opening links or attachments
> 
> 
> The structure instance retunred by ToStructure() must be deallocated properly.
> 
> Cc: Abner Chang 
> Cc: Igor Kulchytskyy 
> Cc: Nickle Wang 
> Signed-off-by: Mike Maslenkin 
> ---
>  RedfishClientPkg/Features/Bios/v1_0_9/Common/BiosCommon.c| 5 -
>  .../Features/BootOption/v1_0_4/Common/BootOptionCommon.c | 5 -
>  .../Features/Memory/V1_7_1/Common/MemoryCommon.c | 5 -
>  3 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/RedfishClientPkg/Features/Bios/v1_0_9/Common/BiosCommon.c
> b/RedfishClientPkg/Features/Bios/v1_0_9/Common/BiosCommon.c
> index 1eb269a84222..f40fe215afeb 100644
> --- a/RedfishClientPkg/Features/Bios/v1_0_9/Common/BiosCommon.c
> +++ b/RedfishClientPkg/Features/Bios/v1_0_9/Common/BiosCommon.c
> @@ -247,7 +247,6 @@ ProvisioningBiosProperties (
>   );
> 
>if (EFI_ERROR (Status)) {
> 
>  DEBUG ((DEBUG_ERROR, "%a, ToJson() failed: %r\n", __func__, Status));
> 
> -return Status;
> 
>}
> 
> 
> 
>//
> 
> @@ -258,6 +257,10 @@ ProvisioningBiosProperties (
>  (EFI_REST_JSON_STRUCTURE_HEADER *)Bios
> 
>  );
> 
> 
> 
> +  if (EFI_ERROR (Status)) {
> 
> +return Status;
> 
> +  }
> 
> +
> 
>return (PropertyChanged ? EFI_SUCCESS : EFI_NOT_FOUND);
> 
>  }
> 
> 
> 
> diff --git
> a/RedfishClientPkg/Features/BootOption/v1_0_4/Common/BootOptionCommon.
> c
> b/RedfishClientPkg/Features/BootOption/v1_0_4/Common/BootOptionCommon.
> c
> index 339c8ba04103..358b32253973 100644
> ---
> a/RedfishClientPkg/Features/BootOption/v1_0_4/Common/BootOptionCommon.
> c
> +++
> b/RedfishClientPkg/Features/BootOption/v1_0_4/Common/BootOptionCommo
> +++ n.c
> @@ -334,7 +334,6 @@ ON_RELEASE:
>   );
> 
>if (EFI_ERROR (Status)) {
> 
>  DEBUG ((DEBUG_ERROR, "%a: ToJson() failed: %r\n", __func__, Status));
> 
> -return Status;
> 
>}
> 
> 
> 
>//
> 
> @@ -345,6 +344,10 @@ ON_RELEASE:
>  (EFI_REST_JSON_STRUCTURE_HEADER *)BootOption
> 
>  );
> 
> 
> 
> +  if (EFI_ERROR (Status)) {
> 
> +return Status;
> 
> +  }
> 
> +
> 
>return (PropertyChanged ? EFI_SUCCESS : EFI_NOT_FOUND);
> 
>  }
> 
> 
> 
> diff --git
> a/RedfishClientPkg/Features/Memory/V1_7_1/Common/MemoryCommon.c
> b/RedfishClientPkg/Features/Memory/V1_7_1/Common/MemoryCommon.c
> index e873f05ca040..39ec7ec0c34b 100644
> --- a/RedfishClientPkg/Features/Memory/V1_7_1/Common/MemoryCommon.c
> +++ b/RedfishClientPkg/Features/Memory/V1_7_1/Common/MemoryCommon.c
> @@ -2133,7 +2133,6 @@ ProvisioningMemoryProperties (
>   );
> 
>if (EFI_ERROR (Status)) {
> 
>  DEBUG ((DEBUG_ERROR, "%a, ToJson() failed: %r\n", __func__, Status));
> 
> -return Status;
> 
>}
> 
> 
> 
>//
> 
> @@ -2144,6 +2143,10 @@ ProvisioningMemoryProperties (
>  (EFI_REST_JSON_STRUCTURE_HEADER *)Memory
> 
>  );
> 
> 
> 
> +  if (EFI_ERROR (Status)) {
> 
> +return Status;
> 
> +  }
> 
> +
> 
>return (PropertyChanged ? EFI_SUCCESS : EFI_NOT_FOUND);
> 
>  }
> 
> 
> 
> --
> 2.32.0 (Apple Git-132)
> 
> 
> 
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Re: [edk2-devel] [PATCH 1/4][edk2-redfish-client] RedfishClientPkg: fix memory leak

2024-03-11 Thread Nickle Wang via groups.io




Reviewed-by: Nickle Wang 

Regards,
Nickle

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Mike
> Maslenkin via groups.io
> Sent: Sunday, March 10, 2024 6:42 PM
> To: devel@edk2.groups.io
> Cc: Mike Maslenkin ; Abner Chang
> ; Igor Kulchytskyy ; Nickle Wang
> 
> Subject: [edk2-devel] [PATCH 1/4][edk2-redfish-client] RedfishClientPkg: fix
> memory leak
> 
> External email: Use caution opening links or attachments
> 
> 
> This patch fixes leak of EFI_REDFISH_COMPUTERSYSTEMCOLLECTION instance
> on error path.
> 
> Cc: Abner Chang 
> Cc: Igor Kulchytskyy 
> Cc: Nickle Wang 
> Signed-off-by: Mike Maslenkin 
> ---
>  .../ComputerSystemCollectionDxe.c| 12 +---
>  .../MemoryCollectionDxe/MemoryCollectionDxe.c| 11 ---
>  2 files changed, 17 insertions(+), 6 deletions(-)
> 
> diff --git
> a/RedfishClientPkg/Features/ComputerSystemCollectionDxe/ComputerSystemCo
> llectionDxe.c
> b/RedfishClientPkg/Features/ComputerSystemCollectionDxe/ComputerSystemCo
> llectionDxe.c
> index 55a6d07dbf2e..3deefa824629 100644
> ---
> a/RedfishClientPkg/Features/ComputerSystemCollectionDxe/ComputerSystemCo
> llectionDxe.c
> +++ b/RedfishClientPkg/Features/ComputerSystemCollectionDxe/ComputerSyst
> +++ emCollectionDxe.c
> @@ -174,11 +174,13 @@ HandleCollectionResource (
>CollectionCs = Collection->ComputerSystemCollection;
> 
> 
> 
>if (*CollectionCs->Membersodata_count == 0) {
> 
> -return EFI_NOT_FOUND;
> 
> +Status = EFI_NOT_FOUND;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>if (IsLinkEmpty (>Members)) {
> 
> -return EFI_NOT_FOUND;
> 
> +Status = EFI_NOT_FOUND;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>List = GetFirstLink (>Members);
> 
> @@ -206,12 +208,16 @@ HandleCollectionResource (
>  List = GetNextLink (>Members, List);
> 
>}
> 
> 
> 
> +  Status = EFI_SUCCESS;
> 
> +
> 
> +ON_RELEASE:
> 
> +
> 
>//
> 
>// Release resource.
> 
>//
> 
>Private->JsonStructProtocol->DestoryStructure (Private->JsonStructProtocol,
> (EFI_REST_JSON_STRUCTURE_HEADER *)Collection);
> 
> 
> 
> -  return EFI_SUCCESS;
> 
> +  return Status;
> 
>  }
> 
> 
> 
>  EFI_STATUS
> 
> diff --git
> a/RedfishClientPkg/Features/MemoryCollectionDxe/MemoryCollectionDxe.c
> b/RedfishClientPkg/Features/MemoryCollectionDxe/MemoryCollectionDxe.c
> index d963fb52ad37..38f28f902715 100644
> --- a/RedfishClientPkg/Features/MemoryCollectionDxe/MemoryCollectionDxe.c
> +++ b/RedfishClientPkg/Features/MemoryCollectionDxe/MemoryCollectionDxe.
> +++ c
> @@ -165,11 +165,13 @@ HandleCollectionResource (
>CollectionCs = Collection->MemoryCollection;
> 
> 
> 
>if (*CollectionCs->Membersodata_count == 0) {
> 
> -return EFI_NOT_FOUND;
> 
> +Status = EFI_NOT_FOUND;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>if (IsLinkEmpty (>Members)) {
> 
> -return EFI_NOT_FOUND;
> 
> +Status = EFI_NOT_FOUND;
> 
> +goto ON_RELEASE;
> 
>}
> 
> 
> 
>List = GetFirstLink (>Members);
> 
> @@ -197,12 +199,15 @@ HandleCollectionResource (
>  List = GetNextLink (>Members, List);
> 
>}
> 
> 
> 
> +  Status = EFI_SUCCESS;
> 
> +
> 
> +ON_RELEASE:
> 
>//
> 
>// Release resource.
> 
>//
> 
>Private->JsonStructProtocol->DestoryStructure (Private->JsonStructProtocol,
> (EFI_REST_JSON_STRUCTURE_HEADER *)Collection);
> 
> 
> 
> -  return EFI_SUCCESS;
> 
> +  return Status;
> 
>  }
> 
> 
> 
>  EFI_STATUS
> 
> --
> 2.32.0 (Apple Git-132)
> 
> 
> 
> -=-=-=-=-=-=
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Re: [edk2-devel] [edk2-platforms][PATCH v4 8/8] Platform/Sgi: Add CPPC support for RD-Fremont platform

2024-03-11 Thread Prabin CA

Hi Levi,
Thank you for taking the time to review these patches and providing corrections.

For RD platforms, We don't have any performance limited register. During CPPC 
testing with Linux as the OS, we've observed that Linux utilizes only the 
performance set level channel and does not utilize the performance limit set 
channels. Even when we attempt to set the performance limit from Linux sysfs, 
the kernel handles this internally without forwarding any limit set requests to 
the platform firmware. Consequently, as these registers are optional, we are 
not using these channels. Looking ahead to potential future implementations, 
it's anticipated that the performance limited register will come into play. 
That's why we've included the performance limited register. if you have any 
suggestions, please do share.

The decision to use the fast channel address was influenced by potentially 
misleading information found in the FFH specification v1.2, under chapter 
'B.2.2 Performance Controls', where the performance limited register address 
was indicated as the next address after the 'Desired Performance Register'. 
We've now updated the _CPC object with a value address of 0 for the performance 
limited register (we will make the similar changes for older platforms as well 
and post as a new series). Please do let us know if you have any suggestions on 
using any specific register for the performance limited register. Your input 
would be greatly appreciated.

Thanks,
Prabin CA


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Re: [edk2-devel] [edk2-platforms][PATCH v4 4/8] Platform/Sgi: Add ACPI tables for RD-Fremont platform

2024-03-11 Thread Prabin CA

Hi Levi,

The patches to use dynamic tables are under development and so the PCIe support 
will follow after your patches.

Thanks,

Prabin CA


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[edk2-devel] [edk2-platforms][PATCH v5 9/9] Platform/Sgi: Add CPPC support for RD-Fremont platform

2024-03-11 Thread Prabin CA

Enable ACPI CPPC mechanism for RD-Fremont as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with LCP to set the
desired performance. In addition to this, RD-Fremont platform does not
support CPPC revision 1 and below. So update the _OSC method to let OSPM
know about this fact.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf |   1 +
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 162 

 2 files changed, 163 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
index 7556c1239116..fcaa3299c4ea 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -48,6 +48,7 @@ [FixedPcd]
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
   gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
   gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdOscCppcEnable
   gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
index f921eeb2d99e..9c7266c79285 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -11,6 +11,10 @@
 *   - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States
 *   - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1,
 * Idle management and Low Power Idle states
+*   - ACPI 6.5, Chapter 8, Section 8.4.6, Collaborative Processor Performance
+* Control
+*   - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.2,
+* Performance management and Collaborative Processor Performance Control
 *
 **/
 
@@ -43,6 +47,20 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
   Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
 }
   }
+
+  If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+/* CPPC revision 1 and below not supported */
+And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+
+  If (And (CAP0, OSC_CAP_CPPC2_SUPPORT)) {
+if (LEqual (FixedPcdGet32 (PcdOscCppcEnable), Zero)) {
+  And (CAP0, Not (OSC_CAP_CPPC2_SUPPORT), CAP0)
+  Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+}
+  }
+
 } Else {
   And (STS0, Not (OSC_STS_MASK), STS0)
   Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -116,6 +134,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 0)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200093000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (0)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -131,6 +158,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 1)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200293000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (1)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -146,6 +182,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 2)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200493000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (2)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -161,6 +206,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 3)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200693000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (3)
+})
+
 Method (_LPI, 0, NotSerialized) {
   Return (\_SB.PLPI)
 }
@@ -176,6 +230,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", 
"ARMSGI",
 Name (_UID, 4)
 Name (_STA, 0xF)
 
+Name (_CPC, Package()
+  CPPC_PACKAGE_INIT (0x200893000, 0x0, 20, 160, 160, 85, 85, 5)
+)
+
+Name (_PSD, Package () {
+  Package ()
+PSD_INIT (4)
+})
+
 Method (_LPI, 0, NotSerialized) {

[edk2-devel] [edk2-platforms][PATCH v5 8/9] Platform/Sgi: Low Power Idle States for RD-Fremont

2024-03-11 Thread Prabin CA

RD-Fremont platform supports two LPI states, LPI1 (Standby WFI) and LPI3
(Power-down). The cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf |   1 +
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 154 

 2 files changed, 155 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
index 9d07001dec96..7556c1239116 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -48,6 +48,7 @@ [FixedPcd]
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
   gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
   gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
   gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
index 8812ea877f7a..f921eeb2d99e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -8,6 +8,9 @@
 * @par Specification Reference:
 *   - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description
 * Table (DSDT)
+*   - ACPI 6.5, Chapter 8, Section 8.4.3, Lower Power Idle States
+*   - Arm Functional Fixed Hardware Specification v1.2, Chapter 3, Section 3.1,
+* Idle management and Low Power Idle states
 *
 **/
 
@@ -17,6 +20,93 @@
 DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
  EFI_ACPI_ARM_OEM_REVISION) {
   Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+  CreateDWordField (Arg3, 0x00, STS0)
+  CreateDWordField (Arg3, 0x04, CAP0)
+
+  /* Platform-wide Capabilities */
+  If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+
+  If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+  }
+
+  If (And (CAP0, OSC_CAP_PLAT_COORDINATED_LPI)) {
+if (LEqual (FixedPcdGet32 (PcdOscLpiEnable), Zero)) {
+  And (CAP0, Not (OSC_CAP_PLAT_COORDINATED_LPI), CAP0)
+  Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+}
+  }
+} Else {
+  And (STS0, Not (OSC_STS_MASK), STS0)
+  Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+  } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+  }
+
+  Return (Arg3)
+}
+
+Name (PLPI, Package () {  /* LPI for Processor, support 2 LPI states */
+  0,  // Version
+  0,  // Level Index
+  2,  // Count
+  Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+0,// Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x,   // Address
+3,// Access Size
+  )
+},
+ResourceTemplate () { // Null Residency Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+  Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+  },
+  Package () {// Power Gating state for CPU
+150,  // Min residency (uS)
+350,  // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+0,// Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+  Register (FFixedHW,
+32,   // Bit Width
+0,// Bit Offset
+0x4002,   // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+  )
+},
+

[edk2-devel] [edk2-platforms][PATCH v5 7/9] Platform/Sgi: Extend SMBIOS support for RD-Fremont

2024-03-11 Thread Prabin CA

Extend the SMBIOS support for RD-Fremont platform. RD-Fremont is a
16 core platform with Poseidon CPU. Each of the CPUs include
64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 
+
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 5 
-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 5 
-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 1 +
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 
++
 5 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h 
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 6fa39d407bc9..acfa45910aed 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -51,6 +51,10 @@
 #define RD_V2_PART_NUM0x7F2
 #define RD_V2_CONF_ID 0x1
 
+// RD-Fremont Platform Identification values
+#define RD_Fremont_PART_NUM   0x7EE
+#define RD_Fremont_CONF_ID0x1
+
 #define SGI_CONFIG_MASK   0x0F
 #define SGI_CONFIG_SHIFT  0x1C
 #define SGI_PART_NUM_MASK 0xFFF
@@ -90,6 +94,7 @@ typedef enum {
   RdN2Cfg1,
   RdN2Cfg2,
   RdV2,
+  RdFremont,
 } ARM_RD_PRODUCT_ID;
 
 // Arm ProductId look-up table
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index edf2a5f63c63..9c28b051ebc2 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -34,7 +34,8 @@
   "RdN2\0"  \
   "RdN2Cfg1\0"  \
   "RdN2Cfg2\0"  \
-  "RdV2\0"
+  "RdV2\0"  \
+  "RdFremont\0"
 
 typedef enum {
   ManufacturerName = 1,
@@ -74,6 +75,8 @@ STATIC GUID mSmbiosUid[] = {
   {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1, 
0x60}},
   /* Rd-V2 */
   {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43, 
0x45}},
+  /* Rd-Fremont*/
+  {0x904b28d6, 0x0662, 0x11ed, {0xb9, 0x39, 0x02, 0x42, 0xac, 0x12, 0x00, 
0x02}},
 };
 
 /* System information */
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index ee269f707714..c39c1553f6aa 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -44,6 +44,7 @@
   "Neoverse-N2\0"   \
   "Neoverse-N2\0"   \
   "Neoverse-V2\0"   \
+  "Neoverse-Poseidon\0" \
   "000-0\0" /* Serial number */ \
   "783-3\0" \
   "786-1\0" \
@@ -54,7 +55,8 @@
   "7B7-1\0" \
   "7B6-1\0" \
   "7B7-1\0" \
-  "7F2-1\0"
+  "7F2-1\0" \
+  "7EE-1\0"
 
 typedef enum {
   PartNumber = 1,
@@ -181,6 +183,7 @@ InstallType4ProcessorInformation (
   case RdN2:
   case RdN2Cfg1:
   case RdV2:
+  case RdFremont:
 mArmRdSmbiosType4.Base.CoreCount = CoreCount;
 mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
 mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git 
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c 
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index 4af72919a3f1..4cdea5b3b763 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -335,6 +335,7 @@ InstallType7CacheInformation (
 mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
 break;
   case RdV2:
+  case RdFremont:
 /* L1 instruction cache */
 mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;// 64KB
 mArmRdSmbiosType7[0].Base.InstalledSize2 = 64;   // 64KB
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c 
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index 14b06796ae9c..ae31be142d12 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++

[edk2-devel] [edk2-platforms][PATCH v5 6/9] Platform/Sgi: Add initial support for RD-Fremont platform

2024-03-11 Thread Prabin CA

The RD-Fremont fixed virtual platform simulates 16 CPUs and 8GB of RAM.
Add initial support for this platform by adding the required platform
build configuration files. This platform has considerable differences in
its memory map compared to its predecessors. So add a corresponding
memory map file as well to define the PCDs for its generation of
platforms.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc   | 71 
 Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc | 55 +++
 Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc | 10 +++
 3 files changed, 136 insertions(+)

diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc 
b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc
new file mode 100644
index ..06c3b37388c1
--- /dev/null
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc
@@ -0,0 +1,71 @@
+#
+#  Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[PcdsFixedAtBuild.common]
+  # System Peripherals
+  gArmSgiTokenSpaceGuid.PcdSmcCs0Base|0x0800
+  gArmSgiTokenSpaceGuid.PcdSmcCs1Base|0x06
+  gArmSgiTokenSpaceGuid.PcdSysPeriphBase|0x0C00
+  gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase|0x0C01
+
+  # SP804 dual timer
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x0C11
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x0001
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|216
+
+  # Virtio Disk
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x0C13
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x1
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt|184
+
+  # GPIO controller
+  gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D
+  gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
+  gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|168
+
+   # Ethernet
+  gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x0C15
+  gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|186
+
+  # PL031 RealTimeClock
+  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0C17
+
+  # Virtio P9
+  gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress|0x0C19
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Size|0x1
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt|185
+
+  # PL370 - HDLCD1
+  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0EF6
+
+  # PL011 - Serial Debug UART
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x0EF7
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt|179
+
+  # PL011 - Serial Terminal
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt|112
+
+  # System Memory (2GB - 128MB of Trusted DRAM at the top of the 32bit address 
space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7800
+
+  # SMMU
+  gArmSgiTokenSpaceGuid.PcdSmmuBase|0x28000
+  gArmSgiTokenSpaceGuid.PcdSmmuSize|0x400
+
+  # Non-Volatile variable storage
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x06
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x060140
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x060280
+
+  # Address bus width - 64TB address space
+  gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|46
+
+  # Timer & Watchdog interrupts
+  gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|109
+  gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|108
+  gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|110
+  gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|111
diff --git a/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc 
b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc
new file mode 100644
index ..b52d2f59e15d
--- /dev/null
+++ b/Platform/ARM/SgiPkg/RdFremont/RdFremont.dsc
@@ -0,0 +1,55 @@
+#
+#  Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+[Defines]
+  PLATFORM_NAME  = RdFremont
+  PLATFORM_GUID  = fd140b0f-4467-4314-aa69-cd0bd712e08e
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 0x0001001B
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= AARCH64
+  BUILD_TARGETS  = NOOPT|DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = Platform/ARM/SgiPkg/SgiPlatform.fdf
+  BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc
+  BUILD_NUMBER   = 1
+
+# include common definitions from SgiPlatform.dsc
+!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap3.dsc.inc
+
+# include common/basic libraries from MdePkg.
+!include MdePkg/MdeLibs.dsc.inc
+
+
+#
+# Pcd Section - list of

[edk2-devel] [edk2-platforms][PATCH v5 5/9] Platform/Sgi: Add ACPI tables for RD-Fremont platform

2024-03-11 Thread Prabin CA

From: Shriram K 

RD-Fremont is the next platform in the Arm's reference design platform
series. This platform includes 32 CPUs but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. In preparation for
adding support for this platform, add the initial set of ACPI tables and
reuse existing ACPI tables as applicable to boot a operating system on
this platform.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf |  73 
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl  | 196 

 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 ++
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 +
 4 files changed, 574 insertions(+)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
new file mode 100644
index ..9d07001dec96
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
@@ -0,0 +1,73 @@
+## @file
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2024, Arm Ltd. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 0x0001001A
+  BASE_NAME  = RdFremontAcpiTables
+  FILE_GUID  = c712719a-0aaf-438c-9cdd-35ab4d60207d  # 
gArmSgiAcpiTablesGuid
+  MODULE_TYPE= USER_DEFINED
+  VERSION_STRING = 1.0
+
+[Sources]
+  Dbg2.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  RdFremont/Dsdt.asl
+  RdFremont/Madt.aslc
+  RdFremont/Pptt.aslc
+  Spcr.aslc
+  SsdtEvents.asl
+  SsdtRos.asl
+  SsdtRosVirtioP9.asl
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmPlatformTokenSpaceGuid.PcdClusterCount
+
+  gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
+  gArmSgiTokenSpaceGuid.PcdGpioController0Size
+  gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
+  gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
+  gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
+  gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+  gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+  gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+  gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+  gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+  gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Size
+  gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt
+  gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
+  gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl 
b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
new file mode 100644
index ..8812ea877f7a
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
@@ -0,0 +1,196 @@
+/** @file
+*  Differentiated System Description Table Fields (DSDT)
+*
+*  Copyright (c) 2024, Arm Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+*   - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Description
+* Table (DSDT)
+*
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+  Scope (_SB) {
+Device (CL00) {   // Cluster 0
+  Name (_HID, "ACPI0010")
+  Name (_UID, 0)
+
+  Device (CP00) { // Neoverse Poseidon core 0
+Name (_HID, "ACPI0007")
+Name (_UID, 0)
+Name (_STA, 0xF)
+  }
+}
+
+Device (CL01) {   // Cluster 1
+  Name (_HID, "ACPI0010")
+  Name (_UID, 1)
+
+  Device (CP01) { // Neoverse Poseidon core 1
+Name (_HID, "ACPI0007")
+Name (_UID, 1)
+Name (_STA, 0xF)
+  }
+}
+
+Device (CL02) {   // Cluster 2
+  Name (_HID, "ACPI0010")
+  Name (_UID, 2)
+
+  Device (CP02) { // Neoverse Poseidon core 2
+Name

[edk2-devel] [edk2-platforms][PATCH v5 4/9] Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms

2024-03-11 Thread Prabin CA

Introducing a flag called PCIE_ENABLE, which can be set to TRUE or
FALSE from the respective .dsc files to enable or disable the
PCIe support. As not all reference design platforms have PCIe support
enabled, this flag is introduced.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatform.dec  |  1 +
 Platform/ARM/SgiPkg/SgiPlatform.dsc.inc  |  6 ++
 Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdV1/RdV1.dsc|  4 +++-
 Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc|  4 +++-
 Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc|  4 +++-
 Platform/ARM/SgiPkg/SgiPlatform.fdf  |  4 +++-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf  |  5 -
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 19 
+++
 11 files changed, 43 insertions(+), 16 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec 
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 4087ff6cad2e..af7887e54126 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -31,6 +31,7 @@ [Guids.common]
 [PcdsFeatureFlag.common]
   gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x0001
   gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x0010
+  gArmSgiTokenSpaceGuid.PcdPcieEnable|FALSE|BOOLEAN|0x002E
 
 [PcdsFixedAtBuild]
   gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x0002
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc 
b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 1cfe07c7e4ed..1bf489ffeb39 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -103,6 +103,10 @@ [PcdsFeatureFlag.common]
   gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|FALSE
 
+!if $(PCIE_ENABLE) == TRUE
+  gArmSgiTokenSpaceGuid.PcdPcieEnable|TRUE
+!endif
+
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdVFPEnabled|1
   gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
@@ -330,6 +334,7 @@ [Components.common]
   # Virtio Network
   OvmfPkg/VirtioNetDxe/VirtioNet.inf
 
+!if $(PCIE_ENABLE) == TRUE
   #
   # Required by PCI
   #
@@ -343,6 +348,7 @@ [Components.common]
 
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
   }
+!endif
 
   #
   # AHCI Support
diff --git a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc 
b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
index 32d67d380814..c7463da5203e 100644
--- a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
+++ b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,6 +22,8 @@ [Defines]
   BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.fdf.inc
   BUILD_NUMBER   = 1
 
+  DEFINE PCIE_ENABLE = TRUE
+
 # include common definitions from SgiPlatform.dsc
 !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
 !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
diff --git a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc 
b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
index 6c9a64df054f..77efec9d9533 100644
--- a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
+++ b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,6 +22,8 @@ [Defines]
   BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.fdf.inc
   BUILD_NUMBER   = 1
 
+  DEFINE PCIE_ENABLE = TRUE
+
 # include common definitions from SgiPlatform.dsc
 !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
 !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
diff --git a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc 
b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
index 10e5bfa29b46..521d88925059 100644
--- a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
+++ b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020-2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2020-2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,6 +22,8 @@ [Defines]
   BOARD_DXE_FV_COMPONENTS= 
Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.fdf.inc
   BUILD_NUMBER   = 1
 
+  DEFINE PCIE_ENABLE = TRUE
+
 # include common definitions from SgiPlatform.dsc
 !include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
 !include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
diff --git a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc

[edk2-devel] [edk2-platforms][PATCH v5 3/9] Platform/Sgi: Refactor system memory base and size definitions

2024-03-11 Thread Prabin CA

In preparation of adding the next generation of reference design
platform that have different memory map, refactor the
PcdSystemMemoryBase and PcdSystemMemorySize PCD definitions from the
common PCD definitions file into the various platform generation
specific memory map PCD definitions file.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc  | 8 +++-
 Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 8 +++-
 Platform/ARM/SgiPkg/SgiPlatform.dsc.inc   | 6 +-
 3 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc 
b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
index 0c577c42..eab43b23ec6d 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+#  Copyright (c) 2020 - 2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -67,3 +67,9 @@ [PcdsFixedAtBuild.common]
   gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D
   gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|136
+
+  # System Memory (1GB - 16MB of Trusted DRAM at the top of the
+  # 32bit address space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00
+
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc 
b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index de1d8ea24b89..35e27d42d5a2 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2020 - 2023, Arm Limited. All rights reserved.
+#  Copyright (c) 2020 - 2024, Arm Limited. All rights reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -75,3 +75,9 @@ [PcdsFixedAtBuild.common]
 
   # IO virtualization block
   gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base|0x108000
+
+  # System Memory (1GB - 16MB of Trusted DRAM at the top of the
+  # 32bit address space)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00
+
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc 
b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 26ecd9ed59a7..1cfe07c7e4ed 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -1,5 +1,5 @@
 #
-#  Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
+#  Copyright (c) 2018 - 2024, Arm Limited. All rights reserved.
 #  (C) Copyright 2021 Hewlett Packard Enterprise Development LP
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -131,10 +131,6 @@ [PcdsFixedAtBuild.common]
   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4
   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0
 
-  # System Memory (1GB - 16MB of Trusted DRAM at the top of the 32bit address 
space)
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F00
-
   # ACPI Table Version
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
 
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v5 2/9] Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64

2024-03-11 Thread Prabin CA

From: Vivek Gautam 

On RD-N2 and previous generation platforms, the base address was within
32-bit region. However, on upcoming platforms, the SMMUv3 base address
is beyond 32-bit address region. So, update the datatype of SMMUv3 base
PCD.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/SgiPlatform.dec  | 2 +-
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec 
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 103dff8471a7..4087ff6cad2e 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -79,7 +79,7 @@ [PcdsFixedAtBuild]
   gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|0|UINT32|0x0014
 
   # SMMU
-  gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x001D
+  gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT64|0x001D
   gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x001E
 
   # GPIO Controller
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c 
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
index fa3cfbc730f6..62c212f3c5b0 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2018-2023, ARM Limited. All rights reserved.
+*  Copyright (c) 2018-2024, Arm Limited. All rights reserved.
 *
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
@@ -167,8 +167,8 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Attributes  = 
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
   // Sub System Peripherals - SMMU
-  VirtualMemoryTable[++Index].PhysicalBase  = FixedPcdGet32 (PcdSmmuBase);
-  VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdSmmuBase);
+  VirtualMemoryTable[++Index].PhysicalBase  = FixedPcdGet64 (PcdSmmuBase);
+  VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSmmuBase);
   VirtualMemoryTable[Index].Length  = FixedPcdGet32 (PcdSmmuSize);
   VirtualMemoryTable[Index].Attributes  = 
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v5 1/9] Platform/Sgi: Correct typo in defining CPPC performance limited register

2024-03-11 Thread Prabin CA

The reference design platform currently lacks the CPPC (Collaborative
Processor Performance Control) performance limited register as defined
by the ACPI 6.x specification. There is a typo in the macro definition
where the 'fastchannel address of the performance limited register' is
mentioned instead of the 'performance limited register address'.
Correcting this typo. However, it's important to retain the reference to
the performance limited register in the macro for future use, as it will
prove useful once functionalities such as power metering devices are
enabled.

Signed-off-by: Prabin CA 
---
 Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h 
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 033d398fdb63..3e24f569c95a 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -469,8 +469,7 @@ typedef struct {
 
 @param [in] DesiredPerfReg  Fastchannel address for desired performance
 register.
-@param [in] PerfLimitedReg  Fastchannel address for performance limited
-register.
+@param [in] PerfLimitedReg  Address for performance limited register.
 @param [in] GranularityMHz  Granularity of the performance scale.
 @param [in] HighestPerf Highest performance in linear scale.
 @param [in] NominalPerf Nominal performance in linear scale.
-- 
2.34.1



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[edk2-devel] [edk2-platforms][PATCH v5 0/9] Platform/Sgi: Add support for RD-Fremont platform

2024-03-11 Thread Prabin CA

Changes since V4:
- Addressed the comments shared by Levi for V3.

Changes since V3:
- Rebase on top of latest upstream branch.

Changes since V2:
- Removed author's signed-off on the patches, which is owned by another author.

Changes since V1:
- Corrected memory map in the DSDT file.

This patch series introduce support for RD-Fremont reference design
platform. This platform includes 32 CPUs, but the fixed virtual platform
(FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in
the system and so the FVP simulates 16 clusters. Each of the CPUs
include 64KB L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache.
The platform also includes system level cache of 32MB and 8GB of RAM.
Also, this patch series adding the extended SMBIO support for RD-Fremont
platform.

In addition to patches that introduce RD-Fremont platform, there are
four patches that update support for existing platforms. The first patch
in this series correct the typo while defining the CPPC support.
The second patch in this series changes the data type of PcdSmmuBase
from u32 to u64. The third patch refactor the system memory map base and
size values. The fourth patch add a flag to enable PCIE support for
existing and future platforms.

This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/116262

Link to gitlab branch with the patches in this series -
https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/commits/topics/rdfremont/

Prabin CA (7):
  Platform/Sgi: Correct typo in defining CPPC performance limited register
  Platform/Sgi: Refactor system memory base and size definitions
  Platform/Sgi: Introduce a flag to enable PCIe support for RD Platforms
  Platform/Sgi: Add initial support for RD-Fremont platform
  Platform/Sgi: Extend SMBIOS support for RD-Fremont
  Platform/Sgi: Low Power Idle States for RD-Fremont
  Platform/Sgi: Add CPPC support for RD-Fremont platform

Shriram K (1):
  Platform/Sgi: Add ACPI tables for RD-Fremont platform

Vivek Gautam (1):
  Platform/Sgi: Update the datatype of PcdSmmuBase from u32 to u64

 Platform/ARM/SgiPkg/SgiPlatform.dec   |   
3 +-
 Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc  |   
8 +-
 Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc |   
8 +-
 Platform/ARM/SgiPkg/{SgiMemoryMap2.dsc.inc => SgiMemoryMap3.dsc.inc}  |  
88 ++--
 Platform/ARM/SgiPkg/SgiPlatform.dsc.inc   |  
12 +-
 Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc |   
4 +-
 Platform/ARM/SgiPkg/{RdV1/RdV1.dsc => RdFremont/RdFremont.dsc}|  
14 +-
 Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc |   
4 +-
 Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc |   
4 +-
 Platform/ARM/SgiPkg/RdV1/RdV1.dsc |   
4 +-
 Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc |   
4 +-
 Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc |   
4 +-
 Platform/ARM/SgiPkg/SgiPlatform.fdf   |   
4 +-
 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf|  
75 +++
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf   |   
5 +-
 Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h   |   
3 +-
 Platform/ARM/SgiPkg/Include/SgiPlatform.h |   
5 +
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c|   
5 +-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c |   
5 +-
 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c |   
1 +
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c |   
6 +
 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c  |  
25 +-
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 
512 
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc| 
138 ++
 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc| 
167 +++
 Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc   |  
10 +
 26 files changed, 1033 insertions(+), 85 deletions(-)
 copy Platform/ARM/SgiPkg/{SgiMemoryMap2.dsc.inc => SgiMemoryMap3.dsc.inc} (62%)
 copy Platform/ARM/SgiPkg/{RdV1/RdV1.dsc => RdFremont/RdFremont.dsc} (77%)
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc
 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc
 create mode 100644 Platform/ARM/SgiPkg/RdFremont/RdFremont.fdf.inc

-- 
2.34.1



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Re: [edk2-devel] [PATCH] BaseTools: FMMT Skip empty Lines while parsing FMMTConfig.ini

2024-03-11 Thread Ashraf Ali S

Thanks for the review.

I have triggered the PR under basetools : 
https://github.com/tianocore/edk2-basetools/pull/122

Thanks.,
S, Ashraf Ali

-Original Message-
From: devel@edk2.groups.io  On Behalf Of Yuwei Chen
Sent: Monday, March 11, 2024 1:22 PM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Rebecca Cran ; Liming Gao ; 
Feng, Bob C ; Chaganty, Rangasai V 

Subject: Re: [edk2-devel] [PATCH] BaseTools: FMMT Skip empty Lines while 
parsing FMMTConfig.ini

Ali, please also create PR in BaseTools repo.
Reviewed-by: Yuwei Chen 

> -Original Message-
> From: S, Ashraf Ali 
> Sent: Wednesday, February 28, 2024 5:57 PM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Rebecca Cran 
> ; Liming Gao ; Feng, Bob 
> C ; Chen, Christine ; 
> Chaganty, Rangasai V 
> Subject: [PATCH] BaseTools: FMMT Skip empty Lines while parsing 
> FMMTConfig.ini
> 
> When the FMMTConf.ini file has empty lines then it used to throw 
> errors GuidTool load error!, this patch is to skip checking for empty 
> lines in the ini file
> 
> Cc: Rebecca Cran 
> Cc: Liming Gao 
> Cc: Bob Feng 
> Cc: Yuwei Chen 
> Cc: Chen Christine 
> Cc: Chaganty Rangasai V 
> 
> Signed-off-by: Ashraf Ali 
> ---
>  BaseTools/Source/Python/FMMT/core/GuidTools.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/BaseTools/Source/Python/FMMT/core/GuidTools.py
> b/BaseTools/Source/Python/FMMT/core/GuidTools.py
> index f6bdeffa50..f9cfd4ead0 100644
> --- a/BaseTools/Source/Python/FMMT/core/GuidTools.py
> +++ b/BaseTools/Source/Python/FMMT/core/GuidTools.py
> @@ -153,7 +153,7 @@ class GUIDTools:
>  config_data = fd.readlines()
>  for line in config_data:
>  try:
> -if not line.startswith("#"):
> +if not line.startswith("#") and line.strip():
>  guid, short_name, command = line.split()
>  new_format_guid =
> struct2stream(ModifyGuidFormat(guid.strip()))
>  self.tooldef[new_format_guid] = GUIDTool(
> --
> 2.42.0.windows.2








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Re: [edk2-devel] [PATCH] Maintainers.txt: remove Laszlo's entries

2024-03-11 Thread Zeng, Star

Thank you Laszlo.

Is ler...@redhat.com still reachable for now ? 

-Original Message-
From: devel@edk2.groups.io  On Behalf Of gaoliming via 
groups.io
Sent: Monday, March 11, 2024 8:22 AM
To: devel@edk2.groups.io; pedro.falc...@gmail.com; ler...@redhat.com
Cc: Kinney, Michael D ; 'Andrew Fish' 
; 'Ard Biesheuvel' ; 'Gerd 
Hoffmann' ; Yao, Jiewen ; 'Leif 
Lindholm' ; Kumar, Rahul R 
; Ni, Ray ; 'Sami Mujawar' 

Subject: 回复: [edk2-devel] [PATCH] Maintainers.txt: remove Laszlo's entries

Thank you for your quick and great support on edk2 community. 

Thanks
Liming
> -邮件原件-
> 发件人: devel@edk2.groups.io  代表 Pedro Falcato
> 发送时间: 2024年3月8日 23:07
> 收件人: devel@edk2.groups.io; ler...@redhat.com
> 抄送: michael.d.kin...@intel.com; Andrew Fish ; Ard 
> Biesheuvel ; Gerd Hoffmann 
> ; Yao, Jiewen ; Leif Lindholm 
> ; Kumar, Rahul R ; 
> Ni, Ray ; Sami Mujawar 
> 主题: Re: [edk2-devel] [PATCH] Maintainers.txt: remove Laszlo's entries
> 
> On Fri, Mar 8, 2024 at 9:14 AM Laszlo Ersek  wrote:
> >
> > On 3/6/24 23:22, Michael D Kinney wrote:
> > > Reviewed-by: Michael D Kinney 
> >
> > Merged as commit ccf91b518f22, via
> > .
> >
> > Thank you all for everything,
> 
> Thank you for your great (and often thankless) work throughout the 
> whole of EDK2 and OVMF. It was great to have learned from you 
> throughout the years.
> 
> PS: CREDITS file anyone?
> 
> --
> Pedro
> 
> 
> 
> 










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[edk2-devel] [PATCH v1 26/26] OvmfPkg/LoongArchVirt: Add self introduction file

2024-03-11 Thread Chao Li

Add self introduction file for LoongArch virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Reviewed-by: Bibo Mao 
---
 OvmfPkg/LoongArchVirt/Readme.md | 69 +
 1 file changed, 69 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/Readme.md

diff --git a/OvmfPkg/LoongArchVirt/Readme.md b/OvmfPkg/LoongArchVirt/Readme.md
new file mode 100644
index 00..f57fbf6162
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Readme.md
@@ -0,0 +1,69 @@
+# LoongArch QEMU virt platform
+
+## Overview
+
+  LoongArch QEMU virt is a generic platform that dose not require any actual 
hardware.
+  The minimum required QEMU version is 
[8.1](https://gitlab.com/qemu-project/qemu/-/tags), the minimum required GCC 
version is [GCC13](https://gcc.gnu.org/gcc-13/), the minimum required Binutils 
version is [2.40](https://ftp.gnu.org/gnu/binutils/).
+
+## Prepare (X86 Linux Environment)
+
+### Fedora39 and higher
+Install LoongArch64 cross compiler, LoongArch system QEMU.
+
+yum install gcc-loongarch64-linux-gnu
+yum install qemu-system-loongarch64
+
+### Others X86 OS ENV
+ Configure cross-tools
+
+**Download:**
+
+wget 
https://github.com/loongson/build-tools/releases/download/2023.08.08/x86_64-cross-tools-loongarch64-binutils_2.41-gcc_13.2.0.tar.xz
+
+**Configure the cross-tools environment:**
+
+mkdir /opt/loongarch64_cross-toolchain/
+tar -vxf x86_64-cross-tools-loongarch64-binutils_2.41-gcc_13.2.0.tar.xz -C 
/opt/loongarch64_cross-toolchain/
+export PATH=/opt/loongarch64_cross-toolchain/cross-tools/bin:$PATH
+
+Note: Please obtain [the latest 
cross-compilation](https://github.com/loongson/build-tools) toolchains.
+
+ Build QEMU
+
+git clone https://gitlab.com/qemu-project/qemu.git
+
+Note: Please refer to QEMU compilation rules, located in 
qemu/doc/system/loongarch/virt.rst.
+
+
+## Build LoongArch QEMU virtual machine firmware
+ Get edk2 resouces
+
+git clone --recurse-submodule https://github.com/tianocore/edk2.git
+
+ Building LoongArch QEMU virt FW with GCC
+
+export WORKSPACE=`pwd`
+export GCC5_LOONGARCH64_PREFIX=loongarch64-unknown-linux-gnu-
+export PACKAGES_PATH=$WORKSPACE/edk2
+export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools
+source edk2/edksetup.sh --reconfig
+make -C edk2/BaseTools
+source edk2/edksetup.sh BaseTools
+build -b RELEASE -t GCC5 -a LOONGARCH64 -p 
OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc
+
+## Test LoongArch QEMU virtual machine firmware
+qemu-system-loongarch64 \
+-m 4G \
+-M virt \
+-smp 2 \
+-cpu la464 \
+-bios Build/LoongArchVirtQemu/RELEASE_GCC5/FV/QEMU_EFI.fd \
+-serial stdio
+
+## Test LoongArch QEMU virtual machine OS
+
+* Download ArchLinux QCOW 
[images](https://mirrors.pku.edu.cn/loongarch/archlinux/images) for LoongArch.
+
+* [Running LoongArch ArchLinux on virtual 
machine](https://mirrors.pku.edu.cn/loongarch/archlinux/images/README.html).
+
+* Download openEuler 22.03 LTS QCOW 
[images](https://mirrors.nju.edu.cn/openeuler/openEuler-22.03-LTS/virtual_machine_img/loongarch64/openEuler-22.03-LTS-LoongArch-loongarch64.qcow2.xz)
 for LoongArch.
-- 
2.27.0



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[edk2-devel] [PATCH v1 25/26] OvmfPkg/LoongArchVirt: Add build file

2024-03-11 Thread Chao Li

Add infrastructure files to build edk2 for LoongArch QEMU virtual
machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
Reviewed-by: Bibo Mao 
---
 OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc |  34 +
 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc | 680 
 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf | 313 +
 OvmfPkg/LoongArchVirt/VarStore.fdf.inc  |  67 ++
 4 files changed, 1094 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc
 create mode 100644 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc
 create mode 100644 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf
 create mode 100644 OvmfPkg/LoongArchVirt/VarStore.fdf.inc

diff --git a/OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc 
b/OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc
new file mode 100644
index 00..22373bec6a
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc
@@ -0,0 +1,34 @@
+## @file
+#
+#  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+DEFINE BLOCK_SIZE = 0x1000
+
+
+# FW total
+DEFINE FW_BASE_ADDRESS= 0x1c00
+DEFINE FW_BLOCKS  = 0x400
+DEFINE FW_SIZE= 0x40
+
+
+#Flash code layout
+#Set Sec size in flash
+DEFINE SECFV_SIZE = 0x0001
+
+#Set Pei size in flash
+DEFINE PEIFV_SIZE = 0x0004
+
+#Set Dxe size in flash
+DEFINE DXEFV_SIZE = 0x0035
+
+#Set FVMAIN size
+DEFINE FVMAIN_SIZE= $(SECFV_SIZE) + $(PEIFV_SIZE) 
+$(DXEFV_SIZE)
+
+#Set Memory layout
+DEFINE SEC_PEI_TEMP_RAM_BASE  = 0x1
+DEFINE SEC_PEI_TEMP_RAM_SIZE  = 0x8
+DEFINE DEVICE_TREE_RAM_BASE   = 0x10
diff --git a/OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc 
b/OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc
new file mode 100644
index 00..907132bbe0
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc
@@ -0,0 +1,680 @@
+## @file
+#
+#  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+###
+[Defines]
+  PLATFORM_NAME  = LoongArchVirtQemu
+  PLATFORMPKG_NAME   = LoongArchVirtQemu
+  PLATFORM_GUID  = 7926ea52-b0dc-4ee8-ac63-341eebd84ed4
+  PLATFORM_VERSION   = 0.1
+  DSC_SPECIFICATION  = 1.29
+  OUTPUT_DIRECTORY   = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES= LOONGARCH64
+  BUILD_TARGETS  = DEBUG|RELEASE
+  SKUID_IDENTIFIER   = DEFAULT
+  FLASH_DEFINITION   = OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf
+  TTY_TERMINAL   = FALSE
+
+!include LoongArchVirt.fdf.inc
+
+  #
+  # Defines for default states.  These can be changed on the command line.
+  # -D FLAG=VALUE
+  DEFINE TTY_TERMINAL= FALSE
+  DEFINE SECURE_BOOT_ENABLE  = FALSE
+  DEFINE TPM2_ENABLE = FALSE
+  DEFINE TPM2_CONFIG_ENABLE  = FALSE
+
+  #
+  # Network definition
+  #
+  DEFINE NETWORK_IP6_ENABLE  = FALSE
+  DEFINE NETWORK_HTTP_BOOT_ENABLE= FALSE
+  DEFINE NETWORK_SNP_ENABLE  = FALSE
+  DEFINE NETWORK_TLS_ENABLE  = FALSE
+  DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS  = TRUE
+  DEFINE NETWORK_ISCSI_ENABLE= FALSE
+
+!include NetworkPkg/NetworkDefines.dsc.inc
+
+#
+# Defines for default states.  These can be changed on the command line.
+# -D FLAG=VALUE
+
+[BuildOptions]
+  GCC:RELEASE_*_*_CC_FLAGS   = -DSPEEDUP
+
+  #
+  # Disable deprecated APIs.
+  #
+  GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
+
+!include NetworkPkg/NetworkBuildOptions.dsc.inc
+
+[BuildOptions.LOONGARCH64.EDKII.SEC]
+  *_*_*_CC_FLAGS =
+
+#
+# Default page size is 16K for loongarch qemu tcg
+# code section separated with data section with 16K page alignment, else data
+# write operation in the same page with code section will cause qemu TB flush.
+#
+[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION]
+  GCC:*_*_*_DLINK_FLAGS = -z

[edk2-devel] [PATCH v1 24/26] OvmfPkg/LoongArchVirt: Support PEI phase

2024-03-11 Thread Chao Li

Platfrom PEI module for LoongArch platfrom initialization.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
Reviewed-by: Bibo Mao 
---
 OvmfPkg/LoongArchVirt/PlatformPei/Fv.c|  39 ++
 OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c | 202 +
 OvmfPkg/LoongArchVirt/PlatformPei/Platform.c  | 393 ++
 OvmfPkg/LoongArchVirt/PlatformPei/Platform.h  | 128 ++
 .../LoongArchVirt/PlatformPei/PlatformPei.inf |  72 
 5 files changed, 834 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/Platform.c
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/Platform.h
 create mode 100644 OvmfPkg/LoongArchVirt/PlatformPei/PlatformPei.inf

diff --git a/OvmfPkg/LoongArchVirt/PlatformPei/Fv.c 
b/OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
new file mode 100644
index 00..d46326f135
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/PlatformPei/Fv.c
@@ -0,0 +1,39 @@
+/** @file
+  Build FV related hobs for platform.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include "Platform.h"
+
+/**
+  Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+  and DXE know about them.
+
+  @retval EFI_SUCCESS   Platform PEI FVs were initialized successfully.
+**/
+EFI_STATUS
+PeiFvInitialization (
+  VOID
+  )
+{
+  DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
+
+  //
+  // Create a memory allocation HOB for the PEI FV.
+  //
+  BuildMemoryAllocationHob (
+FixedPcdGet64 (PcdOvmfSecPeiTempRamBase),
+FixedPcdGet32 (PcdOvmfSecPeiTempRamSize),
+EfiBootServicesData
+);
+
+  return EFI_SUCCESS;
+}
diff --git a/OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c 
b/OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
new file mode 100644
index 00..61f61ee099
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c
@@ -0,0 +1,202 @@
+/** @file
+  Memory Detection for Virtual Machines.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "Platform.h"
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS  (128)
+#define LOONGARCH_FW_RAM_TOPBASE_256MB
+
+/**
+  Publish PEI core memory
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+**/
+EFI_STATUS
+PublishPeiMemory (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+  UINT64  Base;
+  UINT64  Size;
+  UINT64  RamTop;
+
+  //
+  // Determine the range of memory to use during PEI
+  //
+  Base   = FixedPcdGet64 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 
(PcdOvmfSecPeiTempRamSize);
+  RamTop = LOONGARCH_FW_RAM_TOP;
+  Size   = RamTop - Base;
+
+  //
+  // Publish this memory to the PEI Core
+  //
+  Status = PublishSystemMemory (Base, Size);
+  ASSERT_EFI_ERROR (Status);
+
+  DEBUG ((DEBUG_INFO, "Publish Memory Initialize done.\n"));
+  return Status;
+}
+
+/**
+  Peform Memory Detection
+  Publish system RAM and reserve memory regions
+**/
+VOID
+InitializeRamRegions (
+  VOID
+  )
+{
+  EFI_STATUSStatus;
+  FIRMWARE_CONFIG_ITEM  FwCfgItem;
+  UINTN FwCfgSize;
+  MEMMAP_ENTRY  MemoryMapEntry;
+  MEMMAP_ENTRY  *StartEntry;
+  MEMMAP_ENTRY  *pEntry;
+  UINTN Processed;
+
+  Status = QemuFwCfgFindFile ("etc/memmap", , );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/memmap error Status %d \n", __func__, 
__LINE__, Status));
+return;
+  }
+
+  if (FwCfgSize % sizeof MemoryMapEntry != 0) {
+DEBUG ((DEBUG_ERROR, "no MemoryMapEntry FwCfgSize:%d\n", FwCfgSize));
+return;
+  }
+
+  QemuFwCfgSelectItem (FwCfgItem);
+  StartEntry = AllocatePages (EFI_SIZE_TO_PAGES (FwCfgSize));
+  QemuFwCfgReadBytes (FwCfgSize, StartEntry);
+  for (Processed = 0; Processed < (FwCfgSize / sizeof MemoryMapEntry); 
Processed++) {
+pEntry = StartEntry + Processed;
+if (pEntry->Length == 0) {
+  continue;
+}
+
+DEBUG ((DEBUG_INFO, "MemmapEntry Base %p length %p  type %d\n", 
pEntry->BaseAddr, pEntry->Length, pEntry->Type));
+if (pEntry->Type != EfiAcpiAddressRangeMemory) {
+  continue;
+}
+
+AddMemoryRangeHob (pEntry->BaseAddr, pEntry->BaseAddr + pEntry->Length);
+  }
+
+  //
+  // When 0 address protection is enabled,
+  // 0-4k memory needs to be preallocated to prevent

[edk2-devel] [PATCH v1 23/26] OvmfPkg/LoongArchVirt: Support SEC phase

2024-03-11 Thread Chao Li

Add SEC code for LoongArch virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
Reviewed-by: Bibo Mao 
---
 OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S | 184 +++
 OvmfPkg/LoongArchVirt/Sec/SecMain.c   | 506 ++
 OvmfPkg/LoongArchVirt/Sec/SecMain.inf |  53 ++
 3 files changed, 743 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S
 create mode 100644 OvmfPkg/LoongArchVirt/Sec/SecMain.c
 create mode 100644 OvmfPkg/LoongArchVirt/Sec/SecMain.inf

diff --git a/OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S 
b/OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S
new file mode 100644
index 00..f3fa79289d
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S
@@ -0,0 +1,184 @@
+#--
+#
+# Start for Loongson LoongArch processor
+#
+# Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#  @par Glossary:
+#- CSR - CPU Status Register
+#- EBASE - Exception Base Address
+#--
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include 
+#include 
+#include 
+
+#define BOOTCORE_ID  0
+//
+// For coding convenience, define the maximum valid
+// LoongArch exception.
+// Since UEFI V2.11, it will be present in DebugSupport.h.
+//
+#define MAX_LOONGARCH_EXCEPTION  64
+
+ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+  /* Disable global interrupt */
+  bl   DisableInterrupts
+
+  /* Disable all local interrupt */
+  li.w $a0, 0x1FFF
+  bl   DisableLocalInterrupts
+
+  /* Read physical cpu number id */
+  bl   GetApicId
+  li.d $t0, BOOTCORE_ID  //0
+  bne  $a0, $t0, SlaveMain
+
+  /* Set BSP stack */
+  li.d $t0, FixedPcdGet64(PcdOvmfSecPeiTempRamBase) + 
FixedPcdGet32(PcdOvmfSecPeiTempRamSize)  # stack base
+  move $sp, $t0
+  addi.d   $sp, $sp, -0x8
+
+  /* Load the exception vector base address */
+  li.d $s0, FixedPcdGet64(PcdCpuExceptionVectorBaseAddress)
+
+  /* Construct SEC and PEI step exception environment */
+  la.pcrel $a1, ExceptionEntryStart
+  la.pcrel $t0, ExceptionEntryEnd
+  sub.d$a2, $t0, $a1
+  li.w $t0, (MAX_LOONGARCH_EXCEPTION +  MAX_LOONGARCH_INTERRUPT) * 512
+  bgeu $a2, $t0, DeadLoop
+  move $a0, $s0
+  bl   CopyMem
+
+  /* Configure BSP reset ebase */
+  move $a0, $s0
+  bl   SetExceptionBaseAddress
+
+CallEntry:
+  /* Call C function make sure parameter true */
+  li.d $a0, FixedPcdGet64(PcdOvmfFdBaseAddress) # FW base
+  addi.d   $a1, $sp, 0x8
+  bl   SecCoreStartupWithStack
+# End of _ModuleEntryPoint
+
+ASM_PFX(ClearMailBox):
+  /* Clear mailbox */
+  li.d  $t1, LOONGARCH_IOCSR_MBUF3
+  iocsrwr.d $zero, $t1
+  li.d  $t1, LOONGARCH_IOCSR_MBUF2
+  iocsrwr.d $zero, $t1
+  li.d  $t1, LOONGARCH_IOCSR_MBUF1
+  iocsrwr.d $zero, $t1
+  li.d  $t1, LOONGARCH_IOCSR_MBUF0
+  iocsrwr.d $zero, $t1
+  jirl  $zero, $ra, 0
+# End of ClearMailBox
+
+ASM_PFX(EnableIPI):
+  /* Enable IPI interrupt */
+  li.w  $t1, BIT12
+  csrxchg   $t1, $t1, LOONGARCH_CSR_ECFG
+
+  li.w  $t2, 0xU
+  li.d  $t1, LOONGARCH_IOCSR_IPI_EN
+  iocsrwr.w $t2, $t1
+  jirl  $zero, $ra, 0
+# End of EeableIPI
+
+#/**
+#   Get APIC ID for every CPU.
+#
+#   @param   NULL
+#   @return  APICID
+#
+#   UINTN
+#   EFI_API
+#   GetApicId (
+# VOID
+# )
+#**/
+ASM_PFX(GetApicId):
+  csrrd $a0, LOONGARCH_CSR_CPUNUM
+  andi  $a0, $a0, 0x3ff
+  jirl  $zero, $ra, 0
+# End of GetApicId
+
+ASM_PFX(ApInitStack):
+  li.d   $t1, SIZE_1KB
+  csrrd  $t0, LOONGARCH_CSR_TMID
+  mul.d  $t1, $t0, $t1
+  li.d   $t2, FixedPcdGet32(PcdCpuMaxLogicalProcessorNumber)
+  bgeu   $t0, $t2, DeadLoop
+  li.d   $t0, FixedPcdGet64(PcdOvmfSecPeiTempRamBase) + 
FixedPcdGet32(PcdOvmfSecPeiTempRamSize) - SIZE_64KB
+  sub.d  $sp, $t0, $t1
+  addi.d $sp, $sp, -0x8
+  jirl   $zero, $ra, 0
+# End of ApInitStack
+
+ASM_PFX(SlaveMain):
+  /* Set AP exception handle in flash */
+  la.pcrel  $a0, ApException
+  blSetExceptionBaseAddress
+
+  /* Clean up local mail box and open INT */
+  blClearMailBox
+  blEnableIPI
+  blEnableInterrupts
+
+WaitForWake:
+  /* Wait for wakeup */
+  blCpuSleep
+  b WaitForWake
+# End of SlaveMain
+
+.align 12
+ASM_PFX(ApException):
+  csrrd $t0, LOONGARCH_CSR_ESTAT
+  srli.d$t0, $t0, 12
+  andi  $t0, $t0, 0x1
+  beqz  $t0, DeadLoop
+
+  li.d  $t0, LOONGARCH_IOCSR_IPI_STATUS
+  iocsrrd.w $t1, $t0
+  li.d  $t0, LOONGARCH_IOCSR_IPI_CLEAR
+  iocsrwr.w $t1, $t0
+
+  /* Read mail buf and jump to specified entry */
+  li.d

[edk2-devel] [PATCH v1 22/26] OvmfPkg/LoongArchVirt: Add reset system library

2024-03-11 Thread Chao Li

This library provides interface related to restart and shudown the
LoongArch64 virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
Reviewed-by: Bibo Mao 
---
 .../BaseResetSystemAcpiGed.c  | 148 ++
 .../BaseResetSystemAcpiGedLib.inf |  36 +++
 .../DxeResetSystemAcpiGed.c   | 259 ++
 .../DxeResetSystemAcpiGedLib.inf  |  41 +++
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.c   | 125 +
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.h   |  23 ++
 6 files changed, 632 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGedLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGed.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/DxeResetSystemAcpiGedLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/ResetSystemAcpiGed.h

diff --git 
a/OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c 
b/OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
new file mode 100644
index 00..0d94a62a38
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/ResetSystemAcpiLib/BaseResetSystemAcpiGed.c
@@ -0,0 +1,148 @@
+/** @file
+  Base ResetSystem library implementation.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "ResetSystemAcpiGed.h"
+
+/**
+  Get configuration item data by the firmware configuration file name.
+
+  @param[in]  Name - Name of file to look up.
+
+  @returnVOID*   The Pointer of Value of Firmware Configuration item 
read.
+**/
+VOID *
+GetFwCfgData (
+  CONST CHAR8  *Name
+  )
+{
+  FIRMWARE_CONFIG_ITEM  FwCfgItem;
+  EFI_STATUSStatus;
+  UINTN FwCfgSize;
+  VOID  *Data;
+
+  Status = QemuFwCfgFindFile (Name, , );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "%a %d read  %s error Status %d \n", __func__, 
__LINE__, Name, Status));
+return NULL;
+  }
+
+  Data = AllocatePool (FwCfgSize);
+  if (Data == NULL) {
+return NULL;
+  }
+
+  QemuFwCfgSelectItem (FwCfgItem);
+  QemuFwCfgReadBytes (FwCfgSize, Data);
+
+  return Data;
+}
+
+/**
+  Find the power manager related info from ACPI table
+
+  @retval RETURN_SUCCESS Successfully find out all the required 
information.
+  @retval RETURN_NOT_FOUND   Failed to find the required info.
+**/
+STATIC EFI_STATUS
+GetPowerManagerByParseAcpiInfo (
+  VOID
+  )
+{
+  EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt   = NULL;
+  EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER  *Rsdp   = NULL;
+  EFI_ACPI_DESCRIPTION_HEADER   *Xsdt   = NULL;
+  EFI_ACPI_DESCRIPTION_HEADER   *Rsdt   = NULL;
+  VOID  *AcpiTables = NULL;
+  UINT32*Entry32= NULL;
+  UINTN Entry32Num;
+  UINT32*Signature = NULL;
+  UINTN Idx;
+
+  Rsdp = GetFwCfgData ("etc/acpi/rsdp");
+  if (Rsdp == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/rsdp error \n", __func__, 
__LINE__));
+return RETURN_NOT_FOUND;
+  }
+
+  AcpiTables = GetFwCfgData ("etc/acpi/tables");
+  if (AcpiTables == NULL) {
+DEBUG ((DEBUG_ERROR, "%a %d read etc/acpi/tables error \n", __func__, 
__LINE__));
+FreePool (Rsdp);
+return RETURN_NOT_FOUND;
+  }
+
+  Rsdt   = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +  
Rsdp->RsdtAddress);
+  Entry32= (UINT32 *)(Rsdt + 1);
+  Entry32Num = (Rsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+  for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+  Fadt = (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *)Signature;
+  DEBUG ((DEBUG_INFO, "Found Fadt in Rsdt\n"));
+  goto Done;
+}
+  }
+
+  Xsdt   = (EFI_ACPI_DESCRIPTION_HEADER *)((UINTN)AcpiTables +  
Rsdp->XsdtAddress);
+  Entry32= (UINT32 *)(Xsdt + 1);
+  Entry32Num = (Xsdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
+  for (Idx = 0; Idx < Entry32Num; Idx++) {
+Signature = (UINT32 *)((UINTN)Entry32[Idx] + (UINTN)AcpiTables);
+if (*Signature == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
+

[edk2-devel] [PATCH v1 21/26] OvmfPkg/LoongArchVirt: Add FdtQemuFwCfgLib

2024-03-11 Thread Chao Li

This library for PEI phase, and obtains the QemuFwCfg base address by
directly parsing the FDT, reads and writes the data in QemuFwCfg by
operating on the QemuFwCfg base address.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
Reviewed-by: Bibo Mao 
---
 .../FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c  | 504 ++
 .../FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.inf|  42 ++
 .../FdtQemuFwCfgLib/QemuFwCfgLibInternal.h|  73 +++
 .../Library/FdtQemuFwCfgLib/QemuFwCfgPei.c| 117 
 4 files changed, 736 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/QemuFwCfgLibInternal.h
 create mode 100644 OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/QemuFwCfgPei.c

diff --git a/OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c 
b/OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
new file mode 100644
index 00..a1f114b327
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c
@@ -0,0 +1,504 @@
+/** @file
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+- FwCfg   - firmWare  Configure
+- CTL   - Control
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "QemuFwCfgLibInternal.h"
+
+EFI_GUID  mFwCfgSelectorAddressGuid = FW_CONFIG_SELECTOR_ADDRESS_HOB_GUID;
+EFI_GUID  mFwCfgDataAddressGuid = FW_CONFIG_DATA_ADDRESS_HOB_GUID;
+
+STATIC UINTN  mFwCfgSelectorAddress;
+STATIC UINTN  mFwCfgDataAddress;
+
+/**
+  To get firmware configure selector address.
+
+  @param VOID
+
+  @retval  firmware configure selector address
+**/
+UINTN
+EFIAPI
+QemuGetFwCfgSelectorAddress (
+  VOID
+  )
+{
+  UINTN  FwCfgSelectorAddress;
+  EFI_HOB_GUID_TYPE  *GuidHob;
+  VOID   *DataInHob;
+
+  FwCfgSelectorAddress = mFwCfgSelectorAddress;
+  GuidHob  = NULL;
+  DataInHob= NULL;
+
+  if (FwCfgSelectorAddress == 0) {
+GuidHob  = GetFirstGuidHob ();
+DataInHob= GET_GUID_HOB_DATA (GuidHob);
+FwCfgSelectorAddress = (UINT64)(*(UINTN *)DataInHob);
+  }
+
+  return FwCfgSelectorAddress;
+}
+
+/**
+  To get firmware configure Data address.
+
+  @param VOID
+
+  @retval  firmware configure data address
+**/
+UINTN
+EFIAPI
+QemuGetFwCfgDataAddress (
+  VOID
+  )
+{
+  UINTN  FwCfgDataAddress;
+  EFI_HOB_GUID_TYPE  *GuidHob;
+  VOID   *DataInHob;
+
+  FwCfgDataAddress = mFwCfgDataAddress;
+  GuidHob  = NULL;
+  DataInHob= NULL;
+
+  if (FwCfgDataAddress == 0) {
+GuidHob  = GetFirstGuidHob ();
+DataInHob= GET_GUID_HOB_DATA (GuidHob);
+FwCfgDataAddress = (UINT64)(*(UINTN *)DataInHob);
+  }
+
+  return FwCfgDataAddress;
+}
+
+/**
+  Selects a firmware configuration item for reading.
+
+  Following this call, any data read from this item will start from
+  the beginning of the configuration item's data.
+
+  @param[in] QemuFwCfgItem - Firmware Configuration item to read
+**/
+VOID
+EFIAPI
+QemuFwCfgSelectItem (
+  IN FIRMWARE_CONFIG_ITEM  QemuFwCfgItem
+  )
+{
+  UINTN  FwCfgSelectorAddress;
+
+  FwCfgSelectorAddress = QemuGetFwCfgSelectorAddress ();
+  MmioWrite16 (FwCfgSelectorAddress, SwapBytes16 
((UINT16)(UINTN)QemuFwCfgItem));
+}
+
+/**
+  Slow READ_BYTES_FUNCTION.
+
+  @param[in]  The size of the data to be read.
+  @param[in]  BufferThe buffer that stores the readout data.
+**/
+VOID
+EFIAPI
+MmioReadBytes (
+  IN UINTN  Size,
+  IN VOID   *Buffer OPTIONAL
+  )
+{
+  UINTN  Left;
+  UINT8  *Ptr;
+  UINT8  *End;
+  UINTN  FwCfgDataAddress;
+
+  Left = Size & 7;
+
+  Size -= Left;
+  Ptr   = Buffer;
+  End   = Ptr + Size;
+
+  FwCfgDataAddress = QemuGetFwCfgDataAddress ();
+  while (Ptr < End) {
+*(UINT64 *)Ptr = MmioRead64 (FwCfgDataAddress);
+Ptr   += 8;
+  }
+
+  if (Left & 4) {
+*(UINT32 *)Ptr = MmioRead32 (FwCfgDataAddress);
+Ptr   += 4;
+  }
+
+  if (Left & 2) {
+*(UINT16 *)Ptr = MmioRead16 (FwCfgDataAddress);
+Ptr   += 2;
+  }
+
+  if (Left & 1) {
+*Ptr = MmioRead8 (FwCfgDataAddress);
+  }
+}
+
+/**
+  Slow WRITE_BYTES_FUNCTION.
+
+  @param[in]  The size of the data to be write.
+  @param[in]  BufferThe buffer that stores the writein data.
+**/
+VOID
+EFIAPI
+MmioWriteBytes (
+  IN UINTN  Size,
+  IN VOID   *Buffer OPTIONAL
+  )
+{
+  UINTN  Idx;
+  UINTN  FwCfgDataAddress;
+
+  FwCfgDataAddress = QemuGetFwCfgDataAddress ();
+  for (Idx = 0; Idx

[edk2-devel] [PATCH v1 20/26] OvmfPkg/LoongArchVirt: Add NorFlashQemuLib

2024-03-11 Thread Chao Li

Add NorFlashQemuLib for LoongArch, it is referenced from ArmVirtPkg.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
Reviewed-by: Bibo Mao 
---
 .../Library/NorFlashQemuLib/NorFlashQemuLib.c | 140 ++
 .../NorFlashQemuLib/NorFlashQemuLib.inf   |  43 ++
 2 files changed, 183 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.inf

diff --git a/OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c 
b/OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
new file mode 100644
index 00..ae9af09c4c
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/NorFlashQemuLib/NorFlashQemuLib.c
@@ -0,0 +1,140 @@
+/** @file
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define QEMU_NOR_BLOCK_SIZE  SIZE_128KB
+
+EFI_STATUS
+VirtNorFlashPlatformInitialization (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
+
+STATIC VIRT_NOR_FLASH_DESCRIPTION  mNorFlashDevices;
+
+EFI_STATUS
+VirtNorFlashPlatformGetDevices (
+  OUT VIRT_NOR_FLASH_DESCRIPTION  **NorFlashDescriptions,
+  OUT UINT32  *Count
+  )
+{
+  FDT_CLIENT_PROTOCOL  *FdtClient;
+  INT32Node;
+  EFI_STATUS   Status;
+  EFI_STATUS   FindNodeStatus;
+  CONST UINT32 *Reg;
+  UINT32   PropSize;
+  UINT64   Base;
+  UINT64   Size;
+
+  Status = gBS->LocateProtocol (
+  ,
+  NULL,
+  (VOID **)
+  );
+  ASSERT_EFI_ERROR (Status);
+
+  FindNodeStatus = FdtClient->FindCompatibleNode (
+FdtClient,
+"cfi-flash",
+
+);
+  ASSERT_EFI_ERROR (FindNodeStatus);
+
+  Status = FdtClient->GetNodeProperty (
+FdtClient,
+Node,
+"reg",
+(CONST VOID **),
+
+);
+  if (EFI_ERROR (Status)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "%a: GetNodeProperty () failed (Status == %r)\n",
+  __func__,
+  Status
+  ));
+return Status;
+  }
+
+  ASSERT ((PropSize % (4 * sizeof (UINT32))) == 0);
+
+  if (PropSize < (4 * sizeof (UINT32))) {
+DEBUG ((
+  DEBUG_ERROR,
+  "%a: reg node size(%d) is too small \n",
+  __func__,
+  PropSize
+  ));
+return EFI_NOT_FOUND;
+  }
+
+  Base = SwapBytes64 (ReadUnaligned64 ((VOID *)[0]));
+  Size = SwapBytes64 (ReadUnaligned64 ((VOID *)[2]));
+
+  mNorFlashDevices.DeviceBaseAddress = (UINTN)Base;
+  mNorFlashDevices.RegionBaseAddress = (UINTN)Base;
+  mNorFlashDevices.Size  = (UINTN)Size;
+  mNorFlashDevices.BlockSize = QEMU_NOR_BLOCK_SIZE;
+
+  Status = PcdSet32S (PcdFlashNvStorageVariableBase, Base);
+  ASSERT_EFI_ERROR (Status);
+
+  /*
+   * Base is the value of PcdFlashNvStorageVariableBase,
+   * PcdFlashNvStorageFtwWorkingBase can be got by
+   *   PcdFlashNvStorageVariableBase + PcdFlashNvStorageVariableSize
+   */
+  Base  += PcdGet32 (PcdFlashNvStorageVariableSize);
+  Status = PcdSet32S (PcdFlashNvStorageFtwWorkingBase, Base);
+  ASSERT_EFI_ERROR (Status);
+
+  /*
+   * Now,Base is the value of PcdFlashNvStorageFtwWorkingBase,
+   * PcdFlashNvStorageFtwSpareBase can be got by
+   *   PcdFlashNvStorageFtwWorkingBase + PcdFlashNvStorageFtwWorkingSize.
+   */
+  Base  += PcdGet32 (PcdFlashNvStorageFtwWorkingSize);
+  Status = PcdSet32S (PcdFlashNvStorageFtwSpareBase, Base);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // UEFI takes ownership of the NOR flash, and exposes its functionality
+  // through the UEFI Runtime Services GetVariable, SetVariable, etc. This
+  // means we need to disable it in the device tree to prevent the OS from
+  // attaching its device driver as well.
+  // Note that this also hides other flash banks, but the only other flash
+  // bank we expect to encounter is the one that carries the UEFI executable
+  // code, which is not intended to be guest updatable, and is usually backed
+  // in a readonly manner by QEMU anyway.
+  //
+  Status = FdtClient->SetNodeProperty (
+FdtClient,
+Node,
+"status",
+"disabled",
+sizeof ("disabled")
+);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_WARN, "Failed to set NOR flash status to 'disabled'\n"));
+  }
+
+  *NorFlashDescriptions = 
+  *Count

[edk2-devel] [PATCH v1 19/26] OvmfPkg/LoongArchVirt: Add real time clock library

2024-03-11 Thread Chao Li

This library is provides real time clock for LoongArch virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
Co-authored-by: Xianglai Li 
Reviewed-by: Bibo Mao 
---
 .../DxeLsRealTimeClockLib.c   | 327 ++
 .../DxeLsRealTimeClockLib.inf |  41 +++
 .../LsRealTimeClockLib/LsRealTimeClock.h  |  47 +++
 .../PeiLsRealTimeClockLib.c   |  31 ++
 .../PeiLsRealTimeClockLib.inf |  29 ++
 5 files changed, 475 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/LsRealTimeClock.h
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/PeiLsRealTimeClockLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/PeiLsRealTimeClockLib.inf

diff --git 
a/OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c 
b/OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
new file mode 100644
index 00..e990728069
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Library/LsRealTimeClockLib/DxeLsRealTimeClockLib.c
@@ -0,0 +1,327 @@
+/** @file
+  Implement EFI RealTimeClock runtime services via RTC Lib.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "LsRealTimeClock.h"
+
+STATIC BOOLEANmInitialized = FALSE;
+STATIC EFI_EVENT  mRtcVirtualAddrChangeEvent;
+STATIC UINTN  mRtcBase;
+
+/*
+  Enable Real-time clock.
+
+  @param VOID
+
+  @retval  VOID
+ */
+VOID
+InitRtc (
+  VOID
+  )
+{
+  UINTN  Val;
+  EFI_HOB_GUID_TYPE  *GuidHob   = NULL;
+  VOID   *DataInHob = NULL;
+
+  if (!mInitialized) {
+/* Enable rtc */
+GuidHob = GetFirstGuidHob ();
+if (GuidHob) {
+  DataInHob = GET_GUID_HOB_DATA (GuidHob);
+  mRtcBase  = (UINT64)(*(UINTN *)DataInHob);
+  Val   = MmioRead32 (mRtcBase + RTC_CTRL_REG);
+  Val  |= TOY_ENABLE_BIT | OSC_ENABLE_BIT;
+  MmioWrite32 (mRtcBase + RTC_CTRL_REG, Val);
+  mInitialized = TRUE;
+} else {
+  DebugPrint (EFI_D_INFO, "RTC register address not found!\n");
+  ASSERT (FALSE);
+}
+  }
+}
+
+/**
+  Returns the current time and date information, and the time-keeping 
capabilities
+  of the hardware platform.
+
+  @param  Time   A pointer to storage to receive a snapshot of 
the current time.
+  @param  Capabilities   An optional pointer to a buffer to receive 
the real time clock
+ device's capabilities.
+
+  @retval EFI_SUCCESSThe operation completed successfully.
+  @retval EFI_INVALID_PARAMETER  Time is NULL.
+  @retval EFI_DEVICE_ERROR   The time could not be retrieved due to 
hardware error.
+  @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an 
authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+  OUT EFI_TIME   *Time,
+  OUT EFI_TIME_CAPABILITIES  *Capabilities
+  )
+{
+  UINT32  Val;
+
+  // Ensure Time is a valid pointer
+  if (Time == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  Val= MmioRead32 (mRtcBase + TOY_READ1_REG);
+  Time->Year = Val + 1900;
+
+  Val  = MmioRead32 (mRtcBase + TOY_READ0_REG);
+  Time->Month  = (Val >> TOY_MON_SHIFT) & TOY_MON_MASK;
+  Time->Day= (Val >> TOY_DAY_SHIFT) & TOY_DAY_MASK;
+  Time->Hour   = (Val >> TOY_HOUR_SHIFT) & TOY_HOUR_MASK;
+  Time->Minute = (Val >> TOY_MIN_SHIFT) & TOY_MIN_MASK;
+  Time->Second = (Val >> TOY_SEC_SHIFT) & TOY_SEC_MASK;
+  Time->Nanosecond = 0;
+  return EFI_SUCCESS;
+}
+
+/**
+  Sets the current local time and date information.
+
+  @param  Time  A pointer to the current time.
+
+  @retval EFI_SUCCESS   The operation completed successfully.
+  @retval EFI_INVALID_PARAMETER A time field is out of range.
+  @retval EFI_DEVICE_ERROR  The time could not be set due due to hardware 
error.
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+  IN  EFI_TIME  *Time
+  )
+{
+  UINT32  Val;
+
+  // Initialize the hardware if not already done
+
+  Val  = 0;
+  Val |= (Time->Second << TOY_SEC_SHIFT);
+  Val |= (Time->Minute << TOY_MIN_SHIFT);
+  Val |= (Time->Hour   << TOY_HOUR_SHIFT);
+  Val |= (Time->Day<< TOY_DAY_SHIFT);
+  Val |= (Time->Month  << TOY_MON_SHIFT);
+  MmioWrite32 (mRtcBase + TOY_WRITE0_REG, Val);
+
+  Val = Time->Year - 1900;
+  MmioWrite32 (mRtcBase + TOY_WRITE1_REG, Val);
+  return EFI_SUCCESS;

[edk2-devel] [PATCH v1 18/26] OvmfPkg/LoongArchVirt: Add the early serial port output library

2024-03-11 Thread Chao Li

Add a early serial port output library into LoongArchVirt that named
EarlyFdtSerialPortLib16550, this library is referenced from
MdeModulePkg.

This library is used in the PEI phase. Since the serial port address can
not be saved in memory of the LoongArch QEMU virtual machine in the PEI
phase, the serial prot base address will be obtained from the FDT before
each output.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Xianglai Li 
Reviewed-by: Bibo Mao 
---
 .../EarlyFdtSerialPortLib16550.c  | 815 ++
 .../EarlyFdtSerialPortLib16550.inf|  46 +
 2 files changed, 861 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.inf

diff --git 
a/OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
 
b/OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
new file mode 100644
index 00..8cc108501c
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/EarlyFdtSerialPortLib16550/EarlyFdtSerialPortLib16550.c
@@ -0,0 +1,815 @@
+/** @file
+  16550 UART Serial Port library functions
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+//
+// PCI Defintions.
+//
+#define PCI_BRIDGE_32_BIT_IO_SPACE  0x01
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF   0// LCR_DLAB = 0
+#define R_UART_TXBUF   0// LCR_DLAB = 0
+#define R_UART_BAUD_LOW0// LCR_DLAB = 1
+#define R_UART_BAUD_HIGH   1// LCR_DLAB = 1
+#define R_UART_IER 1// LCR_DLAB = 0
+#define R_UART_FCR 2
+#define B_UART_FCR_FIFOE   BIT0
+#define B_UART_FCR_FIFO64  BIT5
+#define R_UART_LCR 3
+#define B_UART_LCR_DLABBIT7
+#define R_UART_MCR 4
+#define B_UART_MCR_DTRCBIT0
+#define B_UART_MCR_RTS BIT1
+#define R_UART_LSR 5
+#define B_UART_LSR_RXRDY   BIT0
+#define B_UART_LSR_TXRDY   BIT5
+#define B_UART_LSR_TEMTBIT6
+#define R_UART_MSR 6
+#define B_UART_MSR_CTS BIT4
+#define B_UART_MSR_DSR BIT5
+#define B_UART_MSR_RI  BIT6
+#define B_UART_MSR_DCD BIT7
+
+/**
+  Read an 8-bit 16550 register.  If PcdSerialUseMmio is TRUE, then the value 
is read from
+  MMIO space.  If PcdSerialUseMmio is FALSE, then the value is read from I/O 
space.  The
+  parameter Offset is added to the base address of the 16550 registers that is 
specified
+  by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO 
space access
+  width and defaults to 8 bit access, and supports 8 or 32 bit access.
+
+  @param  BaseThe base address register of UART device.
+  @param  Offset  The offset of the 16550 register to read.
+
+  @return The value read from the 16550 register.
+**/
+UINT8
+SerialPortReadRegister (
+  UINTN  Base,
+  UINTN  Offset
+  )
+{
+  if (PcdGetBool (PcdSerialUseMmio)) {
+if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
+  return (UINT8)MmioRead32 (Base + Offset * PcdGet32 
(PcdSerialRegisterStride));
+}
+
+return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+  } else {
+return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+  }
+}
+
+/**
+  Write an 8-bit 16550 register.  If PcdSerialUseMmio is TRUE, then the value 
is written to
+  MMIO space.  If PcdSerialUseMmio is FALSE, then the value is written to I/O 
space.  The
+  parameter Offset is added to the base address of the 16550 registers that is 
specified
+  by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO 
space access
+  width and defaults to 8 bit access, and supports 8 or 32 bit access.
+
+  @param  BaseThe base address register of UART device.
+  @param  Offset  The offset of the 16550 register to write.
+  @param  Value   The value to write to the 16550 register specified by Offset.
+
+  @return The value written to the 16550 register.
+**/
+UINT8
+SerialPortWriteRegister (
+  UINTN  Base,
+  UINTN  Offset,
+  UINT8  Value
+  )
+{
+  if (PcdGetBool (PcdSerialUseMmio)) {
+if (PcdGet8 (PcdSerialRegisterAccessWidth) == 32) {
+  return (UINT8)MmioWrite32 (Base + Offset * PcdGet32 
(PcdSerialRegisterStride), (UINT8)Value);
+}
+
+return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), 
Value);
+  } else {
+return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), 
Value);
+  }
+}
+
+/**
+  Retrieve the I/O or MMIO base address register for the PCI UART device.
+
+  This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in 
PCI UART
+  Device if

[edk2-devel] [PATCH v1 17/26] OvmfPkg/LoongArchVirt: Add serial port hook library

2024-03-11 Thread Chao Li

Add a serial port hook library in LoongArchVirt named
Fdt16550SerialProtHookLib, this library is referenced from ArmVirtPkg.

LoongArch QEMU virtual machine uses register of LOONGARCH_CSR_KS1 to
transfer serial port base addres from the PEI phase to the DXE phase.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Reviewed-by: Bibo Mao 
---
 .../EarlyFdt16550SerialPortHookLib.c  | 52 +++
 .../EarlyFdt16550SerialPortHookLib.inf| 37 +
 .../Fdt16550SerialPortHookLib.c   | 39 ++
 .../Fdt16550SerialPortHookLib.inf | 33 
 .../Fdt16550SerialPortHookLib.uni | 14 +
 5 files changed, 175 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.uni

diff --git 
a/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
new file mode 100644
index 00..9f1fcc970a
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.c
@@ -0,0 +1,52 @@
+/** @file
+  PEI Phase Early Platform Hook Library instance for 16550 Uart.
+
+  Copyright (c) 2020 - 2023, Arm Ltd. All rights reserved.
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/** Platform hook to retrieve the 16550 UART base address from the platform
+Device tree and store it in the reigster LOONGARCH_CSR_KS1.
+
+  @retval RETURN_SUCCESSSuccess.
+  @retval RETURN_INVALID_PARAMETER  A parameter was invalid.
+  @retval RETURN_NOT_FOUND  Serial port information not found.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+  VOID
+  )
+{
+  RETURN_STATUS  Status;
+  VOID   *DeviceTreeBase;
+  UINT64 SerialConsoleAddress;
+
+  if (PcdGet64 (PcdSerialRegisterBase) != 0) {
+return RETURN_SUCCESS;
+  }
+
+  DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAddress);
+  if (DeviceTreeBase == NULL) {
+return RETURN_NOT_FOUND;
+  }
+
+  Status = FdtSerialGetConsolePort (DeviceTreeBase, );
+  if (RETURN_ERROR (Status)) {
+return Status;
+  }
+
+  CsrWrite (LOONGARCH_CSR_KS1, (UINTN)SerialConsoleAddress);
+
+  return RETURN_SUCCESS;
+}
diff --git 
a/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
new file mode 100644
index 00..55b0c03a01
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/EarlyFdt16550SerialPortHookLib.inf
@@ -0,0 +1,37 @@
+## @file
+#  PEI Phase Early Platform Hook Library instance for 16550 Uart.
+#
+#  Copyright (c) 2020, ARM Ltd. All rights reserved.
+#  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 1.29
+  BASE_NAME  = EarlyFdt16550SerialPortHookLib
+  MODULE_UNI_FILE= Fdt16550SerialPortHookLib.uni
+  FILE_GUID  = 6A5FEBCB-C676-A7C1-A96C-B79D4860EEC5
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = PlatformHookLib|SEC PEI_CORE PEIM
+
+[Sources]
+  EarlyFdt16550SerialPortHookLib.c
+
+[LibraryClasses]
+  BaseLib
+  PcdLib
+  FdtLib
+  FdtSerialPortAddressLib
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  OvmfPkg/OvmfPkg.dec
+
+[Pcd]
+  gUefiOvmfPkgTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git 
a/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
new file mode 100644
index 00..fd188f75b8
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/Fdt16550SerialPortHookLib/Fdt16550SerialPortHookLib.c
@@ -0,0 +1,39 @@
+/** @file
+  Platform Hook Library instance for 16550 Uart.
+
+  Copyright (c) 2020, ARM Ltd. All rights reserved.
+  Copyright (c) 2024 Loongson

[edk2-devel] [PATCH v1 16/26] OvmfPkg/LoongArchVirt: Add a NULL library named CollectApResouceLibNull

2024-03-11 Thread Chao Li

This Library is used to collect APs resources, but is currently NULL
for OvmfPkg, because it is not used by the LoongArch virtual machine.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Reviewed-by: Bibo Mao 
---
 .../CollectApResourceLibNull.c| 38 +++
 .../CollectApResourceLibNull.inf  | 31 +++
 .../CollectApResourceLibNull.uni  |  9 +
 3 files changed, 78 insertions(+)
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
 create mode 100644 
OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni

diff --git 
a/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
new file mode 100644
index 00..471418f11e
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.c
@@ -0,0 +1,38 @@
+/** @file
+  LoongArch64 CPU Collect AP resource NULL Library functions.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "../../../UefiCpuPkg/Library/MpInitLib/LoongArch64/MpLib.h"
+
+VOID
+SaveProcessorResourceData (
+  IN PROCESSOR_RESOURCE_DATA *
+  );
+
+VOID
+EFIAPI
+SaveProcessorResource (
+  PROCESSOR_RESOURCE_DATA  *mProcessorResource
+  )
+{
+  SaveProcessorResourceData (mProcessorResource);
+}
+
+VOID
+EFIAPI
+CollectAllProcessorResource (
+  VOID
+  )
+{
+  return;
+}
diff --git 
a/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
new file mode 100644
index 00..c166df6bbd
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.inf
@@ -0,0 +1,31 @@
+## @file
+#  LoongArch64 CPU Collect AP resource NULL Library.
+#
+#  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 1.29
+  BASE_NAME  = CollectApResourceLibNull
+  MODULE_UNI_FILE= CollectApResourceLibNull.uni
+  FILE_GUID  = 8C3B54BF-6A9F-E8B4-4D57-67B3AB578DD6
+  MODULE_TYPE= PEIM
+  VERSION_STRING = 1.1
+  LIBRARY_CLASS  = PEIM
+
+[Sources.common]
+  CollectApResourceLibNull.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  HobLib
+  MemoryAllocationLib
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
diff --git 
a/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
new file mode 100644
index 00..d1638ab11e
--- /dev/null
+++ 
b/OvmfPkg/LoongArchVirt/Library/CollectApResouceLibNull/CollectApResourceLibNull.uni
@@ -0,0 +1,9 @@
+// @file
+//  LoongArch64 CPU Collect AP resource NULL Library.
+//
+//  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+//  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+#string STR_MODULE_ABSTRACT #language en-US "CPU Collect AP 
resource NULL Library."
+
+#string STR_MODULE_DESCRIPTION  #language en-US "CPU Collect AP 
resource NULL Library."
-- 
2.27.0



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[edk2-devel] [PATCH v1 15/26] OvmfPkg/LoongArchVirt: Add stable timer driver

2024-03-11 Thread Chao Li

Add a CPU timer driver named StableTimerDxe, which proviedes
EFI_TIMER_ARCH_PROTOCOL for LoongArch.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Jordan Justen 
Cc: Gerd Hoffmann 
Cc: Bibo Mao 
Cc: Dongyan Qian 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
Reviewed-by: Bibo Mao 
---
 .../Drivers/StableTimerDxe/Timer.c| 381 ++
 .../Drivers/StableTimerDxe/Timer.h| 127 ++
 .../Drivers/StableTimerDxe/TimerDxe.inf   |  41 ++
 3 files changed, 549 insertions(+)
 create mode 100644 OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
 create mode 100644 OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.h
 create mode 100644 OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/TimerDxe.inf

diff --git a/OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c 
b/OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
new file mode 100644
index 00..0e0f10970a
--- /dev/null
+++ b/OvmfPkg/LoongArchVirt/Drivers/StableTimerDxe/Timer.c
@@ -0,0 +1,381 @@
+/** @file
+  Timer Architectural Protocol as defined in the DXE CIS
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "Timer.h"
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLE  mTimerHandle = NULL;
+EFI_EVENT   EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL  mTimer = {
+  TimerDriverRegisterHandler,
+  TimerDriverSetTimerPeriod,
+  TimerDriverGetTimerPeriod,
+  TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL  *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY  mTimerNotifyFunction;
+
+/**
+  Sets the counter value for timer.
+
+  @param CountThe 16-bit counter value to program into stable timer.
+
+  @retval VOID
+**/
+VOID
+SetPitCount (
+  IN UINT64  Count
+  )
+{
+  if (Count <= 4) {
+return;
+  }
+
+  Count &= LOONGARCH_CSR_TMCFG_TIMEVAL;
+  Count |= LOONGARCH_CSR_TMCFG_EN | LOONGARCH_CSR_TMCFG_PERIOD;
+  CsrWrite (LOONGARCH_CSR_TMCFG, Count);
+}
+
+/**
+  Timer Interrupt Handler.
+
+  @param InterruptTypeThe type of interrupt that occurred
+  @param SystemContextA pointer to the system context when the interrupt 
occurred
+
+  @retval VOID
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+  IN EFI_EXCEPTION_TYPE  InterruptType,
+  IN EFI_SYSTEM_CONTEXT  SystemContext
+  )
+{
+  EFI_TPL  OriginalTPL;
+
+  OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+
+  //
+  // Clear interrupt.
+  //
+  CsrWrite (LOONGARCH_CSR_TINTCLR, 0x1);
+
+  if (mTimerNotifyFunction != NULL) {
+//
+// @bug : This does not handle missed timer interrupts
+//
+mTimerNotifyFunction (mTimerPeriod);
+  }
+
+  gBS->RestoreTPL (OriginalTPL);
+}
+
+/**
+  This function registers the handler NotifyFunction so it is called every time
+  the timer interrupt fires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
+  returned.  If the CPU does not support registering a timer interrupt handler,
+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a 
handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not 
registered,
+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+  is returned.
+
+  @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param NotifyFunction   The function to call when a timer interrupt fires.  
This
+  function executes at TPL_HIGH_LEVEL.  The DXE Core 
will
+  register a handler for the timer interrupt, so it 
can know
+  how much time has passed.  This information is used 
to
+  signal timer based events.  NULL will unregister the 
handler.
+
+  @retvalEFI_SUCCESSThe timer handler was registered.
+  @retvalEFI_UNSUPPORTEDThe platform does not support timer 
interrupts.
+  @retvalEFI_ALREADY_STARTEDNotifyFunction is not NULL, and a 
handler is already
+registered.
+  @retvalEFI_INVALID_PARAMETER  NotifyFunction is NULL, and a handler 
was not
+previously registered.
+  @retvalEFI_DEVICE_ERROR   The timer handler could

[edk2-devel] [PATCH v1 14/26] UefiCpuPkg: Add CpuDxe driver for LoongArch64

2024-03-11 Thread Chao Li

Added LoongArch64 CPU driver into CpuDxe.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
Co-authored-by: Dongyan Qian 
---
 UefiCpuPkg/CpuDxe/CpuDxe.inf  |  23 +-
 UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c| 426 +
 UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.h| 288 
 UefiCpuPkg/CpuDxe/LoongArch64/CpuMp.c | 544 ++
 UefiCpuPkg/CpuDxe/LoongArch64/Exception.c | 159 +++
 5 files changed, 1436 insertions(+), 4 deletions(-)
 create mode 100644 UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c
 create mode 100644 UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.h
 create mode 100644 UefiCpuPkg/CpuDxe/LoongArch64/CpuMp.c
 create mode 100644 UefiCpuPkg/CpuDxe/LoongArch64/Exception.c

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index 9e1c673283..50db9e8ed1 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -3,6 +3,7 @@
 #
 #  Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
 #  Copyright (c) 2017, AMD Incorporated. All rights reserved.
+#  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -22,7 +23,7 @@ [Packages]
   MdeModulePkg/MdeModulePkg.dec
   UefiCpuPkg/UefiCpuPkg.dec
 
-[LibraryClasses]
+[LibraryClasses.common]
   BaseLib
   BaseMemoryLib
   CpuExceptionHandlerLib
@@ -30,9 +31,7 @@ [LibraryClasses]
   DebugLib
   DxeServicesTableLib
   HobLib
-  LocalApicLib
   MemoryAllocationLib
-  MtrrLib
   MpInitLib
   PeCoffGetEntryPointLib
   ReportStatusCodeLib
@@ -41,7 +40,15 @@ [LibraryClasses]
   UefiDriverEntryPoint
   UefiLib
 
-[Sources]
+[LibraryClasses.IA32, LibraryClasses.X64]
+  LocalApicLib
+  MtrrLib
+
+[LibraryClasses.LoongArch64]
+  CacheMaintenanceLib
+  CpuMmuLib
+
+[Sources.IA32, Sources.X64]
   CpuDxe.c
   CpuDxe.h
   CpuGdt.c
@@ -59,6 +66,13 @@ [Sources.X64]
   X64/CpuAsm.nasm
   X64/PagingAttribute.c
 
+[Sources.LoongArch64]
+  CpuMp.h
+  LoongArch64/CpuDxe.c
+  LoongArch64/CpuMp.c
+  LoongArch64/Exception.c
+  LoongArch64/CpuDxe.h
+
 [Protocols]
   gEfiCpuArchProtocolGuid   ## PRODUCES
   gEfiMpServiceProtocolGuid ## PRODUCES
@@ -80,6 +94,7 @@ [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList  ## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize## 
CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuExceptionVectorBaseAddress## 
CONSUMES
 
 [Depex]
   TRUE
diff --git a/UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c 
b/UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c
new file mode 100644
index 00..f7c34fdfee
--- /dev/null
+++ b/UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c
@@ -0,0 +1,426 @@
+/** @file CpuDxe.c
+
+  CPU DXE Module to produce CPU ARCH Protocol.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "CpuDxe.h"
+#include "CpuMp.h"
+#include 
+#include 
+#include 
+#include 
+
+UINT64  mTimerPeriod = 0;
+
+/**
+  IPI Interrupt Handler.
+
+  @param InterruptTypeThe type of interrupt that occurred
+  @param SystemContextA pointer to the system context when the interrupt 
occurred
+**/
+VOID
+EFIAPI
+IpiInterruptHandler (
+  IN EFI_EXCEPTION_TYPE  InterruptType,
+  IN EFI_SYSTEM_CONTEXT  SystemContext
+  );
+
+//
+// Globals used to initialize the protocol
+//
+EFI_HANDLE mCpuHandle = NULL;
+EFI_CPU_ARCH_PROTOCOL  gCpu   = {
+  CpuFlushCpuDataCache,
+  CpuEnableInterrupt,
+  CpuDisableInterrupt,
+  CpuGetInterruptState,
+  CpuInit,
+  CpuRegisterInterruptHandler,
+  CpuGetTimerValue,
+  CpuSetMemoryAttributes,
+  0,  // NumberOfTimers
+  4,  // DmaBufferAlignment
+};
+
+/**
+  This function flushes the range of addresses from Start to Start+Length
+  from the processor's data cache. If Start is not aligned to a cache line
+  boundary, then the bytes before Start to the preceding cache line boundary
+  are also flushed. If Start+Length is not aligned to a cache line boundary,
+  then the bytes past Start+Length to the end of the next cache line boundary
+  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+  supported. If the data cache is fully coherent with all DMA operations, then
+  this function can just return EFI_SUCCESS. If the processor does not support
+  flushing a range of the data cache, then the entire data cache can be 
flushed.
+
+  @param  This The EFI_CPU_ARCH_PROTOCOL instance.
+  @param  StartThe beginning physical address to flush from the 
processor's data
+   cache.
+  @param  Length   The number of bytes to flush from the processor's 
data cache. This
+

[edk2-devel] [PATCH v1 13/26] UefiCpuPkg: Add multiprocessor library for LoongArch64

2024-03-11 Thread Chao Li

Added LoongArch multiprocessor initialization instance into MpInitLib.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
---
 UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf |   21 +-
 .../Library/MpInitLib/LoongArch64/DxeMpLib.c  |  480 +
 .../Library/MpInitLib/LoongArch64/MpLib.c | 1621 +
 .../Library/MpInitLib/LoongArch64/MpLib.h |  361 
 .../Library/MpInitLib/LoongArch64/PeiMpLib.c  |  404 
 UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf |   21 +-
 6 files changed, 2896 insertions(+), 12 deletions(-)
 create mode 100644 UefiCpuPkg/Library/MpInitLib/LoongArch64/DxeMpLib.c
 create mode 100644 UefiCpuPkg/Library/MpInitLib/LoongArch64/MpLib.c
 create mode 100644 UefiCpuPkg/Library/MpInitLib/LoongArch64/MpLib.h
 create mode 100644 UefiCpuPkg/Library/MpInitLib/LoongArch64/PeiMpLib.c

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf 
b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
index bf6e6a095f..c808a8f14b 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
@@ -2,6 +2,7 @@
 #  MP Initialize Library instance for DXE driver.
 #
 #  Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.
+#  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -18,7 +19,7 @@ [Defines]
 #
 # The following information is for reference only and not required by the 
build tools.
 #
-#  VALID_ARCHITECTURES   = IA32 X64
+#  VALID_ARCHITECTURES   = IA32 X64 LOONGARCH64
 #
 
 [Sources.IA32]
@@ -31,7 +32,7 @@ [Sources.X64]
   X64/CreatePageTable.c
   X64/MpFuncs.nasm
 
-[Sources.common]
+[Sources.IA32, Sources.X64]
   AmdSev.c
   DxeMpLib.c
   Microcode.c
@@ -40,6 +41,11 @@ [Sources.common]
   MpLib.h
   MpHandOff.h
 
+[Sources.LoongArch64]
+  LoongArch64/DxeMpLib.c
+  LoongArch64/MpLib.c
+  LoongArch64/MpLib.h
+
 [Packages]
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
@@ -47,17 +53,20 @@ [Packages]
 
 [LibraryClasses]
   BaseLib
-  CcExitLib
   CpuLib
   DebugAgentLib
   HobLib
-  LocalApicLib
   MemoryAllocationLib
-  MicrocodeLib
-  MtrrLib
   PcdLib
   SynchronizationLib
   UefiBootServicesTableLib
+
+[LibraryClasses.IA32, LibraryClasses.X64]
+  CcExitLib
+  LocalApicLib
+  MicrocodeLib
+  MtrrLib
+
 [LibraryClasses.X64]
   CpuPageTableLib
 
diff --git a/UefiCpuPkg/Library/MpInitLib/LoongArch64/DxeMpLib.c 
b/UefiCpuPkg/Library/MpInitLib/LoongArch64/DxeMpLib.c
new file mode 100644
index 00..739da77e32
--- /dev/null
+++ b/UefiCpuPkg/Library/MpInitLib/LoongArch64/DxeMpLib.c
@@ -0,0 +1,480 @@
+/** @file
+  LoongArch64 MP initialize support functions for DXE phase.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "MpLib.h"
+
+#include 
+#include 
+#include 
+
+#include 
+
+CPU_MP_DATA   *mCpuMpData= NULL;
+EFI_EVENT mCheckAllApsEvent  = NULL;
+volatile BOOLEAN  mStopCheckAllApsStatus = TRUE;
+
+/**
+  Enable Debug Agent to support source debugging on AP function.
+
+**/
+VOID
+EnableDebugAgent (
+  VOID
+  )
+{
+  //
+  // Initialize Debug Agent to support source level debug in DXE phase
+  //
+  InitializeDebugAgent (DEBUG_AGENT_INIT_DXE_AP, NULL, NULL);
+}
+
+/**
+  Get the pointer to CPU MP Data structure.
+
+  @return  The pointer to CPU MP Data structure.
+**/
+CPU_MP_DATA *
+GetCpuMpData (
+  VOID
+  )
+{
+  ASSERT (mCpuMpData != NULL);
+  return mCpuMpData;
+}
+
+/**
+  Save the pointer to CPU MP Data structure.
+
+  @param[in] CpuMpData  The pointer to CPU MP Data structure will be saved.
+**/
+VOID
+SaveCpuMpData (
+  IN CPU_MP_DATA  *CpuMpData
+  )
+{
+  mCpuMpData = CpuMpData;
+}
+
+/**
+  Get available EfiBootServicesCode memory below 4GB by specified size.
+
+  This buffer is required to safely transfer AP from real address mode to
+  protected mode or long mode, due to the fact that the buffer returned by
+  GetWakeupBuffer() may be marked as non-executable.
+
+  @param[in] BufferSize   Wakeup transition buffer size.
+
+  @retval other   Return wakeup transition buffer address below 4GB.
+  @retval 0   Cannot find free memory below 4GB.
+**/
+UINTN
+GetModeTransitionBuffer (
+  IN UINTN  BufferSize
+  )
+{
+  return 0;
+}
+
+/**
+  Checks APs status and updates APs status if needed.
+
+**/
+VOID
+CheckAndUpdateApsStatus (
+  VOID
+  )
+{
+  UINTNProcessorNumber;
+  EFI_STATUS   Status;
+  CPU_MP_DATA  *CpuMpData;
+
+  CpuMpData = GetCpuMpData ();
+
+  //
+  // First, check whether pending StartupAllAPs() exists.
+  //
+  if (CpuMpData->WaitEvent != NULL) {
+Status = CheckAllAPs ();
+//
+// If all APs finish for StartupAllAPs(), signal the WaitEvent for it.
+//
+if (Status != EFI_NOT_READY) {
+  Status   = gBS->SignalEvent

[edk2-devel] [PATCH v1 12/26] UefiCpuPkg: Add CpuMmuInitLib to UefiCpuPkg

2024-03-11 Thread Chao Li

Add a new base library named CpuMmuInitLib and add a LoongArch64
instance with in the library.
It is the consumer of the CpuMmuLib.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
Co-authored-by: Dongyan Qian 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
---
 .../Library/CpuMmuInitLib/CpuMmuInitLib.inf   |  42 +++
 .../Library/CpuMmuInitLib/CpuMmuInitLib.uni   |  14 +
 .../CpuMmuInitLib/LoongArch64/CpuMmuInit.c| 242 ++
 .../LoongArch64/TlbExceptionHandle.S  |  51 
 .../LoongArch64/TlbExceptionHandle.h  |  36 +++
 UefiCpuPkg/UefiCpuPkg.dsc |   1 +
 6 files changed, 386 insertions(+)
 create mode 100644 UefiCpuPkg/Library/CpuMmuInitLib/CpuMmuInitLib.inf
 create mode 100644 UefiCpuPkg/Library/CpuMmuInitLib/CpuMmuInitLib.uni
 create mode 100644 UefiCpuPkg/Library/CpuMmuInitLib/LoongArch64/CpuMmuInit.c
 create mode 100644 
UefiCpuPkg/Library/CpuMmuInitLib/LoongArch64/TlbExceptionHandle.S
 create mode 100644 
UefiCpuPkg/Library/CpuMmuInitLib/LoongArch64/TlbExceptionHandle.h

diff --git a/UefiCpuPkg/Library/CpuMmuInitLib/CpuMmuInitLib.inf 
b/UefiCpuPkg/Library/CpuMmuInitLib/CpuMmuInitLib.inf
new file mode 100644
index 00..a1326346fb
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuMmuInitLib/CpuMmuInitLib.inf
@@ -0,0 +1,42 @@
+## @file
+#  CPU Memory Map Unit Initialization library instance.
+#
+#  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 1.29
+  BASE_NAME  = CpuMmuInitLib
+  MODULE_UNI_FILE= CpuMmuInitLib.uni
+  FILE_GUID  = F67EB983-AC2A-7550-AB69-3BC51A1C895B
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = CpuMmuInitLib
+
+#
+#  VALID_ARCHITECTURES   = LOONGARCH64
+#
+
+[Sources.LoongArch64]
+  LoongArch64/TlbExceptionHandle.S | GCC
+  LoongArch64/CpuMmuInit.c
+  LoongArch64/TlbExceptionHandle.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuExceptionVectorBaseAddress
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMmuIsEnabled ## CONSUMES
+
+[LibraryClasses]
+  CacheMaintenanceLib
+  CpuMmuLib
+  DebugLib
+  MemoryAllocationLib
+  PcdLib
diff --git a/UefiCpuPkg/Library/CpuMmuInitLib/CpuMmuInitLib.uni 
b/UefiCpuPkg/Library/CpuMmuInitLib/CpuMmuInitLib.uni
new file mode 100644
index 00..907f024302
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuMmuInitLib/CpuMmuInitLib.uni
@@ -0,0 +1,14 @@
+// /** @file
+// CPU Memory Map Unit Initialization library instance.
+//
+// CPU Memory Map Unit Initialization library instance.
+//
+// Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT #language en-US "CPU Memory Manager 
Unit library instance for PEI modules."
+
+#string STR_MODULE_DESCRIPTION  #language en-US "CPU Memory Manager 
Unit library instance for PEI modules."
diff --git a/UefiCpuPkg/Library/CpuMmuInitLib/LoongArch64/CpuMmuInit.c 
b/UefiCpuPkg/Library/CpuMmuInitLib/LoongArch64/CpuMmuInit.c
new file mode 100644
index 00..41e9328fd0
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuMmuInitLib/LoongArch64/CpuMmuInit.c
@@ -0,0 +1,242 @@
+/** @file
+  CPU Memory Map Unit Initialization library instance.
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "TlbExceptionHandle.h"
+
+//
+// For coding convenience, define the maximum valid
+// LoongArch exception.
+// Since UEFI V2.11, it will be present in DebugSupport.h.
+//
+#define MAX_LOONGARCH_EXCEPTION  64
+
+//
+// Because the page size in edk2 is 4KB, the lowest level
+// page table is align to 12 bits, and the page table width
+// of other levels is set to 9 bits by default, which will
+// be 3 or 4 or 5 level page tables, and continuous.
+//
+// Correspondence between max virtual memory address width
+// and page table level:
+// 39 bit >= VA > 31 bit, 3 level page tables
+// 48 bit >= VA > 40 bit, 4 level page tables
+// 57 bit >= VA > 49 bit, 5 level page tables
+//
+#define BIT_WIDTH_PER_LEVEL  9
+#define MAX_SIZE_OF_PGD  ((1 << BIT_WIDTH_PER_LEVEL) * 8) // 512 items, 8 
Byte each.
+
+/**
+  Create a page table and initialize the memory management unit(MMU).
+
+  @param[in]   MemoryTable   A pointer to a memory ragion table.
+  @param[out]  TranslationTableBase  A pointer to a translation table base 
address.
+

[edk2-devel] [PATCH v1 11/26] UefiCpuPkg: Add CpuMmuInitLib.h to UefiCpuPkg

2024-03-11 Thread Chao Li

This file provide the CPU MMU configure and initialize interface, it
will consumes by CpuMmuLib to configure or initialize the MMU.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Sami Mujawar 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Signed-off-by: Chao Li 
---
 UefiCpuPkg/Include/Library/CpuMmuInitLib.h | 34 ++
 UefiCpuPkg/UefiCpuPkg.dec  |  3 ++
 2 files changed, 37 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Library/CpuMmuInitLib.h

diff --git a/UefiCpuPkg/Include/Library/CpuMmuInitLib.h 
b/UefiCpuPkg/Include/Library/CpuMmuInitLib.h
new file mode 100644
index 00..848050d056
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/CpuMmuInitLib.h
@@ -0,0 +1,34 @@
+/** @file
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_MMU_INIT_LIB_H_
+#define CPU_MMU_INIT_LIB_H_
+
+#include 
+#include 
+
+/**
+  Create a page table and initialize the memory management unit(MMU).
+
+  @param[in]   MemoryTable   A pointer to a memory ragion table.
+  @param[out]  TranslationTableBase  A pointer to a translation table base 
address.
+  @param[out]  TranslationTableSize  A pointer to a translation table base 
size.
+
+  @retval  EFI_SUCCESSConfigure MMU successfully.
+   EFI_INVALID_PARAMETER  MemoryTable is NULL.
+   EFI_UNSUPPORTEDOut of memory space or size not aligned.
+**/
+EFI_STATUS
+EFIAPI
+ConfigureMemoryManagementUnit (
+  IN  EFI_MEMORY_DESCRIPTOR  *MemoryTable,
+  OUT VOID   **TranslationTableBase OPTIONAL,
+  OUT UINTN  *TranslationTableSize  OPTIONAL
+  );
+
+#endif // CPU_MMU_INIT_LIB_H_
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index b27cf88aee..ff5ef5bb00 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -77,6 +77,9 @@ [LibraryClasses.LoongArch64]
   ##  @libraryclass  Provides functions for the memory management unit.
   CpuMmuLib|Include/Library/CpuMmuLib.h
 
+  ##  @libraryclass  Provides functions for Initialize the memory management 
unit.
+  CpuMmuInitLib|Include/Library/CpuMmuInitLib.h
+
 [Guids]
   gUefiCpuPkgTokenSpaceGuid  = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 
0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
   gMsegSmramGuid = { 0x5802bce4, 0x, 0x4e33, { 0xa1, 0x30, 
0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
-- 
2.27.0



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[edk2-devel] [PATCH v1 10/26] UefiCpuPkg: Add CpuMmuLib to UefiCpuPkg

2024-03-11 Thread Chao Li

Add a new base library named CpuMmuLib and add a LoongArch64 instance
with in the library.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
Co-authored-by: Dongyan Qian 
Co-authored-by: Xianglai Li 
Co-authored-by: Bibo Mao 
---
 UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.inf|  38 ++
 UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.uni|  14 +
 .../Library/CpuMmuLib/LoongArch64/CpuMmu.c| 614 ++
 .../Library/CpuMmuLib/LoongArch64/Page.h  |  24 +
 .../CpuMmuLib/LoongArch64/TlbInvalid.S|  24 +
 .../CpuMmuLib/LoongArch64/TlbInvalid.h|  24 +
 UefiCpuPkg/UefiCpuPkg.dsc |   3 +
 7 files changed, 741 insertions(+)
 create mode 100644 UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.inf
 create mode 100644 UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.uni
 create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CpuMmu.c
 create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/Page.h
 create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/TlbInvalid.S
 create mode 100644 UefiCpuPkg/Library/CpuMmuLib/LoongArch64/TlbInvalid.h

diff --git a/UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.inf 
b/UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.inf
new file mode 100644
index 00..57675ae6c0
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.inf
@@ -0,0 +1,38 @@
+## @file
+#  CPU Memory Manager Unit library instance.
+#
+#  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION= 1.29
+  BASE_NAME  = CpuMmuLib
+  MODULE_UNI_FILE= CpuMmuLib.uni
+  FILE_GUID  = DA8F0232-FB14-42F0-922C-63104D2C70BE
+  MODULE_TYPE= BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = CpuMmuLib
+
+#
+#  VALID_ARCHITECTURES   = LOONGARCH64
+#
+
+[Sources.LoongArch64]
+  LoongArch64/TlbInvalid.S   | GCC
+  LoongArch64/CpuMmu.c
+  LoongArch64/Page.h
+  LoongArch64/TlbInvalid.h
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  DebugLib
+  MemoryAllocationLib
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMmuIsEnabled  ## CONSUMES
diff --git a/UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.uni 
b/UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.uni
new file mode 100644
index 00..2408f2f90b
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuMmuLib/CpuMmuLib.uni
@@ -0,0 +1,14 @@
+// /** @file
+// CPU Memory Manager Unit library instance.
+//
+// CPU Memory Manager Unit library instance.
+//
+// Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT #language en-US "CPU Memory Manager 
Unit library instance."
+
+#string STR_MODULE_DESCRIPTION  #language en-US "CPU Memory Manager 
Unit library instance."
diff --git a/UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CpuMmu.c 
b/UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CpuMmu.c
new file mode 100644
index 00..7dde436c7c
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuMmuLib/LoongArch64/CpuMmu.c
@@ -0,0 +1,614 @@
+/** @file
+
+  CPU Memory Map Unit Handler Library common functions.
+
+  Copyright (c) 2011-2020, ARM Limited. All rights reserved.
+  Copyright (c) 2016, Linaro Limited. All rights reserved.
+  Copyright (c) 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2023, Ventana Micro Systems Inc. All Rights Reserved.
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "TlbInvalid.h"
+#include "Page.h"
+
+/**
+  Check to see if mmu successfully initializes.
+
+  @param  VOID.
+
+  @retval  TRUE  Initialization has been completed.
+   FALSE Initialization did not complete.
+**/
+STATIC
+BOOLEAN
+MmuIsInit (
+  VOID
+  )
+{
+  if (CsrRead (LOONGARCH_CSR_PGDL) != 0) {
+return TRUE;
+  }
+
+  return FALSE;
+}
+
+/**
+  Determine if an entry is valid pte.
+
+  @paramEntry   The entry value.
+
+  @retval   TRUEThe entry is a valid pte.
+  @retval   FALSE   The entry is not a valid pte.
+
+**/
+STATIC
+BOOLEAN
+IsValidPte (
+  IN  UINTN  Entry
+  )
+{
+  if (Entry != INVALID_PAGE) {
+return TRUE;
+  } else {
+return FALSE;
+  }
+}
+
+/**
+  Determine if an entry is huge page.
+
+  @paramEntry   The entry value.
+
+  @retval   TRUEThe entry is a huge page.
+  @retval   FALSE   The entry is not a valid huge page.
+
+**/
+STATIC
+BOOLEAN
+IsValidHugePage (
+  IN  UINTN  Entry
+  )
+{
+  if ((Entry & (PAGE_HGLOBAL | PAGE_HUGE)) == (PAGE_HGLOBAL | PAGE_HUGE)) {
+return TRUE;
+  } else {
+return FALSE;
+  }
+}
+
+/**
+  Set an entry to

[edk2-devel] [PATCH v1 09/26] UefiCpuPkg: Added a new PCD named PcdCpuMmuIsEnabled

2024-03-11 Thread Chao Li

Added PcdCpuMmuIsEnabled to instruct that the CPU MMU is enabled.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
---
 UefiCpuPkg/UefiCpuPkg.dec | 5 +
 1 file changed, 5 insertions(+)

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index a23a90ec99..b27cf88aee 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -486,5 +486,10 @@ [PcdsDynamic, PcdsDynamicEx]
   # @Prompt GHCB Hypervisor Features
   gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x6018
 
+  ## This dynamic PCD indicates whether CPU MMU is enabled.
+  #  TRUE  - CPU MMU is enabled.
+  #  FASLE - CPU MMU have not enabled.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMmuIsEnabled|FALSE|BOOLEAN|0x6023
+
 [UserExtensions.TianoCore."ExtraFiles"]
   UefiCpuPkgExtra.uni
-- 
2.27.0



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[edk2-devel] [PATCH v1 08/26] UefiCpuPkg: Added a new PCD named PcdCpuExceptionVectorBaseAddress

2024-03-11 Thread Chao Li

Added PcdCpuExceptionVectorBaseAddress use for storing the CPU exception
vector base address. This PCD can be be populated at build time or
changed at runtime.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
---
 UefiCpuPkg/UefiCpuPkg.dec | 5 +
 1 file changed, 5 insertions(+)

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index ca744fab55..a23a90ec99 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -3,6 +3,7 @@
 #
 # Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.
 # Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -389,6 +390,10 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, 
PcdsDynamicEx]
   # @Prompt Enable performance collecting when processor trace is enabled.
   
gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTracePerformanceCollecting|FALSE|BOOLEAN|0x6020
 
+  ## This PCD Contains the pointer to a CPU exception vector base address.
+  # @Prompt The pointer to a CPU exception vector base address.
+  
gUefiCpuPkgTokenSpaceGuid.PcdCpuExceptionVectorBaseAddress|0x0|UINT64|0x6022
+
 [PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, 
PcdsDynamicEx.X64]
   ## Indicate access to non-SMRAM memory is restricted to reserved, runtime 
and ACPI NVS type after SmmReadyToLock.
   #  MMIO access is always allowed regardless of the value of this PCD.
-- 
2.27.0



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[edk2-devel] [PATCH v1 07/26] UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg

2024-03-11 Thread Chao Li

Add a new header file CpuMmuLib.h, whitch is referenced from
ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for
LoongArch64 is added, and more architectures can be accommodated in the
future.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Sami Mujawar 
Cc: Sunil V L 
Cc: Andrei Warkentin 
Signed-off-by: Chao Li 
---
 UefiCpuPkg/Include/Library/CpuMmuLib.h | 55 ++
 UefiCpuPkg/UefiCpuPkg.dec  |  4 ++
 2 files changed, 59 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Library/CpuMmuLib.h

diff --git a/UefiCpuPkg/Include/Library/CpuMmuLib.h 
b/UefiCpuPkg/Include/Library/CpuMmuLib.h
new file mode 100644
index 00..26d2d65524
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/CpuMmuLib.h
@@ -0,0 +1,55 @@
+/** @file
+
+  Copyright (c) 2024 Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_MMU_LIB_H_
+#define CPU_MMU_LIB_H_
+
+#include 
+
+/**
+  Finds the first of the length and memory properties of the memory region 
corresponding
+  to the specified base address.
+
+  @param[in]   BaseAddress   To find the base address of the memory 
region.
+  @param[in, out]  RegionLength  Pointer holding:
+  - At entry, the length of the memory 
region
+expected to be found.
+  - At exit, the length of the memory 
region found.
+  @param[out]  RegionAttributes  Properties of the memory region found.
+
+  @retval  EFI_SUCCESSThe corresponding memory area was successfully found
+   EFI_NOT_FOUNDNo memory area found
+**/
+EFI_STATUS
+EFIAPI
+GetMemoryRegionAttributes (
+  IN UINTN  BaseAddress,
+  IN OUT UINTN  *RegionLength,
+  OUTUINTN  *RegionAttributes
+  );
+
+/**
+  Sets the Attributes  of the specified memory region.
+
+  @param[in]  BaseAddressThe base address of the memory region to set the 
Attributes.
+  @param[in]  Length The length of the memory region to set the 
Attributes.
+  @param[in]  Attributes The Attributes to be set.
+  @param[in]  AttributeMask  Mask of memory attributes to take into account.
+
+  @retval  EFI_SUCCESSThe Attributes was set successfully
+**/
+EFI_STATUS
+EFIAPI
+SetMemoryRegionAttributes (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINTN Length,
+  IN UINTN Attributes,
+  IN UINT64AttributeMask
+  );
+
+#endif // CPU_MMU_LIB_H_
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 571b59b36f..ca744fab55 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -72,6 +72,10 @@ [LibraryClasses.RISCV64]
   ##
   RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h
 
+[LibraryClasses.LoongArch64]
+  ##  @libraryclass  Provides functions for the memory management unit.
+  CpuMmuLib|Include/Library/CpuMmuLib.h
+
 [Guids]
   gUefiCpuPkgTokenSpaceGuid  = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 
0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
   gMsegSmramGuid = { 0x5802bce4, 0x, 0x4e33, { 0xa1, 0x30, 
0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
-- 
2.27.0



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[edk2-devel] [PATCH v1 06/26] UefiCpuPkg: Add CPU exception library for LoongArch

2024-03-11 Thread Chao Li

Added LoongArch exception handler into CpuExceptionHandlerLib.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
Co-authored-by: Baoqi Zhang 
---
 .../DxeCpuExceptionHandlerLib.inf |  23 +-
 .../LoongArch/DxeExceptionLib.c   | 198 ++
 .../LoongArch/ExceptionCommon.c   | 171 
 .../LoongArch/ExceptionCommon.h   | 131 +++
 .../LoongArch64/ArchExceptionHandler.c| 268 +
 .../LoongArch64/ExceptionHandlerAsm.S | 366 ++
 .../LoongArch/SecPeiExceptionLib.c| 102 +
 .../SecPeiCpuExceptionHandlerLib.inf  |  23 +-
 8 files changed, 1273 insertions(+), 9 deletions(-)
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/DxeExceptionLib.c
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/ExceptionCommon.c
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/ExceptionCommon.h
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/LoongArch64/ArchExceptionHandler.c
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/LoongArch64/ExceptionHandlerAsm.S
 create mode 100644 
UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/SecPeiExceptionLib.c

diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index aabcabff0f..9fcba009d6 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -2,6 +2,7 @@
 #  CPU Exception Handler library instance for DXE modules.
 #
 #  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+#  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -18,7 +19,7 @@ [Defines]
 #
 # The following information is for reference only and not required by the 
build tools.
 #
-#  VALID_ARCHITECTURES   = IA32 X64
+#  VALID_ARCHITECTURES   = IA32 X64 LOONGARCH64
 #
 
 [Sources.Ia32]
@@ -32,12 +33,19 @@ [Sources.X64]
   X64/ArchInterruptDefs.h
   X64/ExceptionHandlerAsm.nasm
 
-[Sources.common]
+[Sources.Ia32, Sources.X64]
   CpuExceptionCommon.h
   CpuExceptionCommon.c
   DxeException.c
   PeiDxeSmmCpuException.c
 
+[Sources.LoongArch64]
+  LoongArch/DxeExceptionLib.c
+  LoongArch/ExceptionCommon.h
+  LoongArch/ExceptionCommon.c
+  LoongArch/LoongArch64/ArchExceptionHandler.c
+  LoongArch/LoongArch64/ExceptionHandlerAsm.S | GCC
+
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
   gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList
@@ -51,16 +59,21 @@ [Packages]
   MdeModulePkg/MdeModulePkg.dec
   UefiCpuPkg/UefiCpuPkg.dec
 
-[LibraryClasses]
+[LibraryClasses.common]
   BaseLib
-  CcExitLib
   DebugLib
-  LocalApicLib
   MemoryAllocationLib
   PeCoffGetEntryPointLib
   PrintLib
   SerialPortLib
   SynchronizationLib
 
+[LibraryClasses.Ia32, LibraryClasses.X64]
+  CcExitLib
+  LocalApicLib
+
+[LibraryClasses.LoongArch64]
+  CpuLib
+
 [BuildOptions]
   XCODE:*_*_X64_NASM_FLAGS = -D NO_ABSOLUTE_RELOCS_IN_TEXT
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/DxeExceptionLib.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/DxeExceptionLib.c
new file mode 100644
index 00..eed5644552
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/LoongArch/DxeExceptionLib.c
@@ -0,0 +1,198 @@
+/** @file DxeExceptionLib.c
+
+  LoongArch exception library implemenation for DXE modules.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "ExceptionCommon.h"
+
+EFI_EXCEPTION_CALLBACK  ExternalInterruptHandler[MAX_LOONGARCH_INTERRUPT + 1] 
= { 0 };
+EFI_EXCEPTION_CALLBACK  ExceptionHandler[MAX_LOONGARCH_EXCEPTION + 1] 
= { 0 };
+
+/**
+  Registers a function to be called from the processor interrupt or exception 
handler.
+
+  This function registers and enables the handler specified by 
InterruptHandler for a processor
+  interrupt or exception type specified by InterruptType. If InterruptHandler 
is NULL, then the
+  handler for the processor interrupt or exception type specified by 
InterruptType is uninstalled.
+  The installed handler is called once for each processor interrupt or 
exception.
+
+  @param  InterruptTypeA pointer to the processor's current interrupt 
state. Set to TRUE if interrupts
+   are enabled and FALSE if interrupts are disabled.
+  @param  InterruptHandler A pointer to a function of type 
EFI_CPU_INTERRUPT_HANDLER that is called
+   when a processor interrupt occurs. If

[edk2-devel] [PATCH v1 05/26] UefiCpuPkg: Add LoongArch64 CPU Timer instance

2024-03-11 Thread Chao Li

Add the LoongArch64 CPU Timer instance to CpuTimerLib, using CPUCFG 0x4
and 0x5 for Stable Counter frequency.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
---
 .../Library/CpuTimerLib/BaseCpuTimerLib.inf   |  15 +-
 .../CpuTimerLib/LoongArch64/CpuTimerLib.c | 251 ++
 UefiCpuPkg/UefiCpuPkg.dsc |   3 +
 3 files changed, 267 insertions(+), 2 deletions(-)
 create mode 100644 UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c

diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf 
b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
index f0f4ae902a..4a1c7c0510 100644
--- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
@@ -1,10 +1,15 @@
 ## @file
 #  Base CPU Timer Library
 #
-#  Provides basic timer support using CPUID Leaf 0x15 XTAL frequency. The 
performance
+#  Provides basic timer support.
+#
+#  In x86, using CPUID Leaf 0x15 XTAL frequency. The performance
 #  counter features are provided by the processors time stamp counter.
 #
+#  In LoongArch64, using CPUCFG 0x4 and 0x5 for Stable Counter frequency.
+#
 #  Copyright (c) 2021, Intel Corporation. All rights reserved.
+#  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##
@@ -18,10 +23,13 @@ [Defines]
   LIBRARY_CLASS  = TimerLib
   MODULE_UNI_FILE= BaseCpuTimerLib.uni
 
-[Sources]
+[Sources.IA32, Sources.X64]
   CpuTimerLib.c
   BaseCpuTimerLib.c
 
+[Sources.LoongArch64]
+  LoongArch64/CpuTimerLib.c
+
 [Packages]
   MdePkg/MdePkg.dec
   UefiCpuPkg/UefiCpuPkg.dec
@@ -31,5 +39,8 @@ [LibraryClasses]
   DebugLib
   PcdLib
 
+[LibraryClasses.LoongArch64]
+  SafeIntLib
+
 [Pcd]
   gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency  ## CONSUMES
diff --git a/UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c 
b/UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c
new file mode 100644
index 00..a5ae8d0185
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/LoongArch64/CpuTimerLib.c
@@ -0,0 +1,251 @@
+/** @file
+  CPUCFG 0x4 and 0x5 for Stable Counter frequency instance of Timer Library.
+
+  Copyright (c) 2024, Loongson Technology Corporation Limited. All rights 
reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Calculate clock frequency using CPUCFG 0x4 and 0x5 registers.
+
+  @param  VOID.
+
+  @return The frequency in Hz.
+
+**/
+STATIC
+UINT64
+CalcConstFreq (
+  VOID
+  )
+{
+  UINT32 BaseFreq;
+  UINT64 ClockMultiplier;
+  UINT32 ClockDivide;
+  CPUCFG_REG4_INFO_DATA  CcFreq;
+  CPUCFG_REG5_INFO_DATA  CpucfgReg5Data;
+  UINT64 StableTimerFreq;
+
+  //
+  // Get the the crystal frequency corresponding to the constant
+  // frequency timer and the clock used by the timer.
+  //
+  AsmCpucfg (CPUCFG_REG4_INFO, );
+
+  //
+  // Get the multiplication factor and frequency division factor
+  // corresponding to the constant frequency timer and the clock
+  // used by the timer.
+  //
+  AsmCpucfg (CPUCFG_REG5_INFO, );
+
+  BaseFreq= CcFreq.Bits.CC_FREQ;
+  ClockMultiplier = CpucfgReg5Data.Bits.CC_MUL & 0x;
+  ClockDivide = CpucfgReg5Data.Bits.CC_DIV & 0x;
+
+  if ((BaseFreq == 0x0) || (ClockMultiplier == 0x0) || (ClockDivide == 0x0)) {
+DEBUG ((
+  DEBUG_ERROR,
+  "LoongArch Stable Timer is not available in the CPU, hence this library 
cannot be used.\n"
+  ));
+ASSERT (FALSE);
+CpuDeadLoop ();
+  }
+
+  StableTimerFreq = ((ClockMultiplier * BaseFreq) / ClockDivide);
+
+  if (StableTimerFreq == 0x0) {
+ASSERT (FALSE);
+  }
+
+  return StableTimerFreq;
+}
+
+/**
+  Stalls the CPU for at least the given number of microseconds.
+
+  Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+  @param  MicroSeconds  The minimum number of microseconds to delay.
+
+  @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+  IN UINTN  MicroSeconds
+  )
+{
+  UINT64 CurrentTicks, ExceptedTicks, Remaining;
+  RETURN_STATUS  Status;
+
+  Status = SafeUint64Mult (MicroSeconds, CalcConstFreq (), );
+  ASSERT_RETURN_ERROR (Status);
+
+  ExceptedTicks  = DivU64x32 (Remaining, 100U);
+  CurrentTicks   = AsmReadStableCounter ();
+  ExceptedTicks += CurrentTicks;
+
+  do {
+CurrentTicks = AsmReadStableCounter ();
+  } while (CurrentTicks < ExceptedTicks);
+
+  return MicroSeconds;
+}
+
+/**
+  Stalls the CPU for at least the given number of nanoseconds.
+
+  Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+  @param  NanoSeconds The minimum number of nanoseconds to delay.
+
+  @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+  IN UINTN  NanoSeconds
+  )
+{
+

[edk2-devel] [PATCH v1 04/26] UefiCpuPkg/CpuDxe: Reorder the INF file alphabetically

2024-03-11 Thread Chao Li

Some of the order is not in alphabetical, reorder.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
---
 UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index 1d3e9f8cdb..9e1c673283 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -25,21 +25,21 @@ [Packages]
 [LibraryClasses]
   BaseLib
   BaseMemoryLib
+  CpuExceptionHandlerLib
   CpuLib
   DebugLib
   DxeServicesTableLib
+  HobLib
+  LocalApicLib
   MemoryAllocationLib
   MtrrLib
+  MpInitLib
+  PeCoffGetEntryPointLib
+  ReportStatusCodeLib
+  TimerLib
   UefiBootServicesTableLib
   UefiDriverEntryPoint
-  LocalApicLib
   UefiLib
-  CpuExceptionHandlerLib
-  HobLib
-  ReportStatusCodeLib
-  MpInitLib
-  TimerLib
-  PeCoffGetEntryPointLib
 
 [Sources]
   CpuDxe.c
@@ -77,9 +77,9 @@ [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard   ## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask   ## 
CONSUMES
   gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask## 
CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList  ## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize## 
CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask## 
CONSUMES
 
 [Depex]
   TRUE
-- 
2.27.0



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[edk2-devel] [PATCH v1 03/26] UefiCpuPkg/MpInitLib: Reorder the INF files alphabetically

2024-03-11 Thread Chao Li

Some of the order is not in alphabetical, reorder.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
---
 UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 28 +--
 UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 24 
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf 
b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
index 55e46d4a1f..bf6e6a095f 100644
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
@@ -23,21 +23,21 @@ [Defines]
 
 [Sources.IA32]
   Ia32/AmdSev.c
-  Ia32/MpFuncs.nasm
   Ia32/CreatePageTable.c
+  Ia32/MpFuncs.nasm
 
 [Sources.X64]
   X64/AmdSev.c
-  X64/MpFuncs.nasm
   X64/CreatePageTable.c
+  X64/MpFuncs.nasm
 
 [Sources.common]
   AmdSev.c
-  MpEqu.inc
   DxeMpLib.c
+  Microcode.c
+  MpEqu.inc
   MpLib.c
   MpLib.h
-  Microcode.c
   MpHandOff.h
 
 [Packages]
@@ -47,17 +47,17 @@ [Packages]
 
 [LibraryClasses]
   BaseLib
+  CcExitLib
+  CpuLib
+  DebugAgentLib
+  HobLib
   LocalApicLib
   MemoryAllocationLib
-  HobLib
+  MicrocodeLib
   MtrrLib
-  CpuLib
-  UefiBootServicesTableLib
-  DebugAgentLib
-  SynchronizationLib
   PcdLib
-  CcExitLib
-  MicrocodeLib
+  SynchronizationLib
+  UefiBootServicesTableLib
 [LibraryClasses.X64]
   CpuPageTableLib
 
@@ -70,6 +70,9 @@ [Guids]
   gEdkiiMicrocodePatchHobGuid   ## SOMETIMES_CONSUMES  ## HOB
 
 [Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard  ## 
CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase   ## 
CONSUMES
+  gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr   ## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber   ## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds  ## 
SOMETIMES_CONSUMES
@@ -82,6 +85,3 @@ [Pcd]
   gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures  ## 
CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase   ## 
SOMETIMES_CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi## 
CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard  ## 
CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase   ## 
CONSUMES
-  gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr   ## 
CONSUMES
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf 
b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
index bc3d716aa9..37d05c7ab4 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
@@ -31,31 +31,33 @@ [Sources.X64]
 
 [Sources.common]
   AmdSev.c
+  Microcode.c
   MpEqu.inc
-  PeiMpLib.c
   MpLib.c
   MpLib.h
-  Microcode.c
   MpHandOff.h
+  PeiMpLib.c
 [Packages]
   MdePkg/MdePkg.dec
-  UefiCpuPkg/UefiCpuPkg.dec
   MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
 
 [LibraryClasses]
   BaseLib
+  CcExitLib
+  CpuLib
+  HobLib
   LocalApicLib
   MemoryAllocationLib
-  HobLib
+  MicrocodeLib
   MtrrLib
-  CpuLib
-  SynchronizationLib
-  PeiServicesLib
   PcdLib
-  CcExitLib
-  MicrocodeLib
+  PeiServicesLib
+  SynchronizationLib
 
 [Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase   ## CONSUMES
+  gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr   ## CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber## CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber   ## CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds  ## 
SOMETIMES_CONSUMES
@@ -66,9 +68,7 @@ [Pcd]
   gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate   ## 
SOMETIMES_CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase   ## 
SOMETIMES_CONSUMES
   gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures  ## CONSUMES
-  gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi ## CONSUMES
-  gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase   ## CONSUMES
-  gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr   ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi## CONSUMES
 
 [Ppis]
   gEdkiiPeiShadowMicrocodePpiGuid## SOMETIMES_CONSUMES
-- 
2.27.0



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[edk2-devel] [PATCH v1 02/26] UefiCpuPkg/CpuExceptionHandlerLib: Reorder the INF files alphabetically

2024-03-11 Thread Chao Li

Some of the order is not in alphabetical, reorder.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
---
 .../DxeCpuExceptionHandlerLib.inf | 20 +--
 .../PeiCpuExceptionHandlerLib.inf | 16 +++
 .../SecPeiCpuExceptionHandlerLib.inf  | 12 +--
 .../SmmCpuExceptionHandlerLib.inf | 16 +++
 4 files changed, 32 insertions(+), 32 deletions(-)

diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
index fdbebadab9..aabcabff0f 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
@@ -22,21 +22,21 @@ [Defines]
 #
 
 [Sources.Ia32]
-  Ia32/ExceptionHandlerAsm.nasm
-  Ia32/ExceptionTssEntryAsm.nasm
   Ia32/ArchExceptionHandler.c
   Ia32/ArchInterruptDefs.h
+  Ia32/ExceptionHandlerAsm.nasm
+  Ia32/ExceptionTssEntryAsm.nasm
 
 [Sources.X64]
-  X64/ExceptionHandlerAsm.nasm
   X64/ArchExceptionHandler.c
   X64/ArchInterruptDefs.h
+  X64/ExceptionHandlerAsm.nasm
 
 [Sources.common]
   CpuExceptionCommon.h
   CpuExceptionCommon.c
-  PeiDxeSmmCpuException.c
   DxeException.c
+  PeiDxeSmmCpuException.c
 
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
@@ -53,14 +53,14 @@ [Packages]
 
 [LibraryClasses]
   BaseLib
-  SerialPortLib
-  PrintLib
-  SynchronizationLib
+  CcExitLib
+  DebugLib
   LocalApicLib
-  PeCoffGetEntryPointLib
   MemoryAllocationLib
-  DebugLib
-  CcExitLib
+  PeCoffGetEntryPointLib
+  PrintLib
+  SerialPortLib
+  SynchronizationLib
 
 [BuildOptions]
   XCODE:*_*_X64_NASM_FLAGS = -D NO_ABSOLUTE_RELOCS_IN_TEXT
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
index 3bcaff5c5f..3a11516e32 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
@@ -22,15 +22,15 @@ [Defines]
 #
 
 [Sources.Ia32]
-  Ia32/ExceptionHandlerAsm.nasm
-  Ia32/ExceptionTssEntryAsm.nasm
   Ia32/ArchExceptionHandler.c
   Ia32/ArchInterruptDefs.h
+  Ia32/ExceptionHandlerAsm.nasm
+  Ia32/ExceptionTssEntryAsm.nasm
 
 [Sources.X64]
-  X64/SecPeiExceptionHandlerAsm.nasm
   X64/ArchExceptionHandler.c
   X64/ArchInterruptDefs.h
+  X64/SecPeiExceptionHandlerAsm.nasm
 
 [Sources.common]
   CpuExceptionCommon.h
@@ -45,14 +45,14 @@ [Packages]
 
 [LibraryClasses]
   BaseLib
-  SerialPortLib
-  PrintLib
-  LocalApicLib
-  PeCoffGetEntryPointLib
+  CcExitLib
   HobLib
+  LocalApicLib
   MemoryAllocationLib
+  PeCoffGetEntryPointLib
+  PrintLib
+  SerialPortLib
   SynchronizationLib
-  CcExitLib
 
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard# CONSUMES
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
index e7b1144f69..f8e597d86d 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
@@ -22,15 +22,15 @@ [Defines]
 #
 
 [Sources.Ia32]
-  Ia32/ExceptionHandlerAsm.nasm
-  Ia32/ExceptionTssEntryAsm.nasm
   Ia32/ArchExceptionHandler.c
   Ia32/ArchInterruptDefs.h
+  Ia32/ExceptionHandlerAsm.nasm
+  Ia32/ExceptionTssEntryAsm.nasm
 
 [Sources.X64]
-  X64/SecPeiExceptionHandlerAsm.nasm
   X64/ArchExceptionHandler.c
   X64/ArchInterruptDefs.h
+  X64/SecPeiExceptionHandlerAsm.nasm
 
 [Sources.common]
   CpuExceptionCommon.h
@@ -44,11 +44,11 @@ [Packages]
 
 [LibraryClasses]
   BaseLib
-  SerialPortLib
-  PrintLib
+  CcExitLib
   LocalApicLib
   PeCoffGetEntryPointLib
-  CcExitLib
+  PrintLib
+  SerialPortLib
 
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
diff --git 
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
index 27f0b96fa9..cc280a6ee7 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
@@ -22,15 +22,15 @@ [Defines]
 #
 
 [Sources.Ia32]
-  Ia32/ExceptionHandlerAsm.nasm
-  Ia32/ExceptionTssEntryAsm.nasm
   Ia32/ArchExceptionHandler.c
   Ia32/ArchInterruptDefs.h
+  Ia32/ExceptionHandlerAsm.nasm
+  Ia32/ExceptionTssEntryAsm.nasm
 
 [Sources.X64]
-  X64/ExceptionHandlerAsm.nasm
   X64/ArchExceptionHandler.c
   X64/ArchInterruptDefs.h
+  X64/ExceptionHandlerAsm.nasm
 
 [Sources.common]
   CpuExceptionCommon.h
@@ -45,13 +45,13 @@ [Packages]
 
 [LibraryClasses]
   BaseLib
-  SerialPortLib
-  PrintLib
-  SynchronizationLib
+  CcExitLib
+  DebugLib
   LocalApicLib
   PeCoffGetEntryPointLib
-

[edk2-devel] [PATCH v1 01/26] UefiCpuPkg/CpuTimerLib: Reorder the INF file alphabetically

2024-03-11 Thread Chao Li

Some of the order is not in alphabetical, reorder.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Signed-off-by: Chao Li 
---
 UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf 
b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
index de0648de91..f0f4ae902a 100644
--- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
@@ -28,8 +28,8 @@ [Packages]
 
 [LibraryClasses]
   BaseLib
-  PcdLib
   DebugLib
+  PcdLib
 
 [Pcd]
   gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency  ## CONSUMES
-- 
2.27.0



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[edk2-devel] [PATCH v1 00/26] Part 2 patch set to enable LoongArch virtual machine in edk2

2024-03-11 Thread Chao Li

This patch set is the part 2 of enable LoongArch virtual machine and is
a continuation of the first patch series v8 submitted at:
https://edk2.groups.io/g/devel/message/114526.

Patch1-Patch4: Reorder some INF files located in UefiCpuPkg
alphabetically.

Patch5-Patch14: Added Timer, CpuMmuLib, CpuMmuInitLib, MpInitLib, CpuDxe
for LoongArch, and added some PCD and header files requested by the
above libraries and drivers.

Patch15-Patch25: LoongArch QEMU virtual machine private code, include
SEC and PEI phase, some libraries and drivers.

Patch26: Added LoongArchVirt's self introduction-file.

Modfied modules: UefiCpuPkg and OvmfPkg

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

PR: https://github.com/tianocore/edk2/pull/5208

Cc: Ray Ni 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Ard Biesheuvel 
Cc: Jiewen Yao 
Cc: Gerd Hoffmann 
Cc: Leif Lindholm 
Cc: Sami Mujawar 
Cc: Sunil V L 
Cc: Bibo Mao 
Cc: Dongyan Qian 

Chao Li (26):
  UefiCpuPkg/CpuTimerLib: Reorder the INF file alphabetically
  UefiCpuPkg/CpuExceptionHandlerLib: Reorder the INF files
alphabetically
  UefiCpuPkg/MpInitLib: Reorder the INF files alphabetically
  UefiCpuPkg/CpuDxe: Reorder the INF file alphabetically
  UefiCpuPkg: Add LoongArch64 CPU Timer instance
  UefiCpuPkg: Add CPU exception library for LoongArch
  UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg
  UefiCpuPkg: Added a new PCD named PcdCpuExceptionVectorBaseAddress
  UefiCpuPkg: Added a new PCD named PcdCpuMmuIsEnabled
  UefiCpuPkg: Add CpuMmuLib to UefiCpuPkg
  UefiCpuPkg: Add CpuMmuInitLib.h to UefiCpuPkg
  UefiCpuPkg: Add CpuMmuInitLib to UefiCpuPkg
  UefiCpuPkg: Add multiprocessor library for LoongArch64
  UefiCpuPkg: Add CpuDxe driver for LoongArch64
  OvmfPkg/LoongArchVirt: Add stable timer driver
  OvmfPkg/LoongArchVirt: Add a NULL library named
CollectApResouceLibNull
  OvmfPkg/LoongArchVirt: Add serial port hook library
  OvmfPkg/LoongArchVirt: Add the early serial port output library
  OvmfPkg/LoongArchVirt: Add real time clock library
  OvmfPkg/LoongArchVirt: Add NorFlashQemuLib
  OvmfPkg/LoongArchVirt: Add FdtQemuFwCfgLib
  OvmfPkg/LoongArchVirt: Add reset system library
  OvmfPkg/LoongArchVirt: Support SEC phase
  OvmfPkg/LoongArchVirt: Support PEI phase
  OvmfPkg/LoongArchVirt: Add build file
  OvmfPkg/LoongArchVirt: Add self introduction file

 .../Drivers/StableTimerDxe/Timer.c|  381 
 .../Drivers/StableTimerDxe/Timer.h|  127 ++
 .../Drivers/StableTimerDxe/TimerDxe.inf   |   41 +
 .../CollectApResourceLibNull.c|   38 +
 .../CollectApResourceLibNull.inf  |   31 +
 .../CollectApResourceLibNull.uni  |9 +
 .../EarlyFdtSerialPortLib16550.c  |  815 +
 .../EarlyFdtSerialPortLib16550.inf|   46 +
 .../EarlyFdt16550SerialPortHookLib.c  |   52 +
 .../EarlyFdt16550SerialPortHookLib.inf|   37 +
 .../Fdt16550SerialPortHookLib.c   |   39 +
 .../Fdt16550SerialPortHookLib.inf |   33 +
 .../Fdt16550SerialPortHookLib.uni |   14 +
 .../FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.c  |  504 +
 .../FdtQemuFwCfgLib/FdtQemuFwCfgPeiLib.inf|   42 +
 .../FdtQemuFwCfgLib/QemuFwCfgLibInternal.h|   73 +
 .../Library/FdtQemuFwCfgLib/QemuFwCfgPei.c|  117 ++
 .../DxeLsRealTimeClockLib.c   |  327 
 .../DxeLsRealTimeClockLib.inf |   41 +
 .../LsRealTimeClockLib/LsRealTimeClock.h  |   47 +
 .../PeiLsRealTimeClockLib.c   |   31 +
 .../PeiLsRealTimeClockLib.inf |   29 +
 .../Library/NorFlashQemuLib/NorFlashQemuLib.c |  140 ++
 .../NorFlashQemuLib/NorFlashQemuLib.inf   |   43 +
 .../BaseResetSystemAcpiGed.c  |  148 ++
 .../BaseResetSystemAcpiGedLib.inf |   36 +
 .../DxeResetSystemAcpiGed.c   |  259 +++
 .../DxeResetSystemAcpiGedLib.inf  |   41 +
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.c   |  125 ++
 .../ResetSystemAcpiLib/ResetSystemAcpiGed.h   |   23 +
 OvmfPkg/LoongArchVirt/LoongArchVirt.fdf.inc   |   34 +
 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.dsc   |  680 +++
 OvmfPkg/LoongArchVirt/LoongArchVirtQemu.fdf   |  313 
 OvmfPkg/LoongArchVirt/PlatformPei/Fv.c|   39 +
 OvmfPkg/LoongArchVirt/PlatformPei/MemDetect.c |  202 ++
 OvmfPkg/LoongArchVirt/PlatformPei/Platform.c  |  393 
 OvmfPkg/LoongArchVirt/PlatformPei/Platform.h  |  128 ++
 .../LoongArchVirt/PlatformPei/PlatformPei.inf |   72 +
 OvmfPkg/LoongArchVirt/Readme.md   |   69 +
 OvmfPkg/LoongArchVirt/Sec/LoongArch64/Start.S |  184 ++
 OvmfPkg/LoongArchVirt/Sec/SecMain.c   |  506 +
 OvmfPkg/LoongArchVirt/Sec/SecMain.inf |   53 +
 OvmfPkg/LoongArchVirt/VarStore.fdf.inc|   67 +
 UefiCpuPkg/CpuDxe/CpuDxe.inf  |   37 +-
 UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.c|  426 +
 UefiCpuPkg/CpuDxe/LoongArch64/CpuDxe.h|  288 +++

Re: [edk2-devel] [PATCH] BaseTools: FMMT Skip empty Lines while parsing FMMTConfig.ini

2024-03-11 Thread Yuwei Chen

Ali, please also create PR in BaseTools repo.
Reviewed-by: Yuwei Chen 

> -Original Message-
> From: S, Ashraf Ali 
> Sent: Wednesday, February 28, 2024 5:57 PM
> To: devel@edk2.groups.io
> Cc: S, Ashraf Ali ; Rebecca Cran
> ; Liming Gao ; Feng, Bob
> C ; Chen, Christine ;
> Chaganty, Rangasai V 
> Subject: [PATCH] BaseTools: FMMT Skip empty Lines while parsing
> FMMTConfig.ini
> 
> When the FMMTConf.ini file has empty lines then it used to throw errors
> GuidTool load error!, this patch is to skip checking for empty lines in the 
> ini
> file
> 
> Cc: Rebecca Cran 
> Cc: Liming Gao 
> Cc: Bob Feng 
> Cc: Yuwei Chen 
> Cc: Chen Christine 
> Cc: Chaganty Rangasai V 
> 
> Signed-off-by: Ashraf Ali 
> ---
>  BaseTools/Source/Python/FMMT/core/GuidTools.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/BaseTools/Source/Python/FMMT/core/GuidTools.py
> b/BaseTools/Source/Python/FMMT/core/GuidTools.py
> index f6bdeffa50..f9cfd4ead0 100644
> --- a/BaseTools/Source/Python/FMMT/core/GuidTools.py
> +++ b/BaseTools/Source/Python/FMMT/core/GuidTools.py
> @@ -153,7 +153,7 @@ class GUIDTools:
>  config_data = fd.readlines()
>  for line in config_data:
>  try:
> -if not line.startswith("#"):
> +if not line.startswith("#") and line.strip():
>  guid, short_name, command = line.split()
>  new_format_guid =
> struct2stream(ModifyGuidFormat(guid.strip()))
>  self.tooldef[new_format_guid] = GUIDTool(
> --
> 2.42.0.windows.2



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[edk2-devel] [PATCH 4/4] AMD/AmdPlatformPkg: Update FspWrapper UPD table for BIOS setup options

2024-03-11 Thread Zhai, MingXin (Duke) via groups.io

From: Duke Zhai 

BZ #:4728
1.Remove useless options like I2C enable
2.Add new option:SocVoltage

Cc: Abner Chang 
Cc: Igniculus Fu 
Reviewed-by: Ken Yao 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 .../edk2/Fsp2WrapperPkg/Include/FspmUpd.h | 71 ++-
 .../FspWrapperPlatformLibSample.c | 29 
 2 files changed, 36 insertions(+), 64 deletions(-)

diff --git 
a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h 
b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h
index 8cadbe430a..875461a58a 100644
--- a/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h
+++ b/Platform/AMD/VanGoghBoard/Override/edk2/Fsp2WrapperPkg/Include/FspmUpd.h
@@ -16,41 +16,42 @@
 /** Fsp M Configuration
 **/
 typedef struct {
-  /** Offset 0x0040**/ UINT32bert_size;
-  /** Offset 0x0044**/ UINT32tseg_size;
-  /** Offset 0x0048**/ UINT32dxio_descriptor_table_pointer;
-  /** Offset 0x004C**/ UINT32pcie_reset_function_pointer;
-  /** Offset 0x0050**/ UINT32ddi_descriptor_table_pointer;
-  /** Offset 0x0054**/ UINT32temp_memory_base_addr;
-  /** Offset 0x0058**/ UINT32temp_memory_size;
-  /** Offset 0x005C**/ UINT32fsp_o_pei_volume_address;
-  /** Offset 0x0060**/ UINT32fsp_o_pei_upd_address;
-  /** Offset 0x0064**/ UINT32pei_reset_ppi_addr;
-  /** Offset 0x0068**/ UINT32resource_size_for_each_rb_ptr;
-  /** Offset 0x006C**/ UINT32resource_size_for_each_rb_size;
-  /** Offset 0x0070**/ UINT32total_number_of_root_bridges_ptr;
-  /** Offset 0x0074**/ UINT32total_number_of_root_bridges_size;
-  /** Offset 0x0078**/ UINT32amd_pbs_setup_ptr;
-  /** Offset 0x007C**/ UINT32amd_pbs_setup_size;
-  /** Offset 0x0080**/ UINT32ap_sync_flag_nv_ptr;
-  /** Offset 0x0084**/ UINT32ap_sync_flag_nv_size;
-  /** Offset 0x0088**/ UINT8 DbgFchUsbUsb0DrdMode;
-  /** Offset 0x0089**/ UINT8 DbgFchUsbUsb2DrdMode;
-  /** Offset 0x008A**/ UINT32CmnGnbGfxUmaFrameBufferSize;
-  /** Offset 0x008E**/ UINT8 CmnGnbNbIOMMU;
-  /** Offset 0x008F**/ UINT32DbgFastPPTLimit;
-  /** Offset 0x0093**/ UINT32DbgSlowPPTLimit;
-  /** Offset 0x0097**/ UINT32CmnCpuVoltageOffset;
-  /** Offset 0x009B**/ UINT32CmnGpuVoltageOffset;
-  /** Offset 0x009F**/ UINT32CmnSocVoltageOffset;
-  /** Offset 0x00A3**/ UINT8 CmnGnbGfxUmaMode;
-  /** Offset 0x00A4**/ UINT8 CmnFchI2C0Config;
-  /** Offset 0x00A5**/ UINT8 CmnFchI2C1Config;
-  /** Offset 0x00A6**/ UINT8 CmnFchI2C2Config;
-  /** Offset 0x00A7**/ UINT8 CmnFchI2C3Config;
-  /** Offset 0x00A8**/ UINT32ids_nv_table_address;
-  /** Offset 0x00AC**/ UINT32ids_nv_table_size;
-  /** Offset 0x00B0**/ UINT16UpdTerminator;
+   /** Offset 0x0040**/UINT32  bert_size;
+   /** Offset 0x0044**/UINT32  tseg_size;
+   /** Offset 0x0048**/UINT32  
dxio_descriptor_table_pointer;
+   /** Offset 0x004C**/UINT32  
pcie_reset_function_pointer;
+   /** Offset 0x0050**/UINT32  
ddi_descriptor_table_pointer;
+   /** Offset 0x0054**/UINT32  
temp_memory_base_addr;
+   /** Offset 0x0058**/UINT32  temp_memory_size;
+   /** Offset 0x005C**/UINT32  
fsp_o_pei_volume_address;
+   /** Offset 0x0060**/UINT32  
fsp_o_pei_upd_address;
+   /** Offset 0x0064**/UINT32  pei_reset_ppi_addr;
+   /** Offset 0x0068**/UINT32  
resource_size_for_each_rb_ptr;
+   /** Offset 0x006C**/UINT32  
resource_size_for_each_rb_size;
+   /** Offset 0x0070**/UINT32  
total_number_of_root_bridges_ptr;
+   /** Offset 0x0074**/UINT32  
total_number_of_root_bridges_size;
+   /** Offset 0x0078**/UINT32  amd_pbs_setup_ptr;
+   /** Offset 0x007C**/UINT32  amd_pbs_setup_size;
+   /** Offset 0x0080**/UINT32  ap_sync_flag_nv_ptr;
+   /** Offset 0x0084**/UINT32  
ap_sync_flag_nv_size;
+   /** Offset 0x0088**/UINT8   FchUsbUsb0DrdMode;
+   /** Offset 0x0089**/UINT8   FchUsbUsb2DrdMode;
+   /** Offset 0x008A**/UINT8   CmnGnbGfxUmaMode;
+   /** Offset 0x008B**/UINT32  
CmnGnbGfxUmaFrameBufferSize;
+   /** Offset 0x008F**/UINT8   CmnGnbNbIOMMU;
+   /** Offset 0x0090**/UINT8   PPTCtl;
+   /** Offset 0x0091**/UINT32  FastPPTLimit;
+   /** Offset 0x0095**/UINT32  SlowPPTLimit;
+   /** Offset 0x0099**/UINT8

[edk2-devel] [PATCH 3/4] AMD/AmdPlatformPkg: Enable capsule at linux build

2024-03-11 Thread Zhai, MingXin (Duke) via groups.io

From: Duke Zhai 

BZ #:4720
Linux build script include capsule build.
Fix winodws capsule build issue.

Cc: Abner Chang 
Cc: Igniculus Fu 
Reviewed-by: Ken Yao 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 .../ChachaniBoardPkg/GenCapsule.bat   |  2 +-
 .../VanGoghBoard/ChachaniBoardPkg/build.sh| 22 +--
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
index 7dca22a4e3..c55f561772 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/GenCapsule.bat
@@ -36,7 +36,7 @@ if not exist %WORKSPACE%\%BIOS_FILE_NAME% (
   goto ERROR
 )

- Setup OpenSSL Command Line Environment
+echo Setup OpenSSL Command Line Environment
 if not "%OPENSSL_PATH%" == "" (
   set OPENSSL_PATH_TEMP=%OPENSSL_PATH%
 )
diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
index f4652e91c6..0984876ef2 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/build.sh
@@ -1,3 +1,4 @@
+#!/bin/bash
 ## @file
 # Linux build script file to launch Chachani Board BIOS build
 #
@@ -22,6 +23,7 @@ export OemBoard=Chachani
 export PLATFORM_PATH=edk2-platforms/Platform/AMD/VanGoghBoard
 export BUILD_TYPE=RELEASE
 export TOOLCHAIN_TAG=CLANGPDB
+export OTA_CAPSULE_NAME=OTACAPSULE # You need to keep this name sync with 
PlatformCapsule.fdf
 #TRUE / FALSE
 export COMPRESS_FSP_REGION=TRUE
 export KEY_MODE=TK
@@ -35,16 +37,25 @@ export NASM_PREFIX=
 export GCC5_BIN=
 #CLANG_BIN shall end with a slash.
 export CLANG_BIN=
+#OPENSSL_PATH shall end with a slash.
+export OPENSSL_PATH=

 echo "Building for ${OemBoard} board, ${BUILD_TYPE} mode with 
${TOOLCHAIN_TAG}."
-echo "IASL: ${IASL_PREFIX}iasl, NASM: ${NASM_PREFIX}nasm, GCC: ${GCC5_BIN}gcc, 
CLANG:${CLANG_BIN}clang."
+echo "IASL: ${IASL_PREFIX}iasl, NASM: ${NASM_PREFIX}nasm, GCC: ${GCC5_BIN}gcc, 
CLANG:${CLANG_BIN}clang, OPENSSL:${OPENSSL_PATH}openssl."
 [[ ${COMPRESS_FSP_REGION} == "TRUE" ]] && echo "FSP will be built with 
compress support."
 # Env check
 echo_section "Checking compilation environment"
 [[ "${IASL_PREFIX}" == "" ]] && export IASL_PREFIX=$(dirname $(which iasl))/
 [[ "${NASM_PREFIX}" == "" ]] && export NASM_PREFIX=$(dirname $(which nasm))/
+[[ "${OPENSSL_PATH}" == "" ]] && export OPENSSL_PATH=$(dirname $(which 
openssl))/
 [[ -f ${IASL_PREFIX}iasl ]] || (echo "IASL not found! Please specify 
IASL_PREFIX!";exit -1)
-[[ -f ${IASL_PREFIX}nasm ]] || (echo "NASM not found! Please specify 
NASM_PREFIX!";exit -1)
+[[ -f ${NASM_PREFIX}nasm ]] || (echo "NASM not found! Please specify 
NASM_PREFIX!";exit -1)
+[[ -f ${OPENSSL_PATH}openssl ]] || (echo "OpenSSL not found! Please specify 
OPENSSL_PATH!";exit -1)
+
+echo "IASL version $(LC_ALL=C ${IASL_PREFIX}iasl -v | sed -n '3,3p' | cut -d' 
' -f5) detected."
+echo "NASM version $(LC_ALL=C ${NASM_PREFIX}nasm --version | head -n1 | cut 
-d' ' -f3) detected."
+echo "OpenSSL version $(LC_ALL=C ${OPENSSL_PATH}openssl version | head -n1 | 
cut -d' ' -f2) detected."
+
 if [ ${TOOLCHAIN_TAG} != "CLANGPDB" ]
 then
 [[ "${GCC5_BIN}" == "" ]]   && export GCC5_BIN=$(dirname $(which gcc))/
@@ -174,4 +185,11 @@ python3 FlashABImage32M.py ${F1_ECSIG} ${F2_EC} ${F3_EFS} 
${F4_PSP_L1_DIRECTORY}
 ${F6_SLOT_HEADER_1} ${F7_SLOT_HEADER_2} ${F8_SLOT_A} ${F9_SLOT_B} 
${F10_OUT_IMAGE}
 popd

+echo_section "Generating Capsule image"
+rm -r 
${WORKSPACE}/Build/ChachaniBoardPkg/${BUILD_TYPE}_${TOOLCHAIN_TAG}/FV/SYSTEMFIRMWAREUPDATECARGO*
+touch 
${WORKSPACE}/Build/ChachaniBoardPkg/${BUILD_TYPE}_${TOOLCHAIN_TAG}/FV/SYSTEMFIRMWAREUPDATECARGO.Fv
+build -p ${PROJECT_PKG}/PlatformCapsule.dsc -t ${TOOLCHAIN_TAG} -b 
${BUILD_TYPE} -D BIOS_FILE=${BIOSNAME}UDK.FD
+[[ $? -ne 0 ]] && exit -1
+cp 
${WORKSPACE}/Build/ChachaniBoardPkg/${BUILD_TYPE}_${TOOLCHAIN_TAG}/FV/${OTA_CAPSULE_NAME}.Cap
 .
+
 echo_section "Build success @ $(date)"
--
2.31.1



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[edk2-devel] [PATCH 1/4] AMD/AmdPlatformPkg: Use HpetTimerDxe to replace 8254Timer.

2024-03-11 Thread Zhai, MingXin (Duke) via groups.io

From: Duke Zhai 

BZ #:4718
As the new EDK2 no supports 8254 timer, so used HpetTimer to replace it.

Cc: Abner Chang 
Cc: Igniculus Fu 
Reviewed-by: Ken Yao 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc | 2 --
 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf | 3 +--
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
index 510ce10c0c..20f06dd851 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.dsc
@@ -745,8 +745,6 @@
   MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
   FatPkg/EnhancedFatDxe/Fat.inf
   PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
-  OvmfPkg/8259InterruptControllerDxe/8259.inf
-  OvmfPkg/8254TimerDxe/8254Timer.inf
   
MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
   
MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf

diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
index 5194a8c10d..0d844689b3 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Project.fdf
@@ -416,8 +416,7 @@ NumBlocks = 0x100
   # Platform
   #
   INF  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
-  INF  OvmfPkg/8259InterruptControllerDxe/8259.inf
-  INF  OvmfPkg/8254TimerDxe/8254Timer.inf
+  INF  PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf

   #
   # ACPI
--
2.31.1



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[edk2-devel] [PATCH 2/4] AMD/AmdPlatformPkg: Fix Bug Microcode version cannot show correctly at BIOS setup

2024-03-11 Thread Zhai, MingXin (Duke) via groups.io

From: Duke Zhai 

BZ #:4719
Microcode not load correct cause BIOS setup not show microcode version, modify 
Microcode binary's instance to fixed this issue.

Cc: Abner Chang 
Cc: Igniculus Fu 
Reviewed-by: Ken Yao 
Reviewed-by: Eric Xing 
Signed-off-by: Duke Zhai 
---
 .../AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml 
b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
index 22af6623e2..585e12d487 100644
--- a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
+++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/BIOSImageDirectory32M.xml
@@ -57,7 +57,7 @@
 
 
 
-
+
 
   
 
--
2.31.1



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[edk2-devel] [PATCH 0/4] Update Vangogh platform reference code

2024-03-11 Thread Zhai, MingXin (Duke) via groups.io

From: Duke Zhai 

1. Use HPET timer to replace 8254 timer
2.Fix Bug Microcode version cannot show correctly at BIOS setup
3.Enable capsule at linux build
4.Update FspWrapper UPD table for BIOS setup options

Duke Zhai (4):
  AMD/AmdPlatformPkg: Use HpetTimerDxe to replace 8254Timer.
  AMD/AmdPlatformPkg: Fix Bug Microcode version cannot show correctly at
BIOS setup
  AMD/AmdPlatformPkg: Enable capsule at linux build
  AMD/AmdPlatformPkg: Update FspWrapper UPD table for BIOS setup options

 .../BIOSImageDirectory32M.xml |  2 +-
 .../ChachaniBoardPkg/GenCapsule.bat   |  2 +-
 .../VanGoghBoard/ChachaniBoardPkg/Project.dsc |  2 -
 .../VanGoghBoard/ChachaniBoardPkg/Project.fdf |  3 +-
 .../VanGoghBoard/ChachaniBoardPkg/build.sh| 22 +-
 .../edk2/Fsp2WrapperPkg/Include/FspmUpd.h | 71 ++-
 .../FspWrapperPlatformLibSample.c | 29 
 7 files changed, 59 insertions(+), 72 deletions(-)

--
2.31.1



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Re: [edk2-devel] EDK II CI issues installing choco dependencies - RESOLVED

2024-03-11 Thread Michael D Kinney

This issue appears to be resolved

Mike

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Michael
> D Kinney
> Sent: Sunday, March 10, 2024 12:16 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D 
> Subject: [edk2-devel] EDK II CI issues installing choco dependencies
> 
> I am seeing some EDK II CI failures installing choco
> dependencies on windows CI agents.
> 
> Here is an example:
> 
> https://github.com/tianocore/edk2/pull/5454
> https://dev.azure.com/tianocore/edk2-
> ci/_build/results?buildId=120411=logs=d32104f1-f467-5bda-fd84-
> d1a8627a9794=da01f8aa-41f1-5e7f-f8f1-aaec629da65f=85
> 
> I see a similar description here that was opened yesterday and
> closed as a choco issue
> 
> https://github.com/actions/runner-images/issues/9476
> 
> Let me know if anyone notices any resolutions/workarounds.
> 
> Mike
> 
> 
> 
> 
> 



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