Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: Load Serial driver earlier in DXE

[Albecki, Mateusz]

Sorry, I didn't want to make an impression that I expected solution to be 
delivered, I was merely trying to explain some of the complexity we are trying 
to handle on our side and why we didn't went for SerialDxe and instead opted to 
make PciSioSerialDxe work for our use case. Anyway thanks for the ideas, we 
will definitely look into implementing step h you mentioned in case other 
maintainers also disagree with this patch.

Thanks,
Mateusz


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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: Load Serial driver earlier in DXE

[Albecki, Mateusz]

Is the idea to refactor PciSioSerialDxe to extract functions that access the HW 
and wrap it in the SerialPortLib instance? That solution would still save us 
some maintenance cost. However exploring the idea further I see following 
problems:

1. Relying on driver binding produces a fairly nice flow: platform driver 
initializes enough platform HW for UART to work -> platform driver calls 
ConnectController -> driver initializes UART. With SerialDxe a depex would have 
to be injected through our instance of SerialPortLib to stop the SerialDxe 
dispatch until platform driver made the platform ready.
2. I am wondering how it would work in case we want to allow dynamic 
configuration of debug port(basically selecting which UART controller would be 
used). With current solution we can select which one(or which ones) will be 
used by simply installing and connecting corresponding handles. With library 
solution I guess library would have to locate some protocols(possibly the same 
PCI_IO and DEVICE_PATH) that were installed by platform driver. It would also 
need to install notify on those protocols installation in case platform wants 
to add more uarts later on in the boot flow.
3. We still end up with 2 UART drivers in flash since PciSioSerialDxe is needed 
for PCI UARTs.

I also think this solution is comparable in effort to refactoring the 
PciSioSerialDxe so that it doesn't use driver binding when used as a DXE 
driver. In this solution driver would have one .c file for code with driver 
binding and one .c file for code when everything is done in entry point, it 
would still use DEVICE_PATH and PCI_IO/SIO. While I still think using the 
driver as is in DXE is best for us, in case that solution gets blocked I would 
like to understand if everyone would be ok with such refactoring.

Thanks,
Mateusz


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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: Load Serial driver earlier in DXE

[Albecki, Mateusz]

1. Using SerialDxe instead of PciSioSerialDxe - from our perspective the main 
idea is to avoid maintaining our own implementation of functions that actually 
communicate with UART controller. To use SerialDxe we would have to still 
maintain our own SerialPortLib that actually goes and sends data over UART. 
Also a note on LPSS UART - in terms of registers it is just a standard UART 
controller, the only quirk here is how to access it hence the custom 
PCI_IO_PROTOCOL implementation.

2. Using ConnectController before BDS - I noticed that the section I quoted 
says that BDS will use ConnectController however it doesn't say that it can't 
be used outside of that context. I did search the UEFI spec to see whether it 
provides additional restrictions and the only section that elaborates on this 
is the following:
"Under the UEFI Driver Model , the act of connecting and disconnecting drivers 
from controllers in a platform is under the platform firmware’s control. This 
will typically be implemented as part of the UEFI Boot Manager, but other 
implementations are possible. " - from  Section 2.5.6 Platform components
It seems to be rather permissive when it comes to who and when can call it.

3. How to make sure dispatch is early enough and not too late - this will 
depend on the overall platform implementation. For our part - we simply put it 
into flash as early as we can get away with. Even apriori section isn't 
strictly necessary if the platform is comfortable with relying on the fact that 
DXE core in MdeModulePkg dispatches modules in order of their placement in 
flash(that's not architectural as far as I know). Other platforms might choose 
to introduce explicit depex on gEfiSerialIoProtocolGuid. To reiterate this is 
the implementation that works for us in a sense that we get logs from all 
modules that change frequently from generation to generation, I understand that 
the same might not be true for platforms other than Intel however I think 
majority of platforms could still make at least some use of early UART 
debugging.

4. When exactly do we connect LPSS UART and start logging - we try to be as 
early as possible for this interface. We miss all of DXE_CORE logs(obviously), 
Pcd.inf and a couple of modules that implement some of the architectural 
protocols(from PciSio perspective metronome is the only actually required as 
far as we can tell since stall has to work).

I also want to note that I get why this is a controversial change. I didn't 
realize it earlier but it would be the first DXE_DRIVER in EDK2 tree that 
implements driver binding and in general it is strange to have PCI device 
driver that could potentially dispatch before PCI bus driver(however it is 
worth noting here that PciSioSerialDxe is not just a PCI driver, it is a combo 
driver capable of supporting PCI and SIO). That said I still think EDK2 in 
general needs a way to support early device drivers and using DXE_DRIVER seems 
like the least invasive idea. We need early drivers not just for debug(although 
that is one of the most important use cases I would say) other important use 
case is platform management through SMBUS/I2C/other serial interface which 
might be required to even be able to enumerate full PCI hierarchy(for instance 
some of the PCI slots might be powered down and you need to power them on 
sending commands over I2C) or maybe flash access to EFI variable 
storage(nothing says that you can't have it connected to PCI SPI controller) or 
maybe GPIO control to do any number of platform specific things.

Thanks,
Mateusz


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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: Load Serial driver earlier in DXE

[Albecki, Mateusz]

Hi,

I was originally responsible for suggesting this change internally(more 
specifically - to switch from Intel specific LPSS UART driver to EDK2 driver 
which on inspection seemed to cover all relevant modes of operations of LPSS 
UART).

First I would like to explain how exactly we are using this driver when LPSS 
UART is used for debug messages:

1. LPSS UART is a PCI device(although it can be put into hidden mode where 
standard PCI enumerator doesn't see it, this is the mode we use for debug) 
integrated in a chipset.
2. PciSioSerialDxe driver will be placed in apriori section of the DXE FW to 
ensure it is loaded early the same goes for a special platform specific driver.
3. During EarlyDxe platform specific driver setup LPSS UART and install 
PCI_IO_PROTOCOL and DEVICE_PATH_PROTOCOL instance for LPSS UART. Setup includes 
assigning MMIO, enabling memory path to LPSS UART etc.
4. Next platform specific module will call connect controller on a handle with 
installed PCI_IO_PROTOCOL and DEVICE_PATH_PROTOCOL. Note that it will only 
connect LPSS UART(and any other critical device). It will not connect entire 
system. In fact connecting entire system is not possible as majority of other 
PCI drivers(including PciBus) are not loaded at this point.
5. PciSioSerialDxe performs normal binding flow at this point and produces 
SERIAL_IO_PROTOCOL
6. When other modules call DEBUG() macro our DebugLib will try to locate that 
SERIAL_IO_PROTOCOL and if located print over it. NOTE: there is no additional 
depex introduced to modules that use debug lib. If protocol is not present 
debug will simply not happen.

Next I want to go broadly over concerns raised in this thread:

*1. UEFI driver model violation*

To be honest this is the first time I am hearing that DXE_DRIVER shouldn't or 
can't install EFI_DRIVER_BINDING_PROTOCOL or use PCI_IO_PROTOCOL. I checked in 
PI specification to see whether it places any restrictions on DXE_DRIVERS and 
the protocols it can consume/produce and it seems like it doesn't. In fact it 
explicitly states that DXE drivers can be UEFI driver model compliant.

from: https://uefi.org/specs/PI/1.8/V2_DXE_Drivers.html#dxe-drivers

As for UEFI driver writes guide I really don't see any restrictions placed on 
DXE drivers in this spec, it seems to be mostly focused on describing types of 
UEFI drivers and their typical behavior.

*2. Rewrite the change so that it doesn't use PCI_IO_PROTOCOL and driver 
binding*

While possible I think this is a really bad idea that doesn't provide much 
value and only introduces additional interfaces for edk2 community to maintain.

- Replacing PCI_IO_PROTOCOL with PciSegment and friends would still require to 
pass information such as BDF, MMIO and mechanism to enable memory decode. So we 
still need some protocol interface. We could potentially drop PCI_IO entirely 
and instead say if you are in early DXE use EFI_SIO_PROTOCOL, but that one is 
less robust than PCI_IO. Note that in our implementation we do not require full 
PCI enumeration since LPSS UART is placed outside of the main PCI 
tree(situation is somewhat similar to IncompatiblePciDeviceSupport.c in EDK2).

- Rewriting driver binding introduces additional cost without any real benefit 
I believe. Having driver binding allows the platform to call ConnectController 
when it is finished initializing enough of the HW so that UART can work. 
Dropping driver binding and instead doing everything in entry point would 
require depending on driver dispatch order or on some additional protocol which 
would be placed in depex section of PciSioSerialDxe and installed by platform 
driver. It would also complicate the way in which we would support multiple 
UART devices which can be ready to operate on different stages in boot.

- Other drawbacks - if we have completely separate entry point for DXE driver 
we need to keep 2 EFI modules in flash - 1 DXE only UART driver and 2nd UEFI 
only UART driver. As it is now we can simply keep the DXE_DRIVER instance in 
flash and it supports both early UARTS that are used for debug and late UARTS 
that are used for console redirection.

Thanks,
Mateusz


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[edk2-devel] [PATCHv2 2/2] MdePkg/Test: Add DevicePathLib host test module

[Albecki, Mateusz]

This commit adds host-based unit tests for device path lib.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 

Signed-off-by: Mateusz Albecki 
---
 MdePkg/MdePkg.ci.yaml |   5 +-
 MdePkg/Test/MdePkgHostTest.dsc|   2 +
 .../Library/DevicePathLib/TestDevicePathLib.c | 638 ++
 .../Library/DevicePathLib/TestDevicePathLib.h |  26 +
 .../DevicePathLib/TestDevicePathLibHost.inf   |  33 +
 .../TestDevicePathStringConversions.c | 370 ++
 6 files changed, 1073 insertions(+), 1 deletion(-)
 create mode 100644 
MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.c
 create mode 100644 
MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.h
 create mode 100644 
MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLibHost.inf
 create mode 100644 
MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathStringConversions.c

diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index c3faf4913d..45f4fb537b 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -74,7 +74,10 @@
 "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c",
 "Library/BaseFdtLib",
 "Library/MipiSysTLib/mipi_syst.h",
-"Include/Register/Amd/SmramSaveStateMap.h"
+"Include/Register/Amd/SmramSaveStateMap.h",
+"Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.c",
+"Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.h",
+
"Test/UnitTest/Library/DevicePathLib/TestDevicePathStringConversions.c"
 ]
 },
 ## options defined ci/Plugin/CompilerPlugin
diff --git a/MdePkg/Test/MdePkgHostTest.dsc b/MdePkg/Test/MdePkgHostTest.dsc
index 529ea69024..b92b564d43 100644
--- a/MdePkg/Test/MdePkgHostTest.dsc
+++ b/MdePkg/Test/MdePkgHostTest.dsc
@@ -21,6 +21,7 @@
 
 [LibraryClasses]
   SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf
 
 [Components]
   #
@@ -29,6 +30,7 @@
   MdePkg/Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLibHost.inf
   MdePkg/Test/UnitTest/Library/BaseLib/BaseLibUnitTestsHost.inf
   MdePkg/Test/GoogleTest/Library/BaseSafeIntLib/GoogleTestBaseSafeIntLib.inf
+  MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLibHost.inf
 
   #
   # Build HOST_APPLICATION Libraries
diff --git a/MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.c 
b/MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.c
new file mode 100644
index 00..687497278c
--- /dev/null
+++ b/MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.c
@@ -0,0 +1,638 @@
+/** @file
+  UEFI OS based application for unit testing the DevicePathLib.
+
+  Copyright (c) 2023, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "TestDevicePathLib.h"
+
+#define UNIT_TEST_NAME "DevicePathLib Unit Test Application"
+#define UNIT_TEST_VERSION  "0.1"
+
+typedef struct {
+  ACPI_HID_DEVICE_PATHAcpiPath;
+  PCI_DEVICE_PATH PciPathRootPort;
+  PCI_DEVICE_PATH PciPathEndPoint;
+  USB_DEVICE_PATH UsbPath;
+  EFI_DEVICE_PATH_PROTOCOLEnd;
+} TEST_COMPLEX_DEVICE_PATH;
+
+GLOBAL_REMOVE_IF_UNREFERENCED TEST_COMPLEX_DEVICE_PATH  mComplexDevicePath = {
+  { // ACPI device path with root bridge EISA_PNP_ID
+{
+  ACPI_DEVICE_PATH,
+  ACPI_DP,
+  {
+(UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+(UINT8)((sizeof (ACPI_HID_DEVICE_PATH)) >> 8)
+  }
+},
+EISA_PNP_ID (0x0A03),
+0
+  },
+  { // PCI device path - root port (0x2:0x0)
+{
+  HARDWARE_DEVICE_PATH,
+  HW_PCI_DP,
+  {
+(UINT8)(sizeof (PCI_DEVICE_PATH)),
+(UINT8)((sizeof (PCI_DEVICE_PATH)) >> 8)
+  }
+},
+0x2,
+0x0
+  },
+  { // PCI device path - endpoint (0x0:0x0)
+{
+  HARDWARE_DEVICE_PATH,
+  HW_PCI_DP,
+  {
+(UINT8)(sizeof (PCI_DEVICE_PATH)),
+(UINT8)((sizeof (PCI_DEVICE_PATH)) >> 8)
+  }
+},
+0x0,
+0x0
+  },
+  { // USB interface
+{
+  MESSAGING_DEVICE_PATH,
+  MSG_USB_DP,
+  {
+(UINT8)(sizeof (USB_DEVICE_PATH)),
+(UINT8)((sizeof (USB_CLASS_DEVICE_PATH)) >> 8)
+  }
+},
+0,
+2
+  },
+  {
+END_DEVICE_PATH_TYPE,
+END_ENTIRE_DEVICE_PATH_SUBTYPE,
+{
+  (UINT8)(sizeof (EFI_DEVICE_PATH_PROTOCOL)),
+  (UINT8)((sizeof (EFI_DEVICE_PATH_PROTOCOL)) >> 8)
+}
+  }
+};
+
+CONST GLOBAL_REMOVE_IF_UNREFERENCED CHAR16  *mComplexDevicePathString = 
L"PciRoot(0x0)/Pci(0x0,0x2)/Pci(0x0,0x0)/USB(0x0,0x2)";
+
+CONST GLOBAL_REMOVE_IF_UNREFERENCED CHAR16  *mPciEndPointPathString = 
L"Pci(0x0, 0x0)";
+
+typedef struct {
+  ACPI_HID_DEVICE_PATHAcpiPath;
+  EFI_DEVICE_PATH_PROTOCOLEnd;
+} TEST_SIMPLE_DEVICE_PATH;
+
+GLOBAL_REMOVE_IF_UNREFERENCED TEST_SIMPLE_DEVICE_PATH  mSimpleDevicePath = {
+  { // ACPI device 

[edk2-devel] [PATCHv2 1/2] MdePkg/UefiDevicePathLib: Fix AcpiEx print logic

[Albecki, Mateusz]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4555

Add logic that checks if the code doesn't overflow
ACPI_EXTENDED_HID_DEVICE_PATH node when searching for optional
strings. If the string is not provided in the device path node
default value of "\0" is used.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 

Signed-off-by: Mateusz Albecki 
---
 .../UefiDevicePathLib/DevicePathToText.c  | 69 +++
 1 file changed, 42 insertions(+), 27 deletions(-)

diff --git a/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c 
b/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c
index dd90dfa58e..bd8d1de201 100644
--- a/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c
+++ b/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c
@@ -418,23 +418,38 @@ DevPathToTextAcpiEx (
   )
 {
   ACPI_EXTENDED_HID_DEVICE_PATH  *AcpiEx;
-  CHAR8  *HIDStr;
-  CHAR8  *UIDStr;
-  CHAR8  *CIDStr;
   CHAR16 HIDText[11];
   CHAR16 CIDText[11];
-
-  AcpiEx = DevPath;
-  HIDStr = (CHAR8 *)(((UINT8 *)AcpiEx) + sizeof 
(ACPI_EXTENDED_HID_DEVICE_PATH));
-  UIDStr = HIDStr + AsciiStrLen (HIDStr) + 1;
-  CIDStr = UIDStr + AsciiStrLen (UIDStr) + 1;
+  UINTN  CurrentLength;
+  CHAR8  *CurrentPos;
+  UINTN  NextStringOffset;
+  CHAR8  *Strings[3];
+  CONST UINT8HidStrIndex = 0;
+  CONST UINT8UidStrIndex = 1;
+  CONST UINT8CidStrIndex = 2;
+  UINT8  StrIndex;
+
+  AcpiEx   = DevPath;
+  Strings[HidStrIndex] = NULL;
+  Strings[UidStrIndex] = NULL;
+  Strings[CidStrIndex] = NULL;
+  CurrentLength= sizeof (ACPI_EXTENDED_HID_DEVICE_PATH);
+  CurrentPos   = (CHAR8 *)(((UINT8 *)AcpiEx) + sizeof 
(ACPI_EXTENDED_HID_DEVICE_PATH));
+  StrIndex = 0;
+  while (CurrentLength < AcpiEx->Header.Length[0] && StrIndex < ARRAY_SIZE 
(Strings)) {
+Strings[StrIndex] = CurrentPos;
+NextStringOffset  = AsciiStrLen (CurrentPos) + 1;
+CurrentLength+= NextStringOffset;
+CurrentPos   += NextStringOffset;
+StrIndex++;
+  }
 
   if (DisplayOnly) {
 if ((EISA_ID_TO_NUM (AcpiEx->HID) == 0x0A03) ||
 ((EISA_ID_TO_NUM (AcpiEx->CID) == 0x0A03) && (EISA_ID_TO_NUM 
(AcpiEx->HID) != 0x0A08)))
 {
-  if (AcpiEx->UID == 0) {
-UefiDevicePathLibCatPrint (Str, L"PciRoot(%a)", UIDStr);
+  if (Strings[UidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"PciRoot(%a)", Strings[UidStrIndex]);
   } else {
 UefiDevicePathLibCatPrint (Str, L"PciRoot(0x%x)", AcpiEx->UID);
   }
@@ -443,8 +458,8 @@ DevPathToTextAcpiEx (
 }
 
 if ((EISA_ID_TO_NUM (AcpiEx->HID) == 0x0A08) || (EISA_ID_TO_NUM 
(AcpiEx->CID) == 0x0A08)) {
-  if (AcpiEx->UID == 0) {
-UefiDevicePathLibCatPrint (Str, L"PcieRoot(%a)", UIDStr);
+  if (Strings[UidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"PcieRoot(%a)", Strings[UidStrIndex]);
   } else {
 UefiDevicePathLibCatPrint (Str, L"PcieRoot(0x%x)", AcpiEx->UID);
   }
@@ -475,7 +490,10 @@ DevPathToTextAcpiEx (
 (AcpiEx->CID >> 16) & 0x
 );
 
-  if ((*HIDStr == '\0') && (*CIDStr == '\0') && (*UIDStr != '\0')) {
+  if (((Strings[HidStrIndex] != NULL) && (*Strings[HidStrIndex] == '\0')) &&
+  ((Strings[CidStrIndex] != NULL) && (*Strings[CidStrIndex] == '\0')) &&
+  ((Strings[UidStrIndex] != NULL) && (*Strings[UidStrIndex] != '\0')))
+  {
 //
 // use AcpiExp()
 //
@@ -484,7 +502,7 @@ DevPathToTextAcpiEx (
 Str,
 L"AcpiExp(%s,0,%a)",
 HIDText,
-UIDStr
+Strings[UidStrIndex]
 );
 } else {
   UefiDevicePathLibCatPrint (
@@ -492,28 +510,25 @@ DevPathToTextAcpiEx (
 L"AcpiExp(%s,%s,%a)",
 HIDText,
 CIDText,
-UIDStr
+Strings[UidStrIndex]
 );
 }
   } else {
 if (DisplayOnly) {
-  //
-  // display only
-  //
-  if (AcpiEx->HID == 0) {
-UefiDevicePathLibCatPrint (Str, L"AcpiEx(%a,", HIDStr);
+  if (Strings[HidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"AcpiEx(%a,", Strings[HidStrIndex]);
   } else {
 UefiDevicePathLibCatPrint (Str, L"AcpiEx(%s,", HIDText);
   }
 
-  if (AcpiEx->CID == 0) {
-UefiDevicePathLibCatPrint (Str, L"%a,", CIDStr);
+  if (Strings[CidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"%a,", Strings[CidStrIndex]);
   } else {
 UefiDevicePathLibCatPrint (Str, L"%s,", CIDText);
   }
 
-  if (AcpiEx->UID == 0) {
-UefiDevicePathLibCatPrint (Str, L"%a)", UIDStr);
+  if (Strings[UidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"%a)", Strings[UidStrIndex]);
   } else {
 

[edk2-devel] [PATCHv2 0/2] MdePkg/UefiDevicePathLib: Fix buffer overflows in DevPathToTextAcpiEx

[Albecki, Mateusz]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4555

Github PR: https://github.com/tianocore/edk2/pull/4865

Fix for buffer overlows that arise in DevPathToTextAcpiEx when device path node
producer doesn't specify all of the optional strings.

Changes in v2:
- Fix AcpiExp print logic that got broken in V1
- Don't pass NULL string to print function

Tests:
- Booted the platform and confirmed that platform doesn't hang when special 
pool is enabled
  (special pool detects accesses outside of allocated pool)
- Examined the output of the DevPathToTextAcpiEx, here are some example strings:
  AcpiEx(@@@,@@@,0x0,INTC10E7,,) - this device path doesn't specify 
UIDSTR and CIDSTR
  PciRoot(0x0)/AcpiEx(UAR0002,@@@,0x0,UART2,,) - this device path specifies 
empty UIDSTR and CIDSTR
- Unit tests added in second patch are passing

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 

Mateusz Albecki (2):
  MdePkg/UefiDevicePathLib: Fix AcpiEx print logic
  MdePkg/Test: Add DevicePathLib host test module

 .../UefiDevicePathLib/DevicePathToText.c  |  69 +-
 MdePkg/MdePkg.ci.yaml |   5 +-
 MdePkg/Test/MdePkgHostTest.dsc|   2 +
 .../Library/DevicePathLib/TestDevicePathLib.c | 638 ++
 .../Library/DevicePathLib/TestDevicePathLib.h |  26 +
 .../DevicePathLib/TestDevicePathLibHost.inf   |  33 +
 .../TestDevicePathStringConversions.c | 370 ++
 7 files changed, 1115 insertions(+), 28 deletions(-)
 create mode 100644 
MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.c
 create mode 100644 
MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.h
 create mode 100644 
MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathLibHost.inf
 create mode 100644 
MdePkg/Test/UnitTest/Library/DevicePathLib/TestDevicePathStringConversions.c

-- 
2.39.2

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handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
moze zawierac informacje poufne. W razie przypadkowego otrzymania tej 
wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; 
jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
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Re: [edk2-devel] [PATCH 1/1] MdePkg/UefiDevicePathLib: Fix AcpiEx print logic

[Albecki, Mateusz]

This patch has a bug related to AcpiExp device path. I will resend the fixed 
version along with unit tests to cover AcpiExp cases.

Thanks,
Mateusz


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[edk2-devel] [PATCH 1/1] MdePkg/UefiDevicePathLib: Fix AcpiEx print logic

[Albecki, Mateusz]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4555

Add logic that checks if the code doesn't overflow
ACPI_EXTENDED_HID_DEVICE_PATH node when searching for optional
strings. If the string is not provided in the device path node
default value of "\0" is used.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 

Signed-off-by: Mateusz Albecki 
---
 .../UefiDevicePathLib/DevicePathToText.c  | 66 +++
 1 file changed, 39 insertions(+), 27 deletions(-)

diff --git a/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c 
b/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c
index dd90dfa58e..5012dfef6b 100644
--- a/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c
+++ b/MdePkg/Library/UefiDevicePathLib/DevicePathToText.c
@@ -418,23 +418,38 @@ DevPathToTextAcpiEx (
   )
 {
   ACPI_EXTENDED_HID_DEVICE_PATH  *AcpiEx;
-  CHAR8  *HIDStr;
-  CHAR8  *UIDStr;
-  CHAR8  *CIDStr;
   CHAR16 HIDText[11];
   CHAR16 CIDText[11];
-
-  AcpiEx = DevPath;
-  HIDStr = (CHAR8 *)(((UINT8 *)AcpiEx) + sizeof 
(ACPI_EXTENDED_HID_DEVICE_PATH));
-  UIDStr = HIDStr + AsciiStrLen (HIDStr) + 1;
-  CIDStr = UIDStr + AsciiStrLen (UIDStr) + 1;
+  UINTN  CurrentLength;
+  CHAR8  *CurrentPos;
+  UINTN  NextStringOffset;
+  CHAR8  *Strings[3];
+  CONST UINT8HidStrIndex = 0;
+  CONST UINT8UidStrIndex = 1;
+  CONST UINT8CidStrIndex = 2;
+  UINT8  StrIndex;
+
+  AcpiEx   = DevPath;
+  Strings[HidStrIndex] = NULL;
+  Strings[UidStrIndex] = NULL;
+  Strings[CidStrIndex] = NULL;
+  CurrentLength= sizeof (ACPI_EXTENDED_HID_DEVICE_PATH);
+  CurrentPos   = (CHAR8 *)(((UINT8 *)AcpiEx) + sizeof 
(ACPI_EXTENDED_HID_DEVICE_PATH));
+  StrIndex = 0;
+  while (CurrentLength < AcpiEx->Header.Length[0] && StrIndex < ARRAY_SIZE 
(Strings)) {
+Strings[StrIndex] = CurrentPos;
+NextStringOffset  = AsciiStrLen (CurrentPos) + 1;
+CurrentLength+= NextStringOffset;
+CurrentPos   += NextStringOffset;
+StrIndex++;
+  }
 
   if (DisplayOnly) {
 if ((EISA_ID_TO_NUM (AcpiEx->HID) == 0x0A03) ||
 ((EISA_ID_TO_NUM (AcpiEx->CID) == 0x0A03) && (EISA_ID_TO_NUM 
(AcpiEx->HID) != 0x0A08)))
 {
-  if (AcpiEx->UID == 0) {
-UefiDevicePathLibCatPrint (Str, L"PciRoot(%a)", UIDStr);
+  if (Strings[UidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"PciRoot(%a)", Strings[UidStrIndex]);
   } else {
 UefiDevicePathLibCatPrint (Str, L"PciRoot(0x%x)", AcpiEx->UID);
   }
@@ -443,8 +458,8 @@ DevPathToTextAcpiEx (
 }
 
 if ((EISA_ID_TO_NUM (AcpiEx->HID) == 0x0A08) || (EISA_ID_TO_NUM 
(AcpiEx->CID) == 0x0A08)) {
-  if (AcpiEx->UID == 0) {
-UefiDevicePathLibCatPrint (Str, L"PcieRoot(%a)", UIDStr);
+  if (Strings[UidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"PcieRoot(%a)", Strings[UidStrIndex]);
   } else {
 UefiDevicePathLibCatPrint (Str, L"PcieRoot(0x%x)", AcpiEx->UID);
   }
@@ -475,7 +490,7 @@ DevPathToTextAcpiEx (
 (AcpiEx->CID >> 16) & 0x
 );
 
-  if ((*HIDStr == '\0') && (*CIDStr == '\0') && (*UIDStr != '\0')) {
+  if ((Strings[HidStrIndex] == NULL) && (Strings[CidStrIndex] == NULL) && 
(Strings[UidStrIndex] != NULL)) {
 //
 // use AcpiExp()
 //
@@ -484,7 +499,7 @@ DevPathToTextAcpiEx (
 Str,
 L"AcpiExp(%s,0,%a)",
 HIDText,
-UIDStr
+Strings[UidStrIndex]
 );
 } else {
   UefiDevicePathLibCatPrint (
@@ -492,28 +507,25 @@ DevPathToTextAcpiEx (
 L"AcpiExp(%s,%s,%a)",
 HIDText,
 CIDText,
-UIDStr
+Strings[UidStrIndex]
 );
 }
   } else {
 if (DisplayOnly) {
-  //
-  // display only
-  //
-  if (AcpiEx->HID == 0) {
-UefiDevicePathLibCatPrint (Str, L"AcpiEx(%a,", HIDStr);
+  if (Strings[HidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"AcpiEx(%a,", Strings[HidStrIndex]);
   } else {
 UefiDevicePathLibCatPrint (Str, L"AcpiEx(%s,", HIDText);
   }
 
-  if (AcpiEx->CID == 0) {
-UefiDevicePathLibCatPrint (Str, L"%a,", CIDStr);
+  if (Strings[CidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"%a,", Strings[CidStrIndex]);
   } else {
 UefiDevicePathLibCatPrint (Str, L"%s,", CIDText);
   }
 
-  if (AcpiEx->UID == 0) {
-UefiDevicePathLibCatPrint (Str, L"%a)", UIDStr);
+  if (Strings[UidStrIndex] != NULL) {
+UefiDevicePathLibCatPrint (Str, L"%a)", Strings[UidStrIndex]);
   } else {
 UefiDevicePathLibCatPrint (Str, L"0x%x)", AcpiEx->UID);
   }
@@ -524,9 +536,9 @@ DevPathToTextAcpiEx (
 HIDText,
 CIDText,

[edk2-devel] [PATCH 0/1] MdePkg/UefiDevicePathLib: Fix buffer overflows in DevPathToTextAcpiEx

[Albecki, Mateusz]

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4555

Github PR: https://github.com/tianocore/edk2/pull/4865

Fix for buffer overlows that arise in DevPathToTextAcpiEx when device path node
producer doesn't specify all of the optional strings.

Tests:
- Booted the platform and confirmed that platform doesn't hang when special 
pool is enabled
  (special pool detects accesses outside of allocated pool)
- Examined the output of the DevPathToTextAcpiEx, here are some example strings:
  AcpiEx(@@@,@@@,0x0,INTC10E7,,) - this device path doesn't specify 
UIDSTR and CIDSTR
  PciRoot(0x0)/AcpiEx(UAR0002,@@@,0x0,UART2,,) - this device path specifies 
empty UIDSTR and CIDSTR

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 

Mateusz Albecki (1):
  MdePkg/UefiDevicePathLib: Fix AcpiEx print logic

 .../UefiDevicePathLib/DevicePathToText.c  | 64 +++
 1 file changed, 37 insertions(+), 27 deletions(-)

-- 
2.39.2

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z 
dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach 
handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
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[edk2-devel] [edk2-staging][PATCH 1/1] BaseTools/Fmmt: Fix GCC warnings

[Albecki, Mateusz]

GCC is throwing a warning during BaseTools compilation which leads
to build errors when Wall is set. This commit removes all conditions
which are always true/false(Waddress warning) and wraps one snprintf
in compiler pragma to disable format-truncation warning.

Cc: Bob Feng 
Cc: Liming Gao 
Cc: Yuwei Chen 
Signed-off-by: Mateusz Albecki 
---
 BaseTools/Source/C/BfmLib/BfmLib.c| 36 +--
 BaseTools/Source/C/FCE/BinaryParse.c  |  3 ++
 BaseTools/Source/C/FCE/IfrParse.c | 24 -
 .../Source/C/FMMT/FirmwareModuleManagement.c  |  8 ++---
 BaseTools/Source/C/FMMT/FmmtLib.c | 20 +--
 5 files changed, 31 insertions(+), 60 deletions(-)

diff --git a/BaseTools/Source/C/BfmLib/BfmLib.c 
b/BaseTools/Source/C/BfmLib/BfmLib.c
index c247cc8e1d..14d29077c8 100644
--- a/BaseTools/Source/C/BfmLib/BfmLib.c
+++ b/BaseTools/Source/C/BfmLib/BfmLib.c
@@ -3738,18 +3738,16 @@ LibLocateFvViaFvId (
   FvIndex1 = (UINT8) atoi (FvId + 2);
 
   while (FvInFd != NULL) {
-if (((*FvInFd)->FvName) != NULL) {
-  FvIndex2 = (UINT8) atoi ((*FvInFd)->FvName + 2);
+FvIndex2 = (UINT8) atoi ((*FvInFd)->FvName + 2);
 
-  if ((FvIndex2 <= FvIndex1) && (((*FvInFd)->FvLevel + FvIndex2) -1 >= 
FvIndex1)) {
-FvFoundFlag = TRUE;
-break;
-  }
-  if ((*FvInFd)->FvNext == 0) {
-break;
-  }
-  *FvInFd = (*FvInFd)->FvNext;
+if ((FvIndex2 <= FvIndex1) && (((*FvInFd)->FvLevel + FvIndex2) -1 >= 
FvIndex1)) {
+  FvFoundFlag = TRUE;
+  break;
+}
+if ((*FvInFd)->FvNext == 0) {
+  break;
 }
+*FvInFd = (*FvInFd)->FvNext;
   }
 
   //
@@ -4292,18 +4290,16 @@ LibLocateBfv(
   *FvInFd = FdData->Fv;
 
   while (FvInFd != NULL) {
-if (((*FvInFd)->FvName) != NULL) {
-  FvIndex2 = (UINT8) atoi ((*FvInFd)->FvName + 2);
+FvIndex2 = (UINT8) atoi ((*FvInFd)->FvName + 2);
 
-  if ((FvIndex2 <= FvIndex1) && (((*FvInFd)->FvLevel + FvIndex2) -1 >= 
FvIndex1)) {
-FvFoundFlag = TRUE;
-break;
-  }
-  if ((*FvInFd)->FvNext == 0) {
-break;
-  }
-  *FvInFd = (*FvInFd)->FvNext;
+if ((FvIndex2 <= FvIndex1) && (((*FvInFd)->FvLevel + FvIndex2) -1 >= 
FvIndex1)) {
+  FvFoundFlag = TRUE;
+  break;
+}
+if ((*FvInFd)->FvNext == 0) {
+  break;
 }
+*FvInFd = (*FvInFd)->FvNext;
   }
 
   //
diff --git a/BaseTools/Source/C/FCE/BinaryParse.c 
b/BaseTools/Source/C/FCE/BinaryParse.c
index 6854d546ac..def8089ae4 100644
--- a/BaseTools/Source/C/FCE/BinaryParse.c
+++ b/BaseTools/Source/C/FCE/BinaryParse.c
@@ -1244,7 +1244,10 @@ Done:
 Status = EFI_ABORTED;
 goto Done;
   }
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wformat-truncation"
   snprintf (FileNameArry, 300, "%s%c%s", FolderName, OS_SEP, 
pDirent->d_name);
+#pragma GCC diagnostic pop
   FfsFile = fopen (FileNameArry, "rb");
   Status = ReadFfsHeader (FfsFile, (UINT32 *));
   if (EFI_ERROR (Status)) {
diff --git a/BaseTools/Source/C/FCE/IfrParse.c 
b/BaseTools/Source/C/FCE/IfrParse.c
index ba7320f14c..e47afaef66 100644
--- a/BaseTools/Source/C/FCE/IfrParse.c
+++ b/BaseTools/Source/C/FCE/IfrParse.c
@@ -3936,11 +3936,6 @@ StringPrintormSetTitle (
 FormSet->Guid.Data4[5],FormSet->Guid.Data4[6],
 FormSet->Guid.Data4[7]);
   StringPrint("\n");
-
-  if (&(FormSet->EnUsStringList) == NULL && VarDefaultName != NULL && 
FormSet->FormSetTitle != 0) {
-free (VarDefaultName);
-VarDefaultName = NULL;
-  }
 }
 
 /**
@@ -4019,10 +4014,6 @@ PrintOneOfOptions (
 
 LogUnicodeString (VarDefaultName);
 StringPrint("\n");
-if (&(FormSet->EnUsStringList) == NULL && VarDefaultName != NULL && 
Option->Text != 0) {
-  free (VarDefaultName);
-  VarDefaultName = NULL;
-}
 Link = GetNextNode (>OptionListHead, Link);
   }
   return Status;
@@ -4061,12 +4052,6 @@ StringPrintormTitle (
 
   LogUnicodeString (VarDefaultName);
   StringPrint("\n");
-
-  if (&(FormSet->EnUsStringList) == NULL && VarDefaultName != NULL && 
Form->FormTitle != 0) {
-free (VarDefaultName);
-VarDefaultName  = NULL;
-  }
-
 }
 
 /**
@@ -4513,11 +4498,6 @@ PrintQuestion (
 break;
   }
 
-  if (&(FormSet->EnUsStringList) == NULL & != NULL && 
Question->Prompt != 0) {
-free (VarDefaultName);
-VarDefaultName = NULL;
-  }
-
   if (PrintOrNot && Question->Storage) {
 StringPrint("// size = 0x%x", Question->StorageWidth);
 StringPrint("\n// offset = 0x%x", Question->VarStoreInfo.VarOffset);
@@ -4545,10 +4525,6 @@ PrintQuestion (
 assert (!EFI_ERROR (Status));
 LogUnicodeString (VarDefaultName);
 StringPrint("\n");
-if (&(FormSet->EnUsStringList) == NULL & != NULL && 
Question->Help != 0) {
-  free (VarDefaultName);
-  VarDefaultName = NULL;
-}
   }
 
 }
diff --git a/BaseTools/Source/C/FMMT/FirmwareModuleManagement.c 
b/BaseTools/Source/C/FMMT/FirmwareModuleManagement.c
index 38056153fb..ff4e555881 100644
--- 

[edk2-devel] [PATCHv2 1/1] MdeModulePkg/Ahci: Skip retry for non-transient errors

[Albecki, Mateusz]

Currently AHCI driver will try to retry all failed packets
regardless of the failure cause. This is a problem in password
unlock flow where number of password retries is tracked by the
device. If user passes a wrong password Ahci driver will try
to send the wrong password multiple times which will exhaust
number of password retries and force the user to restart the
machine. This commit introduces a logic to check for the cause
of packet failure and only retry packets which failed due to
transient conditions on the link. With this patch only packets for
which CRC error is flagged are retried.

Cc: Hao A Wu 
Cc: Ray Ni 
Cc: Hunter Chang 
Cc: Baraneedharan Anbazhagan 

Signed-off-by: Mateusz Albecki 
---
 .../Bus/Ata/AtaAtapiPassThru/AhciMode.c   | 71 +--
 .../Bus/Ata/AtaAtapiPassThru/AhciMode.h   |  3 +-
 2 files changed, 69 insertions(+), 5 deletions(-)

diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c 
b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
index 06c4a3e052..c0c8ffbd9e 100644
--- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
+++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
@@ -737,12 +737,68 @@ AhciRecoverPortError (
 Status = AhciResetPort (PciIo, Port);
 if (EFI_ERROR (Status)) {
   DEBUG ((DEBUG_ERROR, "Failed to reset the port %d\n", Port));
+  return EFI_DEVICE_ERROR;
 }
   }
 
   return EFI_SUCCESS;
 }
 
+/**
+  This function will check if the failed command should be retired. Only error
+  conditions which are a result of transient conditions on a link(either to 
system or to device).
+
+  @param[in] PciIoPointer to AHCI controller PciIo.
+  @param[in] Port SATA port index on which to check.
+
+  @retval TRUE   Command failure was caused by transient condition and should 
be retried
+  @retval FALSE  Command should not be retried
+**/
+BOOLEAN
+AhciShouldCmdBeRetried (
+  IN EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN UINT8Port
+  )
+{
+  UINT32  Offset;
+  UINT32  PortInterrupt;
+  UINT32  Serr;
+  UINT32  Tfd;
+
+  Offset= EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + 
EFI_AHCI_PORT_IS;
+  PortInterrupt = AhciReadReg (PciIo, Offset);
+  Offset= EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + 
EFI_AHCI_PORT_SERR;
+  Serr  = AhciReadReg (PciIo, Offset);
+  Offset= EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + 
EFI_AHCI_PORT_TFD;
+  Tfd   = AhciReadReg (PciIo, Offset);
+
+  //
+  // This can occur if there was a CRC error on a path from system memory to
+  // host controller.
+  //
+  if (PortInterrupt & EFI_AHCI_PORT_IS_HBDS) {
+return TRUE;
+//
+// This can occur if there was a CRC error detected by host during 
communication
+// with the device
+//
+  } else if ((PortInterrupt & (EFI_AHCI_PORT_IS_IFS | EFI_AHCI_PORT_IS_INFS)) 
&&
+ (Serr & EFI_AHCI_PORT_SERR_CRCE))
+  {
+return TRUE;
+//
+// This can occur if there was a CRC error detected by device during 
communication
+// with the host. Device returns error status to host with D2H FIS.
+//
+  } else if ((PortInterrupt & EFI_AHCI_PORT_IS_TFES) &&
+ (Tfd & EFI_AHCI_PORT_TFD_ERR_INT_CRC))
+  {
+return TRUE;
+  }
+
+  return FALSE;
+}
+
 /**
   Checks if specified FIS has been received.
 
@@ -950,6 +1006,7 @@ AhciPioTransfer (
   UINT32 PrdCount;
   UINT32 Retry;
   EFI_STATUS RecoveryStatus;
+  BOOLEANDoRetry;
 
   if (Read) {
 Flag = EfiPciIoOperationBusMasterWrite;
@@ -1027,8 +1084,9 @@ AhciPioTransfer (
 
 if (Status == EFI_DEVICE_ERROR) {
   DEBUG ((DEBUG_ERROR, "PIO command failed at retry %d\n", Retry));
+  DoRetry= AhciShouldCmdBeRetried (PciIo, Port); // needs to be 
called before error recovery
   RecoveryStatus = AhciRecoverPortError (PciIo, Port);
-  if (EFI_ERROR (RecoveryStatus)) {
+  if (!DoRetry || EFI_ERROR (RecoveryStatus)) {
 break;
   }
 } else {
@@ -1124,6 +1182,7 @@ AhciDmaTransfer (
   EFI_TPLOldTpl;
   UINT32 Retry;
   EFI_STATUS RecoveryStatus;
+  BOOLEANDoRetry;
 
   Map   = NULL;
   PciIo = Instance->PciIo;
@@ -1222,8 +1281,9 @@ AhciDmaTransfer (
   Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
   if (Status == EFI_DEVICE_ERROR) {
 DEBUG ((DEBUG_ERROR, "DMA command failed at retry: %d\n", Retry));
+DoRetry= AhciShouldCmdBeRetried (PciIo, Port); // needs to be 
called before error recovery
 RecoveryStatus = AhciRecoverPortError (PciIo, Port);
-if (EFI_ERROR (RecoveryStatus)) {
+if (!DoRetry || EFI_ERROR (RecoveryStatus)) {
   break;
 }
   } else {
@@ -1263,6 +1323,7 @@ AhciDmaTransfer (
   Status = AhciCheckFisReceived (PciIo, Port, SataFisD2H);
   if (Status 

[edk2-devel] [PATCHv2 0/1] MdeModulePkg/Ahci: Skip retry for non-transient errors

[Albecki, Mateusz]

Fix for the recovery logic which causes hdd unlock to fail if user supplies 
incorrect
password. Every failed packet used to be recovered which is causing the
incorrect password to be tried multiple times. This patch series fixes the logic
to only retry commands that failed due to CRC error.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4011

Github pull: https://github.com/tianocore/edk2/pull/4157

Tests:
- tested basic linux boot from AHCI on qemu
- tested basic linux boot from AHCI on custom qemu which will fail 50% of the 
DMA commands with CRC error.
  Observed that all of the packets that failed were successfully retried. 
Custom Qemu: https://github.com/matalbec/qemu/tree/sata_dma_50p_fail
- additionally Hunter Chang tested and confirmed that the password issue is no 
longer observed.

Changes in V2:
- Fixed code formatting issues

Cc: Hao A Wu 
Cc: Ray Ni 
Cc: Hunter Chang 
Cc: Baraneedharan Anbazhagan 

Mateusz Albecki (1):
  MdeModulePkg/Ahci: Skip retry for non-transient errors

 .../Bus/Ata/AtaAtapiPassThru/AhciMode.c   | 71 +--
 .../Bus/Ata/AtaAtapiPassThru/AhciMode.h   |  3 +-
 2 files changed, 69 insertions(+), 5 deletions(-)

-- 
2.39.1.windows.1

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z 
dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach 
handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
moze zawierac informacje poufne. W razie przypadkowego otrzymania tej 
wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; 
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Re: [edk2-devel] [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for non-transient errors

[Albecki, Mateusz]

Seems like a code formatting issue. I will address it tomorrow.

Regards,
Mateusz


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[edk2-devel] [PATCH 1/1] MdeModulePkg/Ahci: Skip retry for non-transient errors

[Albecki, Mateusz]

bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4011

Currently AHCI driver will try to retry all failed packets
regardless of the failure cause. This is a problem in password
unlock flow where number of password retries is tracked by the
device. If user passes a wrong password Ahci driver will try
to send the wrong password multiple times which will exhaust
number of password retries and force the user to restart the
machine. This commit introduces a logic to check for the cause
of packet failure and only retry packets which failed due to
transient conditions on the link. With this patch only packets for
which CRC error is flagged are retried.

Cc: Hao A Wu 
Cc: Ray Ni 
Cc: Hunter Chang 

Signed-off-by: Mateusz Albecki 
---
 .../Bus/Ata/AtaAtapiPassThru/AhciMode.c   | 69 +--
 .../Bus/Ata/AtaAtapiPassThru/AhciMode.h   |  3 +-
 2 files changed, 67 insertions(+), 5 deletions(-)

diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c 
b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
index 06c4a3e052..90c9b4e69d 100644
--- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
+++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
@@ -737,12 +737,66 @@ AhciRecoverPortError (
 Status = AhciResetPort (PciIo, Port);
 if (EFI_ERROR (Status)) {
   DEBUG ((DEBUG_ERROR, "Failed to reset the port %d\n", Port));
+  return EFI_DEVICE_ERROR;
 }
   }
 
   return EFI_SUCCESS;
 }
 
+/**
+  This function will check if the failed command should be retired. Only error
+  conditions which are a result of transient conditions on a link(either to 
system or to device).
+
+  @param[in] PciIoPointer to AHCI controller PciIo.
+  @param[in] Port SATA port index on which to check.
+
+  @retval TRUE   Command failure was caused by transient condition and should 
be retried
+  @retval FALSE  Command should not be retried
+**/
+BOOLEAN
+AhciShouldCmdBeRetried (
+  IN EFI_PCI_IO_PROTOCOL *PciIo,
+  IN UINT8   Port
+  )
+{
+  UINT32  Offset;
+  UINT32  PortInterrupt;
+  UINT32  Serr;
+  UINT32  Tfd;
+
+  Offset= EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + 
EFI_AHCI_PORT_IS;
+  PortInterrupt = AhciReadReg (PciIo, Offset);
+  Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + 
EFI_AHCI_PORT_SERR;
+  Serr = AhciReadReg (PciIo, Offset);
+  Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + 
EFI_AHCI_PORT_TFD;
+  Tfd = AhciReadReg (PciIo, Offset);
+
+  //
+  // This can occur if there was a CRC error on a path from system memory to
+  // host controller.
+  //
+  if (PortInterrupt & EFI_AHCI_PORT_IS_HBDS) {
+return TRUE;
+  //
+  // This can occur if there was a CRC error detected by host during 
communication
+  // with the device
+  //
+  } else if ((PortInterrupt & (EFI_AHCI_PORT_IS_IFS | EFI_AHCI_PORT_IS_INFS)) 
&&
+ (Serr & EFI_AHCI_PORT_SERR_CRCE)) {
+return TRUE;
+  //
+  // This can occur if there was a CRC error detected by device during 
communication
+  // with the host. Device returns error status to host with D2H FIS.
+  //
+  } else if ((PortInterrupt & EFI_AHCI_PORT_IS_TFES) &&
+ (Tfd & EFI_AHCI_PORT_TFD_ERR_INT_CRC)) {
+return TRUE;
+  }
+
+  return FALSE;
+}
+
 /**
   Checks if specified FIS has been received.
 
@@ -950,6 +1004,7 @@ AhciPioTransfer (
   UINT32 PrdCount;
   UINT32 Retry;
   EFI_STATUS RecoveryStatus;
+  BOOLEANDoRetry;
 
   if (Read) {
 Flag = EfiPciIoOperationBusMasterWrite;
@@ -1027,8 +1082,9 @@ AhciPioTransfer (
 
 if (Status == EFI_DEVICE_ERROR) {
   DEBUG ((DEBUG_ERROR, "PIO command failed at retry %d\n", Retry));
+  DoRetry = AhciShouldCmdBeRetried (PciIo, Port); // needs to be called 
before error recovery
   RecoveryStatus = AhciRecoverPortError (PciIo, Port);
-  if (EFI_ERROR (RecoveryStatus)) {
+  if (!DoRetry || EFI_ERROR (RecoveryStatus)) {
 break;
   }
 } else {
@@ -1124,6 +1180,7 @@ AhciDmaTransfer (
   EFI_TPLOldTpl;
   UINT32 Retry;
   EFI_STATUS RecoveryStatus;
+  BOOLEANDoRetry;
 
   Map   = NULL;
   PciIo = Instance->PciIo;
@@ -1222,8 +1279,9 @@ AhciDmaTransfer (
   Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
   if (Status == EFI_DEVICE_ERROR) {
 DEBUG ((DEBUG_ERROR, "DMA command failed at retry: %d\n", Retry));
+DoRetry = AhciShouldCmdBeRetried (PciIo, Port); // needs to be called 
before error recovery
 RecoveryStatus = AhciRecoverPortError (PciIo, Port);
-if (EFI_ERROR (RecoveryStatus)) {
+if (!DoRetry || EFI_ERROR (RecoveryStatus)) {
   break;
 }
   } else {
@@ -1263,6 +1321,7 @@ AhciDmaTransfer (
   Status = AhciCheckFisReceived (PciIo, Port, SataFisD2H);
   if (Status == EFI_DEVICE_ERROR) {
 

[edk2-devel] [PATCH 0/1] MdeModulePkg/Ahci: Skip retry for non-transient errors

[Albecki, Mateusz]

Fix for the recovery logic which causes hdd unlock to fail if user supplies 
incorrect
password. Every failed packet used to be recovered which is causing the
incorrect password to be tried multiple times. This patch series fixes the logic
to only retry commands that failed due to CRC error.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4011

Github pull: https://github.com/tianocore/edk2/pull/4157

Tests:
- tested basic linux boot from AHCI on qemu
- tested basic linux boot from AHCI on custom qemu which will fail 50% of the 
DMA commands with CRC error.
  Observed that all of the packets that failed were successfully retried. 
Custom Qemu: https://github.com/matalbec/qemu/tree/sata_dma_50p_fail
- additionally Hunter Chang tested and confirmed that the password issue is no 
longer observed.

Cc: Hao A Wu 
Cc: Ray Ni 
Cc: Hunter Chang 

Mateusz Albecki (1):
  MdeModulePkg/Ahci: Skip retry for non-transient errors

 .../Bus/Ata/AtaAtapiPassThru/AhciMode.c   | 69 +--
 .../Bus/Ata/AtaAtapiPassThru/AhciMode.h   |  3 +-
 2 files changed, 67 insertions(+), 5 deletions(-)

-- 
2.39.1.windows.1

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z 
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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg/Ata: Fix command status reporting

[Albecki, Mateusz]

Hello,

I've done some investigation into the password issue and I think I have the 
proposition on how to solve it. The issue arises due to the driver checking the 
PxIS.TFES(task file error status) and if TFES is set it performs recovery 
steps(this is correct according to AHCI spec 6.2.2) and restarts the 
command(this is left up to the SW according to AHCI spec). In the case of 
SECURITY UNLOCK command if the password is incorrect device will set the abort 
bit in ERROR register and error bit in status register which will cause the 
controller to set the PxIS.TFES bit which will  trigger command retires. In 
case of security commands retries are particularly bad since every incorrect 
password unlock attempt is decreasing the retry counter on the device side 
which eventually leads to device locking itself and aborting further unlock 
commands(power cycle is required to recover).

My proposition for a fix is as follows:

1. The logic in AhciRecoverPortError seems to be largely correct. Even if the 
TFES error bit shouldn't necessarily mean that the command should be retried, 
according to AHCI spec when TFES is set controller will enter the ERR:Fatal 
state and PxCMD.CR needs to be restarted. The only thing that we need to change 
in this function is to return EFI_DEVICE_ERROR when the port restart failed(as 
discussed below).
2. We need to add a logic which will decide if the cmd should be retried. This 
logic should check following conditions:

a) If HBDS is set command should be attempted again. HBDS indicates that there 
was a CRC error during accessing the system memory during DMA transfer(AHCI 
spec 6.1.1).
b) If HBFS is set do not attempt to send the command again. HBFS indicates that 
the pointer given to the AHCI controller is incorrect. Retries won't solve 
that(AHCI spec 6.1.1)
c) If IFS or INFS is set further check PxSERR.ERR and PxSERR.DIAG(based on AHCI 
spec 6.1.2).
i) for PxSERR.DIAG.C(CRC error) -> restart command
ii) for PxSERR.DIAG.B(disparity error) -> CRC error should also be reported so 
it is covered by above
iii) for PxSERR.ERR.P(protocol error) -> do not restart. Protocol errors are 
unlikely to be transient although I am not sure if Internal buffer overflows 
can't be caused by transient conditions on the devices side.
iv) for PxSERR.DIAG.H(handshake errors) -> do not restart. Acording to spec 
handshake errors might be caused by transient conditions such as CRC errors but 
I hope in such case HBA will also signal CRC in PxSERR.DIAG.C(spec is not super 
clear on that point though)
d) If TFES is set further check PxTFD.ERR if PxTFD.ERR bit 7 is set(INTERFACE 
CRC according to ACS-3 spec). For others do not retry.

Hopefully this will catch majority of errors caused by transient conditions 
while also avoiding restarts on commands that are simply malformed. I will 
start working on a patch and if anyone has any suggestions/objections please 
respond.

I will also update bz with this data: 
https://bugzilla.tianocore.org/show_bug.cgi?id=4011 ( 
https://bugzilla.tianocore.org/show_bug.cgi?id=4011 )

Thanks,
Mateusz


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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg/Ata: Fix command status reporting

[Albecki, Mateusz]

Hello,

Really sorry for missing the mails. Seems like my mail was misconfigured and I 
didn't get the messages(had to check the group site).

"I cannot remember why EFI_SUCCESS is eventually returned for the above error 
case. Could you help to remind me of the details? Thanks."

To answer this - I don't remember either, and that's potentially a bug. Failing 
to reset the device should render the device unusable and we probably should 
probably treat it as a hot unplug and block further packets on that port. This 
would require bigger change. Let me know if you want me to simply add return 
EFI_DEVICE_ERROR there to stop additional retries.

As for the patch failing to fix the 
https://bugzilla.tianocore.org/show_bug.cgi?id=4011 it seems like I 
misunderstood the issue. My initial understanding was that we have the issue 
since we return success even when the password failed in following flow:

1. Incorrect password is supplied
2. Driver tries for 5 times and it fails 5 times
3. Driver returns success(bug that this patch is supposed to fix)
4. Higher level SW thinks the password is ok but in reality it wasn't(bug)

Seems like step 2 is also causing issues and we can't retry password 5 times. 
This will require driver to check for the error type and only retry on specific 
errors like CRC. Let me investigate more what can we check and what kinds of 
errors should be retried and come back to this thread. In the meantime I still 
think we can submit the change to solve failing SCT tests.

Thanks,
Mateusz


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[edk2-devel] [PATCH 1/1] MdeModulePkg/Ata: Fix command status reporting

[Albecki, Mateusz]

Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4016

AtaAtapiPassThru driver was reporting recovery status on failed command
packets which led to incorrect flows in upper layers and to SCT tests
fails. This commit will change the logic to report command status.

Cc: Hao A Wu 
Cc: Ray Ni 

Signed-off-by: Mateusz Albecki 
---
 .../Bus/Ata/AtaAtapiPassThru/AhciMode.c   | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c 
b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
index a240be940d..06c4a3e052 100644
--- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
+++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
@@ -949,6 +949,7 @@ AhciPioTransfer (
   EFI_AHCI_COMMAND_LIST  CmdList;
   UINT32 PrdCount;
   UINT32 Retry;
+  EFI_STATUS RecoveryStatus;
 
   if (Read) {
 Flag = EfiPciIoOperationBusMasterWrite;
@@ -1026,8 +1027,8 @@ AhciPioTransfer (
 
 if (Status == EFI_DEVICE_ERROR) {
   DEBUG ((DEBUG_ERROR, "PIO command failed at retry %d\n", Retry));
-  Status = AhciRecoverPortError (PciIo, Port);
-  if (EFI_ERROR (Status)) {
+  RecoveryStatus = AhciRecoverPortError (PciIo, Port);
+  if (EFI_ERROR (RecoveryStatus)) {
 break;
   }
 } else {
@@ -1122,6 +1123,7 @@ AhciDmaTransfer (
   EFI_PCI_IO_PROTOCOL*PciIo;
   EFI_TPLOldTpl;
   UINT32 Retry;
+  EFI_STATUS RecoveryStatus;
 
   Map   = NULL;
   PciIo = Instance->PciIo;
@@ -1220,8 +1222,8 @@ AhciDmaTransfer (
   Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
   if (Status == EFI_DEVICE_ERROR) {
 DEBUG ((DEBUG_ERROR, "DMA command failed at retry: %d\n", Retry));
-Status = AhciRecoverPortError (PciIo, Port);
-if (EFI_ERROR (Status)) {
+RecoveryStatus = AhciRecoverPortError (PciIo, Port);
+if (EFI_ERROR (RecoveryStatus)) {
   break;
 }
   } else {
@@ -1261,14 +1263,14 @@ AhciDmaTransfer (
   Status = AhciCheckFisReceived (PciIo, Port, SataFisD2H);
   if (Status == EFI_DEVICE_ERROR) {
 DEBUG ((DEBUG_ERROR, "DMA command failed at retry: %d\n", 
Task->RetryTimes));
-Status = AhciRecoverPortError (PciIo, Port);
+RecoveryStatus = AhciRecoverPortError (PciIo, Port);
 //
 // If recovery passed mark the Task as not started and change the 
status
 // to EFI_NOT_READY. This will make the higher level call this 
function again
 // and on next call the command will be re-issued due to IsStart being 
FALSE.
 // This also makes the next condition decrement the RetryTimes.
 //
-if (Status == EFI_SUCCESS) {
+if (RecoveryStatus == EFI_SUCCESS) {
   Task->IsStart = FALSE;
   Status= EFI_NOT_READY;
 }
@@ -1375,6 +1377,7 @@ AhciNonDataTransfer (
   EFI_AHCI_COMMAND_FIS   CFis;
   EFI_AHCI_COMMAND_LIST  CmdList;
   UINT32 Retry;
+  EFI_STATUS RecoveryStatus;
 
   //
   // Package read needed
@@ -1415,8 +1418,8 @@ AhciNonDataTransfer (
 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
 if (Status == EFI_DEVICE_ERROR) {
   DEBUG ((DEBUG_ERROR, "Non data transfer failed at retry %d\n", Retry));
-  Status = AhciRecoverPortError (PciIo, Port);
-  if (EFI_ERROR (Status)) {
+  RecoveryStatus = AhciRecoverPortError (PciIo, Port);
+  if (EFI_ERROR (RecoveryStatus)) {
 break;
   }
 } else {
-- 
2.28.0.windows.1

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z 
dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach 
handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
moze zawierac informacje poufne. W razie przypadkowego otrzymania tej 
wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; 
jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
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[edk2-devel] [PATCH 0/1] MdeModulePkg/Ata: Fix command status reporting

[Albecki, Mateusz]

Fix for a bug introduced during SATA recovery implementation

Failing SCT: https://bugzilla.tianocore.org/show_bug.cgi?id=4016
Failing password input: https://bugzilla.tianocore.org/show_bug.cgi?id=4011

The bug was due to recovery status aliasing with command status. This patch 
should resolve both
issues and should remove the need for reconfigurable retries. I have only 
tested SCT test case
though.

Github pull: https://github.com/tianocore/edk2/pull/3495

Tests:
- tested on qemu with ovmf - SCT test now passes (custom qemu needed from: 
https://github.com/matalbec/qemu/tree/sata_abort_completion)
- it should be noted that qemu doesn't really support trust protocol on SATA 
drive but for the purposes of the test it should be enough.

Cc: Hao A Wu 
Cc: Ray Ni 

Signed-off-by: Mateusz Albecki 

Mateusz Albecki (1):
  MdeModulePkg/Ata: Fix command status reporting

 .../Bus/Ata/AtaAtapiPassThru/AhciMode.c   | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

-- 
2.28.0.windows.1

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z 
dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach 
handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
moze zawierac informacje poufne. W razie przypadkowego otrzymania tej 
wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; 
jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole 
use of the intended recipient(s). If you are not the intended recipient, please 
contact the sender and delete all copies; any review or distribution by others 
is strictly prohibited.



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[edk2-devel] [PATCHv3 1/1] MdePkg/UefiDevicePathLib: Add support for PEIMs

[Albecki, Mateusz]

DevicePathLib utilities are useful in PEI to locate the devices which need
an opal unlock on S3 resume. This commit reuses the implementation done
for standalone MM support and makes the StandaloneMm library Base.

Signed-off-by: Mateusz Albecki 

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 

---
 ...athUtilitiesStandaloneMm.c => DevicePathUtilitiesBase.c} | 0
 ...icePathLibStandaloneMm.inf => UefiDevicePathLibBase.inf} | 6 +++---
 MdePkg/MdePkg.dsc   | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)
 rename MdePkg/Library/UefiDevicePathLib/{DevicePathUtilitiesStandaloneMm.c => 
DevicePathUtilitiesBase.c} (100%)
 rename MdePkg/Library/UefiDevicePathLib/{UefiDevicePathLibStandaloneMm.inf => 
UefiDevicePathLibBase.inf} (87%)

diff --git a/MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesStandaloneMm.c 
b/MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesBase.c
similarity index 100%
rename from MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesStandaloneMm.c
rename to MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesBase.c
diff --git a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf 
b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf
similarity index 87%
rename from MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
rename to MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf
index 23fedf38b7..323043033f 100644
--- a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
+++ b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf
@@ -16,10 +16,10 @@
   BASE_NAME  = UefiDevicePathLib
   MODULE_UNI_FILE= UefiDevicePathLib.uni
   FILE_GUID  = D8E58437-44D3-4154-B7A7-EB794923EF12
-  MODULE_TYPE= MM_STANDALONE
+  MODULE_TYPE= BASE
   PI_SPECIFICATION_VERSION   = 0x00010032
   VERSION_STRING = 1.0
-  LIBRARY_CLASS  = DevicePathLib | MM_STANDALONE 
MM_CORE_STANDALONE
+  LIBRARY_CLASS  = DevicePathLib
 
 
 #
@@ -28,7 +28,7 @@
 
 [Sources]
   DevicePathUtilities.c
-  DevicePathUtilitiesStandaloneMm.c
+  DevicePathUtilitiesBase.c
   DevicePathToText.c
   DevicePathFromText.c
   UefiDevicePathLib.c
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index 3d8874e647..9daee93523 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -111,7 +111,7 @@
   
MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPortProtocol.inf
   MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
   MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
-  MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
+  MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibBase.inf
   
MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf
   
MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
   MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-- 
2.28.0.windows.1

-
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[edk2-devel] [PATCHv3 0/1] MdePkg/UefiDevicePathLib: Add support for PEIMs

[Albecki, Mateusz]

This patch adds support for PEIMs in UefiDevicePathLib. Although this library 
and DEVICE_PATH_PROTOCOL
itself was initially intended for DXE the use case of unlocking opal-locked 
storage devices during S3
resume makes it useful in PEI.

As it is the change will break the users who will need to change the name of 
the infs. This can be avoided at the cost of
a dedicated inf file just for PEI or by keeping the name 
UefiDevicePathLibStandaloneMm without adding Pei phase indication.

This change is a preparation for a more robust support for PCIe enumeration in 
PEI. More details on DevicePath use cases in PEI can
be found in this discussion:
https://edk2.groups.io/g/rfc/topic/proposal_to_add_support_for/86658203?p=,,,20,0,0,0::recentpostdate/sticky,,,20,2,0,86658203,previd=1640220793375011242,nextid=1626916856753718458=1640220793375011242=1626916856753718458

Tests:
- Change has been tested by building a PEI PciHostBridgeLib instance which uses 
AppendDevicePathNode function. That PciHostBridgeLib was
  then used in PEIM that enumerates PCI devices and that PEIM was able to get 
the root bridge information along with the correct root
  bridge device path.

Changes in v2:
- Reverted file name changes, PEIM is added to UefiDevicePathLibStandaloneMm.inf

Change in v3:
- Converted UefiDevicePathLibStandaloneMm.inf to UefiDevicePathLibBase.inf Base 
lib can be used in every environment but
  but some functionalities in FileDevicePath will not work due to lack of 
access to EFI_HANDLE in SEC/PEI/SMM.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 

Mateusz Albecki (1):
  MdePkg/UefiDevicePathLib: Add support for PEIMs

 MdePkg/Library/UefiDevicePathLib/DevicePathUtilities.c  | 6 ++
 ...athUtilitiesStandaloneMm.c => DevicePathUtilitiesBase.c} | 0
 ...icePathLibStandaloneMm.inf => UefiDevicePathLibBase.inf} | 6 +++---
 MdePkg/MdePkg.dsc   | 2 +-
 4 files changed, 10 insertions(+), 4 deletions(-)
 rename MdePkg/Library/UefiDevicePathLib/{DevicePathUtilitiesStandaloneMm.c => 
DevicePathUtilitiesBase.c} (100%)
 rename MdePkg/Library/UefiDevicePathLib/{UefiDevicePathLibStandaloneMm.inf => 
UefiDevicePathLibBase.inf} (87%)

-- 
2.28.0.windows.1

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
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Re: [edk2-devel] [PATCH V1 1/1] MdeModulePkg: Add Definition of EDKII_PEI_VARIABLE_PPI

[Albecki, Mateusz]

Hi,

I think it would be better to avoid using PEI and PPI in the structure names. 
This would allow us to install this structure as protocol in DXE/SMM and 
potentially use it in a common code.

Thanks,
Mateusz


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Re: [edk2-devel] [PATCH v5 1/6] MdeModulePkg/PciHostBridge: io range is not mandatory

[Albecki, Mateusz]

On Mon, May 23, 2022 at 11:24 PM, Gerd Hoffmann wrote:

> 
> On Mon, May 23, 2022 at 04:48:05AM -0700, Albecki, Mateusz wrote:
> 
>> @Ni, Ray
>> 
>> I think EDK2 needs to provide a way for root port to operate without IO
>> space assigned in a platform-independent way. I can think of the following
>> cases when root port didn't get IO space:
>> 
>> 1. We have run out of IO space but it's fine since the device under the
>> root port doesn't use IO or has only non-critical functionalities under IO
>> 
>> 2. We have run out of IO space and it's really not fine since device needs
>> IO
>> 3. We are running on a CPU which doesn't support IO
>> 
>> For 1. the question is whether the device driver in EDK2 understands that
>> IO bar for that device is optional and will bother to check if it has been
>> assigned and either fail gracefully or continue operation in limited
>> capacity. For 2. the question is whether the driver will fail gracefully.
>> 3 is for completeness at this point I think since the only other
>> architecture that uses EDK2 is ARM which has to deal with it in some way
>> right now which I think maps IO region into MMIO so in a way it supports
>> IO.
> 
> Well, the case I'm trying to handle here is qemu microvm. It's x86, but
> io address space support for pcie devices is not wired up. So the pcie
> host bridge doesn't support io, which is rather close to case (3).
> 
> 
>> I've checked the device driver behavior in EDK2 for devices which use IO
>> bar here is the rundown:
>> 1. IDE - Doesn't check if IO has been assigned, not giving IO results in
>> undefined behavior
>> 2. SerialIo -> Doesn't check, will assert the system when IO is not
>> assigned (although the logic there is really strange as it can use 3
>> different access methods)
>> 3. UHCI -> Checks but too late, will most likely result in undefined
>> behavior
> 
> Current edk2 behavior is that the initialization of the pcie host bridge
> fails in case no io space is present (and all devices connected to it are
> not initialized either of course).
> 
> With this patch applied pcie host bridge initialization works. PCIe
> devices without io bars are enumerated and initialized sucessfully.
> PCIe devices with io bar fail to initialize. That isn't much of a
> problem tough as a qemu microvm typically has no pcie devices with io
> bars.

You mention that devices with IO bar fail to initialize but that is contrary to 
what I would expect from code review. I've run an experiment with your change 
in which I am telling
EDK2 that no IO space is available on the system by not updating the IO range 
in PciHostBridgeLib. Sure enough Devices that need an IO are still enumerated, 
device path and PciIo are installed
and in general everything works as it used to. If I had an UHCI controller on 
that system UHCI driver would be loaded and it could potentially result in some 
strange behavior since that driver isn't smart enough to check
if IO space has been allocated for the device.

To make things worse I see that if we return success there EDK2 will actually 
go ahead and start assigning trash addresses to the device and enable IO space 
decoding in case of the PCI root port which means that device will try to decode
invalid IO ranges. Not an issue for a system without an IO but for a system in 
which we have run out of the IO and we have entered this code branch this new 
behavior is potentially more dangerous then simply not enumerating the device.

Logs:
PciBus: Resource Map for Root Bridge PciRoot(0x0)
Type =   Io16; Base = 0x; Length = 0x1000; Alignment = 0xFFF
Base = 0x0; Length = 0x4; Alignment = 0x3; Owner = PPB [00|06|04:14]
Base = 0x0; Length = 0x4; Alignment = 0x3; Owner = PPB [00|06|00:14]
Base = 0xFFFC; Length = 0x4; Alignment = 0x3; Owner = PCI [00|04|00:24]
Base = 0xFFFC; Length = 0x4; Alignment = 0x3; Owner = PCI [00|04|00:20]
Base = 0xFFFC; Length = 0x4; Alignment = 0x3; Owner = PCI [00|04|00:1C]
Base = 0xFFFC; Length = 0x4; Alignment = 0x3; Owner = PCI [00|04|00:18]

> 
> 
>> Even with those bad device drivers I would agree that taking this
>> change presents low risk given that those devices are pretty old and
>> should be mostly unused on new systems(SerialIo being an exception but
>> that one is usually an RCIEP).
> 
> Also note that for pcie root bridges which do support io address space
> this patch changes nothing.

It seems to me like it does. Specifically the error scenario where the system 
has run out of IO space will not be handled properly I think.

> 
> 
>> That said I think we are missing a larger issue here - why are we
>> running out of IO when we have 16 root ports?
> 
> I don't th

[edk2-devel] [PATCHv2 1/1] MdePkg/UefiDevicePathLib: Add support for PEIMs

[Albecki, Mateusz]

DevicePathLib utilities are useful in PEI to locate the devices which need
an opal unlock on S3 resume. This commit reuses the implementation done
to support Standalone MM for PEI.

Signed-off-by: Mateusz Albecki 

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
---
 .../Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf 
b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
index 23fedf38b7..5d59b17f8b 100644
--- a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
+++ b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
@@ -19,7 +19,7 @@
   MODULE_TYPE= MM_STANDALONE
   PI_SPECIFICATION_VERSION   = 0x00010032
   VERSION_STRING = 1.0
-  LIBRARY_CLASS  = DevicePathLib | MM_STANDALONE 
MM_CORE_STANDALONE
+  LIBRARY_CLASS  = DevicePathLib | MM_STANDALONE 
MM_CORE_STANDALONE PEIM
 
 
 #
-- 
2.28.0.windows.1

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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Re: [edk2-devel] [PATCH v5 1/6] MdeModulePkg/PciHostBridge: io range is not mandatory

[Albecki, Mateusz]

@Ni, Ray

I think EDK2 needs to provide a way for root port to operate without IO space 
assigned in a platform-independent way. I can think of the following cases when 
root port didn't get IO space:

1. We have run out of IO space but it's fine since the device under the root 
port doesn't use IO or has only non-critical functionalities under IO
2. We have run out of IO space and it's really not fine since device needs IO
3. We are running on a CPU which doesn't support IO

For 1. the question is whether the device driver in EDK2 understands that IO 
bar for that device is optional and will bother to check if it has been 
assigned and either fail gracefully or continue operation in limited capacity. 
For 2. the question is whether the driver will fail gracefully. 3 is for 
completeness at this point I think since the only other architecture that uses 
EDK2 is ARM which has to deal with it in some way right now which I think maps 
IO region into MMIO so in a way it supports IO.

I've checked the device driver behavior in EDK2 for devices which use IO bar 
here is the rundown:
1. IDE - Doesn't check if IO has been assigned, not giving IO results in 
undefined behavior
2. SerialIo -> Doesn't check, will assert the system when IO is not assigned 
(although the logic there is really strange as it can use 3 different access 
methods)
3. UHCI -> Checks but too late, will most likely result in undefined behavior

Even with those bad device drivers I would agree that taking this change 
presents low risk given that those devices are pretty old and should be mostly 
unused on new systems(SerialIo being an exception but that one is usually an 
RCIEP). That said I think we are missing a larger issue here - why are we 
running out of IO when we have 16 root ports? Surely we don't have a device 
with IO requirement behind each of those root ports so is the BIOS blindly 
assigning IO to root ports which have no requirement? I see on my system that 
when we don't have IO requirement behind the root port BIOS sets IOBASE to 0xF0 
and IOLIMIT to 0x0 which means no IO decode will be performed.

Thanks,
Mateusz


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Re: [edk2-devel] [PATCH 1/1] MdePkg/UefiDevicePathLib: Add support for PEIMs

[Albecki, Mateusz]

Thanks Mike I will send a new patch with inf file name untouched.

Mateusz


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[edk2-devel] [PATCH 1/1] MdePkg/UefiDevicePathLib: Add support for PEIMs

[Albecki, Mateusz]

DevicePathLib utilities are useful in PEI to locate the devices which need
an opal unlock on S3 resume. This commit reuses the implementation done
to support Standalone MM for PEI.

Signed-off-by: Mateusz Albecki 

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
---
 ...iesStandaloneMm.c => DevicePathUtilitiesPeiStandaloneMm.c} | 0
 ...bStandaloneMm.inf => UefiDevicePathLibPeiStandaloneMm.inf} | 4 ++--
 MdePkg/MdePkg.dsc | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)
 rename MdePkg/Library/UefiDevicePathLib/{DevicePathUtilitiesStandaloneMm.c => 
DevicePathUtilitiesPeiStandaloneMm.c} (100%)
 rename MdePkg/Library/UefiDevicePathLib/{UefiDevicePathLibStandaloneMm.inf => 
UefiDevicePathLibPeiStandaloneMm.inf} (93%)

diff --git a/MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesStandaloneMm.c 
b/MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesPeiStandaloneMm.c
similarity index 100%
rename from MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesStandaloneMm.c
rename to MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesPeiStandaloneMm.c
diff --git a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf 
b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibPeiStandaloneMm.inf
similarity index 93%
rename from MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
rename to MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibPeiStandaloneMm.inf
index 23fedf38b7..2f39a29aa2 100644
--- a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
+++ b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibPeiStandaloneMm.inf
@@ -19,7 +19,7 @@
   MODULE_TYPE= MM_STANDALONE
   PI_SPECIFICATION_VERSION   = 0x00010032
   VERSION_STRING = 1.0
-  LIBRARY_CLASS  = DevicePathLib | MM_STANDALONE 
MM_CORE_STANDALONE
+  LIBRARY_CLASS  = DevicePathLib | MM_STANDALONE 
MM_CORE_STANDALONE PEIM
 
 
 #
@@ -28,7 +28,7 @@
 
 [Sources]
   DevicePathUtilities.c
-  DevicePathUtilitiesStandaloneMm.c
+  DevicePathUtilitiesPeiStandaloneMm.c
   DevicePathToText.c
   DevicePathFromText.c
   UefiDevicePathLib.c
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index a94959169b..3345404cc1 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -111,7 +111,7 @@
   
MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPortProtocol.inf
   MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
   MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
-  MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibStandaloneMm.inf
+  MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibPeiStandaloneMm.inf
   
MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf
   
MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
   MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
-- 
2.28.0.windows.1

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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[edk2-devel] [PATCH 0/1] MdePkg/UefiDevicePathLib: Add support for PEIMs

[Albecki, Mateusz]

This patch adds support for PEIMs in UefiDevicePathLib. Although this library 
and DEVICE_PATH_PROTOCOL
itself was initially intended for DXE the use case of unlocking opal-locked 
storage devices during S3
resume makes it useful in PEI.

As it is the change will break the users who will need to change the name of 
the infs. This can be avoided at the cost of
a dedicated inf file just for PEI or by keeping the name 
UefiDevicePathLibStandaloneMm without adding Pei phase indication.

Tests:
- Change has been tested by building a PEI PciHostBridgeLib instance which uses 
AppendDevicePathNode function. That PciHostBridgeLib was
  then used in PEIM that enumerates PCI devices and that PEIM was able to get 
the root bridge information along with the correct root
  bridge device path.

This change is a preparation for a more robust support for PCIe enumeration in 
PEI. More details on DevicePath use cases in PEI can
be found in this discussion:
https://edk2.groups.io/g/rfc/topic/proposal_to_add_support_for/86658203?p=,,,20,0,0,0::recentpostdate/sticky,,,20,2,0,86658203,previd=1640220793375011242,nextid=1626916856753718458=1640220793375011242=1626916856753718458

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 

Mateusz Albecki (1):
  MdePkg/UefiDevicePathLib: Add support for PEIMs

 .../DevicePathUtilitiesPei.c  | 40 +++
 ...c => DevicePathUtilitiesPeiStandaloneMm.c} |  0
 .../UefiDevicePathLib/UefiDevicePathLib.inf   |  2 +-
 ...f => UefiDevicePathLibPeiStandaloneMm.inf} |  4 +-
 MdePkg/MdePkg.dsc |  2 +-
 5 files changed, 44 insertions(+), 4 deletions(-)
 create mode 100644 MdePkg/Library/UefiDevicePathLib/DevicePathUtilitiesPei.c
 rename MdePkg/Library/UefiDevicePathLib/{DevicePathUtilitiesStandaloneMm.c => 
DevicePathUtilitiesPeiStandaloneMm.c} (100%)
 rename MdePkg/Library/UefiDevicePathLib/{UefiDevicePathLibStandaloneMm.inf => 
UefiDevicePathLibPeiStandaloneMm.inf} (93%)

-- 
2.28.0.windows.1

-
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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Re: [edk2-devel] [PATCH 1/2] MdeModulePkg/SataControllerDxe: Add support for drives in RAID mode

[Albecki, Mateusz]

Hello,

Sorry for getting in so late on the conversation but I want to make sure we are 
not going to break some platforms with this change. Excuse me if I am simply 
repeating what was being said before.


  1.  We can’t have SataControllerDxe report supported for all raid interface 
devices on the market. As far as I know Intel RAID is rather special in that it 
implements AHCI interface underneath and if we encounter a RAID controller like 
that we will falsely claim that we support it. It’s hard to say whether this 
will have any consequences for the data integrity on the RAID array but at the 
very least we will prevent appropriate driver from binding to this RAID 
controller(potentially unbootable system).
  2.  On newer Intel systems(not sure about G33) we have a dedicated RAID 
driver(RST driver) which will bind to integrated SATA in RAID mode. On such 
systems we have both RST driver and traditional SATA stack(SataControllerDxe, 
AtaAtapiPassThru etc) to allow runtime change between AHCI and RAID modes. If 
SataControllerDxe starts claiming SATA controller it will potentially make the 
system unbootable in RAID mode(if RAID is configured). What is more on those 
systems going through RAID config with volume managed by RST to standard AHCI 
config will corrupt RAID volumes. I can’t go into details on why is that but it 
has to do with how RST configures GPT partition.

In summary I don’t think we can add simple checks for RAID mode. Even adding a 
build flag could be potentially problematic since on desktop systems you never 
know what kind of controller user will plug in their slots. One potential 
solution would be to keep a list of controllers which do support AHCI interface 
even though they are reporting RAID class code but even then the solution could 
potentially break systems with both RST and AHCI stack present. Maybe we should 
have a platform provided protocol that would say whether AHCI drivers should 
load on such RAID controller?

Thanks,
Mateusz
From: devel@edk2.groups.io  On Behalf Of Vitaly Cheptsov
Sent: Wednesday, December 16, 2020 10:31 AM
To: Kinney, Michael D 
Cc: devel@edk2.groups.io; Wu, Hao A ; Ni, Ray 
; Wang, Jian J ; Albecki, Mateusz 
; Laszlo Ersek 
Subject: Re: [edk2-devel] [PATCH 1/2] MdeModulePkg/SataControllerDxe: Add 
support for drives in RAID mode

Mike,

That’s right. And due to that interface being vendor-specific, Intel 
controllers work fine. I am not positive more logic is needed since it is 
opt-in. These patches are not new, and so far they worked reliably on a broad 
amount of systems for several years.

From what it looks like, you are strongly opposed to getting this land into EDK 
II mainline, since it is too specific (at least that is how I understand your 
arguments). If this is the case, I guess we could abandon these changes.

Best regards,
Vitaly

15 дек. 2020 г., в 23:01, Kinney, Michael D 
mailto:michael.d.kin...@intel.com>> написал(а):

Another issue with this approach is that the formal PCI definition of this 
class code is in the following spec.

https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf

04h 00h RAID controller - vendor-specific interface


#define   PCI_CLASS_MASS_STORAGE_IDE0x01

#define PCI_CLASS_MASS_STORAGE_SATADPA   0x06
#define   PCI_IF_MASS_STORAGE_SATA 0x00
#define   PCI_IF_MASS_STORAGE_AHCI 0x01

#define   PCI_CLASS_MASS_STORAGE_RAID   0x04


#define IS_PCI_IDE(_p)IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, 
PCI_CLASS_MASS_STORAGE_IDE)
#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, 
PCI_CLASS_MASS_STORAGE_SATADPA)
#define IS_PCI_RAID(_p)   IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, 
PCI_CLASS_MASS_STORAGE_RAID)

So the IS_PCI_RAID() macro checks for the RAID class code and the PCI spec 
states that the interface is vendor specific.  There is no guarantee what so 
ever that the controller that passes IS_PCI_RAID() check has a SATA interface.

There are lost of risks in using this macro to see if it is a SATA controller 
(even if enabled by a PCD).  You need to add more logic to even know it is safe 
to assume SATA registers.

Mike





From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> 
mailto:devel@edk2.groups.io>> On Behalf Of Vitaly Cheptsov
Sent: Tuesday, December 15, 2020 11:47 AM
To: Kinney, Michael D 
mailto:michael.d.kin...@intel.com>>
Cc: devel@edk2.groups.io<mailto:devel@edk2.groups.io>; Wu, Hao A 
mailto:hao.a...@intel.com>>; Ni, Ray 
mailto:ray...@intel.com>>; Wang, Jian J 
mailto:jian.j.w...@intel.com>>; Albecki, Mateusz 
mailto:mateusz.albe...@intel.com>>; Laszlo Ersek 
mailto:ler...@redhat.com>>
Subject: Re: [edk2-devel] [PATCH 1/2] MdeModulePkg/SataControllerDxe: Add 
support for drives in RAID mode

Mike,

I understand that very well and thus the PCD rather than my original patch :)

Best,
Vitaly


On 15 Dec 2020, at 22:41, Kinney, Michael D 
mailto:m

[edk2-devel] [PATCHv3 1/5] MdeModulePkg/SdMmcPciHcDxe: Enhance driver traces

[Albecki, Mateusz]

To allow for easier debug of failing commands we
have added a capability to print TRB and command
packet when we start execution of the TRB(on
DEBUG_VERBOSE level) and when the TRB failed to
execute correctly(on DEBUG_ERROR level). Additionally
we will also print error interrupt status and interrupt
status register on failed SD command.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 87 
 1 file changed, 87 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 43626fff48..71cf5a78f9 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1645,6 +1645,82 @@ BuildAdmaDescTable (
   return EFI_SUCCESS;
 }
 
+/**
+  Prints the contents of the command packet to the debug port.
+
+  @param[in] DebugLevel  Debug level at which the packet should be printed.
+  @param[in] Packet  Pointer to packet to print.
+**/
+VOID
+SdMmcPrintPacket (
+  IN UINT32   DebugLevel,
+  IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET  *Packet
+  )
+{
+  if (Packet == NULL) {
+return;
+  }
+
+  DEBUG ((DebugLevel, "Printing EFI_SD_MMC_PASS_THRU_COMMAND_PACKET\n"));
+  if (Packet->SdMmcCmdBlk != NULL) {
+DEBUG ((DebugLevel, "Command index: %d, argument: %X\n", 
Packet->SdMmcCmdBlk->CommandIndex, Packet->SdMmcCmdBlk->CommandArgument));
+DEBUG ((DebugLevel, "Command type: %d, response type: %d\n", 
Packet->SdMmcCmdBlk->CommandType, Packet->SdMmcCmdBlk->ResponseType));
+  }
+  if (Packet->SdMmcStatusBlk != NULL) {
+DEBUG ((DebugLevel, "Response 0: %X, 1: %X, 2: %X, 3: %X\n",
+   Packet->SdMmcStatusBlk->Resp0,
+   Packet->SdMmcStatusBlk->Resp1,
+   Packet->SdMmcStatusBlk->Resp2,
+   Packet->SdMmcStatusBlk->Resp3
+   ));
+  }
+  DEBUG ((DebugLevel, "Timeout: %ld\n", Packet->Timeout));
+  DEBUG ((DebugLevel, "InDataBuffer: %p\n", Packet->InDataBuffer));
+  DEBUG ((DebugLevel, "OutDataBuffer: %p\n", Packet->OutDataBuffer));
+  DEBUG ((DebugLevel, "InTransferLength: %d\n", Packet->InTransferLength));
+  DEBUG ((DebugLevel, "OutTransferLength: %d\n", Packet->OutTransferLength));
+  DEBUG ((DebugLevel, "TransactionStatus: %r\n", Packet->TransactionStatus));
+}
+
+/**
+  Prints the contents of the TRB to the debug port.
+
+  @param[in] DebugLevel  Debug level at which the TRB should be printed.
+  @param[in] Trb Pointer to the TRB structure.
+**/
+VOID
+SdMmcPrintTrb (
+  IN UINT32 DebugLevel,
+  IN SD_MMC_HC_TRB  *Trb
+  )
+{
+  if (Trb == NULL) {
+return;
+  }
+
+  DEBUG ((DebugLevel, "Printing SD_MMC_HC_TRB\n"));
+  DEBUG ((DebugLevel, "Slot: %d\n", Trb->Slot));
+  DEBUG ((DebugLevel, "BlockSize: %d\n", Trb->BlockSize));
+  DEBUG ((DebugLevel, "Data: %p\n", Trb->Data));
+  DEBUG ((DebugLevel, "DataLen: %d\n", Trb->DataLen));
+  DEBUG ((DebugLevel, "Read: %d\n", Trb->Read));
+  DEBUG ((DebugLevel, "DataPhy: %lX\n", Trb->DataPhy));
+  DEBUG ((DebugLevel, "DataMap: %p\n", Trb->DataMap));
+  DEBUG ((DebugLevel, "Mode: %d\n", Trb->Mode));
+  DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode));
+  DEBUG ((DebugLevel, "Event: %p\n", Trb->Event));
+  DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));
+  DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout));
+  DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
+  DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc));
+  DEBUG ((DebugLevel, "Adma64V3Desc: %p\n", Trb->Adma64V3Desc));
+  DEBUG ((DebugLevel, "Adma64V4Desc: %p\n", Trb->Adma64V4Desc));
+  DEBUG ((DebugLevel, "AdmaMap: %p\n", Trb->AdmaMap));
+  DEBUG ((DebugLevel, "AdmaPages: %X\n", Trb->AdmaPages));
+
+  SdMmcPrintPacket (DebugLevel, Trb->Packet);
+}
+
 /**
   Create a new TRB for the SD/MMC cmd request.
 
@@ -2236,6 +2312,10 @@ SdMmcCheckAndRecoverErrors (
 return Status;
   }
 
+  DEBUG ((DEBUG_ERROR, "Error reported by SDHCI\n"));
+  DEBUG ((DEBUG_ERROR, "Interrupt status = %X\n", IntStatus));
+  DEBUG ((DEBUG_ERROR, "Error interrupt status = %X\n", ErrIntStatus));
+
   //
   // If the data timeout error is reported
   // but data transfer is signaled as completed we
@@ -2439,6 +2519,13 @@ Done:
 
   if (Status != EFI_NOT_READY) {
 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "TRB failed with %r\n", Status));
+  SdMmcPrintTrb (DEBUG_ERROR, Trb);
+} else {
+  DEBUG ((DEBUG_VERBOSE, "TRB success\n"));
+  SdMmcPrintTrb (DEBUG_VERBOSE, Trb);
+}
   }
 
   return Status;
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 

[edk2-devel] [PATCHv3 0/5] MdeModulePkg/SdMmcPciHcDxe: Refactor command processing

[Albecki, Mateusz]

This patch series aims to refactor command processing to achieve following

- Trace the failing TRB packets to see what commands are failing and for what 
reasons
- Get the response data even if data transfer timed out to allow easier 
debugging
- Fix the PIO mode which is currently completely broken.

Changes in v2:
- Moved verbose packet prints after the command is finished to capture the 
successfull command response
- Fixed the debug prints
- PIO data will be moved with width matching the alignment of the block size. 
For majority of transfers that means UINT32 width.

Changes in v3
- Fixed the memory map in non DMA case(PATCHv3 4/5)

Tests performed:
- Each patch in the series has passed boot from eMMC with ADMAv3 data transfer 
mode
- SDMA based boot has been tested with the full patch series
- PIO based boot has been tested with the full patch series
- PIO based data transfer has been additionally tested by creating and modyfing 
a file in EFI shell
- Tested async PIO transfer - results below

Tests performed v3:
- Booted OS in ADMA mode(V3 64bit)
- Booted OS in PIO mode

Async test results:
After fixing memory map issue PIO works reliably in both async and sync cases 
on all paltforms.

All tests were performed with eMMC in HS400 @200MHz clock frequency.

For easier review & integration patch has been pushed here:
Whole series: https://github.com/malbecki/edk2/tree/emmc_transfer_refactor

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 


Mateusz Albecki (5):
  MdeModulePkg/SdMmcPciHcDxe: Enhance driver traces
  MdeModulePkg/SdMmcPciHcDxe: Read response on command completion
  MdeModulePkg/SdMmcPciHcDxe: Refactor data transfer completion
  MdeModulePkg/SdMmcPciHcDxe: Do not map memory for non DMA transfer
  MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   4 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 609 -
 2 files changed, 478 insertions(+), 135 deletions(-)

-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.

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[edk2-devel] [PATCHv3 2/5] MdeModulePkg/SdMmcPciHcDxe: Read response on command completion

[Albecki, Mateusz]

SdMmcPciHcDxe driver used to read response only after
command and data transfer completed. According to SDHCI
specification response data is ready after the command
complete status is set by the host controller. Getting
the response data early will help debugging the cases
when command completed but data transfer timed out.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   1 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 201 +++--
 2 files changed, 144 insertions(+), 58 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 5bc3577ba2..15b7d12596 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -153,6 +153,7 @@ typedef struct {
 
   EFI_EVENT   Event;
   BOOLEAN Started;
+  BOOLEAN CommandComplete;
   UINT64  Timeout;
   UINT32  Retries;
 
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 71cf5a78f9..205ec86032 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1710,6 +1710,7 @@ SdMmcPrintTrb (
   DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode));
   DEBUG ((DebugLevel, "Event: %p\n", Trb->Event));
   DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));
+  DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete));
   DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout));
   DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
   DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc));
@@ -1760,6 +1761,7 @@ SdMmcCreateTrb (
   Trb->Packet= Packet;
   Trb->Event = Event;
   Trb->Started   = FALSE;
+  Trb->CommandComplete = FALSE;
   Trb->Timeout   = Packet->Timeout;
   Trb->Retries   = SD_MMC_TRB_RETRIES;
   Trb->Private   = Private;
@@ -2350,6 +2352,99 @@ SdMmcCheckAndRecoverErrors (
   return ErrorStatus;
 }
 
+/**
+  Reads the response data into the TRB buffer.
+  This function assumes that caller made sure that
+  command has completed.
+
+  @param[in] Private  A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb  The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS  Response read successfully.
+  @retval Others   Failed to get response.
+**/
+EFI_STATUS
+SdMmcGetResponse (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb
+  )
+{
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET  *Packet;
+  UINT8Index;
+  UINT32   Response[4];
+  EFI_STATUS   Status;
+
+  Packet = Trb->Packet;
+
+  if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeBc) {
+return EFI_SUCCESS;
+  }
+
+  for (Index = 0; Index < 4; Index++) {
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_RESPONSE + Index * 4,
+   TRUE,
+   sizeof (UINT32),
+   [Index]
+   );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+}
+  CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Checks if the command completed. If the command
+  completed it gets the response and records the
+  command completion in the TRB.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+  @param[in] IntStatus  Snapshot of the normal interrupt status register.
+
+  @retval EFI_SUCCESS   Command completed successfully.
+  @retval EFI_NOT_READY Command completion still pending.
+  @retval OthersCommand failed to complete.
+**/
+EFI_STATUS
+SdMmcCheckCommandComplete (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb,
+  IN UINT16  IntStatus
+  )
+{
+  UINT16  Data16;
+  EFI_STATUS  Status;
+
+  if ((IntStatus & BIT0) != 0) {
+Data16 = BIT0;
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_NOR_INT_STS,
+   FALSE,
+   sizeof (Data16),
+   
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Status = SdMmcGetResponse (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Trb->CommandComplete = TRUE;
+return EFI_SUCCESS;
+  }
+
+  return EFI_NOT_READY;
+}
+
 /**
   Check the TRB execution result.
 
@@ -2370,9 +2465,7 @@ SdMmcCheckTrbResult (
   EFI_STATUS  Status;
   EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
   UINT16   

[edk2-devel] [PATCHv3 5/5] MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode

[Albecki, Mateusz]

Current driver does not support PIO transfer mode for
commands other then tuning. This change adds the code
to transfer PIO data.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   3 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 132 +
 2 files changed, 114 insertions(+), 21 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 15b7d12596..fd89306fab 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -157,6 +157,9 @@ typedef struct {
   UINT64  Timeout;
   UINT32  Retries;
 
+  BOOLEAN PioModeTransferCompleted;
+  UINT32  PioBlockIndex;
+
   SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
   SD_MMC_HC_ADMA_64_V3_DESC_LINE  *Adma64V3Desc;
   SD_MMC_HC_ADMA_64_V4_DESC_LINE  *Adma64V4Desc;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 422862577e..497ac08355 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1713,6 +1713,8 @@ SdMmcPrintTrb (
   DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete));
   DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout));
   DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
+  DEBUG ((DebugLevel, "PioModeTransferCompleted: %d\n", 
Trb->PioModeTransferCompleted));
+  DEBUG ((DebugLevel, "PioBlockIndex: %d\n", Trb->PioBlockIndex));
   DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc));
   DEBUG ((DebugLevel, "Adma64V3Desc: %p\n", Trb->Adma64V3Desc));
   DEBUG ((DebugLevel, "Adma64V4Desc: %p\n", Trb->Adma64V4Desc));
@@ -1817,6 +1819,8 @@ SdMmcCreateTrb (
   Trb->CommandComplete = FALSE;
   Trb->Timeout   = Packet->Timeout;
   Trb->Retries   = SD_MMC_TRB_RETRIES;
+  Trb->PioModeTransferCompleted = FALSE;
+  Trb->PioBlockIndex = 0;
   Trb->Private   = Private;
 
   if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
@@ -2479,6 +2483,104 @@ SdMmcCheckCommandComplete (
   return EFI_NOT_READY;
 }
 
+/**
+  Transfers data from card using PIO method.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+  @param[in] IntStatus  Snapshot of the normal interrupt status register.
+
+  @retval EFI_SUCCESS   PIO transfer completed successfully.
+  @retval EFI_NOT_READY PIO transfer completion still pending.
+  @retval OthersPIO transfer failed to complete.
+**/
+EFI_STATUS
+SdMmcTransferDataWithPio (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb,
+  IN UINT16  IntStatus
+  )
+{
+  EFI_STATUS  Status;
+  UINT16  Data16;
+  UINT32  BlockCount;
+  EFI_PCI_IO_PROTOCOL_WIDTH  Width;
+  UINTN   Count;
+
+  BlockCount = (Trb->DataLen / Trb->BlockSize);
+  if (Trb->DataLen % Trb->BlockSize != 0) {
+BlockCount += 1;
+  }
+
+  if (Trb->PioBlockIndex >= BlockCount) {
+return EFI_SUCCESS;
+  }
+
+  switch (Trb->BlockSize % sizeof (UINT32)) {
+case 0:
+  Width = EfiPciIoWidthFifoUint32;
+  Count = Trb->BlockSize / sizeof (UINT32);
+  break;
+case 2:
+  Width = EfiPciIoWidthFifoUint16;
+  Count = Trb->BlockSize / sizeof (UINT16);
+  break;
+case 1:
+case 3:
+default:
+  Width = EfiPciIoWidthFifoUint8;
+  Count = Trb->BlockSize;
+  break;
+}
+
+  if (Trb->Read) {
+if ((IntStatus & BIT5) == 0) {
+  return EFI_NOT_READY;
+}
+Data16 = BIT5;
+SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, 
sizeof (Data16), );
+
+Status = Private->PciIo->Mem.Read (
+   Private->PciIo,
+   Width,
+   Trb->Slot,
+   SD_MMC_HC_BUF_DAT_PORT,
+   Count,
+   (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * 
Trb->PioBlockIndex))
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Trb->PioBlockIndex++;
+  } else {
+if ((IntStatus & BIT4) == 0) {
+  return EFI_NOT_READY;
+}
+Data16 = BIT4;
+SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, 
sizeof (Data16), );
+
+Status = Private->PciIo->Mem.Write (
+   Private->PciIo,
+   Width,
+   Trb->Slot,
+   SD_MMC_HC_BUF_DAT_PORT,
+   Count,
+   (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * 
Trb->PioBlockIndex))
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Trb->PioBlockIndex++;
+  }
+
+  if (Trb->PioBlockIndex >= 

[edk2-devel] [PATCHv3 3/5] MdeModulePkg/SdMmcPciHcDxe: Refactor data transfer completion

[Albecki, Mateusz]

This patch refactors the way in which the driver will check
the data transfer completion. Data transfer related
functionalities have been moved to separate function.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 181 ++-
 1 file changed, 112 insertions(+), 69 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 205ec86032..bb699027e3 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -2445,6 +2445,112 @@ SdMmcCheckCommandComplete (
   return EFI_NOT_READY;
 }
 
+/**
+  Update the SDMA address on the SDMA buffer boundary interrupt.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS  Updated SDMA buffer address.
+  @retval Others   Failed to update SDMA buffer address.
+**/
+EFI_STATUS
+SdMmcUpdateSdmaAddress (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb
+  )
+{
+  UINT64  SdmaAddr;
+  EFI_STATUS  Status;
+
+  SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
+
+  if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_ADMA_SYS_ADDR,
+   FALSE,
+   sizeof (UINT64),
+   
+   );
+  } else {
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_SDMA_ADDR,
+   FALSE,
+   sizeof (UINT32),
+   
+   );
+  }
+
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
+  return EFI_SUCCESS;
+}
+
+/**
+  Checks if the data transfer completed and performs any actions
+  neccessary to continue the data transfer such as SDMA system
+  address fixup or PIO data transfer.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+  @param[in] IntStatus  Snapshot of the normal interrupt status register.
+
+  @retval EFI_SUCCESS   Data transfer completed successfully.
+  @retval EFI_NOT_READY Data transfer completion still pending.
+  @retval OthersData transfer failed to complete.
+**/
+EFI_STATUS
+SdMmcCheckDataTransfer (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb,
+  IN UINT16  IntStatus
+  )
+{
+  UINT16  Data16;
+  EFI_STATUS  Status;
+
+  if ((IntStatus & BIT1) != 0) {
+Data16 = BIT1;
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_NOR_INT_STS,
+   FALSE,
+   sizeof (Data16),
+   
+   );
+return Status;
+  }
+
+  if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) != 0)) {
+Data16 = BIT3;
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_NOR_INT_STS,
+   FALSE,
+   sizeof (Data16),
+   
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Status = SdMmcUpdateSdmaAddress (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  }
+
+  return EFI_NOT_READY;
+}
+
 /**
   Check the TRB execution result.
 
@@ -2465,7 +2571,6 @@ SdMmcCheckTrbResult (
   EFI_STATUS  Status;
   EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
   UINT16  IntStatus;
-  UINT64  SdmaAddr;
   UINT32  PioLength;
 
   Packet  = Trb->Packet;
@@ -2528,80 +2633,18 @@ SdMmcCheckTrbResult (
 Status = SdMmcCheckCommandComplete (Private, Trb, IntStatus);
 if (EFI_ERROR (Status)) {
   goto Done;
-} else {
-  //
-  // If the command doesn't require data transfer skip the transfer
-  // complete checking.
-  //
-  if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
-  (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
-  (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
-goto Done;
-  }
 }
   }
 
-  //
-  // Check Transfer Complete bit is set or not.
-  //
-  if ((IntStatus & BIT1) == BIT1) {
-goto Done;
-  }
-
-  //
-  // Check if DMA interrupt is signalled for the SDMA transfer.
-  //
-  if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
-//
-// Clear DMA interrupt bit.
-//
-IntStatus = BIT3;
-Status= SdMmcHcRwMmio (
-  Private->PciIo,
-  Trb->Slot,
-  

[edk2-devel] [PATCHv3 4/5] MdeModulePkg/SdMmcPciHcDxe: Do not map memory for non DMA transfer

[Albecki, Mateusz]

Driver code used to map memory for DMA transfer even if host doesn't
support DMA. This is causing memory corruption when driver transfers
data using PIO. This change refactors the code to skip call to
PciIo->Map for non DMA transfers.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 88 
 1 file changed, 61 insertions(+), 27 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index bb699027e3..422862577e 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1722,6 +1722,62 @@ SdMmcPrintTrb (
   SdMmcPrintPacket (DebugLevel, Trb->Packet);
 }
 
+/**
+  Sets up host memory to allow DMA transfer.
+
+  @param[in] Private  A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Slot The slot number of the SD card to send the command to.
+  @param[in] Packet   A pointer to the SD command data structure.
+
+  @retval EFI_SUCCESS  Memory has been mapped for DMA transfer.
+  @retval Others   Memory has not been mapped.
+**/
+EFI_STATUS
+SdMmcSetupMemoryForDmaTransfer (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN UINT8   Slot,
+  IN SD_MMC_HC_TRB   *Trb
+  )
+{
+  EFI_PCI_IO_PROTOCOL_OPERATION Flag;
+  EFI_PCI_IO_PROTOCOL   *PciIo;
+  UINTN MapLength;
+  EFI_STATUSStatus;
+
+  if (Trb->Read) {
+Flag = EfiPciIoOperationBusMasterWrite;
+  } else {
+Flag = EfiPciIoOperationBusMasterRead;
+  }
+
+  PciIo = Private->PciIo;
+  if (Trb->Data != NULL && Trb->DataLen != 0) {
+MapLength = Trb->DataLen;
+Status = PciIo->Map (
+  PciIo,
+  Flag,
+  Trb->Data,
+  ,
+  >DataPhy,
+  >DataMap
+  );
+if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
+  return EFI_BAD_BUFFER_SIZE;
+}
+  }
+
+  if (Trb->Mode == SdMmcAdma32bMode ||
+  Trb->Mode == SdMmcAdma64bV3Mode ||
+  Trb->Mode == SdMmcAdma64bV4Mode) {
+Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  }
+
+  return EFI_SUCCESS;
+}
+
 /**
   Create a new TRB for the SD/MMC cmd request.
 
@@ -1746,9 +1802,6 @@ SdMmcCreateTrb (
   SD_MMC_HC_TRB *Trb;
   EFI_STATUSStatus;
   EFI_TPL   OldTpl;
-  EFI_PCI_IO_PROTOCOL_OPERATION Flag;
-  EFI_PCI_IO_PROTOCOL   *PciIo;
-  UINTN MapLength;
 
   Trb = AllocateZeroPool (sizeof (SD_MMC_HC_TRB));
   if (Trb == NULL) {
@@ -1791,29 +1844,6 @@ SdMmcCreateTrb (
(Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) {
 Trb->Mode = SdMmcPioMode;
   } else {
-if (Trb->Read) {
-  Flag = EfiPciIoOperationBusMasterWrite;
-} else {
-  Flag = EfiPciIoOperationBusMasterRead;
-}
-
-PciIo = Private->PciIo;
-if (Trb->DataLen != 0) {
-  MapLength = Trb->DataLen;
-  Status = PciIo->Map (
-PciIo,
-Flag,
-Trb->Data,
-,
->DataPhy,
->DataMap
-);
-  if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) {
-Status = EFI_BAD_BUFFER_SIZE;
-goto Error;
-  }
-}
-
 if (Trb->DataLen == 0) {
   Trb->Mode = SdMmcNoData;
 } else if (Private->Capability[Slot].Adma2 != 0) {
@@ -1831,12 +1861,16 @@ SdMmcCreateTrb (
   if (Private->ControllerVersion[Slot] >= SD_MMC_HC_CTRL_VER_410) {
 Trb->AdmaLengthMode = SdMmcAdmaLen26b;
   }
-  Status = BuildAdmaDescTable (Trb, Private->ControllerVersion[Slot]);
+  Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);
   if (EFI_ERROR (Status)) {
 goto Error;
   }
 } else if (Private->Capability[Slot].Sdma != 0) {
   Trb->Mode = SdMmcSdmaMode;
+  Status = SdMmcSetupMemoryForDmaTransfer (Private, Slot, Trb);
+  if (EFI_ERROR (Status)) {
+goto Error;
+  }
 } else {
   Trb->Mode = SdMmcPioMode;
 }
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.

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jakiekolwiek
przegladanie lub rozpowszechnianie jest zabronione.
This 

[edk2-devel] [PATCHv2 0/1] MdeModulePkg/SdMmcPciHcDxe: Increase driver reliability

[Albecki, Mateusz]

This patch series aims to increase the reliability of the eMMC detection by 
exectuing the SEND_STATUS after SWITCH command on the lower frequency. 
Currently the driver will first switch the frequency to the new target and then 
execute SEND_STATUS to see if SWITCH was a success. While this behavior is not 
against the eMMC/SD specification it has been observed that on some designs 
switching to
HS200 @200MHz will make the SEND_STATUS fail consitently with CRC error(5/5 
times) while if we skip the SEND_STATUS and execute the clock tuning the link 
remains stable. My working theory (unconfirmed) is that CMD lane Tx path works 
fine so host is able to send command to the device (and that is why the clock 
tuning passes) but Rx path is broken so when device transmits response the CRC 
error is signaled(tuning command is a special case that doesn't send response 
on CMD). After the tuning is executed the CMD line seems to be working properly.

PATCHv2:
Removed unneccessary check in EmmcIsFrequencySupportedOnBusTiming as the code 
that calls bus timing switch has already validated the target frequency and any 
frequency lower then that is also valid.

Tests:
- Several platforms that have been failing before(some of them with 100% repro 
rate) have been stress tested and are able to detect eMMC device every time

Spec compliance:
While the spec doesn't require or forbids the host from sending the SEND_STATUS 
at any point in cards operation (with the exception of busy polling the SWITCH 
change but we are not doing that anyway) the HS200 switch sequence in eMMC 5.1 
specification section 6.6.2.2 indicates that host may send SEND_STATUS before 
changing the frequency. While it is not a hard requierment some eMMC vendors 
have indicated that the driver is at fault for not following the spec. After 
this patch the SEND_STATUS of every frequency upgrade path, including the 
switch from legacy timing -> HS200, will be sent before the frequency increase 
which will bring the driver closer to spec(although I don't think it can be 
said the driver violated it in the first place).

Github
https://github.com/malbecki/edk2/tree/emmc_stable_send_status

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 


Mateusz Albecki (1):
  MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c| 88 --
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c |  2 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |  1 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   |  2 +
 4 files changed, 69 insertions(+), 24 deletions(-)

-- 
2.14.1.windows.1



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ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.

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[edk2-devel] [PATCHv2 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140

To avoid stability issues on some designs the driver
will now send SEND_STATUS at previous, lower, frequency
when upgrading the bus timing.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c| 88 --
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c |  2 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |  1 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   |  2 +
 4 files changed, 69 insertions(+), 24 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 776c0e796c..8b5f8e8ee7 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -558,6 +558,43 @@ EmmcTuningClkForHs200 (
   return EFI_DEVICE_ERROR;
 }
 
+/**
+  Check the SWITCH operation status.
+
+  @param[in] PassThru  A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+  @param[in] Slot  The slot number on which command should be sent.
+  @param[in] Rca   The relative device address.
+
+  @retval EFI_SUCCESS  The SWITCH finished siccessfully.
+  @retval others   The SWITCH failed.
+**/
+EFI_STATUS
+EmmcCheckSwitchStatus (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN UINT8  Slot,
+  IN UINT16 Rca
+  )
+{
+  EFI_STATUS  Status;
+  UINT32  DevStatus;
+
+  Status = EmmcSendStatus (PassThru, Slot, Rca, );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: Send status fails with %r\n", 
Status));
+return Status;
+  }
+
+  //
+  // Check the switch operation is really successful or not.
+  //
+  if ((DevStatus & BIT7) != 0) {
+DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: The switch operation fails as 
DevStatus is 0x%08x\n", DevStatus));
+return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
+
 /**
   Switch the bus width to specified width.
 
@@ -591,7 +628,6 @@ EmmcSwitchBusWidth (
   UINT8   Index;
   UINT8   Value;
   UINT8   CmdSet;
-  UINT32  DevStatus;
 
   //
   // Write Byte, the Value field is written into the byte pointed by Index.
@@ -617,18 +653,10 @@ EmmcSwitchBusWidth (
 return Status;
   }
 
-  Status = EmmcSendStatus (PassThru, Slot, Rca, );
+  Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
   if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails with %r\n", 
Status));
 return Status;
   }
-  //
-  // Check the switch operation is really successful or not.
-  //
-  if ((DevStatus & BIT7) != 0) {
-DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: The switch operation fails as 
DevStatus is 0x%08x\n", DevStatus));
-return EFI_DEVICE_ERROR;
-  }
 
   Status = SdMmcHcSetBusWidth (PciIo, Slot, BusWidth);
 
@@ -669,9 +697,9 @@ EmmcSwitchBusTiming (
   UINT8 Index;
   UINT8 Value;
   UINT8 CmdSet;
-  UINT32DevStatus;
   SD_MMC_HC_PRIVATE_DATA*Private;
   UINT8 HostCtrl1;
+  BOOLEAN   DelaySendStatus;
 
   Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
   //
@@ -695,7 +723,7 @@ EmmcSwitchBusTiming (
   Value = 0;
   break;
 default:
-  DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d\n)", 
BusTiming));
+  DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d)\n", 
BusTiming));
   return EFI_INVALID_PARAMETER;
   }
 
@@ -724,6 +752,26 @@ EmmcSwitchBusTiming (
 return Status;
   }
 
+  //
+  // For cases when we switch bus timing to higher mode from current we want to
+  // send SEND_STATUS at current, lower, frequency then the target frequency 
to avoid
+  // stability issues. It has been observed that some designs are unable to 
process the
+  // SEND_STATUS at higher frequency during switch to HS200 @200MHz 
irrespective of the number of retries
+  // and only running the clock tuning is able to make them work at target 
frequency.
+  //
+  // For cases when we are downgrading the frequency and current high 
frequency is invalid
+  // we have to first change the frequency to target frequency and then send 
the SEND_STATUS.
+  //
+  if (Private->Slot[Slot].CurrentFreq < (ClockFreq * 1000)) {
+Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+DelaySendStatus = FALSE;
+  } else {
+DelaySendStatus = TRUE;
+  }
+
   //
   // Convert the clock freq unit from MHz to KHz.
   //
@@ -732,17 +780,11 @@ EmmcSwitchBusTiming (
 return Status;
   }
 
-  Status = EmmcSendStatus (PassThru, Slot, Rca, );
-  if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Send status fails with %r\n", 
Status));
-return Status;
-  }
-  //
-  // 

Re: [edk2-devel] [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency

[Albecki, Mateusz]

Hi,

Yes I am fine with this change being pushed after the stable tag.

Regarding the review comments - I will remove the 
EmmcIsFrequencySupportedOnBusTiming. When I first implemented it I thought that 
frequencies <26MHz are not supported on HS200/HS400 for some reason and I 
forgot to remove the extra check after I have found out that is not the case.

Thanks,
Mateusz

> -Original Message-
> From: Wu, Hao A 
> Sent: Monday, February 24, 2020 8:01 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming 
> Subject: RE: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send
> SEND_STATUS at lower frequency
> 
> > -Original Message-
> > From: Albecki, Mateusz
> > Sent: Friday, February 21, 2020 11:17 PM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao,
> > Liming
> > Subject: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send
> SEND_STATUS at
> > lower frequency
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
> >
> > To avoid stability issues on some designs the driver will now send
> > SEND_STATUS at previous, lower, frequency when upgrading the bus
> > timing.
> 
> 
> Hello Mateusz,
> 
> The patch looks like a refinement. So I plan to push it (after the reviewing
> process) after the upcoming stable tag. Does it work for you?
> 
> A couple of inline comments below:
> 
> 
> >
> > Cc: Hao A Wu 
> > Cc: Marcin Wojtas 
> > Cc: Zhichao Gao 
> > Cc: Liming Gao 
> >
> > Signed-off-by: Mateusz Albecki 
> > ---
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c| 124
> > +
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c |   2 +-
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   1 +
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   |   2 +
> >  4 files changed, 105 insertions(+), 24 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > index 776c0e796c..c2ebd37623 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > @@ -558,6 +558,41 @@ EmmcTuningClkForHs200 (
> >return EFI_DEVICE_ERROR;
> >  }
> >
> > +/**
> > +  Check the SWITCH operation status.
> > +
> > +  @param[in] PassThru  A pointer to the
> > EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
> 
> 
> Please help to add the comments for parameters 'Slot' and 'Rca'.
> 
> 
> > +
> > +  @retval EFI_SUCCESS  The SWITCH finished siccessfully.
> > +  @retval others   The SWITCH failed.
> > +**/
> > +EFI_STATUS
> > +EmmcCheckSwitchStatus (
> > +  IN EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
> > +  IN UINT8  Slot,
> > +  IN UINT16 Rca
> > +  )
> > +{
> > +  EFI_STATUS  Status;
> > +  UINT32  DevStatus;
> > +
> > +  Status = EmmcSendStatus (PassThru, Slot, Rca, );  if
> > + (EFI_ERROR (Status)) {
> > +DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: Send status fails
> > with %r\n", Status));
> > +return Status;
> > +  }
> > +
> > +  //
> > +  // Check the switch operation is really successful or not.
> > +  //
> > +  if ((DevStatus & BIT7) != 0) {
> > +DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: The switch
> > operation fails as DevStatus is 0x%08x\n", DevStatus));
> > +return EFI_DEVICE_ERROR;
> > +  }
> > +
> > +  return EFI_SUCCESS;
> > +}
> > +
> >  /**
> >Switch the bus width to specified width.
> >
> > @@ -591,7 +626,6 @@ EmmcSwitchBusWidth (
> >UINT8   Index;
> >UINT8   Value;
> >UINT8   CmdSet;
> > -  UINT32  DevStatus;
> >
> >//
> >// Write Byte, the Value field is written into the byte pointed by Index.
> > @@ -617,24 +651,53 @@ EmmcSwitchBusWidth (
> >  return Status;
> >}
> >
> > -  Status = EmmcSendStatus (PassThru, Slot, Rca, );
> > +  Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
> >if (EFI_ERROR (Status)) {
> > -DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails
> > with %r\n", Status));
> >  return Status;
> >}
> > -  //
> > -  // Check the switch operation is really successful or not.
> > -  //
> > -  if ((DevStatus & BIT7) != 0

[edk2-devel] [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140

To avoid stability issues on some designs the driver
will now send SEND_STATUS at previous, lower, frequency
when upgrading the bus timing.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c| 124 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c |   2 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   1 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   |   2 +
 4 files changed, 105 insertions(+), 24 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 776c0e796c..c2ebd37623 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -558,6 +558,41 @@ EmmcTuningClkForHs200 (
   return EFI_DEVICE_ERROR;
 }
 
+/**
+  Check the SWITCH operation status.
+
+  @param[in] PassThru  A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+
+  @retval EFI_SUCCESS  The SWITCH finished siccessfully.
+  @retval others   The SWITCH failed.
+**/
+EFI_STATUS
+EmmcCheckSwitchStatus (
+  IN EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
+  IN UINT8  Slot,
+  IN UINT16 Rca
+  )
+{
+  EFI_STATUS  Status;
+  UINT32  DevStatus;
+
+  Status = EmmcSendStatus (PassThru, Slot, Rca, );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: Send status fails with %r\n", 
Status));
+return Status;
+  }
+
+  //
+  // Check the switch operation is really successful or not.
+  //
+  if ((DevStatus & BIT7) != 0) {
+DEBUG ((DEBUG_ERROR, "EmmcCheckSwitchStatus: The switch operation fails as 
DevStatus is 0x%08x\n", DevStatus));
+return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
+
 /**
   Switch the bus width to specified width.
 
@@ -591,7 +626,6 @@ EmmcSwitchBusWidth (
   UINT8   Index;
   UINT8   Value;
   UINT8   CmdSet;
-  UINT32  DevStatus;
 
   //
   // Write Byte, the Value field is written into the byte pointed by Index.
@@ -617,24 +651,53 @@ EmmcSwitchBusWidth (
 return Status;
   }
 
-  Status = EmmcSendStatus (PassThru, Slot, Rca, );
+  Status = EmmcCheckSwitchStatus (PassThru, Slot, Rca);
   if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: Send status fails with %r\n", 
Status));
 return Status;
   }
-  //
-  // Check the switch operation is really successful or not.
-  //
-  if ((DevStatus & BIT7) != 0) {
-DEBUG ((DEBUG_ERROR, "EmmcSwitchBusWidth: The switch operation fails as 
DevStatus is 0x%08x\n", DevStatus));
-return EFI_DEVICE_ERROR;
-  }
 
   Status = SdMmcHcSetBusWidth (PciIo, Slot, BusWidth);
 
   return Status;
 }
 
+/**
+  Checks if given clock frequency is supported on
+  given bus timing.
+
+  @param[in] ClockFreq  Clock frequency to check in KHz.
+  @param[in] BusTiming  Bus timing against which frequency will be compared.
+
+  @retval TRUE   Frequency is valid for given bus timing.
+  @retval FALSE  Frequency is invalid for given bus timing.
+**/
+BOOLEAN
+EmmcIsFrequencySupportedOnBusTiming (
+  IN UINT64   ClockFreq,
+  IN SD_MMC_BUS_MODE  BusTiming
+  )
+{
+  UINT32  MaxFreq;
+
+  switch (BusTiming) {
+case SdMmcMmcLegacy:
+  MaxFreq = 26000;
+  break;
+case SdMmcMmcHsSdr:
+case SdMmcMmcHsDdr:
+  MaxFreq = 52000;
+  break;
+case SdMmcMmcHs200:
+case SdMmcMmcHs400:
+  MaxFreq = 20;
+  break;
+default:
+  return FALSE;
+  }
+
+  return (ClockFreq <= MaxFreq);
+}
+
 /**
   Switch the bus timing and clock frequency.
 
@@ -669,9 +732,9 @@ EmmcSwitchBusTiming (
   UINT8 Index;
   UINT8 Value;
   UINT8 CmdSet;
-  UINT32DevStatus;
   SD_MMC_HC_PRIVATE_DATA*Private;
   UINT8 HostCtrl1;
+  BOOLEAN   DelaySendStatus;
 
   Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
   //
@@ -695,7 +758,7 @@ EmmcSwitchBusTiming (
   Value = 0;
   break;
 default:
-  DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d\n)", 
BusTiming));
+  DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d)\n", 
BusTiming));
   return EFI_INVALID_PARAMETER;
   }
 
@@ -724,6 +787,27 @@ EmmcSwitchBusTiming (
 return Status;
   }
 
+  //
+  // For cases when we switch bus timing to higher mode from current we want to
+  // send SEND_STATUS at current, lower, frequency then the target frequency 
to avoid
+  // stability issues. It has been observed that some designs are unable to 
process the
+  // SEND_STATUS at higher frequency during switch to HS200 @200MHz 
irrespective of the number of retries
+  // and only running the clock tuning is able to make them work on target 
frequency.
+  //
+  // For 

[edk2-devel] [PATCH 0/1] MdeModulePkg/SdMmcPciHcDxe: Increase driver reliability

[Albecki, Mateusz]

This patch series aims to increase the reliability of the eMMC detection by
exectuing the SEND_STATUS after SWITCH command on the lower frequency. Currently
the driver will first switch the frequency to the new target and then execute
SEND_STATUS to see if SWITCH was a success. While this behavior is not against 
the
eMMC/SD specification it has been observed that on some designs switching to
HS200 @200MHz will make the SEND_STATUS fail consitently with CRC error(5/5 
times) while if
we skip the SEND_STATUS and execute the clock tuning the link remains stable. 
My working
theory (unconfirmed) is that CMD lane Tx path works fine so host is able to 
send command to the device
(and that is why the clock tuning passes) but Rx path is broken so when device 
transmits
response the CRC error is signaled(tuning command is a special case that 
doesn't send
response on CMD). After the tuning is executed the CMD line seems to be working 
properly.

Tests:
- Several platforms that have been failing before(some of them with 100% repro 
rate) have been stress tested and are able to detect eMMC device every time

Spec compliance:
While the spec doesn't require or forbids the host from sending the SEND_STATUS 
at any point in cards operation
(with the exception of busy polling the SWITCH change but we are not doing that 
anyway) the HS200 switch
sequence in eMMC 5.1 specification section 6.6.2.2 indicates that host may send 
SEND_STATUS before changing the
frequency. While it is not a hard requierment some eMMC vendors have indicated 
that the driver is at fault for
not following the spec. After this patch the SEND_STATUS of every frequency 
upgrade path, including the switch
from legacy timing -> HS200, will be sent before the frequency increase which 
will bring the driver closer to
spec(although I don't think it can be said the driver violated it in the first 
place).

Github
https://github.com/malbecki/edk2/tree/emmc_stable_send_status

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Mateusz Albecki (1):
  MdeModulePkg/SdMmcPciHcDxe: Send SEND_STATUS at lower frequency

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c| 124 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c |   2 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   1 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   |   2 +
 4 files changed, 105 insertions(+), 24 deletions(-)

-- 
2.14.1.windows.1



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Re: [edk2-devel] [PATCHv2 0/4] MdeModulePkg/SdMmcPciHcDxe: Refactor command processing

[Albecki, Mateusz]

Hi,

After fixing the test app code(thanks Hao for reminding me that 
UEFI_APPLICATION is not the same as UEFI_DRIVER). I was able to execute 5 async 
writes and 5 async reads to eMMC device using PIO mode. Logs below:

Scheduling write 0
Scheduling write 1
Scheduling write 2
Scheduling write 3
Scheduling write 4
All writes scheduled
Emmc Async Request: CmdIndex[6] Arg[03B3] Success
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[25] Arg[] Success
Write Event done
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[25] Arg[0001] Success
Write Event done
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[25] Arg[0002] Success
Write Event done
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[25] Arg[0003] Success
Write Event done
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[25] Arg[0004] Success
Write Event done
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[18] Arg[] Success
Dumping read buffer
 1 2 5 3 4 2 1 5 0 11
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[18] Arg[0001] Success
Dumping read buffer
 1 2 5 3 4 2 1 5 0 11
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[18] Arg[0002] Success
Dumping read buffer
 1 2 5 3 4 2 1 5 0 11
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[18] Arg[0003] Success
Dumping read buffer
 1 2 5 3 4 2 1 5 0 11
Emmc Async Request: CmdIndex[23] Arg[0001] Success
Emmc Async Request: CmdIndex[18] Arg[0004] Success
Dumping read buffer
 1 2 5 3 4 2 1 5 0 11

Thanks,
Mateusz

> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Albecki,
> Mateusz
> Sent: Thursday, February 20, 2020 1:36 PM
> To: Wu, Hao A ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming 
> Subject: Re: [edk2-devel] [PATCHv2 0/4] MdeModulePkg/SdMmcPciHcDxe:
> Refactor command processing
> 
> Hi,
> 
> Github with test code:
> https://github.com/malbecki/edk2/tree/test_code_for_async
> 
> This test code was used as is on Platform2 and it worked if I have only
> scheduled one request. On platform 1 I had to rebuild it a couple of times to
> make it read instead of writing when testing after reboot.
> 
> Regarding the push - I am fine with this change making it to master after the
> stable tag.
> 
> Thanks,
> Mateusz
> 
> > -Original Message-
> > From: Wu, Hao A 
> > Sent: Thursday, February 20, 2020 1:40 AM
> > To: Albecki, Mateusz ; devel@edk2.groups.io
> > Cc: Marcin Wojtas ; Gao, Zhichao
> > ; Gao, Liming 
> > Subject: RE: [PATCHv2 0/4] MdeModulePkg/SdMmcPciHcDxe: Refactor
> > command processing
> >
> > > -Original Message-----
> > > From: Albecki, Mateusz
> > > Sent: Thursday, February 20, 2020 12:05 AM
> > > To: devel@edk2.groups.io
> > > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao,
> > > Liming
> > > Subject: [PATCHv2 0/4] MdeModulePkg/SdMmcPciHcDxe: Refactor
> > command
> > > processing
> > >
> > > This patch series aims to refactor command processing to achieve
> > > following
> > >
> > > - Trace the failing TRB packets to see what commands are failing and
> > > for what reasons
> > > - Get the response data even if data transfer timed out to allow
> > > easier debugging
> > > - Fix the PIO mode which is currently completely broken.
> > >
> > > Changes in v2:
> > > - Moved verbose packet prints after the command is finished to
> > > capture the successfull command response
> > > - Fixed the debug prints
> > > - PIO data will be moved with width matching the alignment of the
> > > block
> > size.
> > > For majority of transfers that means UINT32 width.
> > >
> > > Tests performed:
> > > - Each patch in the series has passed boot from eMMC with ADMAv3
> > > data transfer mode
> > > - SDMA based boot has been tested with the full patch series
> > > - PIO based boot has been tested with the full patch series
> > > - PIO based data transfer has been additionally tested by creating
> > > and modyfing a file in EFI shell
> > > - Tested async PIO transfer - results below
> > >
> > > Async test results:
> > > I've tested a simple async write and then readback from the eMMMC
> > > device using block IO v2. I have observed that while the requests
> > > are processed correctly by the eMM

Re: [edk2-devel] [PATCHv2 0/4] MdeModulePkg/SdMmcPciHcDxe: Refactor command processing

[Albecki, Mateusz]

Hi,

Github with test code: https://github.com/malbecki/edk2/tree/test_code_for_async

This test code was used as is on Platform2 and it worked if I have only 
scheduled one request. On platform 1 I had to rebuild it a couple of times to 
make it read instead of writing when testing after reboot.

Regarding the push - I am fine with this change making it to master after the 
stable tag.

Thanks,
Mateusz

> -Original Message-
> From: Wu, Hao A 
> Sent: Thursday, February 20, 2020 1:40 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming 
> Subject: RE: [PATCHv2 0/4] MdeModulePkg/SdMmcPciHcDxe: Refactor
> command processing
> 
> > -Original Message-
> > From: Albecki, Mateusz
> > Sent: Thursday, February 20, 2020 12:05 AM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao,
> > Liming
> > Subject: [PATCHv2 0/4] MdeModulePkg/SdMmcPciHcDxe: Refactor
> command
> > processing
> >
> > This patch series aims to refactor command processing to achieve
> > following
> >
> > - Trace the failing TRB packets to see what commands are failing and
> > for what reasons
> > - Get the response data even if data transfer timed out to allow
> > easier debugging
> > - Fix the PIO mode which is currently completely broken.
> >
> > Changes in v2:
> > - Moved verbose packet prints after the command is finished to capture
> > the successfull command response
> > - Fixed the debug prints
> > - PIO data will be moved with width matching the alignment of the block
> size.
> > For majority of transfers that means UINT32 width.
> >
> > Tests performed:
> > - Each patch in the series has passed boot from eMMC with ADMAv3 data
> > transfer mode
> > - SDMA based boot has been tested with the full patch series
> > - PIO based boot has been tested with the full patch series
> > - PIO based data transfer has been additionally tested by creating and
> > modyfing a file in EFI shell
> > - Tested async PIO transfer - results below
> >
> > Async test results:
> > I've tested a simple async write and then readback from the eMMMC
> > device using block IO v2. I have observed that while the requests are
> > processed correctly by the eMMC driver as soon as they finish platform
> > will sometimes mibehave. I've tested async without my changes and the
> > strange behavior reproduces. Right now I am suspecting there is some
> > problem either in the EDK2 core that performs async or in the platform
> > specific code. It is also possible that I coded the Async BlockIo
> > incorrectly although the test code was rather simple. Additionally I
> > was able to observe that on many eMMC controllers PIO based data
> > transfer is broken.
> > I was only able to find one platform
> > that supported PIO. Detailed observation below
> >
> > Platform 1 (PIO working).
> > - Test code was able to perform async write to eMMC LBA 0
> > - As soon as the callback is called CPU exception happens
> > - After reboot test code was able to perform async read
> > - As soon as the callback is called CPU exception happens
> > - After reboot sync read was able to confirm that data matches what
> > was written by async write
> >
> > Platform2 (PIO is returning trash data - all 0xAF)
> > - Test code was able to perform async write(although it didn't realyl
> > came through to the device)
> > - After write finished test code was able to perform async read(again
> > all data was 0xAF but the logic in the driver works)
> >
> > Platform2 (again PIO is returning trash data)
> > - Test code scheduled 5 async writes. 2 writes finished and after that
> > CPU exception was signaled.
> >
> > Platform3(also trash data from PIO)
> > - Test code scheduled one async write as soon as it was done platform
> > rebooted
> >
> > I didn't want to spend any more time debugging this issue as I think
> > it would turn into the platform debug and what I observed gave me some
> > confidence that PIO in async is generally working.
> 
> 
> Hello Mateusz,
> 
> Could you help to share your async test codes?
> I can help to double confirm whether the issue you observed is related with
> them or not.
> 
> Also, since edk2 repo is under soft freeze period for the next stable tag, I
> would prefer for the series to get into the code base after the formal
> announce of the stable tag (2020-02-28). I will still give the 'Reviewed-by'
> after my review of the series though.
> 
> Do you have concern for t

[edk2-devel] [PATCHv2 0/4] MdeModulePkg/SdMmcPciHcDxe: Refactor command processing

[Albecki, Mateusz]

This patch series aims to refactor command processing to achieve following

- Trace the failing TRB packets to see what commands are failing and for what 
reasons
- Get the response data even if data transfer timed out to allow easier 
debugging
- Fix the PIO mode which is currently completely broken.

Changes in v2:
- Moved verbose packet prints after the command is finished to capture the 
successfull command response
- Fixed the debug prints
- PIO data will be moved with width matching the alignment of the block size. 
For majority of transfers that means UINT32 width.

Tests performed:
- Each patch in the series has passed boot from eMMC with ADMAv3 data transfer 
mode
- SDMA based boot has been tested with the full patch series
- PIO based boot has been tested with the full patch series
- PIO based data transfer has been additionally tested by creating and modyfing 
a file in EFI shell
- Tested async PIO transfer - results below

Async test results:
I've tested a simple async write and then readback from the eMMMC device using 
block IO v2. I have observed
that while the requests are processed correctly by the eMMC driver as soon as 
they finish platform will sometimes
mibehave. I've tested async without my changes and the strange behavior 
reproduces. Right now I am suspecting there
is some problem either in the EDK2 core that performs async or in the platform 
specific code. It is also possible that
I coded the Async BlockIo incorrectly although the test code was rather simple. 
Additionally I was able
to observe that on many eMMC controllers PIO based data transfer is broken. I 
was only able to find one platform
that supported PIO. Detailed observation below

Platform 1 (PIO working).
- Test code was able to perform async write to eMMC LBA 0
- As soon as the callback is called CPU exception happens
- After reboot test code was able to perform async read
- As soon as the callback is called CPU exception happens
- After reboot sync read was able to confirm that data matches what was written 
by async write

Platform2 (PIO is returning trash data - all 0xAF)
- Test code was able to perform async write(although it didn't realyl came 
through to the device)
- After write finished test code was able to perform async read(again all data 
was 0xAF but the logic in the driver works)

Platform2 (again PIO is returning trash data)
- Test code scheduled 5 async writes. 2 writes finished and after that CPU 
exception was signaled.

Platform3(also trash data from PIO)
- Test code scheduled one async write as soon as it was done platform rebooted

I didn't want to spend any more time debugging this issue as I think it would 
turn into the platform debug and what I
observed gave me some confidence that PIO in async is generally working.

All tests were performed with eMMC in HS400 @200MHz clock frequency.

For easier review & integration patch has been pushed here:
Whole series: https://github.com/malbecki/edk2/tree/emmc_transfer_refactor
Whole series + SDMA force code(test 3): 
https://github.com/malbecki/edk2/tree/emmc_transfer_refactor_force_sdma
Whole series + PIO force code(test 4): 
https://github.com/malbecki/edk2/tree/emmc_transfer_refactor_force_pio

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Mateusz Albecki (4):
  MdeModulePkg/SdMmcPciHcDxe: Enhance driver traces
  MdeModulePkg/SdMmcPciHcDxe: Read response on command completion
  MdeModulePkg/SdMmcPciHcDxe: Refactor data transfer completion
  MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   4 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 521 -
 2 files changed, 417 insertions(+), 108 deletions(-)

-- 
2.14.1.windows.1



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[edk2-devel] [PATCHv2 3/4] MdeModulePkg/SdMmcPciHcDxe: Refactor data transfer completion

[Albecki, Mateusz]

This patch refactors the way in which the driver will check
the data transfer completion. Data transfer related
functionalities have been moved to separate function.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 181 ++-
 1 file changed, 112 insertions(+), 69 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 38a8099426..5bdc200827 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -2444,6 +2444,112 @@ SdMmcCheckCommandComplete (
   return EFI_NOT_READY;
 }
 
+/**
+  Update the SDMA address on the SDMA buffer boundary interrupt.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS  Updated SDMA buffer address.
+  @retval Others   Failed to update SDMA buffer address.
+**/
+EFI_STATUS
+SdMmcUpdateSdmaAddress (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb
+  )
+{
+  UINT64  SdmaAddr;
+  EFI_STATUS  Status;
+
+  SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
+
+  if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_ADMA_SYS_ADDR,
+   FALSE,
+   sizeof (UINT64),
+   
+   );
+  } else {
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_SDMA_ADDR,
+   FALSE,
+   sizeof (UINT32),
+   
+   );
+  }
+
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
+  return EFI_SUCCESS;
+}
+
+/**
+  Checks if the data transfer completed and performs any actions
+  neccessary to continue the data transfer such as SDMA system
+  address fixup or PIO data transfer.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+  @param[in] IntStatus  Snapshot of the normal interrupt status register.
+
+  @retval EFI_SUCCESS   Data transfer completed successfully.
+  @retval EFI_NOT_READY Data transfer completion still pending.
+  @retval OthersData transfer failed to complete.
+**/
+EFI_STATUS
+SdMmcCheckDataTransfer (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb,
+  IN UINT16  IntStatus
+  )
+{
+  UINT16  Data16;
+  EFI_STATUS  Status;
+
+  if ((IntStatus & BIT1) != 0) {
+Data16 = BIT1;
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_NOR_INT_STS,
+   FALSE,
+   sizeof (Data16),
+   
+   );
+return Status;
+  }
+
+  if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) != 0)) {
+Data16 = BIT3;
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_NOR_INT_STS,
+   FALSE,
+   sizeof (Data16),
+   
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Status = SdMmcUpdateSdmaAddress (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  }
+
+  return EFI_NOT_READY;
+}
+
 /**
   Check the TRB execution result.
 
@@ -2464,7 +2570,6 @@ SdMmcCheckTrbResult (
   EFI_STATUS  Status;
   EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
   UINT16  IntStatus;
-  UINT64  SdmaAddr;
   UINT32  PioLength;
 
   Packet  = Trb->Packet;
@@ -2527,80 +2632,18 @@ SdMmcCheckTrbResult (
 Status = SdMmcCheckCommandComplete (Private, Trb, IntStatus);
 if (EFI_ERROR (Status)) {
   goto Done;
-} else {
-  //
-  // If the command doesn't require data transfer skip the transfer
-  // complete checking.
-  //
-  if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
-  (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
-  (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
-goto Done;
-  }
 }
   }
 
-  //
-  // Check Transfer Complete bit is set or not.
-  //
-  if ((IntStatus & BIT1) == BIT1) {
-goto Done;
-  }
-
-  //
-  // Check if DMA interrupt is signalled for the SDMA transfer.
-  //
-  if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
-//
-// Clear DMA interrupt bit.
-//
-IntStatus = BIT3;
-Status= SdMmcHcRwMmio (
-  Private->PciIo,
-  Trb->Slot,
-  

[edk2-devel] [PATCHv2 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode

[Albecki, Mateusz]

Current driver does not support PIO transfer mode for
commands other then tuning. This change adds the code
to transfer PIO data.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   3 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 132 +
 2 files changed, 114 insertions(+), 21 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 15b7d12596..fd89306fab 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -157,6 +157,9 @@ typedef struct {
   UINT64  Timeout;
   UINT32  Retries;
 
+  BOOLEAN PioModeTransferCompleted;
+  UINT32  PioBlockIndex;
+
   SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
   SD_MMC_HC_ADMA_64_V3_DESC_LINE  *Adma64V3Desc;
   SD_MMC_HC_ADMA_64_V4_DESC_LINE  *Adma64V4Desc;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 5bdc200827..73c43110f0 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1711,6 +1711,8 @@ SdMmcPrintTrb (
   DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete));
   DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout));
   DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
+  DEBUG ((DebugLevel, "PioModeTransferCompleted: %d\n", 
Trb->PioModeTransferCompleted));
+  DEBUG ((DebugLevel, "PioBlockIndex: %d\n", Trb->PioBlockIndex));
   DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc));
   DEBUG ((DebugLevel, "Adma64V3Desc: %p\n", Trb->Adma64V3Desc));
   DEBUG ((DebugLevel, "Adma64V4Desc: %p\n", Trb->Adma64V4Desc));
@@ -1762,6 +1764,8 @@ SdMmcCreateTrb (
   Trb->CommandComplete = FALSE;
   Trb->Timeout   = Packet->Timeout;
   Trb->Retries   = SD_MMC_TRB_RETRIES;
+  Trb->PioModeTransferCompleted = FALSE;
+  Trb->PioBlockIndex = 0;
   Trb->Private   = Private;
 
   if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
@@ -2444,6 +2448,104 @@ SdMmcCheckCommandComplete (
   return EFI_NOT_READY;
 }
 
+/**
+  Transfers data from card using PIO method.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+  @param[in] IntStatus  Snapshot of the normal interrupt status register.
+
+  @retval EFI_SUCCESS   PIO transfer completed successfully.
+  @retval EFI_NOT_READY PIO transfer completion still pending.
+  @retval OthersPIO transfer failed to complete.
+**/
+EFI_STATUS
+SdMmcTransferDataWithPio (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb,
+  IN UINT16  IntStatus
+  )
+{
+  EFI_STATUS  Status;
+  UINT16  Data16;
+  UINT32  BlockCount;
+  EFI_PCI_IO_PROTOCOL_WIDTH  Width;
+  UINTN   Count;
+
+  BlockCount = (Trb->DataLen / Trb->BlockSize);
+  if (Trb->DataLen % Trb->BlockSize != 0) {
+BlockCount += 1;
+  }
+
+  if (Trb->PioBlockIndex >= BlockCount) {
+return EFI_SUCCESS;
+  }
+
+  switch (Trb->BlockSize % sizeof (UINT32)) {
+case 0:
+  Width = EfiPciIoWidthFifoUint32;
+  Count = Trb->BlockSize / sizeof (UINT32);
+  break;
+case 2:
+  Width = EfiPciIoWidthFifoUint16;
+  Count = Trb->BlockSize / sizeof (UINT16);
+  break;
+case 1:
+case 3:
+default:
+  Width = EfiPciIoWidthFifoUint8;
+  Count = Trb->BlockSize;
+  break;
+}
+
+  if (Trb->Read) {
+if ((IntStatus & BIT5) == 0) {
+  return EFI_NOT_READY;
+}
+Data16 = BIT5;
+SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, 
sizeof (Data16), );
+
+Status = Private->PciIo->Mem.Read (
+   Private->PciIo,
+   Width,
+   Trb->Slot,
+   SD_MMC_HC_BUF_DAT_PORT,
+   Count,
+   (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * 
Trb->PioBlockIndex))
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Trb->PioBlockIndex++;
+  } else {
+if ((IntStatus & BIT4) == 0) {
+  return EFI_NOT_READY;
+}
+Data16 = BIT4;
+SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, 
sizeof (Data16), );
+
+Status = Private->PciIo->Mem.Write (
+   Private->PciIo,
+   Width,
+   Trb->Slot,
+   SD_MMC_HC_BUF_DAT_PORT,
+   Count,
+   (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * 
Trb->PioBlockIndex))
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Trb->PioBlockIndex++;
+  }
+
+  if (Trb->PioBlockIndex >= 

[edk2-devel] [PATCHv2 1/4] MdeModulePkg/SdMmcPciHcDxe: Enhance driver traces

[Albecki, Mateusz]

To allow for easier debug of failing commands we
have added a capability to print TRB and command
packet when we start execution of the TRB(on
DEBUG_VERBOSE level) and when the TRB failed to
execute correctly(on DEBUG_ERROR level). Additionally
we will also print error interrupt status and interrupt
status register on failed SD command.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 87 
 1 file changed, 87 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index b05c818462..9bf9963848 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1643,6 +1643,82 @@ BuildAdmaDescTable (
   return EFI_SUCCESS;
 }
 
+/**
+  Prints the contents of the command packet to the debug port.
+
+  @param[in] DebugLevel  Debug level at which the packet should be printed.
+  @param[in] Packet  Pointer to packet to print.
+**/
+VOID
+SdMmcPrintPacket (
+  IN UINT32   DebugLevel,
+  IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET  *Packet
+  )
+{
+  if (Packet == NULL) {
+return;
+  }
+
+  DEBUG ((DebugLevel, "Printing EFI_SD_MMC_PASS_THRU_COMMAND_PACKET\n"));
+  if (Packet->SdMmcCmdBlk != NULL) {
+DEBUG ((DebugLevel, "Command index: %d, argument: %X\n", 
Packet->SdMmcCmdBlk->CommandIndex, Packet->SdMmcCmdBlk->CommandArgument));
+DEBUG ((DebugLevel, "Command type: %d, response type: %d\n", 
Packet->SdMmcCmdBlk->CommandType, Packet->SdMmcCmdBlk->ResponseType));
+  }
+  if (Packet->SdMmcStatusBlk != NULL) {
+DEBUG ((DebugLevel, "Response 0: %X, 1: %X, 2: %X, 3: %X\n",
+   Packet->SdMmcStatusBlk->Resp0,
+   Packet->SdMmcStatusBlk->Resp1,
+   Packet->SdMmcStatusBlk->Resp2,
+   Packet->SdMmcStatusBlk->Resp3
+   ));
+  }
+  DEBUG ((DebugLevel, "Timeout: %ld\n", Packet->Timeout));
+  DEBUG ((DebugLevel, "InDataBuffer: %p\n", Packet->InDataBuffer));
+  DEBUG ((DebugLevel, "OutDataBuffer: %p\n", Packet->OutDataBuffer));
+  DEBUG ((DebugLevel, "InTransferLength: %d\n", Packet->InTransferLength));
+  DEBUG ((DebugLevel, "OutTransferLength: %d\n", Packet->OutTransferLength));
+  DEBUG ((DebugLevel, "TransactionStatus: %r\n", Packet->TransactionStatus));
+}
+
+/**
+  Prints the contents of the TRB to the debug port.
+
+  @param[in] DebugLevel  Debug level at which the TRB should be printed.
+  @param[in] Trb Pointer to the TRB structure.
+**/
+VOID
+SdMmcPrintTrb (
+  IN UINT32 DebugLevel,
+  IN SD_MMC_HC_TRB  *Trb
+  )
+{
+  if (Trb == NULL) {
+return;
+  }
+
+  DEBUG ((DebugLevel, "Printing SD_MMC_HC_TRB\n"));
+  DEBUG ((DebugLevel, "Slot: %d\n", Trb->Slot));
+  DEBUG ((DebugLevel, "BlockSize: %d\n", Trb->BlockSize));
+  DEBUG ((DebugLevel, "Data: %p\n", Trb->Data));
+  DEBUG ((DebugLevel, "DataLen: %d\n", Trb->DataLen));
+  DEBUG ((DebugLevel, "Read: %d\n", Trb->Read));
+  DEBUG ((DebugLevel, "DataPhy: %lX\n", Trb->DataPhy));
+  DEBUG ((DebugLevel, "DataMap: %p\n", Trb->DataMap));
+  DEBUG ((DebugLevel, "Mode: %d\n", Trb->Mode));
+  DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode));
+  DEBUG ((DebugLevel, "Event: %p\n", Trb->Event));
+  DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));
+  DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout));
+  DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
+  DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc));
+  DEBUG ((DebugLevel, "Adma64V3Desc: %p\n", Trb->Adma64V3Desc));
+  DEBUG ((DebugLevel, "Adma64V4Desc: %p\n", Trb->Adma64V4Desc));
+  DEBUG ((DebugLevel, "AdmaMap: %p\n", Trb->AdmaMap));
+  DEBUG ((DebugLevel, "AdmaPages: %X\n", Trb->AdmaPages));
+
+  SdMmcPrintPacket (DebugLevel, Trb->Packet);
+}
+
 /**
   Create a new TRB for the SD/MMC cmd request.
 
@@ -2235,6 +2311,10 @@ SdMmcCheckAndRecoverErrors (
 return Status;
   }
 
+  DEBUG ((DEBUG_ERROR, "Error reported by SDHCI\n"));
+  DEBUG ((DEBUG_ERROR, "Interrupt status = %X\n", IntStatus));
+  DEBUG ((DEBUG_ERROR, "Error interrupt status = %X\n", ErrIntStatus));
+
   //
   // If the data timeout error is reported
   // but data transfer is signaled as completed we
@@ -2438,6 +2518,13 @@ Done:
 
   if (Status != EFI_NOT_READY) {
 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "TRB failed with %r\n", Status));
+  SdMmcPrintTrb (DEBUG_ERROR, Trb);
+} else {
+  DEBUG ((DEBUG_VERBOSE, "TRB success\n"));
+  SdMmcPrintTrb (DEBUG_VERBOSE, Trb);
+}
   }
 
   return Status;
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
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[edk2-devel] [PATCHv2 2/4] MdeModulePkg/SdMmcPciHcDxe: Read response on command completion

[Albecki, Mateusz]

SdMmcPciHcDxe driver used to read response only after
command and data transfer completed. According to SDHCI
specification response data is ready after the command
complete status is set by the host controller. Getting
the response data early will help debugging the cases
when command completed but data transfer timed out.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   1 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 201 +++--
 2 files changed, 144 insertions(+), 58 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 5bc3577ba2..15b7d12596 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -153,6 +153,7 @@ typedef struct {
 
   EFI_EVENT   Event;
   BOOLEAN Started;
+  BOOLEAN CommandComplete;
   UINT64  Timeout;
   UINT32  Retries;
 
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 9bf9963848..38a8099426 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1708,6 +1708,7 @@ SdMmcPrintTrb (
   DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode));
   DEBUG ((DebugLevel, "Event: %p\n", Trb->Event));
   DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));
+  DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete));
   DEBUG ((DebugLevel, "Timeout: %ld\n", Trb->Timeout));
   DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
   DEBUG ((DebugLevel, "Adma32Desc: %p\n", Trb->Adma32Desc));
@@ -1758,6 +1759,7 @@ SdMmcCreateTrb (
   Trb->Packet= Packet;
   Trb->Event = Event;
   Trb->Started   = FALSE;
+  Trb->CommandComplete = FALSE;
   Trb->Timeout   = Packet->Timeout;
   Trb->Retries   = SD_MMC_TRB_RETRIES;
   Trb->Private   = Private;
@@ -2349,6 +2351,99 @@ SdMmcCheckAndRecoverErrors (
   return ErrorStatus;
 }
 
+/**
+  Reads the response data into the TRB buffer.
+  This function assumes that caller made sure that
+  command has completed.
+
+  @param[in] Private  A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb  The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS  Response read successfully.
+  @retval Others   Failed to get response.
+**/
+EFI_STATUS
+SdMmcGetResponse (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb
+  )
+{
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET  *Packet;
+  UINT8Index;
+  UINT32   Response[4];
+  EFI_STATUS   Status;
+
+  Packet = Trb->Packet;
+
+  if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeBc) {
+return EFI_SUCCESS;
+  }
+
+  for (Index = 0; Index < 4; Index++) {
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_RESPONSE + Index * 4,
+   TRUE,
+   sizeof (UINT32),
+   [Index]
+   );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+}
+  CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Checks if the command completed. If the command
+  completed it gets the response and records the
+  command completion in the TRB.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+  @param[in] IntStatus  Snapshot of the normal interrupt status register.
+
+  @retval EFI_SUCCESS   Command completed successfully.
+  @retval EFI_NOT_READY Command completion still pending.
+  @retval OthersCommand failed to complete.
+**/
+EFI_STATUS
+SdMmcCheckCommandComplete (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb,
+  IN UINT16  IntStatus
+  )
+{
+  UINT16  Data16;
+  EFI_STATUS  Status;
+
+  if ((IntStatus & BIT0) != 0) {
+Data16 = BIT0;
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_NOR_INT_STS,
+   FALSE,
+   sizeof (Data16),
+   
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Status = SdMmcGetResponse (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Trb->CommandComplete = TRUE;
+return EFI_SUCCESS;
+  }
+
+  return EFI_NOT_READY;
+}
+
 /**
   Check the TRB execution result.
 
@@ -2369,9 +2464,7 @@ SdMmcCheckTrbResult (
   EFI_STATUS  Status;
   EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
   UINT16   

Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode

[Albecki, Mateusz]

I will write a test code and update the results in next patch series.

Regarding the buffer data port read. Reading the spec I am not entirely sure on 
the behavior of the host when the data transfer is not aligned to DWORD 
boundary. I will test it with width set to 32bit and if that works I will fix 
it in v2.

Thanks,
Mateusz
> -Original Message-
> From: Wu, Hao A 
> Sent: Wednesday, February 5, 2020 4:16 AM
> To: devel@edk2.groups.io; Albecki, Mateusz 
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming 
> Subject: RE: [edk2-devel] [PATCH 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix
> PIO transfer mode
> 
> > -Original Message-
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Albecki, Mateusz
> > Sent: Monday, February 03, 2020 10:19 PM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao,
> > Liming
> > Subject: [edk2-devel] [PATCH 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix
> PIO
> > transfer mode
> >
> > Current driver does not support PIO transfer mode for commands other
> > then tuning. This change adds the code to transfer PIO data.
> 
> 
> Hello Mateusz,
> 
> Try to provide some feedbacks before I can test the patch.
> 
> One test request, is it possible for you to test the asynchronous transfer for
> the PIO mode?
> 
> A possible method can be using an UEFI application to locate the BlockIO 2
> protocol from a specific SD or eMMC device (which forced to PIO transfer
> mode).
> And test with the WriteBlocksEx() & ReadBlocksEx() services to see if the RW
> is successful.
> 
> Also, one more inline comment below:
> 
> 
> >
> > Cc: Hao A Wu 
> > Cc: Marcin Wojtas 
> > Cc: Zhichao Gao 
> > Cc: Liming Gao 
> >
> > Signed-off-by: Mateusz Albecki 
> > ---
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   3 +
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 113
> > +
> >  2 files changed, 95 insertions(+), 21 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > index 15b7d12596..fd89306fab 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > @@ -157,6 +157,9 @@ typedef struct {
> >UINT64  Timeout;
> >UINT32  Retries;
> >
> > +  BOOLEAN PioModeTransferCompleted;
> > +  UINT32  PioBlockIndex;
> > +
> >SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
> >SD_MMC_HC_ADMA_64_V3_DESC_LINE  *Adma64V3Desc;
> >SD_MMC_HC_ADMA_64_V4_DESC_LINE  *Adma64V4Desc;
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > index 480a1664ea..43703974f7 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > @@ -1711,6 +1711,8 @@ SdMmcPrintTrb (
> >DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb-
> > >CommandComplete));
> >DEBUG ((DebugLevel, "Timeout: %d\n", Trb->Timeout));
> >DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
> > +  DEBUG ((DebugLevel, "PioModeTransferCompleted: %d\n", Trb-
> > >PioModeTransferCompleted));
> > +  DEBUG ((DebugLevel, "PioBlockIndex: %d\n", Trb->PioBlockIndex));
> >DEBUG ((DebugLevel, "Adma32Desc: %X\n", Trb->Adma32Desc));
> >DEBUG ((DebugLevel, "Adma64V3Desc: %X\n", Trb->Adma64V3Desc));
> >DEBUG ((DebugLevel, "Adma64V4Desc: %X\n", Trb->Adma64V4Desc));
> > @@ -1762,6 +1764,8 @@ SdMmcCreateTrb (
> >Trb->CommandComplete = FALSE;
> >Trb->Timeout   = Packet->Timeout;
> >Trb->Retries   = SD_MMC_TRB_RETRIES;
> > +  Trb->PioModeTransferCompleted = FALSE;
> > +  Trb->PioBlockIndex = 0;
> >Trb->Private   = Private;
> >
> >if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
> > @@ -2447,6 +2451,85 @@ SdMmcCheckCommandComplete (
> >return EFI_NOT_READY;
> >  }
> >
> > +/**
> > +  Transfers data from card using PIO method.
> > +
> > +  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA
> > instance.
> > +  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
> > +  @param[in

Re: [edk2-devel] [PATCH 3/4] MdeModulePkg/SdMmcPciHcDxe: Refactor data transfer completion

[Albecki, Mateusz]

Hi,

As in the patch 2/4 section 3.7.1.2 recommends that we clear the transfer 
complete(step 6) just after reading it(step 5).

Thanks,
Mateusz

> -Original Message-
> From: Wu, Hao A 
> Sent: Wednesday, February 5, 2020 4:16 AM
> To: devel@edk2.groups.io; Albecki, Mateusz 
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming 
> Subject: RE: [edk2-devel] [PATCH 3/4] MdeModulePkg/SdMmcPciHcDxe:
> Refactor data transfer completion
> 
> Just a similar question to PATCH 2/4 below:
> 
> 
> > -Original Message-
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Albecki, Mateusz
> > Sent: Monday, February 03, 2020 10:19 PM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao,
> > Liming
> > Subject: [edk2-devel] [PATCH 3/4] MdeModulePkg/SdMmcPciHcDxe:
> > Refactor data transfer completion
> >
> > This patch refactors the way in which the driver will check the data
> > transfer completion. Data transfer related functionalities have been
> > moved to separate function.
> >
> > Cc: Hao A Wu 
> > Cc: Marcin Wojtas 
> > Cc: Zhichao Gao 
> > Cc: Liming Gao 
> >
> > Signed-off-by: Mateusz Albecki 
> > ---
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 181
> > ++-
> >  1 file changed, 112 insertions(+), 69 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > index 3dfaae8542..480a1664ea 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > @@ -2447,6 +2447,112 @@ SdMmcCheckCommandComplete (
> >return EFI_NOT_READY;
> >  }
> >
> > +/**
> > +  Update the SDMA address on the SDMA buffer boundary interrupt.
> > +
> > +  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA
> > instance.
> > +  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
> > +
> > +  @retval EFI_SUCCESS  Updated SDMA buffer address.
> > +  @retval Others   Failed to update SDMA buffer address.
> > +**/
> > +EFI_STATUS
> > +SdMmcUpdateSdmaAddress (
> > +  IN SD_MMC_HC_PRIVATE_DATA  *Private,
> > +  IN SD_MMC_HC_TRB   *Trb
> > +  )
> > +{
> > +  UINT64  SdmaAddr;
> > +  EFI_STATUS  Status;
> > +
> > +  SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy,
> > SD_MMC_SDMA_BOUNDARY);
> > +
> > +  if (Private->ControllerVersion[Trb->Slot] >=
> > + SD_MMC_HC_CTRL_VER_400)
> > {
> > +Status = SdMmcHcRwMmio (
> > +   Private->PciIo,
> > +   Trb->Slot,
> > +   SD_MMC_HC_ADMA_SYS_ADDR,
> > +   FALSE,
> > +   sizeof (UINT64),
> > +   
> > +   );
> > +  } else {
> > +Status = SdMmcHcRwMmio (
> > +   Private->PciIo,
> > +   Trb->Slot,
> > +   SD_MMC_HC_SDMA_ADDR,
> > +   FALSE,
> > +   sizeof (UINT32),
> > +   
> > +   );
> > +  }
> > +
> > +  if (EFI_ERROR (Status)) {
> > +return Status;
> > +  }
> > +
> > +  Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
> > +  return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > +  Checks if the data transfer completed and performs any actions
> > +  neccessary to continue the data transfer such as SDMA system
> > +  address fixup or PIO data transfer.
> > +
> > +  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA
> > instance.
> > +  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
> > +  @param[in] IntStatus  Snapshot of the normal interrupt status register.
> > +
> > +  @retval EFI_SUCCESS   Data transfer completed successfully.
> > +  @retval EFI_NOT_READY Data transfer completion still pending.
> > +  @retval OthersData transfer failed to complete.
> > +**/
> > +EFI_STATUS
> > +SdMmcCheckDataTransfer (
> > +  IN SD_MMC_HC_PRIVATE_DATA  *Private,
> > +  IN SD_MMC_HC_TRB   *Trb,
> > +  IN UINT16  IntStatus
> > +  )
> > +{
> > +  UINT16  Data16;
> > +  EFI_STATUS  Status;
> > +
> > +  if ((IntStatus & BIT1) != 0) {
> > +Data16 = BIT1;
> > +Status = SdMmcHcRwMmio (
> > +   Private->PciIo,
> > +   

Re: [edk2-devel] [PATCH 2/4] MdeModulePkg/SdMmcPciHcDxe: Read response on command completion

[Albecki, Mateusz]

Hi,

Yes, the new behavior should be more aligned with the SD host controller spec. 
I have been referring to section 3.7.1.2 The sequence to finalize a command 
which recommends to clear the interrupt in step 2 and then get the response 
data in step 3.

Thanks,
Mateusz

> -Original Message-
> From: Wu, Hao A 
> Sent: Wednesday, February 5, 2020 4:16 AM
> To: devel@edk2.groups.io; Albecki, Mateusz 
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming 
> Subject: RE: [edk2-devel] [PATCH 2/4] MdeModulePkg/SdMmcPciHcDxe:
> Read response on command completion
> 
> One question below:
> 
> 
> > -Original Message-
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Albecki, Mateusz
> > Sent: Monday, February 03, 2020 10:19 PM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao,
> > Liming
> > Subject: [edk2-devel] [PATCH 2/4] MdeModulePkg/SdMmcPciHcDxe: Read
> > response on command completion
> >
> > SdMmcPciHcDxe driver used to read response only after command and
> data
> > transfer completed. According to SDHCI specification response data is
> > ready after the command complete status is set by the host controller.
> > Getting the response data early will help debugging the cases when
> > command completed but data transfer timed out.
> >
> > Cc: Hao A Wu 
> > Cc: Marcin Wojtas 
> > Cc: Zhichao Gao 
> > Cc: Liming Gao 
> >
> > Signed-off-by: Mateusz Albecki 
> > ---
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   1 +
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 201
> > +++--
> >  2 files changed, 144 insertions(+), 58 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > index 5bc3577ba2..15b7d12596 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > @@ -153,6 +153,7 @@ typedef struct {
> >
> >EFI_EVENT   Event;
> >BOOLEAN Started;
> > +  BOOLEAN CommandComplete;
> >UINT64  Timeout;
> >UINT32  Retries;
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > index 959645bf26..3dfaae8542 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > @@ -1708,6 +1708,7 @@ SdMmcPrintTrb (
> >DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb-
> >AdmaLengthMode));
> >DEBUG ((DebugLevel, "Event: %d\n", Trb->Event));
> >DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));
> > +  DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb-
> > >CommandComplete));
> >DEBUG ((DebugLevel, "Timeout: %d\n", Trb->Timeout));
> >DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
> >DEBUG ((DebugLevel, "Adma32Desc: %X\n", Trb->Adma32Desc)); @@
> > -1758,6 +1759,7 @@ SdMmcCreateTrb (
> >Trb->Packet= Packet;
> >Trb->Event = Event;
> >Trb->Started   = FALSE;
> > +  Trb->CommandComplete = FALSE;
> >Trb->Timeout   = Packet->Timeout;
> >Trb->Retries   = SD_MMC_TRB_RETRIES;
> >Trb->Private   = Private;
> > @@ -2352,6 +2354,99 @@ SdMmcCheckAndRecoverErrors (
> >return ErrorStatus;
> >  }
> >
> > +/**
> > +  Reads the response data into the TRB buffer.
> > +  This function assumes that caller made sure that
> > +  command has completed.
> > +
> > +  @param[in] Private  A pointer to the SD_MMC_HC_PRIVATE_DATA
> > instance.
> > +  @param[in] Trb  The pointer to the SD_MMC_HC_TRB instance.
> > +
> > +  @retval EFI_SUCCESS  Response read successfully.
> > +  @retval Others   Failed to get response.
> > +**/
> > +EFI_STATUS
> > +SdMmcGetResponse (
> > +  IN SD_MMC_HC_PRIVATE_DATA  *Private,
> > +  IN SD_MMC_HC_TRB   *Trb
> > +  )
> > +{
> > +  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET  *Packet;
> > +  UINT8Index;
> > +  UINT32   Response[4];
> > +  EFI_STATUS   Status;
> > +
> > +  Packet = Trb->Packet;
> > +
> >

[edk2-devel] [PATCH 2/4] MdeModulePkg/SdMmcPciHcDxe: Read response on command completion

[Albecki, Mateusz]

SdMmcPciHcDxe driver used to read response only after
command and data transfer completed. According to SDHCI
specification response data is ready after the command
complete status is set by the host controller. Getting
the response data early will help debugging the cases
when command completed but data transfer timed out.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   1 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 201 +++--
 2 files changed, 144 insertions(+), 58 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 5bc3577ba2..15b7d12596 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -153,6 +153,7 @@ typedef struct {
 
   EFI_EVENT   Event;
   BOOLEAN Started;
+  BOOLEAN CommandComplete;
   UINT64  Timeout;
   UINT32  Retries;
 
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 959645bf26..3dfaae8542 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1708,6 +1708,7 @@ SdMmcPrintTrb (
   DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode));
   DEBUG ((DebugLevel, "Event: %d\n", Trb->Event));
   DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));
+  DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete));
   DEBUG ((DebugLevel, "Timeout: %d\n", Trb->Timeout));
   DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
   DEBUG ((DebugLevel, "Adma32Desc: %X\n", Trb->Adma32Desc));
@@ -1758,6 +1759,7 @@ SdMmcCreateTrb (
   Trb->Packet= Packet;
   Trb->Event = Event;
   Trb->Started   = FALSE;
+  Trb->CommandComplete = FALSE;
   Trb->Timeout   = Packet->Timeout;
   Trb->Retries   = SD_MMC_TRB_RETRIES;
   Trb->Private   = Private;
@@ -2352,6 +2354,99 @@ SdMmcCheckAndRecoverErrors (
   return ErrorStatus;
 }
 
+/**
+  Reads the response data into the TRB buffer.
+  This function assumes that caller made sure that
+  command has completed.
+
+  @param[in] Private  A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] Trb  The pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS  Response read successfully.
+  @retval Others   Failed to get response.
+**/
+EFI_STATUS
+SdMmcGetResponse (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb
+  )
+{
+  EFI_SD_MMC_PASS_THRU_COMMAND_PACKET  *Packet;
+  UINT8Index;
+  UINT32   Response[4];
+  EFI_STATUS   Status;
+
+  Packet = Trb->Packet;
+
+  if (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeBc) {
+return EFI_SUCCESS;
+  }
+
+  for (Index = 0; Index < 4; Index++) {
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_RESPONSE + Index * 4,
+   TRUE,
+   sizeof (UINT32),
+   [Index]
+   );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+}
+  CopyMem (Packet->SdMmcStatusBlk, Response, sizeof (Response));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Checks if the command completed. If the command
+  completed it gets the response and records the
+  command completion in the TRB.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+  @param[in] IntStatus  Snapshot of the normal interrupt status register.
+
+  @retval EFI_SUCCESS   Command completed successfully.
+  @retval EFI_NOT_READY Command completion still pending.
+  @retval OthersCommand failed to complete.
+**/
+EFI_STATUS
+SdMmcCheckCommandComplete (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb,
+  IN UINT16  IntStatus
+  )
+{
+  UINT16  Data16;
+  EFI_STATUS  Status;
+
+  if ((IntStatus & BIT0) != 0) {
+Data16 = BIT0;
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_NOR_INT_STS,
+   FALSE,
+   sizeof (Data16),
+   
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Status = SdMmcGetResponse (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Trb->CommandComplete = TRUE;
+return EFI_SUCCESS;
+  }
+
+  return EFI_NOT_READY;
+}
+
 /**
   Check the TRB execution result.
 
@@ -2372,9 +2467,7 @@ SdMmcCheckTrbResult (
   EFI_STATUS  Status;
   EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
   UINT16

[edk2-devel] [PATCH 4/4] MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode

[Albecki, Mateusz]

Current driver does not support PIO transfer mode for
commands other then tuning. This change adds the code
to transfer PIO data.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   3 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 113 +
 2 files changed, 95 insertions(+), 21 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 15b7d12596..fd89306fab 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -157,6 +157,9 @@ typedef struct {
   UINT64  Timeout;
   UINT32  Retries;
 
+  BOOLEAN PioModeTransferCompleted;
+  UINT32  PioBlockIndex;
+
   SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
   SD_MMC_HC_ADMA_64_V3_DESC_LINE  *Adma64V3Desc;
   SD_MMC_HC_ADMA_64_V4_DESC_LINE  *Adma64V4Desc;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 480a1664ea..43703974f7 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1711,6 +1711,8 @@ SdMmcPrintTrb (
   DEBUG ((DebugLevel, "CommandComplete: %d\n", Trb->CommandComplete));
   DEBUG ((DebugLevel, "Timeout: %d\n", Trb->Timeout));
   DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
+  DEBUG ((DebugLevel, "PioModeTransferCompleted: %d\n", 
Trb->PioModeTransferCompleted));
+  DEBUG ((DebugLevel, "PioBlockIndex: %d\n", Trb->PioBlockIndex));
   DEBUG ((DebugLevel, "Adma32Desc: %X\n", Trb->Adma32Desc));
   DEBUG ((DebugLevel, "Adma64V3Desc: %X\n", Trb->Adma64V3Desc));
   DEBUG ((DebugLevel, "Adma64V4Desc: %X\n", Trb->Adma64V4Desc));
@@ -1762,6 +1764,8 @@ SdMmcCreateTrb (
   Trb->CommandComplete = FALSE;
   Trb->Timeout   = Packet->Timeout;
   Trb->Retries   = SD_MMC_TRB_RETRIES;
+  Trb->PioModeTransferCompleted = FALSE;
+  Trb->PioBlockIndex = 0;
   Trb->Private   = Private;
 
   if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
@@ -2447,6 +2451,85 @@ SdMmcCheckCommandComplete (
   return EFI_NOT_READY;
 }
 
+/**
+  Transfers data from card using PIO method.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+  @param[in] IntStatus  Snapshot of the normal interrupt status register.
+
+  @retval EFI_SUCCESS   PIO transfer completed successfully.
+  @retval EFI_NOT_READY PIO transfer completion still pending.
+  @retval OthersPIO transfer failed to complete.
+**/
+EFI_STATUS
+SdMmcTransferDataWithPio (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb,
+  IN UINT16  IntStatus
+  )
+{
+  EFI_STATUS  Status;
+  UINT16  Data16;
+  UINT32  BlockCount;
+
+  BlockCount = (Trb->DataLen / Trb->BlockSize);
+  if (Trb->DataLen % Trb->BlockSize != 0) {
+BlockCount += 1;
+  }
+
+  if (Trb->PioBlockIndex >= BlockCount) {
+return EFI_SUCCESS;
+  }
+
+  if (Trb->Read) {
+if ((IntStatus & BIT5) == 0) {
+  return EFI_NOT_READY;
+}
+Data16 = BIT5;
+SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, 
sizeof (Data16), );
+
+Status = Private->PciIo->Mem.Read (
+   Private->PciIo,
+   EfiPciIoWidthFifoUint8,
+   Trb->Slot,
+   SD_MMC_HC_BUF_DAT_PORT,
+   Trb->BlockSize,
+   (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * 
Trb->PioBlockIndex))
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Trb->PioBlockIndex++;
+  } else {
+if ((IntStatus & BIT4) == 0) {
+  return EFI_NOT_READY;
+}
+Data16 = BIT4;
+SdMmcHcRwMmio (Private->PciIo, Trb->Slot, SD_MMC_HC_NOR_INT_STS, FALSE, 
sizeof (Data16), );
+
+Status = Private->PciIo->Mem.Write (
+   Private->PciIo,
+   EfiPciIoWidthFifoUint8,
+   Trb->Slot,
+   SD_MMC_HC_BUF_DAT_PORT,
+   Trb->BlockSize,
+   (VOID*)((UINT8*)Trb->Data + (Trb->BlockSize * 
Trb->PioBlockIndex))
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Trb->PioBlockIndex++;
+  }
+
+  if (Trb->PioBlockIndex >= BlockCount) {
+Trb->PioModeTransferCompleted = TRUE;
+return EFI_SUCCESS;
+  } else {
+return EFI_NOT_READY;
+  }
+}
+
 /**
   Update the SDMA address on the SDMA buffer boundary interrupt.
 
@@ -2531,6 +2614,13 @@ SdMmcCheckDataTransfer (
 return Status;
   }
 
+  if (Trb->Mode == SdMmcPioMode && !Trb->PioModeTransferCompleted) {
+Status = SdMmcTransferDataWithPio (Private, Trb, IntStatus);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  }
+
   if 

[edk2-devel] [PATCH 3/4] MdeModulePkg/SdMmcPciHcDxe: Refactor data transfer completion

[Albecki, Mateusz]

This patch refactors the way in which the driver will check
the data transfer completion. Data transfer related
functionalities have been moved to separate function.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 181 ++-
 1 file changed, 112 insertions(+), 69 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 3dfaae8542..480a1664ea 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -2447,6 +2447,112 @@ SdMmcCheckCommandComplete (
   return EFI_NOT_READY;
 }
 
+/**
+  Update the SDMA address on the SDMA buffer boundary interrupt.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+
+  @retval EFI_SUCCESS  Updated SDMA buffer address.
+  @retval Others   Failed to update SDMA buffer address.
+**/
+EFI_STATUS
+SdMmcUpdateSdmaAddress (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb
+  )
+{
+  UINT64  SdmaAddr;
+  EFI_STATUS  Status;
+
+  SdmaAddr = SD_MMC_SDMA_ROUND_UP ((UINTN)Trb->DataPhy, SD_MMC_SDMA_BOUNDARY);
+
+  if (Private->ControllerVersion[Trb->Slot] >= SD_MMC_HC_CTRL_VER_400) {
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_ADMA_SYS_ADDR,
+   FALSE,
+   sizeof (UINT64),
+   
+   );
+  } else {
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_SDMA_ADDR,
+   FALSE,
+   sizeof (UINT32),
+   
+   );
+  }
+
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  Trb->DataPhy = (UINT64)(UINTN)SdmaAddr;
+  return EFI_SUCCESS;
+}
+
+/**
+  Checks if the data transfer completed and performs any actions
+  neccessary to continue the data transfer such as SDMA system
+  address fixup or PIO data transfer.
+
+  @param[in] PrivateA pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] TrbThe pointer to the SD_MMC_HC_TRB instance.
+  @param[in] IntStatus  Snapshot of the normal interrupt status register.
+
+  @retval EFI_SUCCESS   Data transfer completed successfully.
+  @retval EFI_NOT_READY Data transfer completion still pending.
+  @retval OthersData transfer failed to complete.
+**/
+EFI_STATUS
+SdMmcCheckDataTransfer (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb,
+  IN UINT16  IntStatus
+  )
+{
+  UINT16  Data16;
+  EFI_STATUS  Status;
+
+  if ((IntStatus & BIT1) != 0) {
+Data16 = BIT1;
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_NOR_INT_STS,
+   FALSE,
+   sizeof (Data16),
+   
+   );
+return Status;
+  }
+
+  if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) != 0)) {
+Data16 = BIT3;
+Status = SdMmcHcRwMmio (
+   Private->PciIo,
+   Trb->Slot,
+   SD_MMC_HC_NOR_INT_STS,
+   FALSE,
+   sizeof (Data16),
+   
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+Status = SdMmcUpdateSdmaAddress (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  }
+
+  return EFI_NOT_READY;
+}
+
 /**
   Check the TRB execution result.
 
@@ -2467,7 +2573,6 @@ SdMmcCheckTrbResult (
   EFI_STATUS  Status;
   EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet;
   UINT16  IntStatus;
-  UINT64  SdmaAddr;
   UINT32  PioLength;
 
   Packet  = Trb->Packet;
@@ -2530,80 +2635,18 @@ SdMmcCheckTrbResult (
 Status = SdMmcCheckCommandComplete (Private, Trb, IntStatus);
 if (EFI_ERROR (Status)) {
   goto Done;
-} else {
-  //
-  // If the command doesn't require data transfer skip the transfer
-  // complete checking.
-  //
-  if ((Packet->SdMmcCmdBlk->CommandType != SdMmcCommandTypeAdtc) &&
-  (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR1b) &&
-  (Packet->SdMmcCmdBlk->ResponseType != SdMmcResponseTypeR5b)) {
-goto Done;
-  }
 }
   }
 
-  //
-  // Check Transfer Complete bit is set or not.
-  //
-  if ((IntStatus & BIT1) == BIT1) {
-goto Done;
-  }
-
-  //
-  // Check if DMA interrupt is signalled for the SDMA transfer.
-  //
-  if ((Trb->Mode == SdMmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {
-//
-// Clear DMA interrupt bit.
-//
-IntStatus = BIT3;
-Status= SdMmcHcRwMmio (
-  Private->PciIo,
-  Trb->Slot,
-  

[edk2-devel] [PATCH 1/4] MdeModulePkg/SdMmcPciHcDxe: Enhance driver traces

[Albecki, Mateusz]

To allow for easier debug of failing commands we
have added a capability to print TRB and command
packet when we start execution of the TRB(on
DEBUG_VERBOSE level) and when the TRB failed to
execute correctly(on DEBUG_ERROR level). Additionally
we will also print error interrupt status and interrupt
status register on failed SD command.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 87 
 1 file changed, 87 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index b05c818462..959645bf26 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1643,6 +1643,82 @@ BuildAdmaDescTable (
   return EFI_SUCCESS;
 }
 
+/**
+  Prints the contents of the command packet to the debug port.
+
+  @param[in] DebugLevel  Debug level at which the packet should be printed.
+  @param[in] Packet  Pointer to packet to print.
+**/
+VOID
+SdMmcPrintPacket (
+  IN UINT32   DebugLevel,
+  IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET  *Packet
+  )
+{
+  if (Packet == NULL) {
+return;
+  }
+
+  DEBUG ((DebugLevel, "Printing EFI_SD_MMC_PASS_THRU_COMMAND_PACKET\n"));
+  if (Packet->SdMmcCmdBlk != NULL) {
+DEBUG ((DebugLevel, "Command index: %d, argument: %X\n", 
Packet->SdMmcCmdBlk->CommandIndex, Packet->SdMmcCmdBlk->CommandArgument));
+DEBUG ((DebugLevel, "Command type: %d, response type: %d\n", 
Packet->SdMmcCmdBlk->CommandType, Packet->SdMmcCmdBlk->ResponseType));
+  }
+  if (Packet->SdMmcStatusBlk != NULL) {
+DEBUG ((DebugLevel, "Response 0: %X, 1: %X, 2: %X, 3: %X\n",
+   Packet->SdMmcStatusBlk->Resp0,
+   Packet->SdMmcStatusBlk->Resp1,
+   Packet->SdMmcStatusBlk->Resp2,
+   Packet->SdMmcStatusBlk->Resp3
+   ));
+  }
+  DEBUG ((DebugLevel, "Timeout: %d\n", Packet->Timeout));
+  DEBUG ((DebugLevel, "InDataBuffer: %X\n", Packet->InDataBuffer));
+  DEBUG ((DebugLevel, "OutDataBuffer: %X\n", Packet->OutDataBuffer));
+  DEBUG ((DebugLevel, "InTransferLength: %d\n", Packet->InTransferLength));
+  DEBUG ((DebugLevel, "OutTransferLength: %d\n", Packet->OutTransferLength));
+  DEBUG ((DebugLevel, "TransactionStatus: %r\n", Packet->TransactionStatus));
+}
+
+/**
+  Prints the contents of the TRB to the debug port.
+
+  @param[in] DebugLevel  Debug level at which the TRB should be printed.
+  @param[in] Trb Pointer to the TRB structure.
+**/
+VOID
+SdMmcPrintTrb (
+  IN UINT32 DebugLevel,
+  IN SD_MMC_HC_TRB  *Trb
+  )
+{
+  if (Trb == NULL) {
+return;
+  }
+
+  DEBUG ((DebugLevel, "Printing SD_MMC_HC_TRB\n"));
+  DEBUG ((DebugLevel, "Slot: %d\n", Trb->Slot));
+  DEBUG ((DebugLevel, "BlockSize: %d\n", Trb->BlockSize));
+  DEBUG ((DebugLevel, "Data: %X\n", Trb->Data));
+  DEBUG ((DebugLevel, "DataLen: %d\n", Trb->DataLen));
+  DEBUG ((DebugLevel, "Read: %d\n", Trb->Read));
+  DEBUG ((DebugLevel, "DataPhy: %X\n", Trb->DataPhy));
+  DEBUG ((DebugLevel, "DataMap: %X\n", Trb->DataMap));
+  DEBUG ((DebugLevel, "Mode: %d\n", Trb->Mode));
+  DEBUG ((DebugLevel, "AdmaLengthMode: %d\n", Trb->AdmaLengthMode));
+  DEBUG ((DebugLevel, "Event: %d\n", Trb->Event));
+  DEBUG ((DebugLevel, "Started: %d\n", Trb->Started));
+  DEBUG ((DebugLevel, "Timeout: %d\n", Trb->Timeout));
+  DEBUG ((DebugLevel, "Retries: %d\n", Trb->Retries));
+  DEBUG ((DebugLevel, "Adma32Desc: %X\n", Trb->Adma32Desc));
+  DEBUG ((DebugLevel, "Adma64V3Desc: %X\n", Trb->Adma64V3Desc));
+  DEBUG ((DebugLevel, "Adma64V4Desc: %X\n", Trb->Adma64V4Desc));
+  DEBUG ((DebugLevel, "AdmaMap: %X\n", Trb->AdmaMap));
+  DEBUG ((DebugLevel, "AdmaPages: %X\n", Trb->AdmaPages));
+
+  SdMmcPrintPacket (DebugLevel, Trb->Packet);
+}
+
 /**
   Create a new TRB for the SD/MMC cmd request.
 
@@ -1963,6 +2039,9 @@ SdMmcExecTrb (
   UINT64  AdmaAddr;
   BOOLEAN AddressingMode64;
 
+  DEBUG ((DEBUG_VERBOSE, "Starting TRB execution\n"));
+  SdMmcPrintTrb (DEBUG_VERBOSE, Trb);
+
   AddressingMode64 = FALSE;
 
   Packet = Trb->Packet;
@@ -2235,6 +2314,10 @@ SdMmcCheckAndRecoverErrors (
 return Status;
   }
 
+  DEBUG ((DEBUG_ERROR, "Error reported by SDHCI\n"));
+  DEBUG ((DEBUG_ERROR, "Interrupt status = %X\n", IntStatus));
+  DEBUG ((DEBUG_ERROR, "Error interrupt status = %X\n", ErrIntStatus));
+
   //
   // If the data timeout error is reported
   // but data transfer is signaled as completed we
@@ -2438,6 +2521,10 @@ Done:
 
   if (Status != EFI_NOT_READY) {
 SdMmcHcLedOnOff (Private->PciIo, Trb->Slot, FALSE);
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_ERROR, "TRB failed with %r\n", Status));
+  SdMmcPrintTrb (DEBUG_ERROR, Trb);
+}
   }
 
   return Status;
-- 
2.14.1.windows.1

[edk2-devel] [PATCH 0/4] MdeModulePkg/SdMmcPciHcDxe: Refactor command processing

[Albecki, Mateusz]

This patch series aims to refactor command processing to achieve following

1. Trace the failing TRB packets to see what commands are failing and for what 
reasons
2. Get the response data even if data transfer timed out to allow easier 
debugging
3. Fix the PIO mode which is currently completely broken.

Tests performed:
1. Each patch in the series has passed boot from eMMC with ADMAv3 data transfer 
mode
2. SDMA based boot has been tested with the full patch series
3. PIO based boot has been tested with the full patch series
4. PIO based data transfer has been additionally tested by creating and 
modyfing a file in EFI shell

All tests were performed with eMMC in HS400 @200MHz clock frequency.

For easier review & integration patch has been pushed here:
Whole series: https://github.com/malbecki/edk2/tree/emmc_transfer_refactor
Whole series + SDMA force code(test 3): 
https://github.com/malbecki/edk2/tree/emmc_transfer_refactor_force_sdma
Whole series + PIO force code(test 4): 
https://github.com/malbecki/edk2/tree/emmc_transfer_refactor_force_pio

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 


Mateusz Albecki (4):
  MdeModulePkg/SdMmcPciHcDxe: Enhance driver traces
  MdeModulePkg/SdMmcPciHcDxe: Read response on command completion
  MdeModulePkg/SdMmcPciHcDxe: Refactor data transfer completion
  MdeModulePkg/SdMmcPciHcDxe: Fix PIO transfer mode

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   4 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 502 -
 2 files changed, 398 insertions(+), 108 deletions(-)

-- 
2.14.1.windows.1



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[edk2-devel] [PATCHv2 4/4] MdeModulePkg/SdMmcPciHcDxe: Add retries for async commands

[Albecki, Mateusz]

This patch adds retries for async execution for commands that
failed due to the CRC errors.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
index 193b0f24e2..b18ff3e972 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
@@ -211,8 +211,10 @@ Done:
   gBS->SignalEvent (TrbEvent);
   return;
 }
-  }
-  if ((Trb != NULL) && (Status != EFI_NOT_READY)) {
+  } else if ((Trb != NULL) && (Status == EFI_CRC_ERROR) && (Trb->Retries > 0)) 
{
+Trb->Retries--;
+Trb->Started = FALSE;
+  } else if ((Trb != NULL)) {
 RemoveEntryList (Link);
 Trb->Packet->TransactionStatus = Status;
 TrbEvent = Trb->Event;
-- 
2.14.1.windows.1



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[edk2-devel] [PATCHv2 0/4] MdeModulePkg/SdMmcPciHcDxe: Retry the commands that failed due to CRC error

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140

Some of the boards report that just after we change the clock frequency to 
200MHz link is unable to stabilize fast enough and when driver sends the CMD13 
it will often fail randomly with CRC error. To protect against this kind of 
random failures this patch series will make the driver retry the commands that 
failed due to random CRC errors.

Since async code has not yet been tested it has been put into separate patch. 
That patch is not needed to solve most pressing CMD13 issues.

changes in v2:
-Split first patch into bugfix and refactor
-Normal interrupt status register will now only be read once during 
SdMmcCheckTrbResult
-We will no longer clear the data transfer timeout error in 
SdMmcCheckAndRecoverErrors. Instead we will immedieatly return for such case 
and register reset will be done in next SdMmcExecTrb

Tets performed:
-Boot eMMC in HS400
-Boot eMMC in HS400 with simulated CRC error on every first CMD13

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 


Mateusz Albecki (4):
  MdeModulePkg/SdMmcPciHcDxe: Fix DAT lane SW reset
  MdeModulePkg/SdMmcPciHcDxe: Refactor command error detection
  MdeModulePkg/SdMmcPciHcDxe: Add retries for sync commands
  MdeModulePkg/SdMmcPciHcDxe: Add retries for async commands

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c |  89 ++---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   5 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 218 ++---
 3 files changed, 204 insertions(+), 108 deletions(-)

-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
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[edk2-devel] [PATCHv2 2/4] MdeModulePkg/SdMmcPciHcDxe: Refactor command error detection

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140

Error detection function will now check if the command
failure has been caused by one of the errors that can
appear randomly on link(CRC error + end bit error). If
such an error has been a cause of failure, function will
return EFI_CRC_ERROR instead of EFI_DEVICE_ERROR to indicate
to the higher level that command has a chance of succeeding if
resent.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 215 +++
 1 file changed, 140 insertions(+), 75 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index b1f316d444..637455b400 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -2137,6 +2137,137 @@ SdMmcExecTrb (
   return Status;
 }
 
+/**
+  Performs SW reset based on passed error status mask.
+
+  @param[in]  Private   Pointer to driver private data.
+  @param[in]  Slot  Index of the slot to reset.
+  @param[in]  ErrIntStatus  Error interrupt status mask.
+
+  @retval EFI_SUCCESS  Software reset performed successfully.
+  @retval OtherSoftware reset failed.
+**/
+EFI_STATUS
+SdMmcSoftwareReset (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN UINT8   Slot,
+  IN UINT16  ErrIntStatus
+  )
+{
+  UINT8   SwReset;
+  EFI_STATUS  Status;
+
+  SwReset = 0;
+  if ((ErrIntStatus & 0x0F) != 0) {
+SwReset |= BIT1;
+  }
+  if ((ErrIntStatus & 0x70) != 0) {
+SwReset |= BIT2;
+  }
+
+  Status  = SdMmcHcRwMmio (
+  Private->PciIo,
+  Slot,
+  SD_MMC_HC_SW_RST,
+  FALSE,
+  sizeof (SwReset),
+  
+  );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  Status = SdMmcHcWaitMmioSet (
+ Private->PciIo,
+ Slot,
+ SD_MMC_HC_SW_RST,
+ sizeof (SwReset),
+ 0xFF,
+ 0,
+ SD_MMC_HC_GENERIC_TIMEOUT
+ );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Checks the error status in error status register
+  and issues appropriate software reset as described in
+  SD specification section 3.10.
+
+  @param[in] PrivatePointer to driver private data.
+  @param[in] TrbPointer to currently executing TRB.
+  @param[in] IntStatus  Normal interrupt status mask.
+
+  @retval EFI_CRC_ERROR  CRC error happened during CMD execution.
+  @retval EFI_SUCCESSNo error reported.
+  @retval Others Some other error happened.
+
+**/
+EFI_STATUS
+SdMmcCheckAndRecoverErrors (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN UINT8   Slot,
+  IN UINT16  IntStatus
+  )
+{
+  UINT16  ErrIntStatus;
+  EFI_STATUS  Status;
+  EFI_STATUS  ErrorStatus;
+
+  if ((IntStatus & BIT15) == 0) {
+return EFI_SUCCESS;
+  }
+
+  Status = SdMmcHcRwMmio (
+ Private->PciIo,
+ Slot,
+ SD_MMC_HC_ERR_INT_STS,
+ TRUE,
+ sizeof (ErrIntStatus),
+ 
+ );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  //
+  // If the data timeout error is reported
+  // but data transfer is signaled as completed we
+  // have to ignore data timeout. We also assume that no
+  // other error is present on the link since data transfer
+  // completed successfully. Error interrupt status
+  // register is going to be reset when the next command
+  // is started.
+  //
+  if (((ErrIntStatus & BIT4) != 0) && ((IntStatus & BIT1) != 0)) {
+return EFI_SUCCESS;
+  }
+
+  //
+  // We treat both CMD and DAT CRC errors and
+  // end bits errors as EFI_CRC_ERROR. This will
+  // let higher layer know that the error possibly
+  // happened due to random bus condition and the
+  // command can be retried.
+  //
+  if ((ErrIntStatus & (BIT1 | BIT2 | BIT5 | BIT6)) != 0) {
+ErrorStatus = EFI_CRC_ERROR;
+  } else {
+ErrorStatus = EFI_DEVICE_ERROR;
+  }
+
+  Status = SdMmcSoftwareReset (Private, Slot, ErrIntStatus);
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  return ErrorStatus;
+}
+
 /**
   Check the TRB execution result.
 
@@ -2160,10 +2291,8 @@ SdMmcCheckTrbResult (
   UINT32  Response[4];
   UINT64  SdmaAddr;
   UINT8   Index;
-  UINT8   SwReset;
   UINT32  PioLength;
 
-  SwReset = 0;
   Packet  = Trb->Packet;
   //
   // Check Trb execution result by reading Normal Interrupt Status register.
@@ -2179,87 +2308,23 @@ SdMmcCheckTrbResult (
   if (EFI_ERROR (Status)) {
 goto Done;
   }
+
   //
-  // Check Transfer Complete bit is set or not.
+  // Check if there are any errors reported by host 

[edk2-devel] [PATCHv2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add retries for sync commands

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140

To increase the resiliency driver will now attempt to
retry the commands that failed due to the CRC error up
to 5 times. This should address the problems with the commands
that fail due to random condition on links. This should also
help the boards on which CMD13 is particularly unstable after
switching the link frequency.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 83 ++
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |  5 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   |  1 +
 3 files changed, 59 insertions(+), 30 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
index 373f1bed45..193b0f24e2 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
@@ -7,7 +7,7 @@
   It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
 
   Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
-  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -974,6 +974,58 @@ SdMmcPciHcDriverBindingStop (
   return Status;
 }
 
+/**
+  Execute TRB synchronously.
+
+  @param[in] Private  Pointer to driver private data.
+  @param[in] Trb  Pointer to TRB to execute.
+
+  @retval EFI_SUCCESS  TRB executed successfully.
+  @retval OtherTRB failed.
+**/
+EFI_STATUS
+SdMmcPassThruExecSyncTrb (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb
+  )
+{
+  EFI_STATUS  Status;
+  EFI_TPL OldTpl;
+
+  //
+  // Wait async I/O list is empty before execute sync I/O operation.
+  //
+  while (TRUE) {
+OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+if (IsListEmpty (>Queue)) {
+  gBS->RestoreTPL (OldTpl);
+  break;
+}
+gBS->RestoreTPL (OldTpl);
+  }
+
+  while (Trb->Retries) {
+Status = SdMmcWaitTrbEnv (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+
+Status = SdMmcExecTrb (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+
+Status = SdMmcWaitTrbResult (Private, Trb);
+if (Status == EFI_CRC_ERROR) {
+  Trb->Retries--;
+} else {
+  return Status;
+}
+  }
+
+  return Status;
+}
+
 /**
   Sends SD command to an SD card that is attached to the SD controller.
 
@@ -1023,7 +1075,6 @@ SdMmcPassThruPassThru (
   EFI_STATUS  Status;
   SD_MMC_HC_PRIVATE_DATA  *Private;
   SD_MMC_HC_TRB   *Trb;
-  EFI_TPL OldTpl;
 
   if ((This == NULL) || (Packet == NULL)) {
 return EFI_INVALID_PARAMETER;
@@ -1066,34 +1117,8 @@ SdMmcPassThruPassThru (
 return EFI_SUCCESS;
   }
 
-  //
-  // Wait async I/O list is empty before execute sync I/O operation.
-  //
-  while (TRUE) {
-OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
-if (IsListEmpty (>Queue)) {
-  gBS->RestoreTPL (OldTpl);
-  break;
-}
-gBS->RestoreTPL (OldTpl);
-  }
-
-  Status = SdMmcWaitTrbEnv (Private, Trb);
-  if (EFI_ERROR (Status)) {
-goto Done;
-  }
-
-  Status = SdMmcExecTrb (Private, Trb);
-  if (EFI_ERROR (Status)) {
-goto Done;
-  }
+  Status = SdMmcPassThruExecSyncTrb (Private, Trb);
 
-  Status = SdMmcWaitTrbResult (Private, Trb);
-  if (EFI_ERROR (Status)) {
-goto Done;
-  }
-
-Done:
   SdMmcFreeTrb (Trb);
 
   return Status;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 0304960132..5bc3577ba2 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -3,7 +3,7 @@
   Provides some data structure definitions used by the SD/MMC host controller 
driver.
 
 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
-Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -130,6 +130,8 @@ typedef struct {
 
 #define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
 
+#define SD_MMC_TRB_RETRIES5
+
 //
 // TRB (Transfer Request Block) contains information for the cmd request.
 //
@@ -152,6 +154,7 @@ typedef struct {
   EFI_EVENT   Event;
   BOOLEAN Started;
   UINT64  Timeout;
+  UINT32  Retries;
 
   SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
   SD_MMC_HC_ADMA_64_V3_DESC_LINE  *Adma64V3Desc;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 637455b400..b0384a507a 100644
--- 

[edk2-devel] [PATCHv2 1/4] MdeModulePkg/SdMmcPciHcDxe: Fix DAT lane SW reset

[Albecki, Mateusz]

Driver used to reset the DAT lane on a current error which
is not required according to SD specification(it's not going
to help). This patch will reset the DAT lane only on DAT
lane specific errors.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index e7f2fac69b..b1f316d444 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -7,7 +7,7 @@
   It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
 
   Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
-  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -2229,7 +2229,7 @@ SdMmcCheckTrbResult (
 if ((IntStatus & 0x0F) != 0) {
   SwReset |= BIT1;
 }
-if ((IntStatus & 0xF0) != 0) {
+if ((IntStatus & 0x70) != 0) {
   SwReset |= BIT2;
 }
 
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
moze zawierac informacje poufne. W razie przypadkowego otrzymania tej 
wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; 
jakiekolwiek
przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole 
use of the intended recipient(s). If you are not the intended recipient, please 
contact the sender and delete all copies; any review or distribution by
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Re: [edk2-devel] [PATCH 1/3] MdeModulePkg/SdMmcPciHcDxe: Refactor command error detection

[Albecki, Mateusz]

Hi,

I will fix the 2 issues in separate patch probably before doing the refactor to 
avoid reverting it if the refactor introduces some unexpected issues.

Please also see inline.

Thanks,
Mateusz

> -Original Message-
> From: Wu, Hao A 
> Sent: Friday, January 10, 2020 6:38 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming 
> Subject: RE: [PATCH 1/3] MdeModulePkg/SdMmcPciHcDxe: Refactor
> command error detection
> 
> Hello Mateusz,
> 
> Some inline comments below:
> 
> 
> > -Original Message-
> > From: Albecki, Mateusz
> > Sent: Tuesday, January 07, 2020 7:06 PM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao,
> > Liming
> > Subject: [PATCH 1/3] MdeModulePkg/SdMmcPciHcDxe: Refactor
> command
> > error detection
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
> >
> > Error detection function will now check if the command failure has
> > been caused by one of the errors that can appear randomly on link(CRC
> > error + end bit error). If such an error has been a cause of failure
> > function will return EFI_CRC_ERROR instead of EFI_DEVICE_ERROR to
> > indicate to the higher level that command has a chance of succeeding
> > if resent. In addition this patch also fixes 2 small bugs. First one
> > is DAT lane being reset on current limit error. Second one is data
> > timeout error not being cleared after transfer has been completed.
> 
> 
> For the 2 small issues, I would suggest to split them into separate patches,
> which would make this patch into 3 patches. You can either do the
> refactoring or fixing the 2 bugs first.
> 
> 
> >
> > Cc: Hao A Wu 
> > Cc: Marcin Wojtas 
> > Cc: Zhichao Gao 
> > Cc: Liming Gao 
> >
> > Signed-off-by: Mateusz Albecki 
> > ---
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 234
> > +++
> >  1 file changed, 158 insertions(+), 76 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > index e7f2fac69b..8b5e54f321 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > @@ -7,7 +7,7 @@
> >It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer
> use.
> >
> >Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
> > -  Copyright (c) 2015 - 2019, Intel Corporation. All rights
> > reserved.
> > +  Copyright (c) 2015 - 2020, Intel Corporation. All rights
> > + reserved.
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> >  **/
> > @@ -2137,6 +2137,154 @@ SdMmcExecTrb (
> >return Status;
> >  }
> >
> > +/**
> > +  Performs SW reset based on passed error status mask.
> > +
> > +  @param[in]  Private   Pointer to driver private data.
> > +  @param[in]  Slot  Index of the slot to reset.
> > +  @param[in]  ErrIntStatus  Error interrupt status mask.
> > +
> > +  @retval EFI_SUCCESS  Software reset performed successfully.
> > +  @retval OtherSoftware reset failed.
> > +**/
> > +EFI_STATUS
> > +SdMmcSoftwareReset (
> > +  IN SD_MMC_HC_PRIVATE_DATA  *Private,
> > +  IN UINT8   Slot,
> > +  IN UINT16  ErrIntStatus
> > +  )
> > +{
> > +  UINT8   SwReset;
> > +  EFI_STATUS  Status;
> > +
> > +  SwReset = 0;
> > +  if ((ErrIntStatus & 0x0F) != 0) {
> > +SwReset |= BIT1;
> > +  }
> > +  if ((ErrIntStatus & 0x70) != 0) {
> 
> 
> Thanks for this catch.
> Could you help to separate this fix to another patch?
> 
> 
> > +SwReset |= BIT2;
> > +  }
> > +
> > +  Status  = SdMmcHcRwMmio (
> > +  Private->PciIo,
> > +  Slot,
> > +  SD_MMC_HC_SW_RST,
> > +  FALSE,
> > +  sizeof (SwReset),
> > +  
> > +  );
> > +  if (EFI_ERROR (Status)) {
> > +return Status;
> > +  }
> > +
> > +  Status = SdMmcHcWaitMmioSet (
> > + Private->PciIo,
> > + Slot,
> > + SD_MMC_HC_SW_RST,
> > + sizeof (SwReset),
> > + 0xFF,
> > + 0,
> > + SD_MMC_HC_GENERIC_TIMEOUT
> > + );
> > +  if (EFI_ERROR (Status)) {
> > +return St

[edk2-devel] [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix unknown doxygen tag error

[Albecki, Mateusz]

Changed @rtval to @retval in SdMmcHcStartSdClock
function description.

Cc: Hao A Wu 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index e7f2fac69b..d1e60938f9 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -765,7 +765,7 @@ SdMmcHcStopClock (
   @param[in] Slot   The slot number.
 
   @retval EFI_SUCCESS  Succeeded to start the SD clock.
-  @rtval  Others   Failed to start the SD clock.
+  @retval Others   Failed to start the SD clock.
 **/
 EFI_STATUS
 SdMmcHcStartSdClock (
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
index 4753bb6864..16229a846c 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
@@ -485,7 +485,7 @@ SdMmcHcStopClock (
   @param[in] Slot   The slot number.
 
   @retval EFI_SUCCESS  Succeeded to start the SD clock.
-  @rtval  Others   Failed to start the SD clock.
+  @retval Others   Failed to start the SD clock.
 **/
 EFI_STATUS
 SdMmcHcStartSdClock (
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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Re: [edk2-devel] [PATCH 0/3] MdeModulePkg/SdMmcPciHcDxe: Retry the commands that failed due to CRC error

[Albecki, Mateusz]

Missed github info:

Clean patch series is here: https://github.com/malbecki/edk2/tree/sdmmc_retries
Patch series with the applied CRC simulation code is here: 
https://github.com/malbecki/edk2/tree/sdmmc_retries_with_test_code

Thanks,
Mateusz

> -Original Message-
> From: Albecki, Mateusz 
> Sent: Tuesday, January 7, 2020 12:06 PM
> To: devel@edk2.groups.io
> Cc: Albecki, Mateusz ; Wu, Hao A
> ; Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming 
> Subject: [PATCH 0/3] MdeModulePkg/SdMmcPciHcDxe: Retry the
> commands that failed due to CRC error
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
> 
> Some of the boards report that just after we change the clock frequency to
> 200MHz link is unable to stabilize fast enough and when driver sends the
> CMD13 it will often fail randomly with CRC error. To protect against this kind
> of random failures this patch series will make the driver retry the commands
> that failed due to random CRC errors.
> 
> Since async code has not yet been tested it has been put into separate patch.
> That patch is not needed to solve most pressing CMD13 issues.
> 
> Tets performed:
> -Boot eMMC in HS400
> -Boot eMMC in HS400 with simulated CRC error on every first CMD13
> 
> Cc: Hao A Wu 
> Cc: Marcin Wojtas 
> Cc: Zhichao Gao 
> Cc: Liming Gao 
> 
> Signed-off-by: Mateusz Albecki 
> 
> Mateusz Albecki (3):
>   MdeModulePkg/SdMmcPciHcDxe: Refactor command error detection
>   MdeModulePkg/SdMmcPciHcDxe: Add retries for sync commands
>   MdeModulePkg/SdMmcPciHcDxe: Add retries for async commands
> 
>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c |  89 +---
>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   5 +-
>  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 235
> ++---
>  3 files changed, 221 insertions(+), 108 deletions(-)
> 
> --
> 2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
moze zawierac informacje poufne. W razie przypadkowego otrzymania tej 
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[edk2-devel] [PATCH 1/3] MdeModulePkg/SdMmcPciHcDxe: Refactor command error detection

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140

Error detection function will now check if the command
failure has been caused by one of the errors that can
appear randomly on link(CRC error + end bit error). If
such an error has been a cause of failure function will
return EFI_CRC_ERROR instead of EFI_DEVICE_ERROR to indicate
to the higher level that command has a chance of succeeding if
resent. In addition this patch also fixes 2 small bugs. First one
is DAT lane being reset on current limit error. Second one is
data timeout error not being cleared after transfer has been completed.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 234 +++
 1 file changed, 158 insertions(+), 76 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index e7f2fac69b..8b5e54f321 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -7,7 +7,7 @@
   It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
 
   Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
-  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -2137,6 +2137,154 @@ SdMmcExecTrb (
   return Status;
 }
 
+/**
+  Performs SW reset based on passed error status mask.
+
+  @param[in]  Private   Pointer to driver private data.
+  @param[in]  Slot  Index of the slot to reset.
+  @param[in]  ErrIntStatus  Error interrupt status mask.
+
+  @retval EFI_SUCCESS  Software reset performed successfully.
+  @retval OtherSoftware reset failed.
+**/
+EFI_STATUS
+SdMmcSoftwareReset (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN UINT8   Slot,
+  IN UINT16  ErrIntStatus
+  )
+{
+  UINT8   SwReset;
+  EFI_STATUS  Status;
+
+  SwReset = 0;
+  if ((ErrIntStatus & 0x0F) != 0) {
+SwReset |= BIT1;
+  }
+  if ((ErrIntStatus & 0x70) != 0) {
+SwReset |= BIT2;
+  }
+
+  Status  = SdMmcHcRwMmio (
+  Private->PciIo,
+  Slot,
+  SD_MMC_HC_SW_RST,
+  FALSE,
+  sizeof (SwReset),
+  
+  );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  Status = SdMmcHcWaitMmioSet (
+ Private->PciIo,
+ Slot,
+ SD_MMC_HC_SW_RST,
+ sizeof (SwReset),
+ 0xFF,
+ 0,
+ SD_MMC_HC_GENERIC_TIMEOUT
+ );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Checks the error status in error status register
+  and issues appropriate software reset as described in
+  SD specification section 3.10.
+
+  @param[in] Private  Pointer to driver private data.
+  @param[in] Trb  Pointer to currently executing TRB.
+
+  @retval EFI_CRC_ERROR  CRC error happened during CMD execution.
+  @retval EFI_SUCCESSNo error reported.
+  @retval Others Some other error happened.
+
+**/
+EFI_STATUS
+SdMmcCheckAndRecoverErrors (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN UINT8   Slot
+  )
+{
+  UINT16  IntStatus;
+  UINT16  ErrIntStatus;
+  UINT16  ErrIntStatusOr;
+  EFI_STATUS  Status;
+  EFI_STATUS  ErrorStatus;
+
+  Status = SdMmcHcRwMmio (
+ Private->PciIo,
+ Slot,
+ SD_MMC_HC_NOR_INT_STS,
+ TRUE,
+ sizeof (IntStatus),
+ 
+ );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  if ((IntStatus & BIT15) == 0) {
+return EFI_SUCCESS;
+  }
+
+  Status = SdMmcHcRwMmio (
+ Private->PciIo,
+ Slot,
+ SD_MMC_HC_ERR_INT_STS,
+ TRUE,
+ sizeof (ErrIntStatus),
+ 
+ );
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
+  //
+  // We treat both CMD and DAT CRC errors and
+  // end bits errors as EFI_CRC_ERROR. This will
+  // let higher layer know that the error possibly
+  // happened due to random bus condition and the
+  // command can be retried.
+  //
+  if (ErrIntStatus & (BIT1 | BIT2 | BIT5 | BIT6)) {
+ErrorStatus = EFI_CRC_ERROR;
+  } else if ((ErrIntStatus & BIT4) && (IntStatus & BIT1)){
+//
+// If the data timeout error is reported
+// but data transfer is signaled as completed we
+// have to ignore data timeout.
+//
+ErrorStatus = EFI_SUCCESS;
+ErrIntStatusOr = BIT4;
+Status = SdMmcHcOrMmio (
+   Private->PciIo,
+   Slot,
+   SD_MMC_HC_ERR_INT_STS,
+   sizeof (ErrIntStatus),
+   
+   );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  } else {
+ErrorStatus = 

[edk2-devel] [PATCH 2/3] MdeModulePkg/SdMmcPciHcDxe: Add retries for sync commands

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140

To increase the resiliency driver will now attempt to
retry the commands that failed due to the CRC error up
to 5 times. This should address the problems with the commands
that fail due to random condition on links. This should also
help the boards on which CMD13 is particularly unstable after
switching the link frequency.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 83 ++
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |  5 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   |  1 +
 3 files changed, 59 insertions(+), 30 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
index 373f1bed45..193b0f24e2 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
@@ -7,7 +7,7 @@
   It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
 
   Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
-  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -974,6 +974,58 @@ SdMmcPciHcDriverBindingStop (
   return Status;
 }
 
+/**
+  Execute TRB synchronously.
+
+  @param[in] Private  Pointer to driver private data.
+  @param[in] Trb  Pointer to TRB to execute.
+
+  @retval EFI_SUCCESS  TRB executed successfully.
+  @retval OtherTRB failed.
+**/
+EFI_STATUS
+SdMmcPassThruExecSyncTrb (
+  IN SD_MMC_HC_PRIVATE_DATA  *Private,
+  IN SD_MMC_HC_TRB   *Trb
+  )
+{
+  EFI_STATUS  Status;
+  EFI_TPL OldTpl;
+
+  //
+  // Wait async I/O list is empty before execute sync I/O operation.
+  //
+  while (TRUE) {
+OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
+if (IsListEmpty (>Queue)) {
+  gBS->RestoreTPL (OldTpl);
+  break;
+}
+gBS->RestoreTPL (OldTpl);
+  }
+
+  while (Trb->Retries) {
+Status = SdMmcWaitTrbEnv (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+
+Status = SdMmcExecTrb (Private, Trb);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+
+Status = SdMmcWaitTrbResult (Private, Trb);
+if (Status == EFI_CRC_ERROR) {
+  Trb->Retries--;
+} else {
+  return Status;
+}
+  }
+
+  return Status;
+}
+
 /**
   Sends SD command to an SD card that is attached to the SD controller.
 
@@ -1023,7 +1075,6 @@ SdMmcPassThruPassThru (
   EFI_STATUS  Status;
   SD_MMC_HC_PRIVATE_DATA  *Private;
   SD_MMC_HC_TRB   *Trb;
-  EFI_TPL OldTpl;
 
   if ((This == NULL) || (Packet == NULL)) {
 return EFI_INVALID_PARAMETER;
@@ -1066,34 +1117,8 @@ SdMmcPassThruPassThru (
 return EFI_SUCCESS;
   }
 
-  //
-  // Wait async I/O list is empty before execute sync I/O operation.
-  //
-  while (TRUE) {
-OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
-if (IsListEmpty (>Queue)) {
-  gBS->RestoreTPL (OldTpl);
-  break;
-}
-gBS->RestoreTPL (OldTpl);
-  }
-
-  Status = SdMmcWaitTrbEnv (Private, Trb);
-  if (EFI_ERROR (Status)) {
-goto Done;
-  }
-
-  Status = SdMmcExecTrb (Private, Trb);
-  if (EFI_ERROR (Status)) {
-goto Done;
-  }
+  Status = SdMmcPassThruExecSyncTrb (Private, Trb);
 
-  Status = SdMmcWaitTrbResult (Private, Trb);
-  if (EFI_ERROR (Status)) {
-goto Done;
-  }
-
-Done:
   SdMmcFreeTrb (Trb);
 
   return Status;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index 0304960132..5bc3577ba2 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -3,7 +3,7 @@
   Provides some data structure definitions used by the SD/MMC host controller 
driver.
 
 Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
-Copyright (c) 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -130,6 +130,8 @@ typedef struct {
 
 #define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
 
+#define SD_MMC_TRB_RETRIES5
+
 //
 // TRB (Transfer Request Block) contains information for the cmd request.
 //
@@ -152,6 +154,7 @@ typedef struct {
   EFI_EVENT   Event;
   BOOLEAN Started;
   UINT64  Timeout;
+  UINT32  Retries;
 
   SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
   SD_MMC_HC_ADMA_64_V3_DESC_LINE  *Adma64V3Desc;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 8b5e54f321..676ace847b 100644
--- 

[edk2-devel] [PATCH 3/3] MdeModulePkg/SdMmcPciHcDxe: Add retries for async commands

[Albecki, Mateusz]

This patch adds retries for async execution for commands that
failed due to the CRC errors.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
index 193b0f24e2..b18ff3e972 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
@@ -211,8 +211,10 @@ Done:
   gBS->SignalEvent (TrbEvent);
   return;
 }
-  }
-  if ((Trb != NULL) && (Status != EFI_NOT_READY)) {
+  } else if ((Trb != NULL) && (Status == EFI_CRC_ERROR) && (Trb->Retries > 0)) 
{
+Trb->Retries--;
+Trb->Started = FALSE;
+  } else if ((Trb != NULL)) {
 RemoveEntryList (Link);
 Trb->Packet->TransactionStatus = Status;
 TrbEvent = Trb->Event;
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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[edk2-devel] [PATCH 0/3] MdeModulePkg/SdMmcPciHcDxe: Retry the commands that failed due to CRC error

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140

Some of the boards report that just after we change the clock frequency to 
200MHz link is
unable to stabilize fast enough and when driver sends the CMD13 it will often 
fail
randomly with CRC error. To protect against this kind of random failures this 
patch
series will make the driver retry the commands that failed due to random CRC 
errors.

Since async code has not yet been tested it has been put into separate patch. 
That patch
is not needed to solve most pressing CMD13 issues.

Tets performed:
-Boot eMMC in HS400
-Boot eMMC in HS400 with simulated CRC error on every first CMD13

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 

Mateusz Albecki (3):
  MdeModulePkg/SdMmcPciHcDxe: Refactor command error detection
  MdeModulePkg/SdMmcPciHcDxe: Add retries for sync commands
  MdeModulePkg/SdMmcPciHcDxe: Add retries for async commands

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c |  89 +---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |   5 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 235 ++---
 3 files changed, 221 insertions(+), 108 deletions(-)

-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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Re: [edk2-devel] [PATCH 1/2] SdMmcPciHcDxe: Send EdkiiSdMmcSwitchClockFreq after SD clock start

[Albecki, Mateusz]

No problem with new subject from my side.

> -Original Message-
> From: Wu, Hao A 
> Sent: Tuesday, December 24, 2019 3:52 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas ; Gao, Zhichao
> ; Gao, Liming ; Ard
> Biesheuvel 
> Subject: RE: [PATCH 1/2] SdMmcPciHcDxe: Send EdkiiSdMmcSwitchClockFreq
> after SD clock start
> 
> > -Original Message-
> > From: Albecki, Mateusz
> > Sent: Saturday, December 21, 2019 1:13 AM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas; Gao, Zhichao; Gao,
> > Liming
> > Subject: [PATCH 1/2] SdMmcPciHcDxe: Send EdkiiSdMmcSwitchClockFreq
> > after SD clock start
> 
> 
> Hello Mateusz,
> 
> Just a minor format comment, how about changing the subject to:
> MdeModulePkg/SdMmcPciHcDxe: Hook SwitchClockFreq after SD clock start
> 
> If there is no other major concern from other reviewers for the patch, I will
> handle this when pushing the patch.
> 
> Reviewed-by: Hao A Wu 
> 
> Best Regards,
> Hao Wu
> 
> 
> >
> > For eMMC modules we used to notify the platform about frequency
> change
> > only after sending CMD13 which meant that platform might not get a
> > chance to apply required post frequency change fixes to get the clock
> > stable. To fix this notification has been moved to SdMmcHcClockSupply
> > function just after we start the SD clock. During first time setup the
> > notification won't be sent to avoid changing old behavior.
> >
> > Cc: Hao A Wu 
> > Cc: Marcin Wojtas 
> > Cc: Zhichao Gao 
> > Cc: Liming Gao 
> >
> > Signed-off-by: Mateusz Albecki 
> > ---
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c|  20 +---
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c  |  28 ++
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |  24 +
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 107
> +--
> > --
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h   |  44 -
> >  5 files changed, 81 insertions(+), 142 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > index 082904ccc5..776c0e796c 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > @@ -727,7 +727,7 @@ EmmcSwitchBusTiming (
> >//
> >// Convert the clock freq unit from MHz to KHz.
> >//
> > -  Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000,
> > Private-
> > >BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
> > +  Status = SdMmcHcClockSupply (Private, Slot, BusTiming, FALSE,
> > + ClockFreq *
> > 1000);
> >if (EFI_ERROR (Status)) {
> >  return Status;
> >}
> > @@ -745,24 +745,6 @@ EmmcSwitchBusTiming (
> >  return EFI_DEVICE_ERROR;
> >}
> >
> > -  if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > -Status = mOverride->NotifyPhase (
> > -  Private->ControllerHandle,
> > -  Slot,
> > -  EdkiiSdMmcSwitchClockFreqPost,
> > -  
> > -  );
> > -if (EFI_ERROR (Status)) {
> > -  DEBUG ((
> > -DEBUG_ERROR,
> > -"%a: SD/MMC switch clock freq post notifier callback failed - 
> > %r\n",
> > -__FUNCTION__,
> > -Status
> > -));
> > -  return Status;
> > -}
> > -  }
> > -
> >return Status;
> >  }
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > index 336baade9e..d63dc54e8c 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > @@ -1145,29 +1145,11 @@ SdCardSetBusMode (
> >  return Status;
> >}
> >
> > -  Status = SdMmcHcClockSupply (PciIo, Slot, BusMode.ClockFreq * 1000,
> > Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
> > +  Status = SdMmcHcClockSupply (Private, Slot, BusMode.BusTiming,
> > + FALSE,
> > BusMode.ClockFreq * 1000);
> >if (EFI_ERROR (Status)) {
> >  return Status;
> >}
> >
> > -  if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > -Status = mOverride->NotifyPhase (
> > -  Private->Cont

[edk2-devel] [PATCH 1/2] SdMmcPciHcDxe: Send EdkiiSdMmcSwitchClockFreq after SD clock start

[Albecki, Mateusz]

For eMMC modules we used to notify the platform about frequency
change only after sending CMD13 which meant that platform
might not get a chance to apply required post frequency
change fixes to get the clock stable. To fix this
notification has been moved to SdMmcHcClockSupply function
just after we start the SD clock. During first time setup
the notification won't be sent to avoid changing old behavior.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c|  20 +---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c  |  28 ++
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |  24 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 107 +
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h   |  44 -
 5 files changed, 81 insertions(+), 142 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 082904ccc5..776c0e796c 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -727,7 +727,7 @@ EmmcSwitchBusTiming (
   //
   // Convert the clock freq unit from MHz to KHz.
   //
-  Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, 
Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
+  Status = SdMmcHcClockSupply (Private, Slot, BusTiming, FALSE, ClockFreq * 
1000);
   if (EFI_ERROR (Status)) {
 return Status;
   }
@@ -745,24 +745,6 @@ EmmcSwitchBusTiming (
 return EFI_DEVICE_ERROR;
   }
 
-  if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
-Status = mOverride->NotifyPhase (
-  Private->ControllerHandle,
-  Slot,
-  EdkiiSdMmcSwitchClockFreqPost,
-  
-  );
-if (EFI_ERROR (Status)) {
-  DEBUG ((
-DEBUG_ERROR,
-"%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
-__FUNCTION__,
-Status
-));
-  return Status;
-}
-  }
-
   return Status;
 }
 
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
index 336baade9e..d63dc54e8c 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
@@ -1145,29 +1145,11 @@ SdCardSetBusMode (
 return Status;
   }
 
-  Status = SdMmcHcClockSupply (PciIo, Slot, BusMode.ClockFreq * 1000, 
Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
+  Status = SdMmcHcClockSupply (Private, Slot, BusMode.BusTiming, FALSE, 
BusMode.ClockFreq * 1000);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
-  if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
-Status = mOverride->NotifyPhase (
-  Private->ControllerHandle,
-  Slot,
-  EdkiiSdMmcSwitchClockFreqPost,
-  
-  );
-if (EFI_ERROR (Status)) {
-  DEBUG ((
-DEBUG_ERROR,
-"%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
-__FUNCTION__,
-Status
-));
-  return Status;
-}
-  }
-
   if ((BusMode.BusTiming == SdMmcUhsSdr104) || ((BusMode.BusTiming == 
SdMmcUhsSdr50) && (Capability->TuningSDR50 != 0))) {
 Status = SdCardTuningClock (PciIo, PassThru, Slot);
 if (EFI_ERROR (Status)) {
@@ -1345,7 +1327,13 @@ SdCardIdentification (
 goto Error;
   }
 
-  SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], 
Private->ControllerVersion[Slot]);
+  //
+  // Restart the clock with first time parameters.
+  // NOTE: it is not required to actually restart the clock
+  // and go through internal clock setup again. Some time
+  // could be saved if we simply started the SD clock.
+  //
+  SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400);
 
   gBS->Stall (1000);
 
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index c29e48767e..0304960132 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -796,6 +796,30 @@ SdCardIdentification (
   IN UINT8  Slot
   );
 
+/**
+  SD/MMC card clock supply.
+
+  Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.
+
+  @param[in] Private A pointer to the SD_MMC_HC_PRIVATE_DATA instance.
+  @param[in] SlotThe slot number of the SD card to send the 
command to.
+  @param[in] BusTiming   BusTiming at which the frequency change is done.
+  @param[in] FirstTimeSetup  Flag to indicate whether the clock is being setup 
for the first time.
+  @param[in] ClockFreq   The max clock frequency to be set. The unit is 
KHz.
+
+  @retval 

[edk2-devel] [PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: Add function to start SD clock

[Albecki, Mateusz]

In SD card voltage switch flow we used to redo the
entire internal clock setup after voltage switch.
Since internal clock has already been setup this
is wasting time on polling the internal clock stable.
This commit changes it to only start the SD clock.

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c| 11 +++-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 33 
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 15 +++
 3 files changed, 47 insertions(+), 12 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
index d63dc54e8c..b630daab76 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
@@ -1327,13 +1327,10 @@ SdCardIdentification (
 goto Error;
   }
 
-  //
-  // Restart the clock with first time parameters.
-  // NOTE: it is not required to actually restart the clock
-  // and go through internal clock setup again. Some time
-  // could be saved if we simply started the SD clock.
-  //
-  SdMmcHcClockSupply (Private, Slot, 0, TRUE, 400);
+  Status = SdMmcHcStartSdClock (PciIo, Slot);
+  if (EFI_ERROR (Status)) {
+goto Error;
+  }
 
   gBS->Stall (1000);
 
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index f667264c5e..e7f2fac69b 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -758,6 +758,30 @@ SdMmcHcStopClock (
   return Status;
 }
 
+/**
+  Start the SD clock.
+
+  @param[in] PciIo  The PCI IO protocol instance.
+  @param[in] Slot   The slot number.
+
+  @retval EFI_SUCCESS  Succeeded to start the SD clock.
+  @rtval  Others   Failed to start the SD clock.
+**/
+EFI_STATUS
+SdMmcHcStartSdClock (
+  IN EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN UINT8Slot
+  )
+{
+  UINT16ClockCtrl;
+
+  //
+  // Set SD Clock Enable in the Clock Control register to 1
+  //
+  ClockCtrl = BIT2;
+  return SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), 
);
+}
+
 /**
   SD/MMC card clock supply.
 
@@ -879,11 +903,10 @@ SdMmcHcClockSupply (
 return Status;
   }
 
-  //
-  // Set SD Clock Enable in the Clock Control register to 1
-  //
-  ClockCtrl = BIT2;
-  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof 
(ClockCtrl), );
+  Status = SdMmcHcStartSdClock (PciIo, Slot);
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
 
   //
   // We don't notify the platform on first time setup to avoid changing
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
index 826e851b04..4753bb6864 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
@@ -478,6 +478,21 @@ SdMmcHcStopClock (
   IN UINT8  Slot
   );
 
+/**
+  Start the SD clock.
+
+  @param[in] PciIo  The PCI IO protocol instance.
+  @param[in] Slot   The slot number.
+
+  @retval EFI_SUCCESS  Succeeded to start the SD clock.
+  @rtval  Others   Failed to start the SD clock.
+**/
+EFI_STATUS
+SdMmcHcStartSdClock (
+  IN EFI_PCI_IO_PROTOCOL  *PciIo,
+  IN UINT8Slot
+  );
+
 /**
   SD/MMC bus power control.
 
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
moze zawierac informacje poufne. W razie przypadkowego otrzymania tej 
wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; 
jakiekolwiek
przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole 
use of the intended recipient(s). If you are not the intended recipient, please 
contact the sender and delete all copies; any review or distribution by
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[edk2-devel] [PATCH 0/2] MdeModulePkg/SdMmcPciHcDxe: Send the EdkiiSdMmcSwitchClockFreq notification before sending CMD13

[Albecki, Mateusz]

The first patch refactors the SdMmcClockSupply function with a goal
of sending the EdkiiSdMmcSwitchClockFreq notification before we send the
CMD13 to check the switch status in eMMC init flow. This is required to
avoid sending the CMD13 on link that still has not been fixed by platform.

To avoid changing the driver behavior we avoid sending notifications
when the clock is setup for the first time or when we setup the clock
after the voltage switch procedure(adressed in second patch).

The second patch in the series optimizes the SD card detection routine
to stop it from going through the process of internal clock setup
after switching the voltage. According to SD HC specification there
is no need to setup internal clock all over again.

Tests performed:
- Booted eMMC in HS400 mode on platform which required post clock freq fixes

I wasn't able to test SD card yet due to the lack of setup with working SD.

The patch series is available on github here: 
https://github.com/malbecki/edk2/tree/sdmmc_post_freq_notify

Cc: Hao A Wu 
Cc: Marcin Wojtas 
Cc: Zhichao Gao 
Cc: Liming Gao 

Mateusz Albecki (2):
  SdMmcPciHcDxe: Send EdkiiSdMmcSwitchClockFreq after SD clock start
  MdeModulePkg/SdMmcPciHcDxe: Add function to start SD clock

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c|  20 +--
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c  |  25 +---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |  24 
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   | 136 +++--
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h   |  45 ++-
 5 files changed, 112 insertions(+), 138 deletions(-)

-- 
2.14.1.windows.1



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[edk2-devel] [PATCHv2 1/3] MdeModulePkg/SdMmcPciHcDxe: Remove clock stop from HS200 switch

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2218

Stopping the SD clock before switching host controller
bus timing is only neccessary if preset value enable is
set in host controller. Code that performs switch to
HS200 doesn't check this condition right now and we also
don't do the SD clock stop before any other bus timing switch
in host controller. Since the driver is generally not ready to support
host controller with preset value enable set we removed this
code.

Signed-off-by: Mateusz Albecki 
Cc: Hao A Wu 
Cc: Marcin Wojtas 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 29 -
 1 file changed, 29 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 3f4a8e5413..bd70490286 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -837,7 +837,6 @@ EmmcSwitchToHS200 (
   )
 {
   EFI_STATUS   Status;
-  UINT16   ClockCtrl;
   SD_MMC_HC_PRIVATE_DATA  *Private;
 
   Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
@@ -851,40 +850,12 @@ EmmcSwitchToHS200 (
   if (EFI_ERROR (Status)) {
 return Status;
   }
-  //
-  // Stop bus clock at first
-  //
-  Status = SdMmcHcStopClock (PciIo, Slot);
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
 
   Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
BusMode->BusTiming);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
-  //
-  // Wait Internal Clock Stable in the Clock Control register to be 1 before 
set SD Clock Enable bit
-  //
-  Status = SdMmcHcWaitMmioSet (
- PciIo,
- Slot,
- SD_MMC_HC_CLOCK_CTRL,
- sizeof (ClockCtrl),
- BIT1,
- BIT1,
- SD_MMC_HC_GENERIC_TIMEOUT
- );
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-  //
-  // Set SD Clock Enable in the Clock Control register to 1
-  //
-  ClockCtrl = BIT2;
-  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof 
(ClockCtrl), );
-
   Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, 
BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
   if (EFI_ERROR (Status)) {
 return Status;
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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[edk2-devel] [PATCHv2 3/3] MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing handling

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2218

There is a bug in current driver code that makes
it impossible for it to work with devices that
only work in legacy speed mode since the function
EmmcSwitchToHighSpeed will return with EFI_INVALID_ARGUMENT
for such bus mode. Since the logic in that function will
work well for SdMmcMmcLegacy this patch just allows
to call this function with SdMmcMmcLegacy bus mode.

Signed-off-by: Mateusz Albecki 
Cc: Hao A Wu 
Cc: Marcin Wojtas 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 3598a8538a..082904ccc5 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -794,7 +794,7 @@ EmmcSwitchToHighSpeed (
   EFI_STATUS  Status;
   BOOLEAN IsDdr;
 
-  if ((BusMode->BusTiming != SdMmcMmcHsSdr && BusMode->BusTiming != 
SdMmcMmcHsDdr) ||
+  if ((BusMode->BusTiming != SdMmcMmcHsSdr && BusMode->BusTiming != 
SdMmcMmcHsDdr && BusMode->BusTiming != SdMmcMmcLegacy) ||
   BusMode->ClockFreq > 52) {
 return EFI_INVALID_PARAMETER;
   }
@@ -1244,6 +1244,12 @@ EmmcSetBusMode (
   } else if (BusMode.BusTiming == SdMmcMmcHs200) {
 Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, );
   } else {
+//
+// Note that EmmcSwitchToHighSpeed is also called for SdMmcMmcLegacy
+// bus timing. This is because even though we might not want to
+// change the timing itself we still want to allow customization of
+// bus parameters such as clock frequency and bus width.
+//
 Status = EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, );
   }
 
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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[edk2-devel] [PATCHv2 2/3] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence

[Albecki, Mateusz]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2218

SD specification recommends switching card bus timing before
switching bus timing in controller. Emmc driver used to do
this switch other way around. This commit adds controller
timing switch in EmmcSwitchBusTiming function to enforce this
order and removes all controller timing programing from
EmmcSwitchToXXX functions.

Signed-off-by: Mateusz Albecki 
Cc: Hao A Wu 
Cc: Marcin Wojtas 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 70 +
 1 file changed, 26 insertions(+), 44 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index bd70490286..3598a8538a 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -671,6 +671,7 @@ EmmcSwitchBusTiming (
   UINT8 CmdSet;
   UINT32DevStatus;
   SD_MMC_HC_PRIVATE_DATA*Private;
+  UINT8 HostCtrl1;
 
   Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
   //
@@ -704,6 +705,25 @@ EmmcSwitchBusTiming (
 return Status;
   }
 
+  if (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcHsDdr) {
+HostCtrl1 = BIT2;
+Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof 
(HostCtrl1), );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  } else {
+HostCtrl1 = (UINT8)~BIT2;
+Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof 
(HostCtrl1), );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  }
+
+  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
BusTiming);
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
   //
   // Convert the clock freq unit from MHz to KHz.
   //
@@ -771,12 +791,8 @@ EmmcSwitchToHighSpeed (
   IN SD_MMC_BUS_SETTINGS*BusMode
   )
 {
-  EFI_STATUS  Status;
-  UINT8   HostCtrl1;
-  SD_MMC_HC_PRIVATE_DATA  *Private;
-  BOOLEAN IsDdr;
-
-  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+  EFI_STATUS  Status;
+  BOOLEAN IsDdr;
 
   if ((BusMode->BusTiming != SdMmcMmcHsSdr && BusMode->BusTiming != 
SdMmcMmcHsDdr) ||
   BusMode->ClockFreq > 52) {
@@ -794,20 +810,6 @@ EmmcSwitchToHighSpeed (
 return Status;
   }
 
-  //
-  // Set to High Speed timing
-  //
-  HostCtrl1 = BIT2;
-  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof 
(HostCtrl1), );
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
BusMode->BusTiming);
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
   return EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, 
BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
 }
 
@@ -836,10 +838,7 @@ EmmcSwitchToHS200 (
   IN SD_MMC_BUS_SETTINGS*BusMode
   )
 {
-  EFI_STATUS   Status;
-  SD_MMC_HC_PRIVATE_DATA  *Private;
-
-  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
+  EFI_STATUS  Status;
 
   if (BusMode->BusTiming != SdMmcMmcHs200 ||
   (BusMode->BusWidth != 4 && BusMode->BusWidth != 8)) {
@@ -851,11 +850,6 @@ EmmcSwitchToHS200 (
 return Status;
   }
 
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
BusMode->BusTiming);
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
   Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, 
BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
   if (EFI_ERROR (Status)) {
 return Status;
@@ -891,17 +885,15 @@ EmmcSwitchToHS400 (
   IN SD_MMC_BUS_SETTINGS*BusMode
   )
 {
-  EFI_STATUS Status;
-  SD_MMC_HC_PRIVATE_DATA *Private;
-  SD_MMC_BUS_SETTINGSHs200BusMode;
-  UINT32 HsFreq;
+  EFI_STATUS   Status;
+  SD_MMC_BUS_SETTINGS  Hs200BusMode;
+  UINT32   HsFreq;
 
   if (BusMode->BusTiming != SdMmcMmcHs400 ||
   BusMode->BusWidth != 8) {
 return EFI_INVALID_PARAMETER;
   }
 
-  Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
   Hs200BusMode.BusTiming = SdMmcMmcHs200;
   Hs200BusMode.BusWidth = BusMode->BusWidth;
   Hs200BusMode.ClockFreq = BusMode->ClockFreq;
@@ -916,11 +908,6 @@ EmmcSwitchToHS400 (
   // Set to High Speed timing and set the clock frequency to a value less than 
or equal to 52MHz.
   // This step is necessary to be able to switch Bus into 8 bit DDR mode which 
is unsupported in HS200.
   //
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
SdMmcMmcHsSdr);
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
   HsFreq = BusMode->ClockFreq < 52 ? BusMode->ClockFreq : 52;
   Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, 
BusMode->DriverStrength, SdMmcMmcHsSdr, HsFreq);
   if (EFI_ERROR (Status)) {
@@ -932,11 +919,6 @@ EmmcSwitchToHS400 (
 return Status;
   }
 
-  Status = SdMmcHcUhsSignaling 

[edk2-devel] [PATCHv2 0/3] Fix eMMC bus timing switch issue

[Albecki, Mateusz]

SD host controller specification section 3.9 recommends that controller's bus 
timing
should be switched after card's bus timing has been switched. In current eMMC
driver implementation every host controller switch has been done before call to
EmmcSwitchBusTiming which is causing issues on some eMMC controllers.

In HS200 switch sequence we removed stopping and starting the SD clock when
switching the host controller timing. Stopping the clock before bus timing
switch is only neccessary if preset value enable is set in host controller.
Current code doesn't check if this field is enabled or doesn't support
this feature for any other bus timing change so it has been removed.

Third patch fixes issue with switch to SdMmcMmcLegacy speed mode that was
introduced when we implemented v3 of override protocol. In new flow we allowed
EmmcSwitchToHighSpeed to be called with SdMmcMmcLegacy since all of the logic
in that function is ready to service this speed mode.

Tests performed on patch series v1:
- eMMC enumeration and OS boot in HS400
- eMMC enumeration and OS boot in HS200
- eMMC enumeration and OS boot in high speed SDR 8bit @52MHz

Tests have been performed on 2 eMMC host controllers. One that has been failing
with old driver and one that has been passing with old driver. Both controllers
pass all tests with multiple eMMC devices used.

Note: We were unable to test DDR speed mode because on test machines both new 
flow
and old flow was failing with this speed. I suspect it is a hardware problem.

Tests performed on patch series v2:
-eMMC enumeration and OS boot in backwards compatible legacy timing.

Performed on single host controller and 2 eMMC devices(Samsung and SanDisk)

Cc: Hao A Wu 
Cc: Marcin Wojtas 

Albecki, Mateusz (3):
  MdeModulePkg/SdMmcPciHcDxe: Remove clock stop and start from HS200
switch
  MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence
  MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcMmcLegacy bus timing handling

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 107 
 1 file changed, 33 insertions(+), 74 deletions(-)

-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence

[Albecki, Mateusz]

> -Original Message-
> From: Wu, Hao A 
> Sent: Thursday, September 26, 2019 3:36 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas 
> Subject: RE: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing
> switch sequence
> 
> > -Original Message-----
> > From: Albecki, Mateusz
> > Sent: Wednesday, September 25, 2019 10:54 PM
> > To: Wu, Hao A; devel@edk2.groups.io
> > Cc: Marcin Wojtas
> > Subject: RE: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing
> > switch sequence
> >
> >
> >
> > > -Original Message-----
> > > From: Wu, Hao A 
> > > Sent: Wednesday, September 25, 2019 5:34 AM
> > > To: Albecki, Mateusz ;
> > > devel@edk2.groups.io
> > > Cc: Marcin Wojtas 
> > > Subject: RE: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus
> timing
> > > switch sequence
> > >
> > > > -Original Message-
> > > > From: Albecki, Mateusz
> > > > Sent: Monday, September 23, 2019 4:37 PM
> > > > To: devel@edk2.groups.io
> > > > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas
> > > > Subject: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing
> > > switch
> > > > sequence
> > > >
> > > > SD specification recommends switching card bus timing before
> > > > switching bus timing in controller. Emmc driver used to do this
> > > > switch other way around. This commit adds controller timing switch
> > > > in EmmcSwitchBusTiming function to enforce this order and removes
> > > > all controller timing programing from EmmcSwitchToXXX functions.
> > >
> > >
> > > Hello Mateusz,
> > >
> > > I think the changes in the patch look good.
> > >
> > > Could you help to address the below things:
> > >
> > > 1. The 'Private' local variable is no longer being used by below 
> > > functions:
> > > EmmcSwitchToHighSpeed()
> > > EmmcSwitchToHS200()
> > > EmmcSwitchToHS400()
> > >
> > > The GCC compiler seems not happy with it, could you help to resolve it?
> >
> > Sure
> > >
> > > 2. I have submitted a Bugzilla tracker for this issue at:
> > > https://bugzilla.tianocore.org/show_bug.cgi?id=2218
> > >
> > > Could you help to add this information in the commit log message?
> >
> > Sure
> > >
> > > 3. For the removal of bus clock stopping codes in
> > > EmmcSwitchToHS200(), could you split them into another separate
> > > patch? I think they are not
> > directly
> > > related with the bus speed mode changing sequence.
> > >
> >
> > I could do that sure, but since I have to remove the call to
> > SdMmcHcUhsSignaling from this function stopping and starting clock no
> > longer makes any sense so it would result in a nonsensical code in
> > this one patch. Anyway let me know if you still want to split it and I will.
> 
> 
> My initial thought was to split the removal of bus clock stopping and
> resuming codes (before and after the call of function
> SdMmcHcUhsSignaling()) into the 1st patch of the series. Then a 2nd patch
> will relocate the call of function
> SdMmcHcUhsSignaling() to fix the bus mode switching sequence issue.
> 
> I think from your description in the cover-letter, such bus clock stopping and
> resuming is only required when the preset values are being used (which is
> not the case for the current implementation of the driver).
> 
> What do you think of this?
> 

Yeah that makes sense. I will split it like that.

> 
> >
> > > 4. I have performed the below tests on the eMMC device on my side,
> > > for different eMMC bus modes:
> > > HS400 (good)
> > > HS200 (good)
> > > High Speed DDR (good)
> > > High Speed SDR (good)
> > > Legacy MMC (NOT good)
> > >
> > > For the Legacy MMC mode case, the error comes from the
> > > EmmcSwitchToHighSpeed() function returning EFI_INVALID_PARAMETER
> > for
> > > bus mode 'SdMmcMmcLegacy'. I think for the EmmcSetBusMode()
> > function,
> > > the below updates can be made:
> > >
> > >   if (BusMode.BusTiming == SdMmcMmcHs400) {
> > > Status = EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, );
> > >   } else if (BusMode.BusTiming == SdMmcMmcHs200) {
> > > Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, );
> > >   } else {  <== should be updated to:
> > >   } else if (BusMode.BusTiming =

Re: [edk2-devel] [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence

[Albecki, Mateusz]

> -Original Message-
> From: Wu, Hao A 
> Sent: Wednesday, September 25, 2019 5:34 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Cc: Marcin Wojtas 
> Subject: RE: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing
> switch sequence
> 
> > -Original Message-----
> > From: Albecki, Mateusz
> > Sent: Monday, September 23, 2019 4:37 PM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A; Marcin Wojtas
> > Subject: [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing
> switch
> > sequence
> >
> > SD specification recommends switching card bus timing before switching
> > bus timing in controller. Emmc driver used to do this switch other way
> > around. This commit adds controller timing switch in
> > EmmcSwitchBusTiming function to enforce this order and removes all
> > controller timing programing from EmmcSwitchToXXX functions.
> 
> 
> Hello Mateusz,
> 
> I think the changes in the patch look good.
> 
> Could you help to address the below things:
> 
> 1. The 'Private' local variable is no longer being used by below functions:
> EmmcSwitchToHighSpeed()
> EmmcSwitchToHS200()
> EmmcSwitchToHS400()
> 
> The GCC compiler seems not happy with it, could you help to resolve it?

Sure
> 
> 2. I have submitted a Bugzilla tracker for this issue at:
> https://bugzilla.tianocore.org/show_bug.cgi?id=2218
> 
> Could you help to add this information in the commit log message?

Sure
> 
> 3. For the removal of bus clock stopping codes in EmmcSwitchToHS200(),
> could you split them into another separate patch? I think they are not 
> directly
> related with the bus speed mode changing sequence.
> 

I could do that sure, but since I have to remove the call to 
SdMmcHcUhsSignaling from this function stopping and starting clock no longer 
makes any sense so it would result in a nonsensical code in this one patch. 
Anyway let me know if you still want to split it and I will. 

> 4. I have performed the below tests on the eMMC device on my side, for
> different eMMC bus modes:
> HS400 (good)
> HS200 (good)
> High Speed DDR (good)
> High Speed SDR (good)
> Legacy MMC (NOT good)
> 
> For the Legacy MMC mode case, the error comes from the
> EmmcSwitchToHighSpeed() function returning EFI_INVALID_PARAMETER for
> bus mode 'SdMmcMmcLegacy'. I think for the EmmcSetBusMode() function,
> the below updates can be made:
> 
>   if (BusMode.BusTiming == SdMmcMmcHs400) {
> Status = EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, );
>   } else if (BusMode.BusTiming == SdMmcMmcHs200) {
> Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, );
>   } else {  <== should be updated to:
>   } else if (BusMode.BusTiming == SdMmcMmcHsSdr || BusMode.BusTiming
> == SdMmcMmcHsDdr) {
> Status = EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, );
>   }
> 
> think for the Legacy MMC mode, no additional bus mode switch is needed. If
> you agree with this, could you help to add another patch to change the
> above logic (also the debug message after the above-shown code)?
> 
> Best  Regards,
> Hao Wu
> 

That is actually another bug introduced by the previous patch, right? I will 
fix it in the separate patch(but in this series).

> 
> >
> > Signed-off-by: Mateusz Albecki 
> > Cc: Hao A Wu 
> > Cc: Marcin Wojtas 
> > ---
> >  MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 79 +++---
> 
> > ---
> >  1 file changed, 20 insertions(+), 59 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > index 3f4a8e5413..06ee1208be 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > @@ -671,6 +671,7 @@ EmmcSwitchBusTiming (
> >UINT8 CmdSet;
> >UINT32DevStatus;
> >SD_MMC_HC_PRIVATE_DATA*Private;
> > +  UINT8 HostCtrl1;
> >
> >Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >//
> > @@ -704,6 +705,25 @@ EmmcSwitchBusTiming (
> >  return Status;
> >}
> >
> > +  if (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcHsDdr) {
> > +HostCtrl1 = BIT2;
> > +Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1,
> sizeof
> > (HostCtrl1), );
> > +if (EFI_ERROR (Status)) {
> > +  return Status;
> > +}
> > +  } else {
> > +HostCtrl1 = (UINT8)~BIT2;
> > +Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1,
> > sizeof (HostCtrl1), );
>

[edk2-devel] [PATCH 1/1] MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence

[Albecki, Mateusz]

SD specification recommends switching card bus timing before
switching bus timing in controller. Emmc driver used to do
this switch other way around. This commit adds controller
timing switch in EmmcSwitchBusTiming function to enforce this
order and removes all controller timing programing from
EmmcSwitchToXXX functions.

Signed-off-by: Mateusz Albecki 
Cc: Hao A Wu 
Cc: Marcin Wojtas 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 79 +++--
 1 file changed, 20 insertions(+), 59 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 3f4a8e5413..06ee1208be 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -671,6 +671,7 @@ EmmcSwitchBusTiming (
   UINT8 CmdSet;
   UINT32DevStatus;
   SD_MMC_HC_PRIVATE_DATA*Private;
+  UINT8 HostCtrl1;
 
   Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
   //
@@ -704,6 +705,25 @@ EmmcSwitchBusTiming (
 return Status;
   }
 
+  if (BusTiming == SdMmcMmcHsSdr || BusTiming == SdMmcMmcHsDdr) {
+HostCtrl1 = BIT2;
+Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof 
(HostCtrl1), );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  } else {
+HostCtrl1 = (UINT8)~BIT2;
+Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof 
(HostCtrl1), );
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+  }
+
+  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
BusTiming);
+  if (EFI_ERROR (Status)) {
+return Status;
+  }
+
   //
   // Convert the clock freq unit from MHz to KHz.
   //
@@ -772,7 +792,6 @@ EmmcSwitchToHighSpeed (
   )
 {
   EFI_STATUS  Status;
-  UINT8   HostCtrl1;
   SD_MMC_HC_PRIVATE_DATA  *Private;
   BOOLEAN IsDdr;
 
@@ -794,20 +813,6 @@ EmmcSwitchToHighSpeed (
 return Status;
   }
 
-  //
-  // Set to High Speed timing
-  //
-  HostCtrl1 = BIT2;
-  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof 
(HostCtrl1), );
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
BusMode->BusTiming);
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
   return EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, 
BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
 }
 
@@ -837,7 +842,6 @@ EmmcSwitchToHS200 (
   )
 {
   EFI_STATUS   Status;
-  UINT16   ClockCtrl;
   SD_MMC_HC_PRIVATE_DATA  *Private;
 
   Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
@@ -851,39 +855,6 @@ EmmcSwitchToHS200 (
   if (EFI_ERROR (Status)) {
 return Status;
   }
-  //
-  // Stop bus clock at first
-  //
-  Status = SdMmcHcStopClock (PciIo, Slot);
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
BusMode->BusTiming);
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
-  //
-  // Wait Internal Clock Stable in the Clock Control register to be 1 before 
set SD Clock Enable bit
-  //
-  Status = SdMmcHcWaitMmioSet (
- PciIo,
- Slot,
- SD_MMC_HC_CLOCK_CTRL,
- sizeof (ClockCtrl),
- BIT1,
- BIT1,
- SD_MMC_HC_GENERIC_TIMEOUT
- );
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-  //
-  // Set SD Clock Enable in the Clock Control register to 1
-  //
-  ClockCtrl = BIT2;
-  Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof 
(ClockCtrl), );
 
   Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, 
BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
   if (EFI_ERROR (Status)) {
@@ -945,11 +916,6 @@ EmmcSwitchToHS400 (
   // Set to High Speed timing and set the clock frequency to a value less than 
or equal to 52MHz.
   // This step is necessary to be able to switch Bus into 8 bit DDR mode which 
is unsupported in HS200.
   //
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
SdMmcMmcHsSdr);
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
   HsFreq = BusMode->ClockFreq < 52 ? BusMode->ClockFreq : 52;
   Status = EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, 
BusMode->DriverStrength, SdMmcMmcHsSdr, HsFreq);
   if (EFI_ERROR (Status)) {
@@ -961,11 +927,6 @@ EmmcSwitchToHS400 (
 return Status;
   }
 
-  Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, 
BusMode->BusTiming);
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
   return EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, 
BusMode->DriverStrength, BusMode->BusTiming, BusMode->ClockFreq);
 }
 
-- 
2.14.1.windows.1



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ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk 

[edk2-devel] [PATCH 0/1] Fix eMMC bus timing switch issue

[Albecki, Mateusz]

SD host controller specification section 3.9 recommends that controller's bus 
timing
should be switched after card's bus timing has been switched. In current eMMC
driver implementation every host controller switch has been done before call to
EmmcSwitchBusTiming which is causing issues on some eMMC controllers.

In HS200 switch sequence we removed stopping and starting the SD clock when
switching the host controller timing. Stopping the clock before bus timing
switch is only neccessary if preset value enable is set in host controller.
Current code doesn't check if this field is enabled or doesn't support
this feature for any other bus timing change so it has been removed.

Tests performed:
- eMMC enumeration and OS boot in HS400
- eMMC enumeration and OS boot in HS200
- eMMC enumeration and OS boot in high speed SDR 8bit @52MHz

Tests have been performed on 2 eMMC host controllers. One that has been failing
with old driver and one that has been passing with old driver. Both controllers
pass all tests with multiple eMMC devices used.

Note: We were unable to test DDR speed mode because on test machines both new 
flow
and old flow was failing with this speed. I suspect it is a hardware problem.

Cc: Hao A Wu 
Cc: Marcin Wojtas 

Albecki, Mateusz (1):
  MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence

 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 +++--
 1 file changed, 5 insertions(+), 49 deletions(-)

-- 
2.14.1.windows.1



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[edk2-devel] [PATCHv3 3/4] MdeModulePkg/UfsPassThruDxe: Refactor private data to use EDKII_UFS_HC_INFO

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

Private data has been refactored to use EDKII_UFS_HC_INFO structure
to store host controller capabilities and version
information. Getting host controller data has been moved
into single place and is done before host controller enable.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  |  9 +++-
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  | 15 +-
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 57 ++
 3 files changed, 58 insertions(+), 23 deletions(-)

diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
index 1518b251d8..7dce217d49 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -35,7 +35,7 @@ UFS_PASS_THRU_PRIVATE_DATA gUfsPassThruTemplate = {
   },
   0,  // UfsHostController
   0,  // UfsHcBase
-  0,  // Capabilities
+  {0, 0}, // UfsHcInfo
   0,  // TaskTag
   0,  // UtpTrlBase
   0,  // Nutrs
@@ -865,6 +865,11 @@ UfsPassThruDriverBindingStart (
   Private->UfsHostController= UfsHc;
   Private->UfsHcBase= UfsHcBase;
   InitializeListHead (>Queue);
+  Status = GetUfsHcInfo (Private);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to initialize UfsHcInfo\n"));
+goto Error;
+  }
 
   //
   // Initialize UFS Host Controller H/W.
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
index b79be77709..c511aa8c7a 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
@@ -62,7 +62,7 @@ typedef struct _UFS_PASS_THRU_PRIVATE_DATA {
   EFI_UFS_DEVICE_CONFIG_PROTOCOL  UfsDevConfig;
   EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHostController;
   UINTN   UfsHcBase;
-  UINT32  Capabilities;
+  EDKII_UFS_HC_INFO   UfsHcInfo;
 
   UINT8   TaskTag;
 
@@ -959,6 +959,19 @@ UfsRwUfsAttribute (
   IN OUT UINT32*AttrSize
   );
 
+/**
+  Initializes UfsHcInfo field in private data.
+
+  @param[in] Private  Pointer to host controller private data.
+
+  @retval EFI_SUCCESS  UfsHcInfo initialized successfully.
+  @retval Others   Failed to initalize UfsHcInfo.
+**/
+EFI_STATUS
+GetUfsHcInfo (
+  IN UFS_PASS_THRU_PRIVATE_DATA  *Private
+  );
+
 extern EFI_COMPONENT_NAME_PROTOCOL  gUfsPassThruComponentName;
 extern EFI_COMPONENT_NAME2_PROTOCOL gUfsPassThruComponentName2;
 extern EFI_DRIVER_BINDING_PROTOCOL  gUfsPassThruDriverBinding;
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
index 6ea27e473c..74be3efc41 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
@@ -731,7 +731,7 @@ UfsFindAvailableSlotInTrl (
 return Status;
   }
 
-  Nutrs   = (UINT8)((Private->Capabilities & UFS_HC_CAP_NUTRS) + 1);
+  Nutrs   = (UINT8)((Private->UfsHcInfo.Capabilities & UFS_HC_CAP_NUTRS) + 1);
 
   for (Index = 0; Index < Nutrs; Index++) {
 if ((Data & (BIT0 << Index)) == 0) {
@@ -1754,7 +1754,7 @@ UfsAllocateAlignCommonBuffer (
   BOOLEAN  Is32BitAddr;
   EDKII_UFS_HOST_CONTROLLER_PROTOCOL   *UfsHc;
 
-  if ((Private->Capabilities & UFS_HC_CAP_64ADDR) == UFS_HC_CAP_64ADDR) {
+  if ((Private->UfsHcInfo.Capabilities & UFS_HC_CAP_64ADDR) == 
UFS_HC_CAP_64ADDR) {
 Is32BitAddr = FALSE;
   } else {
 Is32BitAddr = TRUE;
@@ -1947,7 +1947,6 @@ UfsInitTaskManagementRequestList (
   IN  UFS_PASS_THRU_PRIVATE_DATA *Private
   )
 {
-  UINT32 Data;
   UINT8  Nutmrs;
   VOID   *CmdDescHost;
   EFI_PHYSICAL_ADDRESS   CmdDescPhyAddr;
@@ -1961,17 +1960,10 @@ UfsInitTaskManagementRequestList (
   CmdDescMapping = NULL;
   CmdDescPhyAddr = 0;
 
-  Status = UfsMmioRead32 (Private, UFS_HC_CAP_OFFSET, );
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
-  Private->Capabilities = Data;
-
   //
   // Allocate and initialize UTP Task Management Request List.
   //
-  Nutmrs = (UINT8) (RShiftU64 ((Private->Capabilities & UFS_HC_CAP_NUTMRS), 
16) + 1);
+  Nutmrs = (UINT8) (RShiftU64 ((Private->UfsHcInfo.Capabilities & 
UFS_HC_CAP_NUTMRS), 16) + 1);
   Status = UfsAllocateAlignCommonBuffer (Private, Nutmrs * sizeof (UTP_TMRD), 
, , );
   if (EFI_ERROR 

[edk2-devel] [PATCHv3 4/4] MdeModulePkg/UfsPassThruDxe: Implement EDKII_UFS_HC_PLATFORM_PROTOCOL

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

This commit adds EDKII_UFS_HC_PLATFORM_PROTOCOL implementation
in UfsPassThruDxe driver in version 1. Driver assumes that at
most one instance of the protocol exists in the system. Presence
of the protocol is not mandatory.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  | 17 ++
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  | 26 
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf  |  3 +-
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 69 +-
 4 files changed, 112 insertions(+), 3 deletions(-)

diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
index 7dce217d49..b12404aacb 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
@@ -36,6 +36,7 @@ UFS_PASS_THRU_PRIVATE_DATA gUfsPassThruTemplate = {
   0,  // UfsHostController
   0,  // UfsHcBase
   {0, 0}, // UfsHcInfo
+  {NULL, NULL},   // UfsHcDriverInterface
   0,  // TaskTag
   0,  // UtpTrlBase
   0,  // Nutrs
@@ -92,6 +93,8 @@ UFS_DEVICE_PATHmUfsDevicePathTemplate = {
 
 UINT8 mUfsTargetId[TARGET_MAX_BYTES];
 
+GLOBAL_REMOVE_IF_UNREFERENCED EDKII_UFS_HC_PLATFORM_PROTOCOL  *mUfsHcPlatform;
+
 /**
   Sends a SCSI Request Packet to a SCSI device that is attached to the SCSI 
channel. This function
   supports both blocking I/O and nonblocking I/O. The blocking I/O 
functionality is required, and the
@@ -864,7 +867,21 @@ UfsPassThruDriverBindingStart (
   Private->ExtScsiPassThru.Mode = >ExtScsiPassThruMode;
   Private->UfsHostController= UfsHc;
   Private->UfsHcBase= UfsHcBase;
+  Private->Handle   = Controller;
+  Private->UfsHcDriverInterface.UfsHcProtocol = UfsHc;
+  Private->UfsHcDriverInterface.UfsExecUicCommand = 
UfsHcDriverInterfaceExecUicCommand;
   InitializeListHead (>Queue);
+
+  //
+  // This has to be done before initializing UfsHcInfo or calling the 
UfsControllerInit
+  //
+  if (mUfsHcPlatform == NULL) {
+Status = gBS->LocateProtocol (, NULL, 
(VOID**));
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_INFO, "No UfsHcPlatformProtocol present\n"));
+}
+  }
+
   Status = GetUfsHcInfo (Private);
   if (EFI_ERROR (Status)) {
 DEBUG ((DEBUG_ERROR, "Failed to initialize UfsHcInfo\n"));
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
index c511aa8c7a..cbc0c2126e 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
@@ -63,6 +63,7 @@ typedef struct _UFS_PASS_THRU_PRIVATE_DATA {
   EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHostController;
   UINTN   UfsHcBase;
   EDKII_UFS_HC_INFO   UfsHcInfo;
+  EDKII_UFS_HC_DRIVER_INTERFACE   UfsHcDriverInterface;
 
   UINT8   TaskTag;
 
@@ -126,6 +127,13 @@ typedef struct {
   UFS_PASS_THRU_SIG \
   )
 
+#define UFS_PASS_THRU_PRIVATE_DATA_FROM_DRIVER_INTF(a) \
+  CR (a, \
+  UFS_PASS_THRU_PRIVATE_DATA, \
+  UfsHcDriverInterface, \
+  UFS_PASS_THRU_SIG \
+  )
+
 typedef struct _UFS_DEVICE_MANAGEMENT_REQUEST_PACKET {
   UINT64   Timeout;
   VOID *DataBuffer;
@@ -959,6 +967,23 @@ UfsRwUfsAttribute (
   IN OUT UINT32*AttrSize
   );
 
+/**
+  Execute UIC command.
+
+  @param[in]  ThisPointer to driver interface produced by the UFS 
controller.
+  @param[in, out] UicCommand  Descriptor of the command that will be executed.
+
+  @retval EFI_SUCCESSCommand executed successfully.
+  @retval EFI_INVALID_PARAMETER  This or UicCommand is NULL.
+  @retval Others Command failed to execute.
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverInterfaceExecUicCommand (
+  IN EDKII_UFS_HC_DRIVER_INTERFACE  *This,
+  IN OUT EDKII_UIC_COMMAND  *UicCommand
+  );
+
 /**
   Initializes UfsHcInfo field in private data.
 
@@ -975,5 +1000,6 @@ GetUfsHcInfo (
 extern EFI_COMPONENT_NAME_PROTOCOL  gUfsPassThruComponentName;
 extern EFI_COMPONENT_NAME2_PROTOCOL gUfsPassThruComponentName2;
 extern EFI_DRIVER_BINDING_PROTOCOL  gUfsPassThruDriverBinding;
+extern EDKII_UFS_HC_PLATFORM_PROTOCOL  *mUfsHcPlatform;
 
 #endif
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
index 24f5ea3a8f..92dc25714b 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
@@ -1,7 +1,7 @@
 ## @file
 # Description file for the Universal Flash Storage (UFS) Pass Thru driver.
 #
-# Copyright (c) 2014 - 2018, Intel 

[edk2-devel] [PATCHv3 2/4] MdeModulePkg/UfsPassThruDxe: Refactor UfsExecUicCommand function

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

UfsExecUicCommand function has been refactored to allow
the caller to check the command results which is important
for commands such as UIC read.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  |  3 +-
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 47 --
 2 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
index 9b68db5ffe..b79be77709 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
index 912d6f8202..6ea27e473c 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
@@ -2,7 +2,7 @@
   UfsPassThruDxe driver is used to produce EFI_EXT_SCSI_PASS_THRU protocol 
interface
   for upper layer application to execute UFS-supported SCSI cmds.
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -1633,11 +1633,8 @@ Exit1:
 /**
   Send UIC command.
 
-  @param[in] Private  The pointer to the UFS_PASS_THRU_PRIVATE_DATA 
data structure.
-  @param[in] UicOpcodeThe opcode of the UIC command.
-  @param[in] Arg1 The value for 1st argument of the UIC command.
-  @param[in] Arg2 The value for 2nd argument of the UIC command.
-  @param[in] Arg3 The value for 3rd argument of the UIC command.
+  @param[in]  Private The pointer to the UFS_PASS_THRU_PRIVATE_DATA 
data structure.
+  @param[in, out] UicCommand  UIC command descriptor. On exit contains UIC 
command results.
 
   @return EFI_SUCCESS  Successfully execute this UIC command and detect 
attached UFS device.
   @return EFI_DEVICE_ERROR Fail to execute this UIC command and detect 
attached UFS device.
@@ -1646,10 +1643,7 @@ Exit1:
 EFI_STATUS
 UfsExecUicCommands (
   IN  UFS_PASS_THRU_PRIVATE_DATA*Private,
-  IN  UINT8 UicOpcode,
-  IN  UINT32Arg1,
-  IN  UINT32Arg2,
-  IN  UINT32Arg3
+  IN OUT EDKII_UIC_COMMAND  *UicCommand
   )
 {
   EFI_STATUS  Status;
@@ -1675,17 +1669,17 @@ UfsExecUicCommands (
   // only after all the UIC command argument registers (UICCMDARG1, UICCMDARG2 
and UICCMDARG3)
   // are set.
   //
-  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG1_OFFSET, Arg1);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG1_OFFSET, UicCommand->Arg1);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
-  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG2_OFFSET, Arg2);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG2_OFFSET, UicCommand->Arg2);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
-  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG3_OFFSET, Arg3);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG3_OFFSET, UicCommand->Arg3);
   if (EFI_ERROR (Status)) {
 return Status;
   }
@@ -1698,7 +1692,7 @@ UfsExecUicCommands (
 return Status;
   }
 
-  Status = UfsMmioWrite32 (Private, UFS_HC_UIC_CMD_OFFSET, (UINT32)UicOpcode);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UIC_CMD_OFFSET, UicCommand->Opcode);
   if (EFI_ERROR (Status)) {
 return Status;
   }
@@ -1712,14 +1706,18 @@ UfsExecUicCommands (
 return Status;
   }
 
-  if (UicOpcode != UfsUicDmeReset) {
-Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG2_OFFSET, );
+  if (UicCommand->Opcode != UfsUicDmeReset) {
+Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG2_OFFSET, 
>Arg2);
 if (EFI_ERROR (Status)) {
   return Status;
 }
-if ((Data & 0xFF) != 0) {
+Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG3_OFFSET, 
>Arg3);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+if ((UicCommand->Arg2 & 0xFF) != 0) {
   DEBUG_CODE_BEGIN();
-DumpUicCmdExecResult (UicOpcode, (UINT8)(Data & 0xFF));
+DumpUicCmdExecResult ((UINT8)UicCommand->Opcode, 
(UINT8)(UicCommand->Arg2 & 0xFF));
   DEBUG_CODE_END();
   return EFI_DEVICE_ERROR;
 }
@@ -1898,16 +1896,21 @@ UfsDeviceDetection (
   IN  UFS_PASS_THRU_PRIVATE_DATA *Private
   )
 {
-  UINTN   Retry;
-  EFI_STATUS  Status;
-  UINT32  Data;
+  UINTN  Retry;
+  EFI_STATUS Status;
+  UINT32 Data;
+  

[edk2-devel] [PATCHv3 1/4] MdeModulePkg: Add definition of the EDKII_UFS_HC_PLATFORM_PROTOCOL

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

EDKII_UFS_HC_PLATFORM_PROTOCOL will allow the platform to inject
platform specific logic into standard UFS flows. Right now we
support callbacks pre and post host controller enable and pre
and post link startup. Provided callbacks allow the platform
driver to inject UIC programming after HCE is set which is
a standard initialization step covered by UFS specification as
well as cover some additional use cases during other calllbacks.
For instance platform driver may switch to fast mode after link
startup.

We also allow the platform to override host controller capabilities
and version which might be usefull to manage silicon bugs or
allow testign experimental features from new versions of the
specification.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 .../Include/Protocol/UfsHostControllerPlatform.h   | 124 +
 MdeModulePkg/MdeModulePkg.dec  |   3 +
 2 files changed, 127 insertions(+)
 create mode 100644 MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h

diff --git a/MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h 
b/MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h
new file mode 100644
index 00..0f6732a1f8
--- /dev/null
+++ b/MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h
@@ -0,0 +1,124 @@
+/** @file
+  EDKII_UFS_HC_PLATFORM_PROTOCOL definition.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EDKII_UFS_HC_PLATFORM_PROTOCOL_H__
+#define __EDKII_UFS_HC_PLATFORM_PROTOCOL_H__
+
+#include 
+
+#define EDKII_UFS_HC_PLATFORM_PROTOCOL_VERSION 1
+
+extern EFI_GUID  gEdkiiUfsHcPlatformProtocolGuid;
+
+typedef struct _EDKII_UFS_HC_PLATFORM_PROTOCOL  EDKII_UFS_HC_PLATFORM_PROTOCOL;
+
+typedef struct _EDKII_UFS_HC_DRIVER_INTERFACE  EDKII_UFS_HC_DRIVER_INTERFACE;
+
+typedef struct {
+  UINT32 Opcode;
+  UINT32 Arg1;
+  UINT32 Arg2;
+  UINT32 Arg3;
+} EDKII_UIC_COMMAND;
+
+/**
+  Execute UIC command
+
+  @param[in]  ThisPointer to driver interface produced by the UFS 
controller.
+  @param[in, out] UicCommand  Descriptor of the command that will be executed.
+
+  @retval EFI_SUCCESSCommand executed successfully.
+  @retval EFI_INVALID_PARAMETER  This or UicCommand is NULL.
+  @retval Others Command failed to execute.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_UFS_EXEC_UIC_COMMAND) (
+  IN  EDKII_UFS_HC_DRIVER_INTERFACE  *This,
+  IN OUT  EDKII_UIC_COMMAND  *UicCommand
+);
+
+struct _EDKII_UFS_HC_DRIVER_INTERFACE {
+  ///
+  /// Protocol to accesss host controller MMIO and PCI registers.
+  ///
+  EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHcProtocol;
+  ///
+  /// Function implementing UIC command execution.
+  ///
+  EDKII_UFS_EXEC_UIC_COMMAND  UfsExecUicCommand;
+};
+
+typedef struct {
+  UINT32 Capabilities;
+  UINT32 Version;
+} EDKII_UFS_HC_INFO;
+
+/**
+  Allows platform protocol to override host controller information
+
+  @param[in]  ControllerHandle  Handle of the UFS controller.
+  @param[in, out] HcInfoPointer EDKII_UFS_HC_INFO associated with 
host controller.
+
+  @retval EFI_SUCCESSFunction completed successfully.
+  @retval EFI_INVALID_PARAMETER  HcInfo is NULL.
+  @retval Others Function failed to complete.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_UFS_HC_PLATFORM_OVERRIDE_HC_INFO) (
+  IN EFI_HANDLE ControllerHandle,
+  IN OUT EDKII_UFS_HC_INFO  *HcInfo
+);
+
+typedef enum {
+  EdkiiUfsHcPreHce,
+  EdkiiUfsHcPostHce,
+  EdkiiUfsHcPreLinkStartup,
+  EdkiiUfsHcPostLinkStartup
+} EDKII_UFS_HC_PLATFORM_CALLBACK_PHASE;
+
+/**
+  Callback function for platform driver.
+
+  @param[in]  ControllerHandle  Handle of the UFS controller.
+  @param[in]  CallbackPhase Specifies when the platform protocol is 
called
+  @param[in, out] CallbackData  Data specific to the callback phase.
+For PreHce and PostHce - 
EDKII_UFS_HC_DRIVER_INTERFACE.
+For PreLinkStartup and PostLinkStartup - 
EDKII_UFS_HC_DRIVER_INTERFACE.
+
+  @retval EFI_SUCCESSOverride function completed successfully.
+  @retval EFI_INVALID_PARAMETER  CallbackPhase is invalid or CallbackData is 
NULL when phase expects valid data.
+  @retval Others Function failed to complete.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_UFS_HC_PLATFORM_CALLBACK) (
+  IN EFI_HANDLEControllerHandle,
+  IN EDKII_UFS_HC_PLATFORM_CALLBACK_PHASE  CallbackPhase,
+  IN OUT VOID  *CallbackData
+);
+
+struct _EDKII_UFS_HC_PLATFORM_PROTOCOL {
+  ///
+  /// Version of the protocol.
+  ///
+  UINT32  Version;
+  ///
+  /// Allows platform driver to override host controller information.
+  ///
+  EDKII_UFS_HC_PLATFORM_OVERRIDE_HC_INFO  

[edk2-devel] [PATCHv3 0/4] Add EDKII_UFS_HC_PLATFORM_PROTOCOL to support platform specific programming of UFS host controllers

[Albecki, Mateusz]

To cover additional host controller programming mentioned in the UFS 
specification we have added an additional protocol that allows the UEFI driver 
to give control to platform driver. This allows the platform to perform any 
additional steps needed for the stable operation.

Changes in v3:
- UFS driver will abort initializaton when it fails to get host controler 
information
- Fixed bug with calling post link startup callback on failed device detection

Test coverage:
Tested on platform with UFS 2.1 host controller with Samsung UFS2.0 part with 3 
LUs enabled All LUs have been enumerated in boot manager.
Tested that enumeration works without platform protocol installed(on host 
controller that can support it) Tested that enumeration works with platform 
protocol installed and with additional programming steps after link 
startup(power mode change to GEAR2).

Cc: Hao A Wu https://edk2.groups.io/g/devel/message/45275
Mute This Topic: https://groups.io/mt/32811056/21656
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Re: [edk2-devel] [PATCHv2 0/4] Add EDKII_UFS_HC_PLATFORM_PROTOCOL to support platform specific programming of UFS host controllers

[Albecki, Mateusz]

Hi,

Please ignore this series. I have used wrong branch when generating patches. V3 
will contain the fixes.

Thanks,
Mateusz

> -Original Message-
> From: Albecki, Mateusz
> Sent: Friday, August 9, 2019 2:21 PM
> To: devel@edk2.groups.io
> Cc: Albecki, Mateusz ; Wu, Hao A
> 
> Subject: [PATCHv2 0/4] Add EDKII_UFS_HC_PLATFORM_PROTOCOL to
> support platform specific programming of UFS host controllers
> 
> To cover additional host controller programming mentioned in the UFS
> specification we have added an additional protocol that allows the UEFI
> driver to give control to platform driver. This allows the platform to perform
> any additional steps needed for the stable operation.
> 
> Changes in v2:
> - UFS driver will abort initializaton when it fails to get host controler
> information
> - Fixed bug with calling post link startup callback on failed device detection
> 
> Test coverage:
> Tested on platform with UFS 2.1 host controller with Samsung UFS2.0 part
> with 3 LUs enabled All LUs have been enumerated in boot manager.
> Tested that enumeration works without platform protocol installed(on host
> controller that can support it) Tested that enumeration works with platform
> protocol installed and with additional programming steps after link
> startup(power mode change to GEAR2).
> 
> Cc: Hao A Wu  
> 
> Mateusz Albecki (4):
>   MdeModulePkg: Add definition of the
> EDKII_UFS_HC_PLATFORM_PROTOCOL
>   MdeModulePkg/UfsPassThruDxe: Refactor UfsExecUicCommand function
>   MdeModulePkg/UfsPassThruDxe: Refactor private data to use
> EDKII_UFS_HC_INFO
>   MdeModulePkg/UfsPassThruDxe: Implement
> EDKII_UFS_HC_PLATFORM_PROTOCOL
> 
>  MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  |  23 ++-
> MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  |  42 -
>  .../Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf  |   1 +
>  .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 170
> -
>  .../Include/Protocol/UfsHostControllerPlatform.h   | 130
> 
>  MdeModulePkg/MdeModulePkg.dec  |   3 +
>  6 files changed, 326 insertions(+), 43 deletions(-)  create mode 100644
> MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h
> 
> --
> 2.14.1.windows.1



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[edk2-devel] [PATCHv2 4/4] MdeModulePkg/UfsPassThruDxe: Implement EDKII_UFS_HC_PLATFORM_PROTOCOL

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

This commit adds EDKII_UFS_HC_PLATFORM_PROTOCOL implementation
in UfsPassThruDxe driver in version 1. Driver assumes that at
most one instance of the protocol exists in the system. Presence
of the protocol is not mandatory.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  | 17 ++
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  | 26 +
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf  |  1 +
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 68 ++
 4 files changed, 112 insertions(+)

diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
index 0c96dacf16..7f0ae36dc5 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
@@ -42,6 +42,7 @@ UFS_PASS_THRU_PRIVATE_DATA gUfsPassThruTemplate = {
   0,  // UfsHostController
   0,  // UfsHcBase
   {0, 0}, // UfsHcInfo
+  {NULL, NULL},   // UfsHcDriverInterface
   0,  // TaskTag
   0,  // UtpTrlBase
   0,  // Nutrs
@@ -98,6 +99,8 @@ UFS_DEVICE_PATHmUfsDevicePathTemplate = {
 
 UINT8 mUfsTargetId[TARGET_MAX_BYTES];
 
+GLOBAL_REMOVE_IF_UNREFERENCED EDKII_UFS_HC_PLATFORM_PROTOCOL  *mUfsHcPlatform;
+
 /**
   Sends a SCSI Request Packet to a SCSI device that is attached to the SCSI 
channel. This function
   supports both blocking I/O and nonblocking I/O. The blocking I/O 
functionality is required, and the
@@ -870,7 +873,21 @@ UfsPassThruDriverBindingStart (
   Private->ExtScsiPassThru.Mode = >ExtScsiPassThruMode;
   Private->UfsHostController= UfsHc;
   Private->UfsHcBase= UfsHcBase;
+  Private->Handle   = Controller;
+  Private->UfsHcDriverInterface.UfsHcProtocol = UfsHc;
+  Private->UfsHcDriverInterface.UfsExecUicCommand = 
UfsHcDriverInterfaceExecUicCommand;
   InitializeListHead (>Queue);
+
+  //
+  // This has to be done before initializing UfsHcInfo or calling the 
UfsControllerInit
+  //
+  if (mUfsHcPlatform == NULL) {
+Status = gBS->LocateProtocol (, NULL, 
(VOID**));
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_INFO, "No UfsHcPlatformProtocol present\n"));
+}
+  }
+
   Status = GetUfsHcInfo (Private);
   if (EFI_ERROR (Status)) {
 DEBUG ((DEBUG_ERROR, "Failed to initialize UfsHcInfo\n"));
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
index 101d0b4bb8..c2025a725e 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
@@ -69,6 +69,7 @@ typedef struct _UFS_PASS_THRU_PRIVATE_DATA {
   EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHostController;
   UINTN   UfsHcBase;
   EDKII_UFS_HC_INFO   UfsHcInfo;
+  EDKII_UFS_HC_DRIVER_INTERFACE   UfsHcDriverInterface;
 
   UINT8   TaskTag;
 
@@ -132,6 +133,13 @@ typedef struct {
   UFS_PASS_THRU_SIG \
   )
 
+#define UFS_PASS_THRU_PRIVATE_DATA_FROM_DRIVER_INTF(a) \
+  CR (a, \
+  UFS_PASS_THRU_PRIVATE_DATA, \
+  UfsHcDriverInterface, \
+  UFS_PASS_THRU_SIG \
+  )
+
 typedef struct _UFS_DEVICE_MANAGEMENT_REQUEST_PACKET {
   UINT64   Timeout;
   VOID *DataBuffer;
@@ -965,6 +973,23 @@ UfsRwUfsAttribute (
   IN OUT UINT32*AttrSize
   );
 
+/**
+  Execute UIC command.
+
+  @param[in]  ThisPointer to driver interface produced by the UFS 
controller.
+  @param[in, out] UicCommand  Descriptor of the command that will be executed.
+
+  @retval EFI_SUCCESSCommand executed successfully.
+  @retval EFI_INVALID_PARAMETER  This or UicCommand is NULL.
+  @retval Others Command failed to execute.
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverInterfaceExecUicCommand (
+  IN EDKII_UFS_HC_DRIVER_INTERFACE  *This,
+  IN OUT EDKII_UIC_COMMAND  *UicCommand
+  );
+
 /**
   Initializes UfsHcInfo field in private data.
 
@@ -981,5 +1006,6 @@ GetUfsHcInfo (
 extern EFI_COMPONENT_NAME_PROTOCOL  gUfsPassThruComponentName;
 extern EFI_COMPONENT_NAME2_PROTOCOL gUfsPassThruComponentName2;
 extern EFI_DRIVER_BINDING_PROTOCOL  gUfsPassThruDriverBinding;
+extern EDKII_UFS_HC_PLATFORM_PROTOCOL  *mUfsHcPlatform;
 
 #endif
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
index 467c533ceb..4838967b5e 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
@@ -59,6 +59,7 @@
   gEfiExtScsiPassThruProtocolGuid   ## BY_START
   gEfiUfsDeviceConfigProtocolGuid   ## BY_START
   

[edk2-devel] [PATCHv2 1/4] MdeModulePkg: Add definition of the EDKII_UFS_HC_PLATFORM_PROTOCOL

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

EDKII_UFS_HC_PLATFORM_PROTOCOL will allow the platform to inject
platform specific logic into standard UFS flows. Right now we
support callbacks pre and post host controller enable and pre
and post link startup. We also allow the platform to override
host controller capabilities and version which might be usefull
to manage silicon bugs or allow testing experimental features
from new version of the specification.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 .../Include/Protocol/UfsHostControllerPlatform.h   | 130 +
 MdeModulePkg/MdeModulePkg.dec  |   3 +
 2 files changed, 133 insertions(+)
 create mode 100644 MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h

diff --git a/MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h 
b/MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h
new file mode 100644
index 00..db7c5a5c99
--- /dev/null
+++ b/MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h
@@ -0,0 +1,130 @@
+/** @file
+  UfsHostControllerPlatformProtocol definition. This protocol is consumed by
+  generic UFS driver.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __EDKII_UFS_HC_PLATFORM_PROTOCOL_H__
+#define __EDKII_UFS_HC_PLATFORM_PROTOCOL_H__
+
+#include 
+
+#define EDKII_UFS_HC_PLATFORM_PROTOCOL_VERSION 1
+
+extern EFI_GUID  gEdkiiUfsHcPlatformProtocolGuid;
+
+typedef struct _EDKII_UFS_HC_PLATFORM_PROTOCOL  EDKII_UFS_HC_PLATFORM_PROTOCOL;
+
+typedef struct _EDKII_UFS_HC_DRIVER_INTERFACE  EDKII_UFS_HC_DRIVER_INTERFACE;
+
+typedef struct {
+  UINT32 Opcode;
+  UINT32 Arg1;
+  UINT32 Arg2;
+  UINT32 Arg3;
+} EDKII_UIC_COMMAND;
+
+/**
+  Execute UIC command
+
+  @param[in]  ThisPointer to driver interface produced by the UFS 
controller.
+  @param[in, out] UicCommand  Descriptor of the command that will be executed.
+
+  @retval EFI_SUCCESS  Command executed successfully.
+  @retval Others   Command failed to execute.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_UFS_EXEC_UIC_COMMAND) (
+  IN  EDKII_UFS_HC_DRIVER_INTERFACE  *This,
+  IN OUT  EDKII_UIC_COMMAND  *UicCommand
+);
+
+struct _EDKII_UFS_HC_DRIVER_INTERFACE {
+  ///
+  /// Protocol to accesss host controller MMIO and PCI registers.
+  ///
+  EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHcProtocol;
+  ///
+  /// Function implementing UIC command execution.
+  ///
+  EDKII_UFS_EXEC_UIC_COMMAND  UfsExecUicCommand;
+};
+
+typedef struct {
+  UINT32 Capabilities;
+  UINT32 Version;
+} EDKII_UFS_HC_INFO;
+
+/**
+  Allows platform protocol to override host controller information
+
+  @param[in]  ControllerHandle  Handle of the UFS controller.
+  @param[in, out] HcInfoPointer EDKII_UFS_HC_INFO associated with 
host controller.
+
+  @retval EFI_SUCCESSFunction completed successfully.
+  @retval EFI_INVALID_PARAMETER  HcInfo is NULL.
+  @retval Others Function failed to complete.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_UFS_HC_PLATFORM_OVERRIDE_HC_INFO) (
+  IN EFI_HANDLE ControllerHandle,
+  IN OUT EDKII_UFS_HC_INFO  *HcInfo
+);
+
+typedef enum {
+  EdkiiUfsHcPreHce,
+  EdkiiUfsHcPostHce,
+  EdkiiUfsHcPreLinkStartup,
+  EdkiiUfsHcPostLinkStartup
+} EDKII_UFS_HC_PLATFORM_CALLBACK_PHASE;
+
+/**
+  Callback function for platform driver.
+
+  @param[in]  ControllerHandle  Handle of the UFS controller.
+  @param[in]  CallbackPhase Specifies when the platform protocol is 
called
+  @param[in, out] CallbackData  Data specific to the callback phase.
+For PreHce and PostHce - 
EDKII_UFS_HC_DRIVER_INTERFACE.
+For PreLinkStartup and PostLinkStartup - 
EDKII_UFS_HC_DRIVER_INTERFACE.
+
+  @retval EFI_SUCCESSOverride function completed successfully.
+  @retval EFI_INVALID_PARAMETER  CallbackPhase is invalid or CallbackData is 
NULL when phase expects valid data.
+  @retval Others Function failed to complete.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_UFS_HC_PLATFORM_CALLBACK) (
+  IN EFI_HANDLEControllerHandle,
+  IN EDKII_UFS_HC_PLATFORM_CALLBACK_PHASE  CallbackPhase,
+  IN OUT VOID  *CallbackData
+);
+
+struct _EDKII_UFS_HC_PLATFORM_PROTOCOL {
+  ///
+  /// Version of the protocol.
+  ///
+  UINT32  Version;
+  ///
+  /// Allows platform driver to override host controller information.
+  

[edk2-devel] [PATCHv2 3/4] MdeModulePkg/UfsPassThruDxe: Refactor private data to use EDKII_UFS_HC_INFO

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

Private data has been refactored to use EDKII_UFS_HC_INFO structure
to store host controller capabilities and version
information. Getting host controller data has been moved
into single place and is done before host controller enable.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  |  6 ++-
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  | 15 +-
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 57 ++
 3 files changed, 56 insertions(+), 22 deletions(-)

diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
index e24eb40333..0c96dacf16 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
@@ -41,7 +41,7 @@ UFS_PASS_THRU_PRIVATE_DATA gUfsPassThruTemplate = {
   },
   0,  // UfsHostController
   0,  // UfsHcBase
-  0,  // Capabilities
+  {0, 0}, // UfsHcInfo
   0,  // TaskTag
   0,  // UtpTrlBase
   0,  // Nutrs
@@ -871,6 +871,10 @@ UfsPassThruDriverBindingStart (
   Private->UfsHostController= UfsHc;
   Private->UfsHcBase= UfsHcBase;
   InitializeListHead (>Queue);
+  Status = GetUfsHcInfo (Private);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to initialize UfsHcInfo\n"));
+  }
 
   //
   // Initialize UFS Host Controller H/W.
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
index fad4a8ee90..101d0b4bb8 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
@@ -68,7 +68,7 @@ typedef struct _UFS_PASS_THRU_PRIVATE_DATA {
   EFI_UFS_DEVICE_CONFIG_PROTOCOL  UfsDevConfig;
   EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHostController;
   UINTN   UfsHcBase;
-  UINT32  Capabilities;
+  EDKII_UFS_HC_INFO   UfsHcInfo;
 
   UINT8   TaskTag;
 
@@ -965,6 +965,19 @@ UfsRwUfsAttribute (
   IN OUT UINT32*AttrSize
   );
 
+/**
+  Initializes UfsHcInfo field in private data.
+
+  @param[in] Private  Pointer to host controller private data.
+
+  @retval EFI_SUCCESS  UfsHcInfo initialized successfully.
+  @retval Others   Failed to initalize UfsHcInfo.
+**/
+EFI_STATUS
+GetUfsHcInfo (
+  IN UFS_PASS_THRU_PRIVATE_DATA  *Private
+  );
+
 extern EFI_COMPONENT_NAME_PROTOCOL  gUfsPassThruComponentName;
 extern EFI_COMPONENT_NAME2_PROTOCOL gUfsPassThruComponentName2;
 extern EFI_DRIVER_BINDING_PROTOCOL  gUfsPassThruDriverBinding;
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
index 27f5711a31..edcd395091 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
@@ -737,7 +737,7 @@ UfsFindAvailableSlotInTrl (
 return Status;
   }
 
-  Nutrs   = (UINT8)((Private->Capabilities & UFS_HC_CAP_NUTRS) + 1);
+  Nutrs   = (UINT8)((Private->UfsHcInfo.Capabilities & UFS_HC_CAP_NUTRS) + 1);
 
   for (Index = 0; Index < Nutrs; Index++) {
 if ((Data & (BIT0 << Index)) == 0) {
@@ -1790,7 +1790,7 @@ UfsAllocateAlignCommonBuffer (
   BOOLEAN  Is32BitAddr;
   EDKII_UFS_HOST_CONTROLLER_PROTOCOL   *UfsHc;
 
-  if ((Private->Capabilities & UFS_HC_CAP_64ADDR) == UFS_HC_CAP_64ADDR) {
+  if ((Private->UfsHcInfo.Capabilities & UFS_HC_CAP_64ADDR) == 
UFS_HC_CAP_64ADDR) {
 Is32BitAddr = FALSE;
   } else {
 Is32BitAddr = TRUE;
@@ -1983,7 +1983,6 @@ UfsInitTaskManagementRequestList (
   IN  UFS_PASS_THRU_PRIVATE_DATA *Private
   )
 {
-  UINT32 Data;
   UINT8  Nutmrs;
   VOID   *CmdDescHost;
   EFI_PHYSICAL_ADDRESS   CmdDescPhyAddr;
@@ -1997,17 +1996,10 @@ UfsInitTaskManagementRequestList (
   CmdDescMapping = NULL;
   CmdDescPhyAddr = 0;
 
-  Status = UfsMmioRead32 (Private, UFS_HC_CAP_OFFSET, );
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
-  Private->Capabilities = Data;
-
   //
   // Allocate and initialize UTP Task Management Request List.
   //
-  Nutmrs = (UINT8) (RShiftU64 ((Private->Capabilities & UFS_HC_CAP_NUTMRS), 
16) + 1);
+  Nutmrs = (UINT8) (RShiftU64 ((Private->UfsHcInfo.Capabilities & 
UFS_HC_CAP_NUTMRS), 16) + 1);
   Status = UfsAllocateAlignCommonBuffer (Private, Nutmrs * sizeof (UTP_TMRD), 
, , );
   if (EFI_ERROR (Status)) {
 return Status;
@@ -2056,7 +2048,6 @@ UfsInitTransferRequestList (
   IN  UFS_PASS_THRU_PRIVATE_DATA *Private
   )
 {
-  UINT32 Data;
   UINT8  Nutrs;
   VOID   *CmdDescHost;
   

[edk2-devel] [PATCHv2 2/4] MdeModulePkg/UfsPassThruDxe: Refactor UfsExecUicCommand function

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

UfsExecUicCommand function has been refactored to allow
the caller to check the command results which is important
for commands such as UIC read.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  |  1 +
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 45 --
 2 files changed, 25 insertions(+), 21 deletions(-)

diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
index e092401f54..fad4a8ee90 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
index 52be852d65..27f5711a31 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
@@ -1669,11 +1669,8 @@ Exit1:
 /**
   Send UIC command.
 
-  @param[in] Private  The pointer to the UFS_PASS_THRU_PRIVATE_DATA 
data structure.
-  @param[in] UicOpcodeThe opcode of the UIC command.
-  @param[in] Arg1 The value for 1st argument of the UIC command.
-  @param[in] Arg2 The value for 2nd argument of the UIC command.
-  @param[in] Arg3 The value for 3rd argument of the UIC command.
+  @param[in]  Private The pointer to the UFS_PASS_THRU_PRIVATE_DATA 
data structure.
+  @param[in, out] UicCommand  UIC command descriptor. On exit contains UIC 
command results.
 
   @return EFI_SUCCESS  Successfully execute this UIC command and detect 
attached UFS device.
   @return EFI_DEVICE_ERROR Fail to execute this UIC command and detect 
attached UFS device.
@@ -1682,10 +1679,7 @@ Exit1:
 EFI_STATUS
 UfsExecUicCommands (
   IN  UFS_PASS_THRU_PRIVATE_DATA*Private,
-  IN  UINT8 UicOpcode,
-  IN  UINT32Arg1,
-  IN  UINT32Arg2,
-  IN  UINT32Arg3
+  IN OUT EDKII_UIC_COMMAND  *UicCommand
   )
 {
   EFI_STATUS  Status;
@@ -1711,17 +1705,17 @@ UfsExecUicCommands (
   // only after all the UIC command argument registers (UICCMDARG1, UICCMDARG2 
and UICCMDARG3)
   // are set.
   //
-  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG1_OFFSET, Arg1);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG1_OFFSET, UicCommand->Arg1);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
-  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG2_OFFSET, Arg2);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG2_OFFSET, UicCommand->Arg2);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
-  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG3_OFFSET, Arg3);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG3_OFFSET, UicCommand->Arg3);
   if (EFI_ERROR (Status)) {
 return Status;
   }
@@ -1734,7 +1728,7 @@ UfsExecUicCommands (
 return Status;
   }
 
-  Status = UfsMmioWrite32 (Private, UFS_HC_UIC_CMD_OFFSET, (UINT32)UicOpcode);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UIC_CMD_OFFSET, UicCommand->Opcode);
   if (EFI_ERROR (Status)) {
 return Status;
   }
@@ -1748,14 +1742,18 @@ UfsExecUicCommands (
 return Status;
   }
 
-  if (UicOpcode != UfsUicDmeReset) {
-Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG2_OFFSET, );
+  if (UicCommand->Opcode != UfsUicDmeReset) {
+Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG2_OFFSET, 
>Arg2);
 if (EFI_ERROR (Status)) {
   return Status;
 }
-if ((Data & 0xFF) != 0) {
+Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG3_OFFSET, 
>Arg3);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+if ((UicCommand->Arg2 & 0xFF) != 0) {
   DEBUG_CODE_BEGIN();
-DumpUicCmdExecResult (UicOpcode, (UINT8)(Data & 0xFF));
+DumpUicCmdExecResult ((UINT8)UicCommand->Opcode, 
(UINT8)(UicCommand->Arg2 & 0xFF));
   DEBUG_CODE_END();
   return EFI_DEVICE_ERROR;
 }
@@ -1934,16 +1932,21 @@ UfsDeviceDetection (
   IN  UFS_PASS_THRU_PRIVATE_DATA *Private
   )
 {
-  UINTN   Retry;
-  EFI_STATUS  Status;
-  UINT32  Data;
+  UINTN  Retry;
+  EFI_STATUS Status;
+  UINT32 Data;
+  EDKII_UIC_COMMAND  LinkStartupCommand;
 
   //
   // Start UFS device detection.
   // Try up to 3 times for establishing data link with device.
   //
   for (Retry = 0; Retry < 3; Retry++) {
-Status = UfsExecUicCommands (Private, UfsUicDmeLinkStartup, 0, 0, 0);
+LinkStartupCommand.Opcode = UfsUicDmeLinkStartup;
+LinkStartupCommand.Arg1 = 0;
+LinkStartupCommand.Arg2 = 0;
+LinkStartupCommand.Arg3 = 0;
+Status = UfsExecUicCommands (Private, );
 if (EFI_ERROR (Status)) {
   return EFI_DEVICE_ERROR;
 }
-- 
2.14.1.windows.1

[edk2-devel] [PATCHv2 0/4] Add EDKII_UFS_HC_PLATFORM_PROTOCOL to support platform specific programming of UFS host controllers

[Albecki, Mateusz]

To cover additional host controller programming mentioned in the UFS 
specification we have added an additional protocol
that allows the UEFI driver to give control to platform driver. This allows the 
platform to perform any additional
steps needed for the stable operation.

Changes in v2:
- UFS driver will abort initializaton when it fails to get host controler 
information
- Fixed bug with calling post link startup callback on failed device detection

Test coverage:
Tested on platform with UFS 2.1 host controller with Samsung UFS2.0 part with 3 
LUs enabled All LUs have been enumerated in boot manager.
Tested that enumeration works without platform protocol installed(on host 
controller that can support it) Tested that enumeration works with platform 
protocol installed and with additional programming steps after link 
startup(power mode change to GEAR2).

Cc: Hao A Wu https://edk2.groups.io/g/devel/message/45265
Mute This Topic: https://groups.io/mt/32809834/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub  [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-

Re: [edk2-devel] [PATCH 4/4] MdeModulePkg/UfsPassThruDxe: Implement EDKII_UFS_HC_PLATFORM_PROTOCOL

[Albecki, Mateusz]

Hi,

Yes that is bug. It should be placed before return EFI_SUCCESS. I will fix it 
in v2.

Thanks,
Mateusz

> -Original Message-
> From: Wu, Hao A
> Sent: Thursday, August 8, 2019 4:37 AM
> To: Albecki, Mateusz ; devel@edk2.groups.io
> Subject: RE: [PATCH 4/4] MdeModulePkg/UfsPassThruDxe: Implement
> EDKII_UFS_HC_PLATFORM_PROTOCOL
> 
> Hello Mateusz,
> 
> One inline comment below:
> 
> 
> > -----Original Message-
> > From: Albecki, Mateusz
> > Sent: Thursday, August 08, 2019 12:51 AM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A
> > Subject: [PATCH 4/4] MdeModulePkg/UfsPassThruDxe: Implement
> > EDKII_UFS_HC_PLATFORM_PROTOCOL
> >
> > https://bugzilla.tianocore.org/show_bug.cgi?id=1343
> >
> > This commit adds EDKII_UFS_HC_PLATFORM_PROTOCOL implementation
> in
> > UfsPassThruDxe driver in version 1. Driver assumes that at most one
> > instance of the protocol exists in the system. Presence of the
> > protocol is not mandatory.
> >
> > Cc: Hao A Wu 
> > Signed-off-by: Mateusz Albecki 
> > ---
> >  MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  | 17 ++
> > MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  | 26 +
> >  .../Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf  |  3 +-
> >  .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 68
> > ++
> >  4 files changed, 113 insertions(+), 1 deletion(-)
> >
> > diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
> > b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
> > index 09333c51d6..1559efe191 100644
> > --- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
> > +++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
> > @@ -36,6 +36,7 @@ UFS_PASS_THRU_PRIVATE_DATA
> gUfsPassThruTemplate = {
> >0,  // UfsHostController
> >0,  // UfsHcBase
> >{0, 0}, // UfsHcInfo
> > +  {NULL, NULL},   // UfsHcDriverInterface
> >0,  // TaskTag
> >0,  // UtpTrlBase
> >0,  // Nutrs
> > @@ -92,6 +93,8 @@ UFS_DEVICE_PATHmUfsDevicePathTemplate = {
> >
> >  UINT8 mUfsTargetId[TARGET_MAX_BYTES];
> >
> > +GLOBAL_REMOVE_IF_UNREFERENCED
> > EDKII_UFS_HC_PLATFORM_PROTOCOL  *mUfsHcPlatform;
> > +
> >  /**
> >Sends a SCSI Request Packet to a SCSI device that is attached to
> > the SCSI channel. This function
> >supports both blocking I/O and nonblocking I/O. The blocking I/O
> > functionality is required, and the @@ -864,7 +867,21 @@
> > UfsPassThruDriverBindingStart (
> >Private->ExtScsiPassThru.Mode = >ExtScsiPassThruMode;
> >Private->UfsHostController= UfsHc;
> >Private->UfsHcBase= UfsHcBase;
> > +  Private->Handle   = Controller;
> > +  Private->UfsHcDriverInterface.UfsHcProtocol = UfsHc;
> > + Private->UfsHcDriverInterface.UfsExecUicCommand =
> > UfsHcDriverInterfaceExecUicCommand;
> >InitializeListHead (>Queue);
> > +
> > +  //
> > +  // This has to be done before initializing UfsHcInfo or calling the
> > UfsControllerInit
> > +  //
> > +  if (mUfsHcPlatform == NULL) {
> > +Status = gBS->LocateProtocol (,
> > + NULL,
> > (VOID**));
> > +if (EFI_ERROR (Status)) {
> > +  DEBUG ((DEBUG_INFO, "No UfsHcPlatformProtocol present\n"));
> > +}
> > +  }
> > +
> >Status = GetUfsHcInfo (Private);
> >if (EFI_ERROR (Status)) {
> >  DEBUG ((DEBUG_ERROR, "Failed to initialize UfsHcInfo\n")); diff
> > --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
> > b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
> > index c511aa8c7a..cbc0c2126e 100644
> > --- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
> > +++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
> > @@ -63,6 +63,7 @@ typedef struct _UFS_PASS_THRU_PRIVATE_DATA {
> >EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHostController;
> >UINTN   UfsHcBase;
> >EDKII_UFS_HC_INFO   UfsHcInfo;
> > +  EDKII_UFS_HC_DRIVER_INTERFACE   UfsHcDriverInterface;
> >
> >UINT8   TaskTag;
> >
> > @@ -126,6 +127,13 @@ typedef struct {
> >UFS_PASS_THRU_SIG \
> >)
> >
> > +#define UFS_PASS_THRU_PRIVATE_DATA_FROM_DRIVER_INTF(a) \
> > +  CR (a

Re: [edk2-devel] [PATCH 3/4] MdeModulePkg/UfsPassThruDxe: Refactor private data to use EDKII_UFS_HC_INFO

[Albecki, Mateusz]

Hi,

Sure I agree. That was my original intention and then I forgot to add goto 
Error.

Thanks,
Mateusz

> -Original Message-
> From: Wu, Hao A
> Sent: Thursday, August 8, 2019 4:37 AM
> To: devel@edk2.groups.io; Albecki, Mateusz 
> Subject: RE: [edk2-devel] [PATCH 3/4] MdeModulePkg/UfsPassThruDxe:
> Refactor private data to use EDKII_UFS_HC_INFO
> 
> Hello Mateusz,
> 
> One inline comment below:
> 
> 
> > -Original Message-
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Albecki, Mateusz
> > Sent: Thursday, August 08, 2019 12:51 AM
> > To: devel@edk2.groups.io
> > Cc: Albecki, Mateusz; Wu, Hao A
> > Subject: [edk2-devel] [PATCH 3/4] MdeModulePkg/UfsPassThruDxe:
> > Refactor private data to use EDKII_UFS_HC_INFO
> >
> > https://bugzilla.tianocore.org/show_bug.cgi?id=1343
> >
> > Private data has been refactored to use EDKII_UFS_HC_INFO structure to
> > store host controller capabilities and version information. Getting
> > host controller data has been moved into single place and is done
> > before host controller enable.
> >
> > Cc: Hao A Wu 
> > Signed-off-by: Mateusz Albecki 
> > ---
> >  MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  |  8 ++-
> > MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  | 15 +-
> >  .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 57 ++--
> --
> > 
> >  3 files changed, 57 insertions(+), 23 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
> > b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
> > index 1518b251d8..09333c51d6 100644
> > --- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
> > +++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
> > @@ -1,6 +1,6 @@
> >  /** @file
> >
> > -  Copyright (c) 2014 - 2018, Intel Corporation. All rights
> > reserved.
> > +  Copyright (c) 2014 - 2019, Intel Corporation. All rights
> > + reserved.
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> >  **/
> > @@ -35,7 +35,7 @@ UFS_PASS_THRU_PRIVATE_DATA
> gUfsPassThruTemplate = {
> >},
> >0,  // UfsHostController
> >0,  // UfsHcBase
> > -  0,  // Capabilities
> > +  {0, 0}, // UfsHcInfo
> >0,  // TaskTag
> >0,  // UtpTrlBase
> >0,  // Nutrs
> > @@ -865,6 +865,10 @@ UfsPassThruDriverBindingStart (
> >Private->UfsHostController= UfsHc;
> >Private->UfsHcBase= UfsHcBase;
> >InitializeListHead (>Queue);
> > +  Status = GetUfsHcInfo (Private);
> > +  if (EFI_ERROR (Status)) {
> > +DEBUG ((DEBUG_ERROR, "Failed to initialize UfsHcInfo\n"));  }
> >
> 
> I think when the driver fails to read the CAP & VER registers of the UFS HC,
> the initialization process should be aborted.
> 
> Do you agree to change the code to:
> 
>   Status = GetUfsHcInfo (Private);
>   if (EFI_ERROR (Status)) {
> DEBUG ((DEBUG_ERROR, "Failed to initialize UfsHcInfo\n"));
> goto Error;
> ^^^
>   }
> 
> when I push this patch?
> 
> Other than this, the patch is good to me,
> Reviewed-by: Hao A Wu 
> 
> Best Regards,
> Hao Wu
> 
> 
> >//
> >// Initialize UFS Host Controller H/W.
> > diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
> > b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
> > index b79be77709..c511aa8c7a 100644
> > --- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
> > +++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
> > @@ -62,7 +62,7 @@ typedef struct _UFS_PASS_THRU_PRIVATE_DATA {
> >EFI_UFS_DEVICE_CONFIG_PROTOCOL  UfsDevConfig;
> >EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHostController;
> >UINTN   UfsHcBase;
> > -  UINT32  Capabilities;
> > +  EDKII_UFS_HC_INFO   UfsHcInfo;
> >
> >UINT8   TaskTag;
> >
> > @@ -959,6 +959,19 @@ UfsRwUfsAttribute (
> >IN OUT UINT32*AttrSize
> >);
> >
> > +/**
> > +  Initializes UfsHcInfo field in private data.
> > +
> > +  @param[in] Private  Pointer to host controller private data.
> > +
> > +  @retval EFI_SUCCESS  UfsHcInfo initialized successfully.
> > +  @retval Others   

[edk2-devel] [PATCH 4/4] MdeModulePkg/UfsPassThruDxe: Implement EDKII_UFS_HC_PLATFORM_PROTOCOL

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

This commit adds EDKII_UFS_HC_PLATFORM_PROTOCOL implementation
in UfsPassThruDxe driver in version 1. Driver assumes that at
most one instance of the protocol exists in the system. Presence
of the protocol is not mandatory.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  | 17 ++
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  | 26 +
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf  |  3 +-
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 68 ++
 4 files changed, 113 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
index 09333c51d6..1559efe191 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
@@ -36,6 +36,7 @@ UFS_PASS_THRU_PRIVATE_DATA gUfsPassThruTemplate = {
   0,  // UfsHostController
   0,  // UfsHcBase
   {0, 0}, // UfsHcInfo
+  {NULL, NULL},   // UfsHcDriverInterface
   0,  // TaskTag
   0,  // UtpTrlBase
   0,  // Nutrs
@@ -92,6 +93,8 @@ UFS_DEVICE_PATHmUfsDevicePathTemplate = {
 
 UINT8 mUfsTargetId[TARGET_MAX_BYTES];
 
+GLOBAL_REMOVE_IF_UNREFERENCED EDKII_UFS_HC_PLATFORM_PROTOCOL  *mUfsHcPlatform;
+
 /**
   Sends a SCSI Request Packet to a SCSI device that is attached to the SCSI 
channel. This function
   supports both blocking I/O and nonblocking I/O. The blocking I/O 
functionality is required, and the
@@ -864,7 +867,21 @@ UfsPassThruDriverBindingStart (
   Private->ExtScsiPassThru.Mode = >ExtScsiPassThruMode;
   Private->UfsHostController= UfsHc;
   Private->UfsHcBase= UfsHcBase;
+  Private->Handle   = Controller;
+  Private->UfsHcDriverInterface.UfsHcProtocol = UfsHc;
+  Private->UfsHcDriverInterface.UfsExecUicCommand = 
UfsHcDriverInterfaceExecUicCommand;
   InitializeListHead (>Queue);
+
+  //
+  // This has to be done before initializing UfsHcInfo or calling the 
UfsControllerInit
+  //
+  if (mUfsHcPlatform == NULL) {
+Status = gBS->LocateProtocol (, NULL, 
(VOID**));
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_INFO, "No UfsHcPlatformProtocol present\n"));
+}
+  }
+
   Status = GetUfsHcInfo (Private);
   if (EFI_ERROR (Status)) {
 DEBUG ((DEBUG_ERROR, "Failed to initialize UfsHcInfo\n"));
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
index c511aa8c7a..cbc0c2126e 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
@@ -63,6 +63,7 @@ typedef struct _UFS_PASS_THRU_PRIVATE_DATA {
   EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHostController;
   UINTN   UfsHcBase;
   EDKII_UFS_HC_INFO   UfsHcInfo;
+  EDKII_UFS_HC_DRIVER_INTERFACE   UfsHcDriverInterface;
 
   UINT8   TaskTag;
 
@@ -126,6 +127,13 @@ typedef struct {
   UFS_PASS_THRU_SIG \
   )
 
+#define UFS_PASS_THRU_PRIVATE_DATA_FROM_DRIVER_INTF(a) \
+  CR (a, \
+  UFS_PASS_THRU_PRIVATE_DATA, \
+  UfsHcDriverInterface, \
+  UFS_PASS_THRU_SIG \
+  )
+
 typedef struct _UFS_DEVICE_MANAGEMENT_REQUEST_PACKET {
   UINT64   Timeout;
   VOID *DataBuffer;
@@ -959,6 +967,23 @@ UfsRwUfsAttribute (
   IN OUT UINT32*AttrSize
   );
 
+/**
+  Execute UIC command.
+
+  @param[in]  ThisPointer to driver interface produced by the UFS 
controller.
+  @param[in, out] UicCommand  Descriptor of the command that will be executed.
+
+  @retval EFI_SUCCESSCommand executed successfully.
+  @retval EFI_INVALID_PARAMETER  This or UicCommand is NULL.
+  @retval Others Command failed to execute.
+**/
+EFI_STATUS
+EFIAPI
+UfsHcDriverInterfaceExecUicCommand (
+  IN EDKII_UFS_HC_DRIVER_INTERFACE  *This,
+  IN OUT EDKII_UIC_COMMAND  *UicCommand
+  );
+
 /**
   Initializes UfsHcInfo field in private data.
 
@@ -975,5 +1000,6 @@ GetUfsHcInfo (
 extern EFI_COMPONENT_NAME_PROTOCOL  gUfsPassThruComponentName;
 extern EFI_COMPONENT_NAME2_PROTOCOL gUfsPassThruComponentName2;
 extern EFI_DRIVER_BINDING_PROTOCOL  gUfsPassThruDriverBinding;
+extern EDKII_UFS_HC_PLATFORM_PROTOCOL  *mUfsHcPlatform;
 
 #endif
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
index 24f5ea3a8f..92dc25714b 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf
@@ -1,7 +1,7 @@
 ## @file
 # Description file for the Universal Flash Storage (UFS) Pass Thru driver.
 #
-# Copyright (c) 2014 - 2018, Intel 

[edk2-devel] [PATCH 2/4] MdeModulePkg/UfsPassThruDxe: Refactor UfsExecUicCommand function

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

UfsExecUicCommand function has been refactored to allow
the caller to check the command results which is important
for commands such as UIC read.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  |  3 +-
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 47 --
 2 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
index 9b68db5ffe..b79be77709 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
index 912d6f8202..6ea27e473c 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
@@ -2,7 +2,7 @@
   UfsPassThruDxe driver is used to produce EFI_EXT_SCSI_PASS_THRU protocol 
interface
   for upper layer application to execute UFS-supported SCSI cmds.
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -1633,11 +1633,8 @@ Exit1:
 /**
   Send UIC command.
 
-  @param[in] Private  The pointer to the UFS_PASS_THRU_PRIVATE_DATA 
data structure.
-  @param[in] UicOpcodeThe opcode of the UIC command.
-  @param[in] Arg1 The value for 1st argument of the UIC command.
-  @param[in] Arg2 The value for 2nd argument of the UIC command.
-  @param[in] Arg3 The value for 3rd argument of the UIC command.
+  @param[in]  Private The pointer to the UFS_PASS_THRU_PRIVATE_DATA 
data structure.
+  @param[in, out] UicCommand  UIC command descriptor. On exit contains UIC 
command results.
 
   @return EFI_SUCCESS  Successfully execute this UIC command and detect 
attached UFS device.
   @return EFI_DEVICE_ERROR Fail to execute this UIC command and detect 
attached UFS device.
@@ -1646,10 +1643,7 @@ Exit1:
 EFI_STATUS
 UfsExecUicCommands (
   IN  UFS_PASS_THRU_PRIVATE_DATA*Private,
-  IN  UINT8 UicOpcode,
-  IN  UINT32Arg1,
-  IN  UINT32Arg2,
-  IN  UINT32Arg3
+  IN OUT EDKII_UIC_COMMAND  *UicCommand
   )
 {
   EFI_STATUS  Status;
@@ -1675,17 +1669,17 @@ UfsExecUicCommands (
   // only after all the UIC command argument registers (UICCMDARG1, UICCMDARG2 
and UICCMDARG3)
   // are set.
   //
-  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG1_OFFSET, Arg1);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG1_OFFSET, UicCommand->Arg1);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
-  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG2_OFFSET, Arg2);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG2_OFFSET, UicCommand->Arg2);
   if (EFI_ERROR (Status)) {
 return Status;
   }
 
-  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG3_OFFSET, Arg3);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UCMD_ARG3_OFFSET, UicCommand->Arg3);
   if (EFI_ERROR (Status)) {
 return Status;
   }
@@ -1698,7 +1692,7 @@ UfsExecUicCommands (
 return Status;
   }
 
-  Status = UfsMmioWrite32 (Private, UFS_HC_UIC_CMD_OFFSET, (UINT32)UicOpcode);
+  Status = UfsMmioWrite32 (Private, UFS_HC_UIC_CMD_OFFSET, UicCommand->Opcode);
   if (EFI_ERROR (Status)) {
 return Status;
   }
@@ -1712,14 +1706,18 @@ UfsExecUicCommands (
 return Status;
   }
 
-  if (UicOpcode != UfsUicDmeReset) {
-Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG2_OFFSET, );
+  if (UicCommand->Opcode != UfsUicDmeReset) {
+Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG2_OFFSET, 
>Arg2);
 if (EFI_ERROR (Status)) {
   return Status;
 }
-if ((Data & 0xFF) != 0) {
+Status = UfsMmioRead32 (Private, UFS_HC_UCMD_ARG3_OFFSET, 
>Arg3);
+if (EFI_ERROR (Status)) {
+  return Status;
+}
+if ((UicCommand->Arg2 & 0xFF) != 0) {
   DEBUG_CODE_BEGIN();
-DumpUicCmdExecResult (UicOpcode, (UINT8)(Data & 0xFF));
+DumpUicCmdExecResult ((UINT8)UicCommand->Opcode, 
(UINT8)(UicCommand->Arg2 & 0xFF));
   DEBUG_CODE_END();
   return EFI_DEVICE_ERROR;
 }
@@ -1898,16 +1896,21 @@ UfsDeviceDetection (
   IN  UFS_PASS_THRU_PRIVATE_DATA *Private
   )
 {
-  UINTN   Retry;
-  EFI_STATUS  Status;
-  UINT32  Data;
+  UINTN  Retry;
+  EFI_STATUS Status;
+  UINT32 Data;
+  

[edk2-devel] [PATCH 3/4] MdeModulePkg/UfsPassThruDxe: Refactor private data to use EDKII_UFS_HC_INFO

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

Private data has been refactored to use EDKII_UFS_HC_INFO structure
to store host controller capabilities and version
information. Getting host controller data has been moved
into single place and is done before host controller enable.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  |  8 ++-
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  | 15 +-
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 57 ++
 3 files changed, 57 insertions(+), 23 deletions(-)

diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
index 1518b251d8..09333c51d6 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -35,7 +35,7 @@ UFS_PASS_THRU_PRIVATE_DATA gUfsPassThruTemplate = {
   },
   0,  // UfsHostController
   0,  // UfsHcBase
-  0,  // Capabilities
+  {0, 0}, // UfsHcInfo
   0,  // TaskTag
   0,  // UtpTrlBase
   0,  // Nutrs
@@ -865,6 +865,10 @@ UfsPassThruDriverBindingStart (
   Private->UfsHostController= UfsHc;
   Private->UfsHcBase= UfsHcBase;
   InitializeListHead (>Queue);
+  Status = GetUfsHcInfo (Private);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to initialize UfsHcInfo\n"));
+  }
 
   //
   // Initialize UFS Host Controller H/W.
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
index b79be77709..c511aa8c7a 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h
@@ -62,7 +62,7 @@ typedef struct _UFS_PASS_THRU_PRIVATE_DATA {
   EFI_UFS_DEVICE_CONFIG_PROTOCOL  UfsDevConfig;
   EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHostController;
   UINTN   UfsHcBase;
-  UINT32  Capabilities;
+  EDKII_UFS_HC_INFO   UfsHcInfo;
 
   UINT8   TaskTag;
 
@@ -959,6 +959,19 @@ UfsRwUfsAttribute (
   IN OUT UINT32*AttrSize
   );
 
+/**
+  Initializes UfsHcInfo field in private data.
+
+  @param[in] Private  Pointer to host controller private data.
+
+  @retval EFI_SUCCESS  UfsHcInfo initialized successfully.
+  @retval Others   Failed to initalize UfsHcInfo.
+**/
+EFI_STATUS
+GetUfsHcInfo (
+  IN UFS_PASS_THRU_PRIVATE_DATA  *Private
+  );
+
 extern EFI_COMPONENT_NAME_PROTOCOL  gUfsPassThruComponentName;
 extern EFI_COMPONENT_NAME2_PROTOCOL gUfsPassThruComponentName2;
 extern EFI_DRIVER_BINDING_PROTOCOL  gUfsPassThruDriverBinding;
diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c 
b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
index 6ea27e473c..74be3efc41 100644
--- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
+++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c
@@ -731,7 +731,7 @@ UfsFindAvailableSlotInTrl (
 return Status;
   }
 
-  Nutrs   = (UINT8)((Private->Capabilities & UFS_HC_CAP_NUTRS) + 1);
+  Nutrs   = (UINT8)((Private->UfsHcInfo.Capabilities & UFS_HC_CAP_NUTRS) + 1);
 
   for (Index = 0; Index < Nutrs; Index++) {
 if ((Data & (BIT0 << Index)) == 0) {
@@ -1754,7 +1754,7 @@ UfsAllocateAlignCommonBuffer (
   BOOLEAN  Is32BitAddr;
   EDKII_UFS_HOST_CONTROLLER_PROTOCOL   *UfsHc;
 
-  if ((Private->Capabilities & UFS_HC_CAP_64ADDR) == UFS_HC_CAP_64ADDR) {
+  if ((Private->UfsHcInfo.Capabilities & UFS_HC_CAP_64ADDR) == 
UFS_HC_CAP_64ADDR) {
 Is32BitAddr = FALSE;
   } else {
 Is32BitAddr = TRUE;
@@ -1947,7 +1947,6 @@ UfsInitTaskManagementRequestList (
   IN  UFS_PASS_THRU_PRIVATE_DATA *Private
   )
 {
-  UINT32 Data;
   UINT8  Nutmrs;
   VOID   *CmdDescHost;
   EFI_PHYSICAL_ADDRESS   CmdDescPhyAddr;
@@ -1961,17 +1960,10 @@ UfsInitTaskManagementRequestList (
   CmdDescMapping = NULL;
   CmdDescPhyAddr = 0;
 
-  Status = UfsMmioRead32 (Private, UFS_HC_CAP_OFFSET, );
-  if (EFI_ERROR (Status)) {
-return Status;
-  }
-
-  Private->Capabilities = Data;
-
   //
   // Allocate and initialize UTP Task Management Request List.
   //
-  Nutmrs = (UINT8) (RShiftU64 ((Private->Capabilities & UFS_HC_CAP_NUTMRS), 
16) + 1);
+  Nutmrs = (UINT8) (RShiftU64 ((Private->UfsHcInfo.Capabilities & 
UFS_HC_CAP_NUTMRS), 16) + 1);
   Status = UfsAllocateAlignCommonBuffer (Private, Nutmrs * sizeof (UTP_TMRD), 
, , );
   if (EFI_ERROR (Status)) {
 return 

[edk2-devel] [PATCH 1/4] MdeModulePkg: Add definition of the EDKII_UFS_HC_PLATFORM_PROTOCOL

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1343

EDKII_UFS_HC_PLATFORM_PROTOCOL will allow the platform to inject
platform specific logic into standard UFS flows. Right now we
support callbacks pre and post host controller enable and pre
and post link startup. Provided callbacks allow the platform
driver to inject UIC programming after HCE is set which is
a standard initialization step covered by UFS specification as
well as cover some additional use cases during other calllbacks.
For instance platform driver may switch to fast mode after link
startup.

We also allow the platform to override host controller capabilities
and version which might be usefull to manage silicon bugs or
allow testign experimental features from new versions of the
specification.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 .../Include/Protocol/UfsHostControllerPlatform.h   | 124 +
 MdeModulePkg/MdeModulePkg.dec  |   3 +
 2 files changed, 127 insertions(+)
 create mode 100644 MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h

diff --git a/MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h 
b/MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h
new file mode 100644
index 00..0f6732a1f8
--- /dev/null
+++ b/MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h
@@ -0,0 +1,124 @@
+/** @file
+  EDKII_UFS_HC_PLATFORM_PROTOCOL definition.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __EDKII_UFS_HC_PLATFORM_PROTOCOL_H__
+#define __EDKII_UFS_HC_PLATFORM_PROTOCOL_H__
+
+#include 
+
+#define EDKII_UFS_HC_PLATFORM_PROTOCOL_VERSION 1
+
+extern EFI_GUID  gEdkiiUfsHcPlatformProtocolGuid;
+
+typedef struct _EDKII_UFS_HC_PLATFORM_PROTOCOL  EDKII_UFS_HC_PLATFORM_PROTOCOL;
+
+typedef struct _EDKII_UFS_HC_DRIVER_INTERFACE  EDKII_UFS_HC_DRIVER_INTERFACE;
+
+typedef struct {
+  UINT32 Opcode;
+  UINT32 Arg1;
+  UINT32 Arg2;
+  UINT32 Arg3;
+} EDKII_UIC_COMMAND;
+
+/**
+  Execute UIC command
+
+  @param[in]  ThisPointer to driver interface produced by the UFS 
controller.
+  @param[in, out] UicCommand  Descriptor of the command that will be executed.
+
+  @retval EFI_SUCCESSCommand executed successfully.
+  @retval EFI_INVALID_PARAMETER  This or UicCommand is NULL.
+  @retval Others Command failed to execute.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_UFS_EXEC_UIC_COMMAND) (
+  IN  EDKII_UFS_HC_DRIVER_INTERFACE  *This,
+  IN OUT  EDKII_UIC_COMMAND  *UicCommand
+);
+
+struct _EDKII_UFS_HC_DRIVER_INTERFACE {
+  ///
+  /// Protocol to accesss host controller MMIO and PCI registers.
+  ///
+  EDKII_UFS_HOST_CONTROLLER_PROTOCOL  *UfsHcProtocol;
+  ///
+  /// Function implementing UIC command execution.
+  ///
+  EDKII_UFS_EXEC_UIC_COMMAND  UfsExecUicCommand;
+};
+
+typedef struct {
+  UINT32 Capabilities;
+  UINT32 Version;
+} EDKII_UFS_HC_INFO;
+
+/**
+  Allows platform protocol to override host controller information
+
+  @param[in]  ControllerHandle  Handle of the UFS controller.
+  @param[in, out] HcInfoPointer EDKII_UFS_HC_INFO associated with 
host controller.
+
+  @retval EFI_SUCCESSFunction completed successfully.
+  @retval EFI_INVALID_PARAMETER  HcInfo is NULL.
+  @retval Others Function failed to complete.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_UFS_HC_PLATFORM_OVERRIDE_HC_INFO) (
+  IN EFI_HANDLE ControllerHandle,
+  IN OUT EDKII_UFS_HC_INFO  *HcInfo
+);
+
+typedef enum {
+  EdkiiUfsHcPreHce,
+  EdkiiUfsHcPostHce,
+  EdkiiUfsHcPreLinkStartup,
+  EdkiiUfsHcPostLinkStartup
+} EDKII_UFS_HC_PLATFORM_CALLBACK_PHASE;
+
+/**
+  Callback function for platform driver.
+
+  @param[in]  ControllerHandle  Handle of the UFS controller.
+  @param[in]  CallbackPhase Specifies when the platform protocol is 
called
+  @param[in, out] CallbackData  Data specific to the callback phase.
+For PreHce and PostHce - 
EDKII_UFS_HC_DRIVER_INTERFACE.
+For PreLinkStartup and PostLinkStartup - 
EDKII_UFS_HC_DRIVER_INTERFACE.
+
+  @retval EFI_SUCCESSOverride function completed successfully.
+  @retval EFI_INVALID_PARAMETER  CallbackPhase is invalid or CallbackData is 
NULL when phase expects valid data.
+  @retval Others Function failed to complete.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EDKII_UFS_HC_PLATFORM_CALLBACK) (
+  IN EFI_HANDLEControllerHandle,
+  IN EDKII_UFS_HC_PLATFORM_CALLBACK_PHASE  CallbackPhase,
+  IN OUT VOID  *CallbackData
+);
+
+struct _EDKII_UFS_HC_PLATFORM_PROTOCOL {
+  ///
+  /// Version of the protocol.
+  ///
+  UINT32  Version;
+  ///
+  /// Allows platform driver to override host controller information.
+  ///
+  EDKII_UFS_HC_PLATFORM_OVERRIDE_HC_INFO  

[edk2-devel] [PATCH 0/4] Add EDKII_UFS_HC_PLATFORM_PROTOCOL to support platform specific programming of UFS host controllers

[Albecki, Mateusz]

To cover additional host controller programming mentioned in the UFS 
specification
we have added an additional protocol that allows the UEFI driver to give control
to platform driver. This allows the platform to perform any additional steps
needed for the stable operation.

Test coverage:
Tested on platform with UFS 2.1 host controller with Samsung UFS2.0 part with 3 
LUs enabled
All LUs have been enumerated in boot manager.
Tested that enumeration works without platform protocol installed(on host 
controller that can support it)
Tested that enumeration works with platform protocol installed and with 
additional programming steps after
link startup(power mode change to GEAR2).

Cc: Hao A Wu 

Mateusz Albecki (4):
  MdeModulePkg: Add definition of the EDKII_UFS_HC_PLATFORM_PROTOCOL
  MdeModulePkg/UfsPassThruDxe: Refactor UfsExecUicCommand function
  MdeModulePkg/UfsPassThruDxe: Refactor private data to use
EDKII_UFS_HC_INFO
  MdeModulePkg/UfsPassThruDxe: Implement EDKII_UFS_HC_PLATFORM_PROTOCOL

 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.c  |  25 ++-
 MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h  |  44 +-
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf  |   3 +-
 .../Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c| 172 -
 .../Include/Protocol/UfsHostControllerPlatform.h   | 124 +++
 MdeModulePkg/MdeModulePkg.dec  |   3 +
 6 files changed, 324 insertions(+), 47 deletions(-)
 create mode 100644 MdeModulePkg/Include/Protocol/UfsHostControllerPlatform.h

-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
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[edk2-devel] [PATCH v4 1/2] MdeModulePkg/SdMmcOverride: Add GetOperatingParam notify phase

[Albecki, Mateusz]

https://bugzilla.tianocore.org/show_bug.cgi?id=1882

The new notify phase allows platform to configure additional
bus paramters in addition to parameters that can already be configured
with capability override. Specifically we allow to configure bus width,
clock frequency and driver strength. If platform doesn't wish to configure
some of the parameters it can left it on default values and driver will
assume it's standard behavior with respect to those parameters.
The definition of the SD_MMC_BUS_MODE has been extended to
incorporate SD card default speed and high speed.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Include/Protocol/SdMmcOverride.h | 60 +++
 1 file changed, 53 insertions(+), 7 deletions(-)

diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h 
b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
index 9c8bf37efd..d44027260a 100644
--- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
+++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
@@ -16,19 +16,66 @@
 #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
   { 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 
0x23 } }
 
-#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION0x2
+#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION0x3
 
 typedef struct _EDKII_SD_MMC_OVERRIDE EDKII_SD_MMC_OVERRIDE;
 
-//
-// Bus timing modes
-//
+#define EDKII_SD_MMC_BUS_WIDTH_IGNORE MAX_UINT8
+#define EDKII_SD_MMC_CLOCK_FREQ_IGNORE MAX_UINT32
+#define EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE  MAX_UINT8
+
+typedef enum {
+  SdDriverStrengthTypeB= 0,
+  SdDriverStrengthTypeA,
+  SdDriverStrengthTypeC,
+  SdDriverStrengthTypeD,
+  SdDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE
+} SD_DRIVER_STRENGTH_TYPE;
+
 typedef enum {
+  EmmcDriverStrengthType0  = 0,
+  EmmcDriverStrengthType1,
+  EmmcDriverStrengthType2,
+  EmmcDriverStrengthType3,
+  EmmcDriverStrengthType4,
+  EmmcDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE
+} EMMC_DRIVER_STRENGTH_TYPE;
+
+typedef union {
+  SD_DRIVER_STRENGTH_TYPE  Sd;
+  EMMC_DRIVER_STRENGTH_TYPEEmmc;
+} EDKII_SD_MMC_DRIVER_STRENGTH;
+
+typedef struct {
+  //
+  // The target width of the bus. If user tells driver to ignore it
+  // or specifies unsupported width driver will choose highest supported
+  // bus width for a given mode.
+  //
+  UINT8 BusWidth;
+  //
+  // The target clock frequency of the bus in MHz. If user tells driver to 
ignore
+  // it or specifies unsupported frequency driver will choose highest supported
+  // clock frequency for a given mode.
+  //
+  UINT32ClockFreq;
+  //
+  // The target driver strength of the bus. If user tells driver to
+  // ignore it or specifies unsupported driver strength, driver will
+  // default to Type0 for eMMC cards and TypeB for SD cards. Driver strength
+  // setting is only considered if chosen bus timing supports them.
+  //
+  EDKII_SD_MMC_DRIVER_STRENGTH  DriverStrength;
+} EDKII_SD_MMC_OPERATING_PARAMETERS;
+
+typedef enum {
+  SdMmcSdDs,
+  SdMmcSdHs,
   SdMmcUhsSdr12,
   SdMmcUhsSdr25,
   SdMmcUhsSdr50,
-  SdMmcUhsSdr104,
   SdMmcUhsDdr50,
+  SdMmcUhsSdr104,
   SdMmcMmcLegacy,
   SdMmcMmcHsSdr,
   SdMmcMmcHsDdr,
@@ -43,10 +90,10 @@ typedef enum {
   EdkiiSdMmcInitHostPost,
   EdkiiSdMmcUhsSignaling,
   EdkiiSdMmcSwitchClockFreqPost,
+  EdkiiSdMmcGetOperatingParam
 } EDKII_SD_MMC_PHASE_TYPE;
 
 /**
-
   Override function for SDHCI capability bits
 
   @param[in]  ControllerHandle  The EFI_HANDLE of the controller.
@@ -70,7 +117,6 @@ EFI_STATUS
   );
 
 /**
-
   Override function for SDHCI controller operations
 
   @param[in]  ControllerHandle  The EFI_HANDLE of the controller.
-- 
2.14.1.windows.1



Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial 
Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | 
Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i 
moze zawierac informacje poufne. W razie przypadkowego otrzymania tej 
wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; 
jakiekolwiek
przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole 
use of the intended recipient(s). If you are not the intended recipient, please 
contact the sender and delete all copies; any review or distribution by
others is strictly prohibited.


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[edk2-devel] [PATCH v4 2/2] MdeModulePkg/SdMmcHcDxe: Implement revision 3 of SdMmcOverrideProtocol

[Albecki, Mateusz]

From: "Albecki, Mateusz" 

https://bugzilla.tianocore.org/show_bug.cgi?id=1882

Implement support for GetOperatingParamters notify phase
in SdMmcHcDxe driver. GetOperatingParameters notify phase
is signaled before we start card detection and initialization.
Code has been updated for both eMMC and SD card controllers to
take into consideration those new parameters. Initialization process
has been divided into 2 steps. In the first step we bring the link
up to the point where we can get card identification data(Extended
CSD in eMMC case and SWITCH command response in SD card case). This
data is later used along with controller capabilities and operating
parameters passed in GetOperatingParameters phase to choose prefered
bus settings in GetTargetBusSettings function. Those settings are later
on to start bus training to high speeds. If user passes incompatible
setting with selected bus timing driver will assume it's standard behavior
with respect to that setting. For instance if HS400 has been selected as a
target bus timing due to card and controller support bus width setting of
4 and 1 bit won't be respected and 8 bit setting will be choosen instead.

Cc: Hao A Wu 
Signed-off-by: Mateusz Albecki 
---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c| 512 +++--
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c  | 410 ++---
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c |  52 ++-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h |  18 +-
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c   |  34 ++
 MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h   |  19 +
 6 files changed, 814 insertions(+), 231 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c 
b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index deaf4468c9..3f4a8e5413 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -641,13 +641,13 @@ EmmcSwitchBusWidth (
   Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host Controller
   Simplified Spec 3.0 Figure 3-3 for details.
 
-  @param[in] PciIo  A pointer to the EFI_PCI_IO_PROTOCOL instance.
-  @param[in] PassThru   A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL 
instance.
-  @param[in] Slot   The slot number of the SD card to send the command 
to.
-  @param[in] RcaThe relative device address to be assigned.
-  @param[in] HsTiming   The value to be written to HS_TIMING field of 
EXT_CSD register.
-  @param[in] Timing The bus mode timing indicator.
-  @param[in] ClockFreq  The max clock frequency to be set, the unit is MHz.
+  @param[in] PciIo   A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param[in] PassThruA pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL 
instance.
+  @param[in] SlotThe slot number of the SD card to send the 
command to.
+  @param[in] Rca The relative device address to be assigned.
+  @param[in] DriverStrength  Driver strength to set for speed modes that 
support it.
+  @param[in] BusTiming   The bus mode timing indicator.
+  @param[in] ClockFreq   The max clock frequency to be set, the unit is 
MHz.
 
   @retval EFI_SUCCESS   The operation is done correctly.
   @retval OthersThe operation fails.
@@ -659,8 +659,8 @@ EmmcSwitchBusTiming (
   IN EFI_SD_MMC_PASS_THRU_PROTOCOL  *PassThru,
   IN UINT8  Slot,
   IN UINT16 Rca,
-  IN UINT8  HsTiming,
-  IN SD_MMC_BUS_MODETiming,
+  IN EDKII_SD_MMC_DRIVER_STRENGTH   DriverStrength,
+  IN SD_MMC_BUS_MODEBusTiming,
   IN UINT32 ClockFreq
   )
 {
@@ -678,12 +678,29 @@ EmmcSwitchBusTiming (
   //
   Access = 0x03;
   Index  = OFFSET_OF (EMMC_EXT_CSD, HsTiming);
-  Value  = HsTiming;
   CmdSet = 0;
+  switch (BusTiming) {
+case SdMmcMmcHs400:
+  Value = (UINT8)((DriverStrength.Emmc << 4) | 3);
+  break;
+case SdMmcMmcHs200:
+  Value = (UINT8)((DriverStrength.Emmc << 4) | 2);
+  break;
+case SdMmcMmcHsSdr:
+case SdMmcMmcHsDdr:
+  Value = 1;
+  break;
+case SdMmcMmcLegacy:
+  Value = 0;
+  break;
+default:
+  DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d\n)", 
BusTiming));
+  return EFI_INVALID_PARAMETER;
+  }
 
   Status = EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet);
   if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Switch to hstiming %d fails 
with %r\n", HsTiming, Status));
+DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Switch to bus timing %d fails 
with %r\n", BusTiming, Status));
 return Status;
   }
 
@@ -713,7 +730,7 @@ EmmcSwitchBusTiming (
   Private->ControllerHandle,
   Slot,