Re: [edk2-devel] [PATCH edk2-platforms v3 0/3] Platform/QemuSbsa: add GIC ITS
Patch series seems sane to me. Reviewed-by: Graeme Gregory (I seem to be moving further and further from ARM development and even further from SBSA machine development so Ill probably remove myself as a reviewer for this machine) On Wed, Jul 19, 2023 at 02:08:39PM +0200, Marcin Juszkiewicz wrote: > SBSA Reference Platform can have GIC ITS present. And when it has then > we can have complex PCI Express setup (and some other things). > > First patch adds support for GIC ITS. Address is read from TF-A via SMC > call. IORT is generated, MADT has ITS information. Linux boots and sees > GIC ITS as expected. SMMU information is also provided in IORT and used. > > Second patch introduces PcdSmmuBase variable to avoid using magic number > in IORT generation. > > Third patch takes care of system where GIC ITS is not present (like QEMU > 8.0). If GIC ITS address is not set then there is no mention of it in > MADT and there is no IORT, Linux boots. > > Changes since v2: > - no ITS == no IORT > > Changes since v1: > - IORT is generated in C > - no ITS == no ITS node in IORT > - introduced PcdSmmuBase > > Marcin Juszkiewicz (2): > Platform/QemuSbsa: add dynamic PcdSmmuBase > Platform/SbsaQemu: handle systems without GIC ITS > > Shashi Mallela (1): > Platform/SbsaQemu: add GIC ITS support > > Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 4 + > Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 4 + > .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + > .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 2 + > .../SbsaQemuPlatformDxe.inf | 1 + > .../Include/IndustryStandard/SbsaQemuAcpi.h | 11 + > .../Include/IndustryStandard/SbsaQemuSmc.h| 1 + > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 208 +- > .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 10 + > 9 files changed, 241 insertions(+), 1 deletion(-) > > -- > 2.41.0 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107734): https://edk2.groups.io/g/devel/message/107734 Mute This Topic: https://groups.io/mt/100233784/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 1/1] Maintainers: add myself as reviewer for sbsa-ref
On Mon, May 15, 2023 at 04:33:52PM +0200, Marcin Juszkiewicz wrote: > At Linaro I work on sbsa-ref, know direction it goes. > > May not get code details each time. > This is probably a good idea, someone else who is actively using the machine Reviewed-by: Graeme Gregory > Signed-off-by: Marcin Juszkiewicz > --- > Maintainers.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Maintainers.txt b/Maintainers.txt > index 24918d1c6ede..d1d75fe6c940 100644 > --- a/Maintainers.txt > +++ b/Maintainers.txt > @@ -375,6 +375,7 @@ M: Ard Biesheuvel > M: Leif Lindholm > R: Graeme Gregory > R: Radoslaw Biernacki > +R: Marcin Juszkiewicz > > Raspberry Pi platforms and silicon > F: Platform/RaspberryPi/ > -- > 2.40.1 > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104939): https://edk2.groups.io/g/devel/message/104939 Mute This Topic: https://groups.io/mt/98904609/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH edk2-non-osi 1/1] Platform/Qemu/Sbsa: Update TF-A binaries to enable FEAT_FGT
On Mon, May 15, 2023 at 06:23:30PM +0200, Marcin Juszkiewicz via groups.io
wrote:
> Update the TF-A binaries to have FEAT_FGT support.
>
> This support was merged into TF-A:
>
> https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19459
>
> This allows SBSA Reference Platform to boot Linux on "max" cpu.
>
The instructions give a way to do this patch without sending the binary
blob to list.
But this looks like a good idea to me.
Reviewed-by: Graeme Gregory
> Signed-off-by: Marcin Juszkiewicz
> ---
> Platform/Qemu/Sbsa/Readme.md | 31 ++-
> Platform/Qemu/Sbsa/bl1.bin | Bin 19461 -> 19413 bytes
> Platform/Qemu/Sbsa/fip.bin | Bin 58098 -> 58098 bytes
> 3 files changed, 14 insertions(+), 17 deletions(-)
>
> diff --git a/Platform/Qemu/Sbsa/Readme.md b/Platform/Qemu/Sbsa/Readme.md
> index aaf920e12daa..d044297dd693 100644
> --- a/Platform/Qemu/Sbsa/Readme.md
> +++ b/Platform/Qemu/Sbsa/Readme.md
> @@ -4,32 +4,29 @@ Qemu SBSA TF-A binaries
> These binaries have been created from the mainline TF-A
> code checked out at the following commit ID:
>
> -commit 5fdb2e5471c6ae564ea60d986505418134e7516f
> -Merge: e550fa127 ccc61e100
> -Author: Olivier Deprez
> -Date: Tue Mar 21 10:46:41 2023 +0100
> +commit dcf430656ca8ef964fa55ad9eb81cf838c7837f2 (tag: v2.9-rc0)
> +Merge: 3011e1afe b1af2676f
> +Author: Manish Pandey
> +Date: Thu May 11 13:41:35 2023 +0200
>
> -Merge changes I924ea85d,I22e128c4,I7a5cfaac into integration
> +Merge "docs(psci): expound runtime instrumentation docs" into integration
>
> -* changes:
> - feat(mt8195): add support for SMC from OP-TEE
> - feat(mediatek): add SMC handler for EMI MPU
> - feat(mediatek): add SiP service for OP-TEE
>
> This ensures that the following feature for qemu_sbsa platform is
> merged upstream and is included in the build:
>
> -commit 226f4c8e35c4441e80ad523b9105eab4ca630396
> -Author: Chen Baozi
> -Date: Wed Feb 22 06:58:39 2023 +
> +commit c598692d0c6a79dd10c34d5a4a740c90261cfc65
> +Author: Marcin Juszkiewicz
> +Date: Tue Feb 14 09:27:59 2023 +0100
>
> -feat(qemu): add "neoverse-n1" cpu support
> +fix(qemu-sbsa): enable FGT
>
> -Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
> -platform.
> +QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.
>
> -Signed-off-by: Chen Baozi
> -Change-Id: I4620e879c71115451ae91a1643812d89ec7c071f
> +So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max
> setup.
> +
> +Signed-off-by: Marcin Juszkiewicz
> +Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238
>
>
> NOTE: No modifications to the source code have been done.
> diff --git a/Platform/Qemu/Sbsa/bl1.bin b/Platform/Qemu/Sbsa/bl1.bin
> index
> 51b22511db2ea1ef51afe282e43680cc3defbe3e..4a5bd925ae43430e72281001ee5b39f8bc124f3a
> 100755
> GIT binary patch
> delta 2565
> zcmZ`)4^R~66@TCEa@;8(_XjTsvU{M#JN`#5huFvpS~a6-l*=U6I5{xX(wHh}G9u})
> zXfiQloMCx4C5~|lrg7wITkGXAWhO>&+Qy{qG}2sKI(7nRreQix1*CeK^ZIt#V;nkx
> z`SyFi-}}Ayz5TxL?Y;gsi}o-#m^z1hA2~AxnR(GKYWV1s8G z>fU7?B4+@=`&*iC(YUIfa(a0SkqPlL08m{3T`svuZ6sXl5Y$?LKlsRhNrvdV6tET`
> zxSmFrI^kpgKo{F>y~smwly`(4(Pz7-98a(u_Ir%5qK=Rm9P#!`{c#@DOXQEY51qZj
> zYuv?tiI#%fxvJ)yu4nx#3GZ)Qs?OLU_Dey_X%Fe;NV#h0Vf<>YdWP`1M55;g<$R0A
> zG!Gt8fR-@<{KpAr$)Hj^=Q)ZEoa4EpOVyuHgayDc#%G1d<9UkkZHgKMsMIUjoTnbw
> zS8;fpDf;T3LzGF=^pa+bW?gqBPraE)ICZ;AR296+InyTvaOli6QN4o|3+@
> z=d_2W7s|1C`{lDQqKn_n0{A9h!`9#@d>tDKrwandjZ0`Zx!E>++~j1N@oCc$b|^ez
> z;u%|o|4j996REh^{3MHFlevR^j$fKrv-9Y(Y+y*|M6Q!}lyJ*>)VEXKgrr!OuCy
> z;Xqn_9%JAaBxRU~gBJwon*tC*TxwPH`LvC6XRtIqZ{s^A2r4Fdz$GZ#7_c7#h1Ae)
> z0tbHmJtUVp!XWrv4uS);H!h(n>MAzZ2M)_IO-Gl)5Agj9cqRQ+?}uL}ddBGJk}upx
> zo0Yr*5%PhYqH5RRCT&@g{}r}n6gu7`Z-)t58fbZ@$T6Ol!Sfl*vPbEpwKGem9H*2W
> zX$PkyoXmK}bzNWJqJGCl-(dZHsSq67Md$B?m;}mj8a6Kytpe3O2zNhV!~{5H81TfR
> z9c%(;=sApAGt214c4ms~BkaqpXKQgL^F=m*4c4bPe;J0YZFE>AHqpB7L83>yYyoPb
> zQBjT^$DKBxdzryX47|P7b+Pg5ppH>X6wgz?j2CT1YaQ`K!z<9RWO1AQyx|mj$
> z-gB@-WfT=yQy0_mV799HH2r zUe7+pwGMlBf_SZ3I?&3|0y(yjGHX>w@Fho17H6PyS`8*S)@hRmEO^RM@c3UqVc
> zX-|>;6>afh8w_a8bA1<6ZxA;_d9|D~UneTRB0SA!c{II>amNvs67I~Z=U5~hb-v43
> zd$=w8&%E^l-JdajG4-D_#HA?1XK?${zjHU1hgas6vb3+u}dzVf4l32sW@E2l^
> z^(0+9@r{h=PgnC%?K5){N5le47qQ(m`Y}Z+OZoI}qUTdwCH z4!66Gu_64@RVax0d=%62uL+iSR+CX6;pTz^?0R^pz{!LcirK#KwPhvTit{-tGXtH6
> z_8rVsS(;(~*#KFZ1jh(*E`g}XWSES_+eQMZ2L-doa_2mU3Xb&#
Re: [edk2-devel] [PATCH edk2-platforms 0/2] SbsaQemu: make GIC base address Pcds dynamic
On Fri, May 12, 2023 at 06:57:51PM +0100, Leif Lindholm wrote: > Currently, the GIC and redistributors base addresses are defined using > FixedPcds. > > In order to enable the QEMU platform to evolve to provide ITS frames, > as well as newer versions of the GIC, convert these accesses to Dynamic. > > Firtsly, this requires fixing the bug of the addresses being read as 32-bit > Pcds, and then moving the declarations and calls to the dynamic form. > Messed this up first time, so... All patches look good to me. Reviewed-by: Graeme Gregory > Cc: Ard Biesheuvel > Cc: Graeme Gregory > Cc: Radoslaw Biernacki > Cc: Marcin Juszkiewicz > > Leif Lindholm (2): > Silicon/Qemu: use 64-bit Pcds for SbsaQemu GIC addresses > Silicon/Qemu: use dynamic Pcds for SbsaQemu GIC addresses > > Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 12 ++-- > Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 7 --- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 5 +++-- > .../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 2 +- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 2 +- > 5 files changed, 15 insertions(+), 13 deletions(-) > > -- > 2.30.2 > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104938): https://edk2.groups.io/g/devel/message/104938 Mute This Topic: https://groups.io/mt/98854530/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH edk2-platforms 1/1] Maintainers.txt : update email for Graeme Gregory
Signed-off-by: Graeme Gregory --- Maintainers.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Maintainers.txt b/Maintainers.txt index da1c98638ddc..747191366070 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -361,7 +361,7 @@ F: Platform/Qemu/SbsaQemu/ F: Silicon/Qemu/SbsaQemu/ M: Ard Biesheuvel M: Leif Lindholm -R: Graeme Gregory +R: Graeme Gregory R: Radoslaw Biernacki Raspberry Pi platforms and silicon -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#100609): https://edk2.groups.io/g/devel/message/100609 Mute This Topic: https://groups.io/mt/97322275/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH edk2-platforms 2/2] Maintainers.txt: update email address for Graeme Gregory
On Thu, Oct 27, 2022 at 12:05:09PM +0100, Leif Lindholm wrote: > From: Leif Lindholm > > Signed-off-by: Leif Lindholm > Cc: Graeme Gregory > Cc: Graeme Gregory > Cc: Michael D Kinney > Cc: Ard Biesheuvel > --- > Maintainers.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Maintainers.txt b/Maintainers.txt > index 1a5b6828a867..bbf9c00c 100644 > --- a/Maintainers.txt > +++ b/Maintainers.txt > @@ -355,7 +355,7 @@ F: Platform/Qemu/SbsaQemu/ > F: Silicon/Qemu/SbsaQemu/ > M: Ard Biesheuvel > M: Leif Lindholm > -R: Graeme Gregory > +R: Graeme Gregory > R: Radoslaw Biernacki > > Raspberry Pi platforms and silicon Acked-by: Graeme Gregory -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95819): https://edk2.groups.io/g/devel/message/95819 Mute This Topic: https://groups.io/mt/94601215/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2 08/17] Silicon/Qemu: Update ARM_CORE_INFO initializer for MPIDR field change
On Thu, Dec 16, 2021 at 03:07:51PM -0700, Rebecca Cran wrote:
> The ARM_CORE_INFO struct has been updated so the MPIDR is now a single
> field instead of separate cluster/core fields. Update the initializer.
>
> Signed-off-by: Rebecca Cran
Looks sane to me
Reviewed-by: Graeme Gregory
> ---
> Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c
> b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c
> index fa9047020e6c..411f653913bd 100644
> --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c
> +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c
> @@ -15,7 +15,7 @@
> ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
>{
> // Cluster 0, Core 0
> -0x0, 0x0,
> +0x000,
>
> // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> (EFI_PHYSICAL_ADDRESS)0,
> @@ -25,7 +25,7 @@ ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
>},
>{
> // Cluster 0, Core 1
> -0x0, 0x1,
> +0x001,
>
> // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> (EFI_PHYSICAL_ADDRESS)0,
> @@ -35,7 +35,7 @@ ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
>},
>{
> // Cluster 0, Core 2
> -0x0, 0x2,
> +0x002,
>
> // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> (EFI_PHYSICAL_ADDRESS)0,
> @@ -45,7 +45,7 @@ ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
>},
>{
> // Cluster 0, Core 3
> -0x0, 0x3,
> +0x003,
>
> // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> (EFI_PHYSICAL_ADDRESS)0,
> --
> 2.31.1
>
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Re: [edk2-devel] [edk2-platforms PATCH v4 10/12] ARM Silicon and Platforms: add SecureBootVariableLib class resolution
On Wed, Jun 30, 2021 at 02:34:10PM +0200, Grzegorz Bernacki wrote: > The edk2 patch > SecurityPkg: Create library for setting Secure Boot variables. > > removes generic functions from SecureBootConfigDxe and places > them into SecureBootVariableLib. This patch adds SecureBootVariableLib > mapping for each ARM platform which uses SecureBootConfigDxe. > For the SBSA Qemu bit Reviewed-by: Graeme Gregory > Signed-off-by: Grzegorz Bernacki > --- > Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc | 1 + > Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 1 + > Platform/RaspberryPi/RPi3/RPi3.dsc | 1 + > Platform/RaspberryPi/RPi4/RPi4.dsc | 1 + > Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 4 > 5 files changed, 8 insertions(+) > > diff --git a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc > b/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc > index fee7cfcc2d..60fdb244ba 100644 > --- a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc > +++ b/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc > @@ -129,6 +129,7 @@ > !if $(SECURE_BOOT_ENABLE) == TRUE > > TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf >AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf > + > SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf > ># re-use the UserPhysicalPresent() dummy implementation from the ovmf tree >PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf > diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > index 11ce361cdb..b1c4030ec9 100644 > --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > @@ -156,6 +156,7 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE ># > > TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf >AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf > + > SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf > ># re-use the UserPhysicalPresent() dummy implementation from the ovmf tree >PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf > diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc > b/Platform/RaspberryPi/RPi3/RPi3.dsc > index 53825bcf62..73f7f2f8c3 100644 > --- a/Platform/RaspberryPi/RPi3/RPi3.dsc > +++ b/Platform/RaspberryPi/RPi3/RPi3.dsc > @@ -167,6 +167,7 @@ > ># re-use the UserPhysicalPresent() dummy implementation from the ovmf tree >PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf > + > SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf > !else > > TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf > > AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf > diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc > b/Platform/RaspberryPi/RPi4/RPi4.dsc > index fd73c4d14b..d38fee8fb8 100644 > --- a/Platform/RaspberryPi/RPi4/RPi4.dsc > +++ b/Platform/RaspberryPi/RPi4/RPi4.dsc > @@ -164,6 +164,7 @@ > !if $(SECURE_BOOT_ENABLE) == TRUE > > TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf >AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf > + > SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf > ># re-use the UserPhysicalPresent() dummy implementation from the ovmf tree >PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf > diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc > b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc > index 88454c1f90..41b7c3bced 100644 > --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc > +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc > @@ -52,6 +52,10 @@ > > > MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibNull.inf > > +!if $(SECURE_BOOT_ENABLE) == TRUE > + > SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf > +!endif > + > [LibraryClasses.common.SEC] >PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf >BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf > -- > 2.25.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#77369): https://edk2.groups.io/g/devel/message/77369 Mute This Topic: https://groups.io/mt/83891040/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms PATCH 1/1] SbsaQemu: Add OemMiscLib boot information and chassis status functions
On Fri, Apr 16, 2021 at 04:26:49PM -0600, Rebecca Cran wrote:
> Add new SMBIOS Type 32 boot information and Type 3 chassis status
> functions that have been added to OemMiscLib in ArmPkg.
>
> Since this is a virtual platform, return fixed values for the chassis
> statuses.
>
Looks sensible and beleivable to me
Reviewed-by: Graeme Gregory
> Signed-off-by: Rebecca Cran
> ---
> Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 91
> Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 2 +-
> 2 files changed, 92 insertions(+), 1 deletion(-)
>
> diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
> b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
> index eb405b259848..b543045de3b7 100644
> --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
> +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
> @@ -239,3 +239,94 @@ OemUpdateSmbiosInfo (
> HiiSetString (HiiHandle, TokenToUpdate, String, NULL);
>}
> }
> +
> +/** Fetches the Type 32 boot information status.
> +
> + @return Boot status.
> +**/
> +MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
> +EFIAPI
> +OemGetBootStatus (
> + VOID
> + )
> +{
> + return BootInformationStatusNoError;
> +}
> +
> +/** Fetches the chassis status when it was last booted.
> +
> + @return Chassis status.
> +**/
> +MISC_CHASSIS_STATE
> +EFIAPI
> +OemGetChassisBootupState (
> + VOID
> + )
> +{
> + return ChassisStateSafe;
> +}
> +
> +/** Fetches the chassis power supply/supplies status when last booted.
> +
> + @return Chassis power supply/supplies status.
> +**/
> +MISC_CHASSIS_STATE
> +EFIAPI
> +OemGetChassisPowerSupplyState (
> + VOID
> + )
> +{
> + return ChassisStateSafe;
> +}
> +
> +/** Fetches the chassis thermal status when last booted.
> +
> + @return Chassis thermal status.
> +**/
> +MISC_CHASSIS_STATE
> +EFIAPI
> +OemGetChassisThermalState (
> + VOID
> + )
> +{
> + return ChassisStateSafe;
> +}
> +
> +/** Fetches the chassis security status when last booted.
> +
> + @return Chassis security status.
> +**/
> +MISC_CHASSIS_SECURITY_STATE
> +EFIAPI
> +OemGetChassisSecurityStatus (
> + VOID
> + )
> +{
> + return ChassisSecurityStatusNone;
> +}
> +
> +/** Fetches the chassis height in RMUs (Rack Mount Units).
> +
> + @return The height of the chassis.
> +**/
> +UINT8
> +EFIAPI
> +OemGetChassisHeight (
> + VOID
> + )
> +{
> + return 1U;
> +}
> +
> +/** Fetches the number of power cords.
> +
> + @return The number of power cords.
> +**/
> +UINT8
> +EFIAPI
> +OemGetChassisNumPowerCords (
> + VOID
> + )
> +{
> + return 1;
> +}
> \ No newline at end of file
> diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> index 9448852967b6..6051fabd683a 100644
> --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> @@ -66,4 +66,4 @@
>
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisVersion|L""|VOID*|0x011A
>
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisManufacturer|L""|VOID*|0x011B
>
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisAssetTag|L""|VOID*|0x011C
> - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSKU|L""|VOID*|0x011D
> + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSKU|L""|VOID*|0x011D
> \ No newline at end of file
> --
> 2.26.2
>
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Re: [edk2-devel] [PATCH edk2-platforms 1/1] Silicon/Qemu: Move SbsaQemu MPIDR-retrieval function to FdtHelperLib
On 02/03/2021 13:38, Leif Lindholm wrote:
Commit 822634fc1bf1 ("SbsaQemu: Update SbsaQemuAcpiDxe to use FdtHelperLib")
replaced the CountCpusFromFdt() function in SbsaQemuAcpiDxe with a call to
FdtHelperCountCpus() in FdtHelperLib. This ended up leaving static variables
FdtFirstCpuOffset and FdtCpuNodeSize uninitialised, such that the GetMpidr()
function kept returning the value for cpu 0.
Resolve this by moving the GetMpidr() function over to FdtHelperLib, where
it can again share these variables with FdtHelperCountCpus().
Fix up coding style issues as part of copy:
- Add m prefix to module-global variables.
- Add doxygen function comment header.
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Radoslaw Biernacki
Cc: Tanmay Jagdale
Cc: Rebecca Cran
Reported-by: Marcin Juszkiewicz
Signed-off-by: Leif Lindholm
Tested-By: Graeme Gregory
This fixes the issue from inspection of APIC table with acpiview!
---
Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 2 --
Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf | 5 +++
Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h | 12 +++
Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 35
+--
Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c | 36
5 files changed, 54 insertions(+), 36 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index a58ebfaf76d5..c6de685bd2c4 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -35,7 +35,6 @@ [LibraryClasses]
DebugLib
DxeServicesLib
FdtHelperLib
- FdtLib
PcdLib
PrintLib
UefiDriverEntryPoint
@@ -46,7 +45,6 @@ [Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
[Depex]
gEfiAcpiTableProtocolGuid ## CONSUMES
diff --git a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf
b/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf
index d84c16f888d1..9c059f3e5851 100644
--- a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf
+++ b/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf
@@ -24,5 +24,10 @@ [Packages]
MdePkg/MdePkg.dec
Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+[LibraryClasses]
+ DebugLib
+ FdtLib
+ PcdLib
+
[FixedPcd]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h
b/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h
index f9045fd5df45..ea9159857215 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h
@@ -10,6 +10,18 @@
#ifndef FDT_HELPER_LIB_
#define FDT_HELPER_LIB_
+/**
+ Get MPIDR for a given cpu from device tree passed by Qemu.
+
+ @param [in] CpuIdIndex of cpu to retrieve MPIDR value for.
+
+ @retvalMPIDR value of CPU at index
+**/
+UINT64
+FdtHelperGetMpidr (
+ IN UINTN CpuId
+ );
+
/** Walks through the Device Tree created by Qemu and counts the number
of CPUs present in it.
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 84120f1c1b51..b8901030ecd0 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -20,39 +20,6 @@
#include
#include
#include
-#include
-#include
-
-STATIC INT32 FdtFirstCpuOffset;
-STATIC INT32 FdtCpuNodeSize;
-
-/*
- * Get MPIDR from device tree passed by Qemu
- */
-STATIC
-UINT64
-GetMpidr (
- IN UINTN CpuId
- )
-{
- VOID *DeviceTreeBase;
- CONST UINT64 *RegVal;
- INT32 Len;
-
- DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress);
- ASSERT (DeviceTreeBase != NULL);
-
- RegVal = fdt_getprop (DeviceTreeBase,
- FdtFirstCpuOffset + (CpuId * FdtCpuNodeSize),
- "reg",
- );
- if (!RegVal) {
-DEBUG ((DEBUG_ERROR, "Couldn't find reg property for CPU:%d\n", CpuId));
-return 0;
- }
-
- return (fdt64_to_cpu (ReadUnaligned64 (RegVal)));
-}
/*
* A Function to Compute the ACPI Table Checksum
@@ -159,7 +126,7 @@ AddMadtTable (
CopyMem (New, , sizeof (EFI_ACPI_6_0_GIC_STRUCTURE));
GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New;
GiccPtr->AcpiProcessorUid = CoreIndex;
-GiccPtr->MPIDR = GetMpidr (CoreIndex);
+GiccPtr->MPIDR = FdtHelperGetMpidr (CoreIndex);
New += sizeof (EFI_ACPI_6_0_GIC_STRUCTU
Re: [edk2-devel] [PATCH edk2-platforms 2/4] SbsaQemu: add MM based UEFI secure boot support
On 16/02/2021 11:35, Masahisa Kojima wrote: Hi Ard, I am encountering strange behavior when I apply this patch "SbsaQemu: add MM based UEFI secure boot support". When I start linux kernel, booting secondary cores failed. # I don't store any secure boot keys, so UEFI Secure Boot itself is disabled. --- linux kernel log --- [0.124805] Remapping and enabling EFI services. [0.132850] smp: Bringing up secondary CPUs ... [1.294478] CPU1: failed to come online [1.295647] CPU1: failed in unknown state : 0x0 [2.426489] CPU2: failed to come online [2.427112] CPU2: failed in unknown state : 0x0 [3.567428] CPU3: failed to come online [3.567912] CPU3: failed in unknown state : 0x0 [3.569010] smp: Brought up 1 node, 1 CPU [3.569555] SMP: Total of 1 processors activated. [3.570395] CPU features: detected: GIC system register CPU interface [3.571183] CPU features: detected: 32-bit EL0 Support [3.587378] CPU: All CPU(s) started at EL2 --- In my check, arch/arm64/kernel/smp.c::secondary_start_kernel() is never called, so wait_for_completion_timeout() is timed out. https://github.com/torvalds/linux/blob/v5.11/arch/arm64/kernel/smp.c#L138 If I set "SECURE_BOOT_ENABLE=FALSE" in edk2 build(non-secure side) and load the same STANDALONE_MM.fd(Secure Payload) and tf-a binary, secondary cores boot successfully. Major difference between success and failure cases is the existence of UEFI secure variable accesses through Standalone MM framework. If edk2 accesses UEFI secure variable through Standalone MM, secondary cores boot fails. I don't come up with any possible reason. # As a reference, there is no issue on Developerbox. Do you have any idea about this error? I don't suppose that we have managed to have conflicting changes and the memory I used for the expanded PSCI state table for upto 512 cores in arm-tf is also the memory you are using for secure MM? Graeme Thanks, Masahisa On Mon, 21 Dec 2020 at 21:52, Masahisa Kojima wrote: This implements support for UEFI secure boot on SbsaQemu using the standalone MM framework. This moves all of the software handling of the UEFI authenticated variable store into the standalone MM context residing in a secure partition. Secure variable storage is located at 0x0100 in secure NOR Flash. Non-secure shared memory between UEFI and standalone MM is allocated at the top of DRAM. DRAM size of SbsaQemu varies depends on the QEMU parameter, the non-secure shared memory base address is passed from trusted-firmware through the device tree "/reserved-memory" node. Signed-off-by: Masahisa Kojima --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 44 --- Platform/Qemu/SbsaQemu/SbsaQemuStandaloneMm.dsc | 40 ++ Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 82 ++-- Platform/Qemu/SbsaQemu/SbsaQemuStandaloneMm.fdf | 7 +- Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf | 2 + Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c | 37 - 6 files changed, 192 insertions(+), 20 deletions(-) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc index f6af3f9111ee..83e7cd21e0c6 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -27,6 +27,8 @@ [Defines] DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x804F + DEFINE SECURE_BOOT_ENABLE = FALSE + # # Network definition # @@ -148,12 +150,10 @@ [LibraryClasses.common] # Secure Boot dependencies # TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf - AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf - VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf @@ -167,6 +167,7 @@ [LibraryClasses.common] ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + NorFlashPlatformLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf @@ -296,6 +297,8 @@ [PcdsFeatureFlag.common] gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|FALSE + [PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100 gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100 @@ -511,6 +514,10 @@ [PcdsDynamicDefault.common]
Re: [edk2-devel] [edk2-platforms PATCH 1/1] Platform/Qemu/SbsaQemu: Add SMBIOS tables
On 10/02/2021 03:24, Rebecca Cran wrote:
o Add SMBIOS 3.4.0 tables using ArmPkg/Universal/Smbios.
o Bump the PcdSmbiosVersion PCD from 0x300 to 0x304 to indicate support
for SMBIOS 3.4.0, as is required by SBBR.
o Add an implementation of OemMiscLib that provides the system
information. The serial numbers, asset tags etc. are currently all
fixed strings, to allow fwts to pass without errors.
o Add SMBIOS PCDs to identify the platform. The processor serial
number, asset tag and part number are populated because otherwise
fwts reports errors.
Signed-off-by: Rebecca Cran
Lack of "To Be Filled by O.E.M."..
Looks good to me.
Reviewed-by: Graeme Gregory
---
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 278
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 37 +++
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 33 ++-
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 7 +
4 files changed, 354 insertions(+), 1 deletion(-)
diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
new file mode 100644
index ..e736096dc607
--- /dev/null
+++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
@@ -0,0 +1,278 @@
+/** @file
+* OemMiscLib.c
+*
+* Copyright (c) 2021, NUVIA Inc. All rights reserved.
+* Copyright (c) 2020, Linaro Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/** Returns whether the specified processor is present or not.
+
+ @param ProcessIndex The processor index to check.
+
+ @return TRUE if the processor is present, FALSE otherwise.
+**/
+BOOLEAN
+OemIsSocketPresent (
+ UINTN ProcessorIndex
+ )
+{
+ if (ProcessorIndex == 0) {
+return TRUE;
+ }
+
+ return FALSE;
+}
+
+/** Gets the CPU frequency of the specified processor.
+
+ @param ProcessorIndex Index of the processor to get the frequency for.
+
+ @return CPU frequency in Hz
+**/
+UINTN OemGetCpuFreq (
+ UINT8 ProcessorIndex
+ )
+{
+ return 20; // 2 GHz
+}
+
+
+/** Walks through the Device Tree created by Qemu and counts the number
+of CPUs present in it.
+
+Copied from Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+
+@return The number of CPUs present.
+**/
+UINT16
+CountCpusFromFdt (
+ VOID
+)
+{
+ VOID *DeviceTreeBase;
+ INT32 Node;
+ INT32 Prev;
+ INT32 CpuNode;
+ INT32 CpuCount;
+
+ DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress);
+ ASSERT (DeviceTreeBase != NULL);
+
+ // Make sure we have a valid device tree blob
+ ASSERT (fdt_check_header (DeviceTreeBase) == 0);
+
+ CpuNode = fdt_path_offset (DeviceTreeBase, "/cpus");
+ if (CpuNode <= 0) {
+DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n"));
+return 0;
+ }
+
+ CpuCount = 0;
+
+ // Walk through /cpus node and count the number of subnodes.
+ // The count of these subnodes corresponds to the number of
+ // CPUs created by Qemu.
+ Prev = fdt_first_subnode (DeviceTreeBase, CpuNode);
+ while (1) {
+CpuCount++;
+Node = fdt_next_subnode (DeviceTreeBase, Prev);
+if (Node < 0) {
+ break;
+}
+Prev = Node;
+ }
+
+ return CpuCount;
+}
+
+/** Gets information about the specified processor and stores it in
+the structures provided.
+
+ @param ProcessorIndex Index of the processor to get the information for.
+ @param ProcessorStatus Processor status.
+ @param ProcessorCharacteristics Processor characteritics.
+ @param MiscProcessorDataMiscellaneous processor information.
+
+ @return TRUE on success, FALSE on failure.
+**/
+BOOLEAN
+OemGetProcessorInformation (
+ IN UINTN ProcessorIndex,
+ IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
+ IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
+ IN OUT OEM_MISC_PROCESSOR_DATA*MiscProcessorData
+ )
+{
+ UINT16 CoreCount = CountCpusFromFdt ();
+
+ if (ProcessorIndex == 0) {
+ProcessorStatus->Bits.CpuStatus = 1; // CPU enabled
+ProcessorStatus->Bits.Reserved1 = 0;
+ProcessorStatus->Bits.SocketPopulated = 1;
+ProcessorStatus->Bits.Reserved2 = 0;
+ } else {
+ProcessorStatus->Bits.CpuStatus = 0; // CPU disabled
+ProcessorStatus->Bits.Reserved1 = 0;
+ProcessorStatus->Bits.SocketPopulated = 0;
+ProcessorStatus->Bits.Reserved2 = 0;
+ }
+
+ ProcessorCharacteristics->ProcessorReserved1 = 0;
+ ProcessorCharacteristics->ProcessorUnknown= 0;
+ ProcessorCharacteristics->Processor64BitCapable = 1;
+ ProcessorCharacteristics->ProcessorMultiCore = 1;
+ ProcessorCharacteristics->ProcessorHardwareThread = 0;
+ ProcessorCharacteristics->ProcessorExecuteProtection = 1;
+ ProcessorCha
[edk2-devel] [PATCH edk2-non-osi 1/1] Platform/Qemu/Sbsa: Update ARM-TF binaries with EC and topology
Based on arm-tf commit 1aabb74fae0e30901884b6cb230d7ea730a74344 With https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5478 applied to support CPU topology used by sbsa-ref machine. With https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5479 applied to support the EC device in sbsa-ref machine so reboot/shutdown function as expected. Signed-off-by: Graeme Gregory --- Patch available for cherrypick https://github.com/xXorAa/edk2-non-osi/tree/qemu-sbsa-update-ec-topology-v1 Platform/Qemu/Sbsa/bl1.bin | Bin 19301 -> 19301 bytes Platform/Qemu/Sbsa/fip.bin | Bin 53973 -> 54002 bytes 2 files changed, 0 insertions(+), 0 deletions(-) diff --git a/Platform/Qemu/Sbsa/bl1.bin b/Platform/Qemu/Sbsa/bl1.bin index bd0b2de1dfcb..794f5b68bd13 100755 Binary files a/Platform/Qemu/Sbsa/bl1.bin and b/Platform/Qemu/Sbsa/bl1.bin differ diff --git a/Platform/Qemu/Sbsa/fip.bin b/Platform/Qemu/Sbsa/fip.bin index 03b327bcd022..a12cfa5ba2c9 100644 Binary files a/Platform/Qemu/Sbsa/fip.bin and b/Platform/Qemu/Sbsa/fip.bin differ -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#65277): https://edk2.groups.io/g/devel/message/65277 Mute This Topic: https://groups.io/mt/76865698/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH edk2-non-osi 1/1] Platform/Qemu/Sbssa: Update ARM-TF binaries with EC and topology
Based on arm-tf commit 1aabb74fae0e30901884b6cb230d7ea730a74344
With https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5478
applied to support CPU topology used by sbsa-ref machine.
With https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5479
applied to support the EC device in sbsa-ref machine so reboot/shutdown
function as expected.
Signed-off-by: Graeme Gregory
---
Platform/Qemu/Sbsa/bl1.bin | Bin 19301 -> 19301 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 53973 -> 54002 bytes
2 files changed, 0 insertions(+), 0 deletions(-)
diff --git a/Platform/Qemu/Sbsa/bl1.bin b/Platform/Qemu/Sbsa/bl1.bin
index
bd0b2de1dfcb23eb3901f3001ab01edd9f15cb52..794f5b68bd13f1383c194b24f18644db9f327b1b
100755
GIT binary patch
delta 3957
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zmFP*|BvTcl)%dQW#9umY7IvoX7}*g%FPcy1_;ZcNW)kx
[edk2-devel] [PATCH edk2-platforms 1/1] Maintainers : Update Graeme Gregory email address
I have moved from Linaro to Nuvia so update my email address as the old one is no longer valid. Signed-off-by: Graeme Gregory --- Maintainers.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Maintainers.txt b/Maintainers.txt index 201192cca247..26b9959bc879 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -271,7 +271,7 @@ F: Platform/Qemu/SbsaQemu/ F: Silicon/Qemu/SbsaQemu/ M: Ard Biesheuvel M: Leif Lindholm -R: Graeme Gregory +R: Graeme Gregory R: Radoslaw Biernacki R: Tanmay Jagdale -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#65159): https://edk2.groups.io/g/devel/message/65159 Mute This Topic: https://groups.io/mt/76729657/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH edk2-platforms 1/1] SbsaQemu: AcpiDxe: Read MPIDR from device tree
On Tue, Sep 01, 2020 at 11:59:38PM +0530, Tanmay Jagdale wrote:
> The Qemu device tree for Sbsa platform now contains MPIDR value
> for every CPU in the form of "reg" property under every CPU's
> node. Hence, add a function that provides support to read this
> value from the device tree.
>
> Signed-off-by: Tanmay Jagdale
This generates the correct APIC table in my testing
Tested-by: Graeme Gregory
> ---
> .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 35 ++-
> 1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index 47a9bd1d423a..fb7c1835c3d7 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -22,6 +22,9 @@
> #include
> #include
>
> +STATIC INT32 FdtFirstCpuOffset;
> +STATIC INT32 FdtCpuNodeSize;
> +
> /*
> * A function that walks through the Device Tree created
> * by Qemu and counts the number of CPUs present in it.
> @@ -56,12 +59,14 @@ CountCpusFromFdt (
>// The count of these subnodes corresponds to the number of
>// CPUs created by Qemu.
>Prev = fdt_first_subnode (DeviceTreeBase, CpuNode);
> + FdtFirstCpuOffset = Prev;
>while (1) {
> CpuCount++;
> Node = fdt_next_subnode (DeviceTreeBase, Prev);
> if (Node < 0) {
>break;
> }
> +FdtCpuNodeSize = Node - Prev;
> Prev = Node;
>}
>
> @@ -69,6 +74,34 @@ CountCpusFromFdt (
>ASSERT_RETURN_ERROR (PcdStatus);
> }
>
> +/*
> + * Get MPIDR from device tree passed by Qemu
> + */
> +STATIC
> +UINT64
> +GetMpidr (
> + IN UINTN CpuId
> + )
> +{
> + VOID *DeviceTreeBase;
> + CONST UINT64 *RegVal;
> + INT32 Len;
> +
> + DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress);
> + ASSERT (DeviceTreeBase != NULL);
> +
> + RegVal = fdt_getprop (DeviceTreeBase,
> + FdtFirstCpuOffset + (CpuId * FdtCpuNodeSize),
> + "reg",
> + );
> + if (!RegVal) {
> +DEBUG ((DEBUG_ERROR, "Couldn't find reg property for CPU:%d\n", CpuId));
> +return 0;
> + }
> +
> + return (fdt64_to_cpu (ReadUnaligned64 (RegVal)));
> +}
> +
> /*
> * A Function to Compute the ACPI Table Checksum
> */
> @@ -173,7 +206,7 @@ AddMadtTable (
> CopyMem (New, , sizeof (EFI_ACPI_6_0_GIC_STRUCTURE));
> GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New;
> GiccPtr->AcpiProcessorUid = NumCores;
> -GiccPtr->MPIDR = NumCores;
> +GiccPtr->MPIDR = GetMpidr (NumCores);
> New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE);
>}
>
> --
> 2.28.0
>
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[edk2-devel] [edk2-plaforms PATCH 1/1] SbsaQemu: Fix numerous SSDT generation problems
1 - The SBSAQEMU_ACPI_ITOA contained a typo that put bogus characters
in the name if number of CPUs was greater than 10. It is safter to use
the AsciiSPrint function from PrintLib.
2 - The _UID fields were bogus, and indicated as bytes in AML instead of
a word. This caused extra Zero's to appear in disassembly. Fixed by
making them AML_WORD_PREFIX and putting CpuId in little endian.
3 - The table was a number of bytes too long causes bogus Zero in
dissassembly at end of table. Re-adjust code slightly to reduce table
size once we know the size of the length field.
Signed-off-by: Graeme Gregory
---
This patch supercedes "SbsaQemu: Fix CPUID generation in SSDT"
as while fixing review comments on that I found the other issues.
.../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 1 +
.../Include/IndustryStandard/SbsaQemuAcpi.h | 5 +---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 25 +++
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index cde9d02f7f90..127eef029f3c 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -36,6 +36,7 @@ [LibraryClasses]
DxeServicesLib
FdtLib
PcdLib
+ PrintLib
UefiDriverEntryPoint
UefiLib
UefiRuntimeServicesTableLib
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 1a7d9dda2b99..f085765d2677 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -50,9 +50,6 @@
#define SBSAQEMU_ACPI_CPU_DEV_LEN0x1C
#define SBSAQEMU_ACPI_CPU_DEV_NAME { 'C', '0', '0', '0' }
-// Macro to convert Integer to Character
-#define SBSAQEMU_ACPI_ITOA(Byte) (0x30 + (Byte > 9 ? (Byte + 1) :
Byte))
-
#define SBSAQEMU_ACPI_CPU_HID {
\
AML_NAME_OP, AML_NAME_CHAR__, 'H', 'I', 'D',
\
AML_STRING_PREFIX, 'A', 'C', 'P', 'I', '0', '0', '0', '7',
\
@@ -60,7 +57,7 @@
}
#define SBSAQEMU_ACPI_CPU_UID{
\
- AML_NAME_OP, AML_NAME_CHAR__, 'U', 'I', 'D', AML_BYTE_PREFIX,
\
+ AML_NAME_OP, AML_NAME_CHAR__, 'U', 'I', 'D', AML_WORD_PREFIX,
\
AML_ZERO_OP, AML_ZERO_OP
\
}
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 06552f4b22f3..47a9bd1d423a 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -248,6 +249,7 @@ AddSsdtTable (
UINT32TableSize;
EFI_PHYSICAL_ADDRESS PageAddress;
UINT8 *New;
+ UINT8 *HeaderAddr;
UINT32CpuId;
UINT32Offset;
UINT8 ScopeOpName[] = SBSAQEMU_ACPI_SCOPE_NAME;
@@ -283,12 +285,12 @@ AddSsdtTable (
return EFI_OUT_OF_RESOURCES;
}
- New = (UINT8 *)(UINTN) PageAddress;
+ HeaderAddr = New = (UINT8 *)(UINTN) PageAddress;
ZeroMem (New, TableSize);
// Add the ACPI Description table header
CopyMem (New, , sizeof (EFI_ACPI_DESCRIPTION_HEADER));
- ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize;
+
New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
// Insert the top level ScopeOp
@@ -296,6 +298,11 @@ AddSsdtTable (
New++;
Offset = SetPkgLength (New,
(TableSize - sizeof (EFI_ACPI_DESCRIPTION_HEADER) - 1));
+
+ // Adjust TableSize now we know header length of _SB
+ TableSize -= (SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH - Offset);
+ ((EFI_ACPI_DESCRIPTION_HEADER*) HeaderAddr)->Length = TableSize;
+
New += Offset;
CopyMem (New, , sizeof (ScopeOpName));
New += sizeof (ScopeOpName);
@@ -303,21 +310,17 @@ AddSsdtTable (
// Add new Device structures for the Cores
for (CpuId = 0; CpuId < NumCores; CpuId++) {
SBSAQEMU_ACPI_CPU_DEVICE *CpuDevicePtr;
-UINT8 CpuIdByte1, CpuIdByte2, CpuIdByte3;
CopyMem (New, , sizeof (SBSAQEMU_ACPI_CPU_DEVICE));
CpuDevicePtr = (SBSAQEMU_ACPI_CPU_DEVICE *) New;
-CpuIdByte1 = CpuId & 0xF;
-CpuIdByte2 = (CpuId >> 4) & 0xF;
-CpuIdByte3 = (CpuId >> 8) & 0xF;
+AsciiSPrint((CHAR8 *)>dev_name[1], 4, "%03X", CpuId);
-CpuDevicePtr->dev_name[1] = SBSAQEMU_ACPI_ITOA(CpuIdByte3);
-CpuDevicePtr->dev_name[2] = SBSAQEMU_ACPI_ITOA(CpuIdByte2);
-CpuDevicePtr->dev_name[3] = SBS
[edk2-devel] [edk2-plaforms PATCH 1/1] SbsaQemu: Fix CPUID generation in SSDT
The SBSAQEMU_ACPI_ITOA contains a typo that puts invalid characters in
the ASL for any number of CPUs > 10.
Signed-off-by: Graeme Gregory
---
Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 1a7d9dda2b99..0f79d8a9c3c8 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -51,7 +51,7 @@
#define SBSAQEMU_ACPI_CPU_DEV_NAME { 'C', '0', '0', '0' }
// Macro to convert Integer to Character
-#define SBSAQEMU_ACPI_ITOA(Byte) (0x30 + (Byte > 9 ? (Byte + 1) :
Byte))
+#define SBSAQEMU_ACPI_ITOA(Byte) (0x30 + (Byte > 9 ? (Byte + 7) :
Byte))
#define SBSAQEMU_ACPI_CPU_HID {
\
AML_NAME_OP, AML_NAME_CHAR__, 'H', 'I', 'D',
\
--
2.25.1
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Re: [edk2-devel] [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime
On Thu, Aug 27, 2020 at 08:26:21AM +0530, Tanmay Jagdale wrote:
> Hi Graeme,
>
>
> On Thu, 27 Aug 2020 at 04:18, Graeme Gregory <[1]gra...@nuviainc.com> wrote:
>
> On Wed, Aug 26, 2020 at 04:35:22PM +0100, Graeme Gregory wrote:
> > On Tue, Aug 25, 2020 at 07:09:55PM +0530, Tanmay Jagdale wrote:
> > > - Add support to create MADT table at runtime.
> > > - Included a macro for GIC Redistributor structure initialisation.
> > >
> > > Signed-off-by: Tanmay Jagdale <[2]tanmay.jagd...@linaro.org>
> > > ---
> > > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf |
> 20 ++-
> > > Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h |
> 15 ++
> > > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c |
> 156
> > > 3 files changed, 190 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/
> SbsaQemuAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/
> SbsaQemuAcpiDxe.inf
> > > index 3795a7e11639..8125e8ba7553 100644
> > > ---
> a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > > +++
> b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > > @@ -41,9 +41,27 @@ [LibraryClasses]
> > > UefiRuntimeServicesTableLib
> > >
> > > [Pcd]
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
> > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
> > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
> > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
> > >
> > > [Depex]
> > > - TRUE
> > > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > > +
> > > +[Guids]
> > > + gEdkiiPlatformHasAcpiGuid
> > > +
> > > +[Protocols]
> > > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > > +
> > > +[FixedPcd]
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > > + gArmTokenSpaceGuid.PcdGicDistributorBase
> > > + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> > > +
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/
> SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/
> SbsaQemuAcpi.h
> > > index eac195b0585c..7a9a0061675f 100644
> > > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > > @@ -22,6 +22,21 @@
> > > FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32
> CreatorRevision */ \
> > > }
> > >
> > > +// Defines for MADT
> > > +#define SBSAQEMU_MADT_GIC_VBASE 0x2c02
> > > +#define SBSAQEMU_MADT_GIC_HBASE 0x2c01
> > > +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23
> > > +#define SBSAQEMU_MADT_GICR_SIZE 0x400
> > > +
> > > +// Macro for MADT GIC Redistributor Structure
> > > +#define SBSAQEMU_MADT_GICR_INIT() {
>
> \
> > > + EFI_ACPI_6_0_GICR, /* Type */
>
> \
> > > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */
>
> \
> > > + EFI_ACPI_RESERVED_WORD, /* Reserved */
>
> \
> > > + FixedPcdGet32 (PcdGicRedistributorsBase), /*
> DiscoveryRangeBaseAddress */ \
> > > + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength
> *
> / \
> > > + }
> > > +
> > > #define SBSAQEMU_UART0_BASE 0x6000
> > >
> > > #define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf000
> > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/
>
Re: [edk2-devel] [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime
On Wed, Aug 26, 2020 at 04:35:22PM +0100, Graeme Gregory wrote:
> On Tue, Aug 25, 2020 at 07:09:55PM +0530, Tanmay Jagdale wrote:
> > - Add support to create MADT table at runtime.
> > - Included a macro for GIC Redistributor structure initialisation.
> >
> > Signed-off-by: Tanmay Jagdale
> > ---
> > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 20 ++-
> > Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 15 ++
> > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 156
> >
> > 3 files changed, 190 insertions(+), 1 deletion(-)
> >
> > diff --git
> > a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > index 3795a7e11639..8125e8ba7553 100644
> > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> > @@ -41,9 +41,27 @@ [LibraryClasses]
> >UefiRuntimeServicesTableLib
> >
> > [Pcd]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
> >gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
> >gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
> >gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
> >
> > [Depex]
> > - TRUE
> > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > +
> > +[Guids]
> > + gEdkiiPlatformHasAcpiGuid
> > +
> > +[Protocols]
> > + gEfiAcpiTableProtocolGuid ## CONSUMES
> > +
> > +[FixedPcd]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > + gArmTokenSpaceGuid.PcdGicDistributorBase
> > + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> > +
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > index eac195b0585c..7a9a0061675f 100644
> > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> > @@ -22,6 +22,21 @@
> > FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32
> > CreatorRevision */ \
> >}
> >
> > +// Defines for MADT
> > +#define SBSAQEMU_MADT_GIC_VBASE 0x2c02
> > +#define SBSAQEMU_MADT_GIC_HBASE 0x2c01
> > +#define SBSAQEMU_MADT_GIC_PMU_IRQ23
> > +#define SBSAQEMU_MADT_GICR_SIZE 0x400
> > +
> > +// Macro for MADT GIC Redistributor Structure
> > +#define SBSAQEMU_MADT_GICR_INIT() {
> > \
> > + EFI_ACPI_6_0_GICR,/* Type */
> > \
> > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */
> > \
> > + EFI_ACPI_RESERVED_WORD, /* Reserved */
> > \
> > + FixedPcdGet32 (PcdGicRedistributorsBase), /* DiscoveryRangeBaseAddress
> > */ \
> > + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */
> > \
> > + }
> > +
> > #define SBSAQEMU_UART0_BASE 0x6000
> >
> > #define SBSAQEMU_PCI_SEG0_CONFIG_BASE0xf000
> > diff --git
> > a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > index 75abdae3b8ce..16cb4e904e6f 100644
> > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > @@ -6,11 +6,17 @@
> > * SPDX-License-Identifier: BSD-2-Clause-Patent
> > *
> > **/
> > +#include
> > +#include
> > +#include
> > +#include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > @@ -61,6 +67,137 @@ CountCpusFromFdt (
> >ASSERT_RETURN_ERROR (PcdStatus);
> > }
> >
> > +/*
> > + * A Function to Compute the ACPI Table Checksum
&g
Re: [edk2-devel] [PATCH v3 edk2-platforms 5/8] SbsaQemu: AcpiDxe: Create MADT table at runtime
On Tue, Aug 25, 2020 at 07:09:55PM +0530, Tanmay Jagdale wrote:
> - Add support to create MADT table at runtime.
> - Included a macro for GIC Redistributor structure initialisation.
>
> Signed-off-by: Tanmay Jagdale
> ---
> Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 20 ++-
> Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 15 ++
> Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 156
>
> 3 files changed, 190 insertions(+), 1 deletion(-)
>
> diff --git
> a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> index 3795a7e11639..8125e8ba7553 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
> @@ -41,9 +41,27 @@ [LibraryClasses]
>UefiRuntimeServicesTableLib
>
> [Pcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
>gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount
>gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
>gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress
>
> [Depex]
> - TRUE
> + gEfiAcpiTableProtocolGuid ## CONSUMES
> +
> +[Guids]
> + gEdkiiPlatformHasAcpiGuid
> +
> +[Protocols]
> + gEfiAcpiTableProtocolGuid ## CONSUMES
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
> diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> index eac195b0585c..7a9a0061675f 100644
> --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
> @@ -22,6 +22,21 @@
> FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision
> */ \
>}
>
> +// Defines for MADT
> +#define SBSAQEMU_MADT_GIC_VBASE 0x2c02
> +#define SBSAQEMU_MADT_GIC_HBASE 0x2c01
> +#define SBSAQEMU_MADT_GIC_PMU_IRQ23
> +#define SBSAQEMU_MADT_GICR_SIZE 0x400
> +
> +// Macro for MADT GIC Redistributor Structure
> +#define SBSAQEMU_MADT_GICR_INIT() {
> \
> + EFI_ACPI_6_0_GICR,/* Type */
> \
> + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */
> \
> + EFI_ACPI_RESERVED_WORD, /* Reserved */
> \
> + FixedPcdGet32 (PcdGicRedistributorsBase), /* DiscoveryRangeBaseAddress */
> \
> + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */
> \
> + }
> +
> #define SBSAQEMU_UART0_BASE 0x6000
>
> #define SBSAQEMU_PCI_SEG0_CONFIG_BASE0xf000
> diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> index 75abdae3b8ce..16cb4e904e6f 100644
> --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> @@ -6,11 +6,17 @@
> * SPDX-License-Identifier: BSD-2-Clause-Patent
> *
> **/
> +#include
> +#include
> +#include
> +#include
> #include
> +#include
> #include
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -61,6 +67,137 @@ CountCpusFromFdt (
>ASSERT_RETURN_ERROR (PcdStatus);
> }
>
> +/*
> + * A Function to Compute the ACPI Table Checksum
> + */
> +VOID
> +AcpiPlatformChecksum (
> + IN UINT8 *Buffer,
> + IN UINTN Size
> + )
> +{
> + UINTN ChecksumOffset;
> +
> + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
> +
> + // Set checksum field to 0 since it is used as part of the calculation
> + Buffer[ChecksumOffset] = 0;
> +
> + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
> +}
> +
> +/*
> + * A function that add the MADT ACPI table.
> + IN EFI_ACPI_COMMON_HEADER*CurrentTable
> + */
> +EFI_STATUS
> +AddMadtTable (
> + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable
> + )
> +{
> + EFI_STATUSStatus;
> + UINTN TableHandle;
> + UINT32TableSize;
> + EFI_PHYSICAL_ADDRESS PageAddress;
> + UINT8 *New;
> + UINT32NumCores;
> +
> + // Initialize MADT ACPI Header
> + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = {
> + SBSAQEMU_ACPI_HEADER
>
Re: [edk2-devel] Silicon/SbsaQemu: Fix NOR flash RegionBaseAddress
On Wed, Jun 17, 2020 at 12:59:13AM +0530, Tanmay Jagdale wrote:
> The EFI_FIMRWARE_VOLUME_HEADER is present at an offset in the
> NOR flash of Sbsa QEMU model. Use the right RegionBaseAddress
> so that the EFI firmware volume header can be found correctly.
>
> Signed-off-by: Tanmay Jagdale
This fixes the problem for me, I have tested setting variables from
efi shell and from debian guest OS and they persist correctly now.
Tested-by: Graeme Gregory
> ---
> .../SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c | 2 +-
> .../Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git
> a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c
> b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c
> index e7bb626596..0946327cb5 100644
> --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c
> +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c
> @@ -23,7 +23,7 @@ NorFlashPlatformInitialization (
> NOR_FLASH_DESCRIPTION mNorFlashDevice =
> {
> FixedPcdGet64(PcdFdBaseAddress),
> - FixedPcdGet64(PcdFdBaseAddress),
> + FixedPcdGet64(PcdFlashNvStorageVariableBase),
> FixedPcdGet32(PcdFdSize),
> QEMU_NOR_BLOCK_SIZE
> };
> diff --git
> a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf
> b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf
> index 82712c8901..f2ba41e1df 100644
> ---
> a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf
> +++
> b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf
> @@ -23,7 +23,9 @@
>ArmPlatformPkg/ArmPlatformPkg.dec
>ArmPkg/ArmPkg.dec
>MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
>
> [FixedPcd]
>gArmTokenSpaceGuid.PcdFdBaseAddress
>gArmTokenSpaceGuid.PcdFdSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
> --
> 2.27.0
>
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Re: [edk2-devel] SbsaQemu: Initial support for static ACPI tables
On Mon, May 25, 2020 at 03:44:24AM +0530, Tanmay Jagdale wrote:
> Add the following static ACPI tables for the SBSA Qemu platform
> - DSDT
> - FADT
> - GTDT
> - MADT
Comment below on MADT
> - MCFG
> - SPCR
>
> Currently we support 4 CPUs.
>
> Co-authored-by: Graeme Gregory
> Co-authored-by: Jonathan Cameron
> Co-authored-by: Tanmay Jagdale
> Signed-off-by: Tanmay Jagdale
> ---
> Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 11 +-
> Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 14 +
> Silicon/Qemu/SbsaQemu/Acpi.dsc.inc| 42 +
> Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h | 61 +
> .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 47 +
> Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 1400 +
> Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc| 85 +
> Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc| 71 +
> Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc| 85 +
> Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc| 50 +
> Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc| 122 ++
> .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c |6 +
> .../SbsaQemuPlatformDxe.inf | 10 +
> 13 files changed, 2003 insertions(+), 1 deletion(-)
> create mode 100644 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.h
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Fadt.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Madt.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
> create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
>
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> index 4db3ab4651..ac1398af8f 100644
> --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
> @@ -300,6 +300,10 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
>gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
>gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
>
> + # Core and Cluster Count
> + gArmPlatformTokenSpaceGuid.PcdCoreCount|4
> + gArmPlatformTokenSpaceGuid.PcdClusterCount|1
> +
># DEBUG_ASSERT_ENABLED 0x01
># DEBUG_PRINT_ENABLED0x02
># DEBUG_CODE_ENABLED 0x04
> @@ -376,7 +380,6 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
>#
>gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE
>
> - gArmPlatformTokenSpaceGuid.PcdCoreCount|1
>gArmTokenSpaceGuid.PcdVFPEnabled|1
>
># System Memory Base -- fixed
> @@ -516,6 +519,7 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
>ShellPkg/Application/Shell/Shell.inf {
>
>
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> +
> NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
>
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
>
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
>
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> @@ -675,3 +679,8 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
>MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
>MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
>MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> + #
> + # ACPI Support
> +!include Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
> +
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
> diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> index be7c78aceb..7f1a60e3ee 100644
> --- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
> @@ -227,6 +227,14 @@ READ_LOCK_STATUS = TRUE
>INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
>INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
>
> + #
> + # ACPI support
> + #
> + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> + INF RuleOverride = ACPITABLE
> Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
> + INF
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
> +
>#
># PCI support
>#
> @@ -301,3 +309,9 @@ READ_LOCK_STATUS = TRUE
>}
>
> !include ArmVirtPkg/ArmVirtRules.fdf.inc
> +
> +[Rule.Common.USER_DEFINED.ACPI
Re: [edk2-devel] [FIXUPS edk2-platforms 0/3] SbsaQemu layout changes and minor cleanup
On Sat, May 23, 2020 at 12:39:41AM +0100, Leif Lindholm wrote:
> The SbsaQemu platform port has been in flight for a long time now,
> so to facilitate getting it merged, here is a set of proposed layout
> changes and minor tweaks that I would prefer to have included.
>
> I also propose changing the commit message as follows:
> ---
> SbsaQemu: add port for SbsaQemu platform
>
> From: Radoslaw Biernacki
>
> The QEMU sbsa-ref platform provides an SBSA-compliant platform,
> providing EL3/EL2 support, non-virtio inerfaces, etc. This patch adds
> initial support for this platform.
>
> We are using FDF to compose EFI flash images with TF-A images.
> Flash0 (secure) is used by BL1 and FIP (BL2 + BL31).
> Flash1 contains EFI code and EFI variables.
>
> Signed-off-by: Tanmay Jagdale
> ---
>
> If Graeme, Radek, or Tanmay acks this set, I will squash this into the
> v4 SbsaQemu patch and push it.
>
Looks all good to me.
Acked-by: Graeme Gregory
> Leif Lindholm (3):
> Silicon/Qemu: mirror Platform layout
> Silicon/Qemu: clean up SbsaQemu.dec
> Maintainers.txt: update format
>
> Maintainers.txt | 23 ---
> Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 8 +++
> Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 2 +-
> .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 0
> .../SbsaQemuPlatformDxe.inf | 2 +-
> .../Library/SbsaQemuLib/SbsaQemuHelper.S | 0
> .../Library/SbsaQemuLib/SbsaQemuLib.c | 0
> .../Library/SbsaQemuLib/SbsaQemuLib.inf | 2 +-
> .../Library/SbsaQemuLib/SbsaQemuMem.c | 0
> .../SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c | 0
> .../SbsaQemuNorFlashLib.inf | 0
> .../SbsaQemuPciHostBridgeLib.c| 0
> .../SbsaQemuPciHostBridgeLib.inf | 0
> .../SbsaQemu.dec} | 3 ---
> 14 files changed, 16 insertions(+), 24 deletions(-)
> rename Silicon/Qemu/{ =>
> SbsaQemu}/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c (100%)
> rename Silicon/Qemu/{ =>
> SbsaQemu}/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf (92%)
> rename Silicon/Qemu/{ => SbsaQemu}/Library/SbsaQemuLib/SbsaQemuHelper.S
> (100%)
> rename Silicon/Qemu/{ => SbsaQemu}/Library/SbsaQemuLib/SbsaQemuLib.c (100%)
> rename Silicon/Qemu/{ => SbsaQemu}/Library/SbsaQemuLib/SbsaQemuLib.inf (92%)
> rename Silicon/Qemu/{ => SbsaQemu}/Library/SbsaQemuLib/SbsaQemuMem.c (100%)
> rename Silicon/Qemu/{ =>
> SbsaQemu}/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c (100%)
> rename Silicon/Qemu/{ =>
> SbsaQemu}/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.inf (100%)
> rename Silicon/Qemu/{ =>
> SbsaQemu}/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c (100%)
> rename Silicon/Qemu/{ =>
> SbsaQemu}/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.inf (100%)
> rename Silicon/Qemu/{SbsaQemuPkg.dec => SbsaQemu/SbsaQemu.dec} (93%)
>
> --
> 2.20.1
>
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