[edk2-devel] [PATCH] UefiCpuPkg: Bug fix in 5LPage handling

[Guenzel, Robert]

When build in DEBUG, the code asserts that 5LPage support is there
when the physical address width is larger than 48.
In a RELEASE build it will just force LA57 to 1 in CR4
even if CPUID(7).ECX[16] says it is not supported.

The hang (in the ASSERT) in DEBUG is not warranted as there are
legal configurations with CPUID(7).ECX[16](==LA57)=0
and with a physical address width of larger than 48 (like 52).

This is also supported by this code:
https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c#L221
There (as long as physical address width is smaller or equal to 52)
any address width above 48 will be reduced to 48 and the
system can and will work without 5LPaging.

The forced setting of LA57 in CR4 (in the absence of LA57 in CPUID(7).ECX)
is a spec violation and should not happen.

Hence the proposed fix
a) removes the assert.
b) only returns TRUE from Is5LevelPagingNeeded if 5LPaging is actually
   supported by HW.

Signed-off-by: Robert Guenzel mailto:robert.guen...@intel.com
---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c 
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index 6587212f4e..f8b1ac31f1 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -104,8 +104,8 @@ Is5LevelPagingNeeded (
 ExtFeatureEcx.Bits.FiveLevelPage
 ));

-  if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) {
-ASSERT (ExtFeatureEcx.Bits.FiveLevelPage == 1);
+  if ((VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) &&
+  (ExtFeatureEcx.Bits.FiveLevelPage == 1)) {
 return TRUE;
   } else {
 return FALSE;
-- 
2.34.1
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de 
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva  
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928



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[edk2-devel] [PATCH 1/2] SimicsOpenBoardPkg: Fix bug in DSDT

[Guenzel, Robert]

The DSDT had a syntax error that was not detected by older iasl versions.
This commit fixes the Syntax error.

Signed-off-by: Robert Guenzel 
---
 Platform/Intel/SimicsOpenBoardPkg/AcpiTables/Dsdt.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/Intel/SimicsOpenBoardPkg/AcpiTables/Dsdt.asl 
b/Platform/Intel/SimicsOpenBoardPkg/AcpiTables/Dsdt.asl
index 8a6c3792..3421c9e8 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/AcpiTables/Dsdt.asl
+++ b/Platform/Intel/SimicsOpenBoardPkg/AcpiTables/Dsdt.asl
@@ -372,7 +372,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "SIMICS  
", 4) {
 
 Package () {0x000E, 0x00, 0, 16},
 Package () {0x000E, 0x01, 0, 17},
-Package () {0x000E, 0x02, 0C, 18},
+Package () {0x000E, 0x02, 0, 18},
 Package () {0x000E, 0x03, 0, 19},
 
 Package () {0x000F, 0x00, 0, 16},
-- 
2.34.1

Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de 
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva  
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928



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[edk2-devel] [PATCH 2/2] SimicsOpenBoardPkg: Override additional Pcd

[Guenzel, Robert]

The Pcd gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable is by default True 
in UefiCpuPkg.
However, the Simics target does not have the MSRs whose access is guarded by 
this Pcd and
hence runs into a GP fault. Consequently, we override the Pcd to be False.

Signed-off-by: Robert Guenzel 
---
 .../Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc   | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc 
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
index e2171dd3..472318cc 100644
--- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
@@ -38,6 +38,7 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
   gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+  gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|FALSE
 
   ##
   # Platform Configuration
-- 
2.34.1

Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de 
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva  
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928



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