[edk2-devel][PATCH][edk2-staging] BaseTools: Fix BaseTools compilation issues
https://bugzilla.tianocore.org/show_bug.cgi?id=4798
This patch removes unused variables that were causing compilation
errors when building EDK2/BaseTools with GCC with the compiler flag
Wunused-but-set-variable set.
Cc: Liming Gao
Cc: Bob Feng
Cc: Yuwei Chen
Signed-off-by: Ted Kuo
---
BaseTools/Source/C/BfmLib/BfmLib.c | 26 --
BaseTools/Source/C/FMMT/FmmtLib.c | 26 --
2 files changed, 52 deletions(-)
diff --git a/BaseTools/Source/C/BfmLib/BfmLib.c
b/BaseTools/Source/C/BfmLib/BfmLib.c
index c247cc8e1d..0893356b08 100644
--- a/BaseTools/Source/C/BfmLib/BfmLib.c
+++ b/BaseTools/Source/C/BfmLib/BfmLib.c
@@ -363,11 +363,9 @@ LibGetFvSize (
)
{
- UINTN BytesRead;
UINT32 Size;
EFI_FV_BLOCK_MAP_ENTRY BlockMap;
- BytesRead = 0;
Size = 0;
if (InputFile == NULL || FvSize == NULL) {
@@ -377,7 +375,6 @@ LibGetFvSize (
fseek (InputFile, sizeof (EFI_FIRMWARE_VOLUME_HEADER) - sizeof
(EFI_FV_BLOCK_MAP_ENTRY), SEEK_CUR);
do {
fread (, sizeof (EFI_FV_BLOCK_MAP_ENTRY), 1, InputFile);
-BytesRead += sizeof (EFI_FV_BLOCK_MAP_ENTRY);
if (BlockMap.NumBlocks != 0) {
Size += BlockMap.NumBlocks * BlockMap.Length;
@@ -1032,7 +1029,6 @@ LibParseSection (
CHAR16 *UIName;
UINT32 UINameSize;
BOOLEAN HasDepexSection;
- UINT32 NumberOfSections;
BOOLEAN IsFfsGenerated;
ENCAP_INFO_DATA *LocalEncapData;
CHAR8 *BlankChar;
@@ -1058,7 +1054,6 @@ LibParseSection (
ParsedLength = 0;
ToolOutputLength = 0;
UINameSize = 0;
- NumberOfSections = 0;
UncompressedLength = 0;
CompressedLength = 0;
CompressionType= 0;
@@ -1116,7 +,6 @@ LibParseSection (
EncapDataNeedUpdata = TRUE;
Level ++;
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].IsLeaf = FALSE;
@@ -1171,7 +1165,6 @@ LibParseSection (
case EFI_SECTION_COMPRESSION:
Level ++;
- NumberOfSections ++;
EncapDataNeedUpdata = TRUE;
//
@@ -1317,7 +1310,6 @@ LibParseSection (
// a GUID defined FV section.
//
Level ++;
- NumberOfSections++;
EncapDataNeedUpdata = TRUE;
//
@@ -1583,7 +1575,6 @@ LibParseSection (
//Leaf sections
//
case EFI_SECTION_RAW:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
if (!ViewFlag) {
if (!IsFfsGenerated) {
@@ -1594,7 +1585,6 @@ LibParseSection (
break;
case EFI_SECTION_PE32:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
if (!ViewFlag) {
if (!IsFfsGenerated) {
@@ -1605,7 +1595,6 @@ LibParseSection (
break;
case EFI_SECTION_PIC:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
if (!ViewFlag) {
if (!IsFfsGenerated) {
@@ -1616,7 +1605,6 @@ LibParseSection (
break;
case EFI_SECTION_TE:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
if (!ViewFlag) {
if (!IsFfsGenerated) {
@@ -1627,7 +1615,6 @@ LibParseSection (
break;
case EFI_SECTION_COMPATIBILITY16:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
if (!ViewFlag) {
@@ -1639,7 +1626,6 @@ LibParseSection (
break;
case EFI_SECTION_FREEFORM_SUBTYPE_GUID:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
if (!ViewFlag) {
if (!IsFfsGenerated) {
@@ -1650,27 +1636,22 @@ LibParseSection (
break;
case EFI_SECTION_VERSION:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
break;
case EFI_SECTION_PEI_DEPEX:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
HasDepexSection = TRUE;
break;
case EFI_SECTION_DXE_DEPEX:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
HasDepexSection = TRUE;
break;
case EFI_SECTION_SMM_DEPEX:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
HasDepexSection = TRUE;
break;
case EFI_SECTION_USER_INTERFACE:
- NumberOfSections ++;
CurrentFv->FfsAttuibutes[*FfsCount].Level = Level;
UiSectionLength = FvBufExpand3ByteSize (((EFI_USER_INTERFACE_SECTION *)
Ptr)->CommonHeader.Size);
@@ -1975,7 +1956,6 @@ LibGetFvInfo (
)
{
EFI_STATUS Status;
- UINTN NumberOfFiles;
BOOLEAN ErasePolarity;
UINTN FvSize;
EFI_FFS_FILE_HEADER2*CurrentFile;
@@ -1983,7 +1963,6 @@ LibGetFvInfo (
ENCAP_INFO_DATA
[edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common files to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
...pWrapperPlatformSecLibResetVectorInFsp.inf | 101 +
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 +--
.../X64/PeiCoreEntry.nasm | 202 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 +++
.../Ia32 => Include}/Fsp.h| 6 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 17 +-
12 files changed, 565 insertions(+), 34 deletions(-)
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (79%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..24c18f25b8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1)
+#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1
/** Fsp T Core UPD
**/
typedef struct {
@@ -34,6 +35,28 @@ typedef struct {
**/
UINT8 Reserved[16];
} FSPT_CORE_UPD;
+#else
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0040
+**/
+ EFI_PHYSICAL_ADDRESSMicrocodeRegionBase;
+
+/** Offset 0x0048
+**/
+ UINT64 MicrocodeRegionSize;
+
+/** Offset 0x0050
+**/
+ EFI_PHYSICAL_ADDRESSCodeRegionBase;
+
+/** Offset 0x0058
+**/
+ UINT64 CodeRegionSize;
+} FSPT_CORE_UPD;
+#endif
#pragma pack()
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..0b3f343991 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2019 - 2024, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
; Module Name:
;
@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"
+#include
SECTION .text
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..6806e000ce 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
## @file
-# Provide FSP wrapper platform sec related function.
+# Provide FSP wrapper platform sec related function for IA32.
#
-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +25,7 @@
#
# The following information is
Re: [edk2-devel][edk2-platforms][PATCH v3] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
Hi Sai,
Thanks for the feedback. I'll change SecFspWrapperPlatformSecLibFspO to
SecFspWrapperPlatformSecLibResetVectorInFsp in patch V4. Regarding the
timestamp, I'm planning to save the TSC value near the entry of FspSecCoreO in
FSP. In patch V4, FSP wrapper/platform code reads the timestamp from mm5
instead of ymm6 and then push it to stack.
Thanks,
Ted
-Original Message-
From: Chaganty, Rangasai V
Sent: Saturday, December 30, 2023 4:34 AM
To: Kuo, Ted ; devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L
; Dong, Eric ; S, Ashraf
Ali ; Duggapu, Chinni B ;
Gao, Liming
Subject: RE: [edk2-devel][edk2-platforms][PATCH v3] MinPlatformPkg: Support
SecFspWrapperPlatformSecLib in X64
Hi Ted,
I see good improvements on V3. Thanks!
Few comments/feedback:
1. Minor feedback - The module name choice SecFspWrapperPlatformSecLibFspO.inf
is assuming FSP owning reset vector will be part of FSP-O. it's an
implementation choice. Perhaps consider the name to be
SecFspWrapperPlatformSecLibResetVectorInFsp or
SecFspWrapperPlatformSecLibFor64Bit (to be more relevant to the purpose of the
file).
2. I see TSC values are pushed into stack. However, I am not seeing a rdtsc
instruction to read the TSC value. Can you clarify how are we getting the TSC
values?
Thanks,
Sai
-Original Message-
From: Kuo, Ted
Sent: Friday, December 22, 2023 2:14 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel
; Desimone, Nathaniel L
; Dong, Eric ; S, Ashraf
Ali ; Duggapu, Chinni B ;
Gao, Liming
Subject: [edk2-devel][edk2-platforms][PATCH v3] MinPlatformPkg: Support
SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common file to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 +-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
.../SecFspWrapperPlatformSecLibFspO.inf | 101
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 --
.../X64/PeiCoreEntry.nasm | 218 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 ++
.../Ia32 => Include}/Fsp.h| 4 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 15 ++
12 files changed, 579 insertions(+), 32 deletions(-) create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibFspO.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (86%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..cc36334227 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file -Copyright (c) 2017, Intel Corporation. All rights
reserved.+Copyright (c) 2017 - 2023, Intel Corporation. All rights
reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6 +10,7
@@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1) +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1 /** Fsp T
Core UPD **/ typedef struct {@@ -34,6 +35,28 @@ typedef struct {
**/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#else+/** Fsp
T Core UPD+**/+typedef struct {++/** Offset 0x0040+**/+ EFI_PHYSICAL_ADDRESS
MicrocodeRegionBase;++/** Offset 0x0048+**/+ UINT64
MicrocodeRegionSize;++/** Offset 0x0050+**/+ EFI_PHYSICAL_ADDRESS
CodeRegionBase;++/** Offset 0x0058+**/+ UINT64
CodeRegionSize;+} FSPT_CORE_UPD;+#endif #pragma pack() diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatf
[edk2-devel][edk2-platforms][PATCH v3] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common file to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 +-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
.../SecFspWrapperPlatformSecLibFspO.inf | 101
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 --
.../X64/PeiCoreEntry.nasm | 218 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 ++
.../Ia32 => Include}/Fsp.h| 4 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 15 ++
12 files changed, 579 insertions(+), 32 deletions(-)
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibFspO.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (86%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..cc36334227 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1)
+#if FixedPcdGet8 (PcdFsptArchUpdRevision) <= 1
/** Fsp T Core UPD
**/
typedef struct {
@@ -34,6 +35,28 @@ typedef struct {
**/
UINT8 Reserved[16];
} FSPT_CORE_UPD;
+#else
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0040
+**/
+ EFI_PHYSICAL_ADDRESSMicrocodeRegionBase;
+
+/** Offset 0x0048
+**/
+ UINT64 MicrocodeRegionSize;
+
+/** Offset 0x0050
+**/
+ EFI_PHYSICAL_ADDRESSCodeRegionBase;
+
+/** Offset 0x0058
+**/
+ UINT64 CodeRegionSize;
+} FSPT_CORE_UPD;
+#endif
#pragma pack()
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..de44066a20 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2019 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
; Module Name:
;
@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"
+#include
SECTION .text
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..2ff931bfe8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
## @file
-# Provide FSP wrapper platform sec related function.
+# Provide FSP wrapper platform sec related function for IA32.
#
-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +25,7 @@
#
# The following information is for reference
Re: [edk2-devel][edk2-platforms][PATCH v2] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
Please drop v2. I'm going to update the patch to v3.
Thanks,
Ted
-Original Message-
From: devel@edk2.groups.io On Behalf Of Kuo, Ted
Sent: Thursday, December 21, 2023 6:37 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel
; Desimone, Nathaniel L
; Dong, Eric ; S, Ashraf
Ali ; Duggapu, Chinni B ;
Gao, Liming
Subject: [edk2-devel][edk2-platforms][PATCH v2] MinPlatformPkg: Support
SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common file to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 +-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
.../SecFspWrapperPlatformSecLibFspO.inf | 101
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 --
.../X64/PeiCoreEntry.nasm | 218 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 ++
.../Ia32 => Include}/Fsp.h| 4 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 15 ++
12 files changed, 579 insertions(+), 32 deletions(-) create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibFspO.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (86%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..7c4ddc09a8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file -Copyright (c) 2017, Intel Corporation. All rights
reserved.+Copyright (c) 2017 - 2023, Intel Corporation. All rights
reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6 +10,28
@@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1) +#if defined (MDE_CPU_X64)+/** Fsp T Core UPD+**/+typedef
struct {++/** Offset 0x0040+**/+ EFI_PHYSICAL_ADDRESS
MicrocodeRegionBase;++/** Offset 0x0048+**/+ UINT64
MicrocodeRegionSize;++/** Offset 0x0050+**/+ EFI_PHYSICAL_ADDRESS
CodeRegionBase;++/** Offset 0x0058+**/+ UINT64
CodeRegionSize;+} FSPT_CORE_UPD;+#else /** Fsp T Core UPD **/ typedef struct
{@@ -34,6 +56,7 @@ typedef struct {
**/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#endif
#pragma pack() diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..de44066a20 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;-; Copyright (c) 2019, Intel Corporation. All rights reserved.+; Copyright
(c) 2019 - 2023, Intel Corporation. All rights reserved. ;
SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"+#include SECTION .text diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..2ff931bfe8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/SecFspWrapperPlatformSe
Re: [edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
Thanks Nate for the feedback. I've sent out patch v2 according to your
comments. Can you please review again?
Thanks,
Ted
-Original Message-
From: Desimone, Nathaniel L
Sent: Thursday, December 21, 2023 8:13 AM
To: Kuo, Ted ; devel@edk2.groups.io
Cc: Chaganty, Rangasai V ; Chiu, Chasel
; Dong, Eric ; S, Ashraf Ali
; Duggapu, Chinni B ; Gao,
Liming
Subject: RE: [edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg: Support
SecFspWrapperPlatformSecLib in X64
Hi Ted,
Looking at this code, the X64 version will only work if
PcdFspWrapperResetVectorInFsp == TRUE. Moreover, the IA32 version will only
work if PcdFspWrapperResetVectorInFsp == FALSE. So... what is the point of
having a PCD if the PCD must always be set to one value or the other? Please
choose one of these options:
Option 1: Make the PCD work correctly for all the 4 cases:
- IA32 + Bootloader Reset Vector
- IA32 + FSP Reset Vector
- X64 + Bootloader Reset Vector
- X64 + FSP Reset Vector
Option 2: Make a separate instance of PlatformSecLib for the case of FSP-O
providing the reset vector.
Additional feedback is below inline.
Thanks,
Nate
> -Original Message-
> From: Kuo, Ted
> Sent: Sunday, December 17, 2023 8:03 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Dong, Eric ; S,
> Ashraf Ali ; Duggapu, Chinni B
> ; Gao, Liming
> Subject: [edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg:
> Support SecFspWrapperPlatformSecLib in X64
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=4623
> 1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
> 2.Made changes in common file to support both IA32 and X64.
> 3.Added the PCDs below for FSP-T UPD revsions and X64 feature.
> - PcdFspWrapperResetVectorInFsp
> - PcdFspWrapperBfvforResetVectorInFsp
> - PcdFsptUpdHeaderRevision
> - PcdFsptArchUpdHeaderRevision
>
> Cc: Sai Chaganty
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Eric Dong
> Cc: Ashraf Ali S
> Cc: Chinni B Duggapu
> Cc: Liming Gao
> Signed-off-by: Ted Kuo
> ---
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 +-
> .../Ia32/SecEntry.nasm| 4 +-
> .../SecFspWrapperPlatformSecLib.inf | 12 +-
> .../SecGetPerformance.c | 11 +-
> .../SecPlatformInformation.c | 8 +-
> .../SecRamInitData.c | 56 -
> .../X64/PeiCoreEntry.nasm | 224 ++
> .../X64/SecEntry.nasm | 214 +
> .../X64/Stack.nasm| 72 ++
> .../Ia32 => Include}/Fsp.h| 4 +-
> .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 21 ++
> 11 files changed, 629 insertions(+), 22 deletions(-) create mode
> 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/X64/PeiCoreEntry.nasm create mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/X64/SecEntry.nasm create mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform
> SecLib/X64/Stack.nasm rename
> Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32 => Include}/Fsp.h (86%)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/FsptCoreUpd.h
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/FsptCoreUpd.h
> index 7c0f605b92..7c4ddc09a8 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/FsptCoreUpd.h
> +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl
> +++ atformSecLib/FsptCoreUpd.h
> @@ -1,6 +1,6 @@
> /** @file
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2023, Intel Corporation. All rights
> +reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -10,6 +10,28 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #pragma pack(1)
>
> +#if defined (MDE_CPU_X64)
> +/** Fsp T Core UPD
> +**/
> +typedef struct {
> +
> +/** Offset 0x0040
> +**/
> + EFI_PHYSICAL_ADDRESSMicrocodeRegionBase;
> +
> +/** Offset 0x0048
> +**/
> + UINT64 MicrocodeRegionSize;
> +
> +/** Offset 0x0050
> +**/
> + EFI_PHYSICAL_ADDRESSCodeRegionBase;
> +
> +/** Offset 0x0058
> +**/
> + UINT64 CodeRegionSize;
> +} FSPT_CORE_UPD;
> +#else
> /** Fsp T Core UPD
> **/
> typedef struct {
> @@ -34,6 +56,7 @@ typedef struct {
> **/
>UINT8 Reserved[16];
> } FSPT_COR
[edk2-devel][edk2-platforms][PATCH v2] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common file to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP.
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 +-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 9 +-
.../SecFspWrapperPlatformSecLibFspO.inf | 101
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 73 --
.../X64/PeiCoreEntry.nasm | 218 ++
.../X64/SecEntry.nasm | 71 ++
.../X64/Stack.nasm| 72 ++
.../Ia32 => Include}/Fsp.h| 4 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 15 ++
12 files changed, 579 insertions(+), 32 deletions(-)
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLibFspO.inf
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (86%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..7c4ddc09a8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,6 +10,28 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1)
+#if defined (MDE_CPU_X64)
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0040
+**/
+ EFI_PHYSICAL_ADDRESSMicrocodeRegionBase;
+
+/** Offset 0x0048
+**/
+ UINT64 MicrocodeRegionSize;
+
+/** Offset 0x0050
+**/
+ EFI_PHYSICAL_ADDRESSCodeRegionBase;
+
+/** Offset 0x0058
+**/
+ UINT64 CodeRegionSize;
+} FSPT_CORE_UPD;
+#else
/** Fsp T Core UPD
**/
typedef struct {
@@ -34,6 +56,7 @@ typedef struct {
**/
UINT8 Reserved[16];
} FSPT_CORE_UPD;
+#endif
#pragma pack()
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..de44066a20 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2019 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
; Module Name:
;
@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"
+#include
SECTION .text
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..2ff931bfe8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
## @file
-# Provide FSP wrapper platform sec related function.
+# Provide FSP wrapper platform sec related function for IA32.
#
-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +25,7 @@
#
# The following information is for reference only and not required
[edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64
https://bugzilla.tianocore.org/show_bug.cgi?id=4623
1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64.
2.Made changes in common file to support both IA32 and X64.
3.Added the PCDs below for FSP-T UPD revsions and X64 feature.
- PcdFspWrapperResetVectorInFsp
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdHeaderRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming Gao
Signed-off-by: Ted Kuo
---
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 +-
.../Ia32/SecEntry.nasm| 4 +-
.../SecFspWrapperPlatformSecLib.inf | 12 +-
.../SecGetPerformance.c | 11 +-
.../SecPlatformInformation.c | 8 +-
.../SecRamInitData.c | 56 -
.../X64/PeiCoreEntry.nasm | 224 ++
.../X64/SecEntry.nasm | 214 +
.../X64/Stack.nasm| 72 ++
.../Ia32 => Include}/Fsp.h| 4 +-
.../Intel/MinPlatformPkg/MinPlatformPkg.dec | 21 ++
11 files changed, 629 insertions(+), 22 deletions(-)
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm
create mode 100644
Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm
rename
Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32
=> Include}/Fsp.h (86%)
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
index 7c0f605b92..7c4ddc09a8 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,6 +10,28 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1)
+#if defined (MDE_CPU_X64)
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0040
+**/
+ EFI_PHYSICAL_ADDRESSMicrocodeRegionBase;
+
+/** Offset 0x0048
+**/
+ UINT64 MicrocodeRegionSize;
+
+/** Offset 0x0050
+**/
+ EFI_PHYSICAL_ADDRESSCodeRegionBase;
+
+/** Offset 0x0058
+**/
+ UINT64 CodeRegionSize;
+} FSPT_CORE_UPD;
+#else
/** Fsp T Core UPD
**/
typedef struct {
@@ -34,6 +56,7 @@ typedef struct {
**/
UINT8 Reserved[16];
} FSPT_CORE_UPD;
+#endif
#pragma pack()
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 7f6d771e41..de44066a20 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
@@ -1,6 +1,6 @@
;--
;
-; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2019 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
; Module Name:
;
@@ -13,7 +13,7 @@
;
;--
-#include "Fsp.h"
+#include
SECTION .text
diff --git
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 2e0d67eae4..99a04cc264 100644
---
a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++
b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,7 +1,7 @@
## @file
# Provide FSP wrapper platform sec related function.
#
-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -47,7 +47,11 @@
Ia32/SecEntry.nasm
Ia32/PeiCoreEntry.nasm
Ia32/Stack.nasm
- Ia32/Fsp.h
+
+[Sources.X64]
+ X64/SecEntry.nasm
+ X64/PeiCoreEntry.nasm
+ X64/Stack.nasm
#
@@ -96,3 +100,7 @@
Re: [edk2-devel] [PATCH] IntelFsp2Pkg/FspMultiPhaseLib: Remove EFIAPI for local function
Reviewed-by: Kuo, Ted Thanks, Ted -Original Message- From: S, Ashraf Ali Sent: Monday, November 13, 2023 4:12 PM To: Ni, Ray ; devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Duggapu, Chinni B ; Ng, Ray Han Lim ; Zeng, Star ; Kuo, Ted ; Mohapatra, Susovan Subject: RE: [PATCH] IntelFsp2Pkg/FspMultiPhaseLib: Remove EFIAPI for local function Reviewed-by: S, Ashraf Ali Thanks., S, Ashraf Ali -Original Message- From: Ni, Ray Sent: Monday, November 13, 2023 1:09 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Duggapu, Chinni B ; Ng, Ray Han Lim ; Zeng, Star ; Kuo, Ted ; S, Ashraf Ali ; Mohapatra, Susovan Subject: [PATCH] IntelFsp2Pkg/FspMultiPhaseLib: Remove EFIAPI for local function FspMultiPhaseWorker() is a local function that's called from FspMultiPhaseMemInitApiHandler() and FspMultiPhaseSiInitApiHandlerV2(). Remove "EFIAPI" from its function header. Signed-off-by: Ray Ni Cc: Chasel Chiu Cc: Nate DeSimone Cc: Duggapu Chinni B Cc: Ray Han Lim Ng Cc: Star Zeng Cc: Ted Kuo Cc: Ashraf Ali S Cc: Susovan Mohapatra --- IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c index 3786da91b1..4fc4104226 100644 --- a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c +++ b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c @@ -1,7 +1,7 @@ /** @file FSP MultiPhase library. - Copyright (c) 2022, Intel Corporation. All rights reserved. + Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -58,7 +58,6 @@ FspVariableRequestSwitchStack ( @retval EFI_DEVICE_ERRORFSP initialization failed. **/ EFI_STATUS -EFIAPI FspMultiPhaseWorker ( IN UINT32 ApiIdx, IN VOID*ApiParam -- 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#60): https://edk2.groups.io/g/devel/message/60 Mute This Topic: https://groups.io/mt/102557250/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B when calling C function in 64bit
Reviewed-by: Ted Kuo mailto:ted@intel.com>> From: Ni, Ray Sent: Tuesday, October 31, 2023 4:26 PM To: devel@edk2.groups.io; Ni, Ray Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Duggapu, Chinni B ; Ng, Ray Han Lim ; Zeng, Star ; Kuo, Ted ; S, Ashraf Ali ; Mohapatra, Susovan Subject: Re: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B when calling C function in 64bit Sorry, I copied the maintainers from Maintainers.txt but forgot to change all M/R to "Cc". That caused not all the maintainers/reviewers are CCed. I will fix the commit message before merging. Thanks, Ray From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> mailto:devel@edk2.groups.io>> on behalf of Ni, Ray mailto:ray...@intel.com>> Sent: Tuesday, October 31, 2023 4:22 PM To: devel@edk2.groups.io<mailto:devel@edk2.groups.io> mailto:devel@edk2.groups.io>> Cc: Chiu, Chasel mailto:chasel.c...@intel.com>> Subject: [edk2-devel] [PATCH] IntelFsp2Pkg/SwitchStack: Reserve 32B when calling C function in 64bit When FSP runs in API mode, it saves the IDTR in its own stack then switches to bootloader's stack before it returns from FspMemoryInit. Next time when the bootloader calls TempRamExit, FSP switches to its own stack and restores IDTR from its stack saved earlier. However, due to a bug in BaseFspSwitchStackLib, the IDTR saved on FSP's stack might be corrupted that results the following TempRamExit call fails inside FSP due to PeiServices pointer cannot be retrieved from IDT.base - 8. The bug is the assembly code doesn't reserve 32 bytes before calling the C routine in 64bit. According to the x86-64 calling convention, caller is responsible for allocating 32 bytes of "shadow space" on the stack right before calling the function (regardless of the actual number of parameters used). When FSP is built in optimization-off mode, the C routine makes use of the 32-byte "shadow space" which is not reserved by the assembly caller. That causes the IDTR saved on the stack is corrupted by the C routine. The patch fixes so by reserving the 32 bytes before calling C routine. Signed-off-by: Ray Ni mailto:ray...@intel.com>> Cc: Chasel Chiu mailto:chasel.c...@intel.com>> M: Nate DeSimone mailto:nathaniel.l.desim...@intel.com>> M: Duggapu Chinni B mailto:chinni.b.dugg...@intel.com>> M: Ray Han Lim Ng mailto:ray.han.lim...@intel.com>> R: Star Zeng mailto:star.z...@intel.com>> R: Ted Kuo mailto:ted@intel.com>> R: Ashraf Ali S mailto:ashraf.al...@intel.com>> R: Susovan Mohapatra mailto:susovan.mohapa...@intel.com>> --- IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm index 1ea1220608..e3a7cf002f 100644 --- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm +++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm @@ -1,6 +1,6 @@ ;-- ; -; Copyright (c) 2022, Intel Corporation. All rights reserved. +; Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved. ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -60,7 +60,9 @@ ASM_PFX(FspSwitchStack): ; Load new stack mov rcx, rsp +sub rsp, 0x20 callASM_PFX(SwapStack) +add rsp, 0x20 mov rsp, rax ; Restore previous contexts -- 2.39.1.windows.1 -=-=-=-=-=-= Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110384): https://edk2.groups.io/g/devel/message/110384 Mute This Topic: https://groups.io/mt/102293342/1712937 Group Owner: devel+ow...@edk2.groups.io<mailto:devel+ow...@edk2.groups.io> Unsubscribe: https://edk2.groups.io/g/devel/leave/3759105/1712937/893644498/xyzzy [ray...@intel.com] -=-=-=-=-=-= -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110387): https://edk2.groups.io/g/devel/message/110387 Mute This Topic: https://groups.io/mt/102293342/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][PATCH v1] SplitFspBin.py cannot support FSP binary with child FV included
Thanks Chasel for the feedback. I've sent patch v2 with changes according to
your comment. Can you please review it again?
Thanks,
Ted
-Original Message-
From: Chiu, Chasel
Sent: Thursday, July 20, 2023 2:14 AM
To: Kuo, Ted ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Zeng, Star
; S, Ashraf Ali ; Duggapu, Chinni
B ; Ng, Ray Han Lim ;
Mohapatra, Susovan
Subject: RE: [edk2-devel][PATCH v1] SplitFspBin.py cannot support FSP binary
with child FV included
Hi Ted,
One question below inline.
Another minor feedback is the commit/patch subject format should be "Package:
title"
Thanks,
Chasel
> -Original Message-----
> From: Kuo, Ted
> Sent: Tuesday, July 18, 2023 7:16 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star ; S,
> Ashraf Ali ; Duggapu, Chinni B
> ; Ng, Ray Han Lim
> ; Mohapatra, Susovan
>
> Subject: [edk2-devel][PATCH v1] SplitFspBin.py cannot support FSP
> binary with child FV included
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=4502
> Update SplitFspBin.py to support child FV in FSP binary. Without the
> patch, the tool won't be able to rebase the images in child FV in FSP binary.
>
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Ashraf Ali S
> Cc: Chinni B Duggapu
> Cc: Ray Han Lim Ng
> Cc: Susovan Mohapatra
> Signed-off-by: Ted Kuo
> ---
> IntelFsp2Pkg/Tools/SplitFspBin.py | 32
> ---
> 1 file changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
> b/IntelFsp2Pkg/Tools/SplitFspBin.py
> index 419e5ba985..2e7550dbb2 100644
> --- a/IntelFsp2Pkg/Tools/SplitFspBin.py
> +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
> @@ -469,6 +469,7 @@ class FirmwareVolume:
> else: self.FvExtHdr = None self.FfsList = []+
> self.ChildFvList =
> [] def ParseFv(self): fvsize = len(self.FvData)@@ -483,8 +484,18
> @@ class
> FirmwareVolume:
> offset = fvsize else: ffs =
> FirmwareFile (offset,
> self.FvData[offset:offset + int(ffshdr.Size)])-ffs.ParseFfs()-
> self.FfsList.append(ffs)+csoffset = offset + sizeof
> (EFI_FFS_FILE_HEADER)+cshdr =
> EFI_COMMON_SECTION_HEADER.from_buffer (self.FvData, csoffset)+
> #
> check if there is child fv+if (ffs.FfsHdr.Type ==
> EFI_FV_FILETYPE.FIRMWARE_VOLUME_IMAGE and cshdr.Type ==
> EFI_SECTION_TYPE.RAW):+childfvoffset = csoffset + sizeof
Is child FV always with EFI_SECTION_TYPE.RAW? Or it could be other types like
EFI_SECTION_TYPE.FIRMWARE_VOLUME_IMAGE?
> (EFI_COMMON_SECTION_HEADER) + int(cshdr.Size)+childfvhdr =
> EFI_FIRMWARE_VOLUME_HEADER.from_buffer (self.FvData, childfvoffset)+
> childfv = FirmwareVolume (childfvoffset,
> self.FvData[childfvoffset:childfvoffset +
> int(childfvhdr.FvLength)])+childfv.ParseFv ()+
> self.ChildFvList.append(childfv)+else:+
> ffs.ParseFfs()+
> self.FfsList.append(ffs) offset += int(ffshdr.Size)
> offset =
> AlignPtr(offset) @@ -789,6 +800,13 @@ def SplitFspBin (fspfile,
> outdir,
> nametemplate):
> hfsp.write(fv.FvData) hfsp.close() +def GetImageFromFv
> (fd,
> parentfvoffset, fv, imglist):+for ffs in fv.FfsList:+for sec in
> ffs.SecList:+
> if sec.SecHdr.Type in [EFI_SECTION_TYPE.TE, EFI_SECTION_TYPE.PE32]: # TE or
> PE32+offset = fd.Offset + parentfvoffset + fv.Offset +
> PE32+ ffs.Offset +
> sec.Offset + sizeof(sec.SecHdr)+imglist.append ((offset,
> len(sec.SecData)
> - sizeof(sec.SecHdr)))+ def RebaseFspBin (FspBinary, FspComponent, FspBase,
> OutputDir, OutputFile): fd = FirmwareDevice(0, FspBinary) fd.ParseFd
> ()@@ -
> 832,11 +850,11 @@ def RebaseFspBin (FspBinary, FspComponent, FspBase,
> OutputDir, OutputFile):
> imglist = [] for fvidx in fsp.FvIdxList: fv =
> fd.FvList[fvidx]-for
> ffs in fv.FfsList:-for sec in ffs.SecList:-
> if sec.SecHdr.Type in
> [EFI_SECTION_TYPE.TE, EFI_SECTION_TYPE.PE32]: # TE or PE32-
> offset = fd.Offset + fv.Offset + ffs.Offset + sec.Offset +
> sizeof(sec.SecHdr)- imglist.append ((offset, len(sec.SecData) -
> sizeof(sec.SecHdr)))+
> GetImageFromFv (fd, 0, fv, imglist)+# get image from child fv+
> for
> childfv in fv.ChildFvList:+print ("Get image from child fv of
> fv%d, parent
> fv offset: 0x%x" % (fvidx, fv.Offset))+GetImageFrom
[edk2-devel][PATCH v2] IntelFsp2Pkg: Support child FV in SplitFspBin.py
https://bugzilla.tianocore.org/show_bug.cgi?id=4502
Update SplitFspBin.py to support child FV in FSP binary. Without the
patch, the tool won't be able to rebase the images in child FV in FSP
binary.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Ray Han Lim Ng
Cc: Susovan Mohapatra
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/Tools/SplitFspBin.py | 44 ++-
1 file changed, 37 insertions(+), 7 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
b/IntelFsp2Pkg/Tools/SplitFspBin.py
index 419e5ba985..558eaf401a 100644
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -469,6 +469,7 @@ class FirmwareVolume:
else:
self.FvExtHdr = None
self.FfsList = []
+self.ChildFvList = []
def ParseFv(self):
fvsize = len(self.FvData)
@@ -483,8 +484,30 @@ class FirmwareVolume:
offset = fvsize
else:
ffs = FirmwareFile (offset, self.FvData[offset:offset +
int(ffshdr.Size)])
-ffs.ParseFfs()
-self.FfsList.append(ffs)
+# check if there is child fv
+childfvfound = 0
+if (ffs.FfsHdr.Type == EFI_FV_FILETYPE.FIRMWARE_VOLUME_IMAGE):
+csoffset = offset + sizeof (EFI_FFS_FILE_HEADER)
+csoffset = AlignPtr(csoffset, 4)
+# find fv section
+while csoffset < (offset + int(ffs.FfsHdr.Size)):
+cshdr = EFI_COMMON_SECTION_HEADER.from_buffer
(self.FvData, csoffset)
+if (cshdr.Type ==
EFI_SECTION_TYPE.FIRMWARE_VOLUME_IMAGE):
+childfvfound = 1
+break
+else:
+# check next section
+csoffset += int(cshdr.Size)
+csoffset = AlignPtr(csoffset, 4)
+if (childfvfound):
+childfvoffset = csoffset + sizeof
(EFI_COMMON_SECTION_HEADER)
+childfvhdr = EFI_FIRMWARE_VOLUME_HEADER.from_buffer
(self.FvData, childfvoffset)
+childfv = FirmwareVolume (childfvoffset,
self.FvData[childfvoffset:childfvoffset + int(childfvhdr.FvLength)])
+childfv.ParseFv ()
+self.ChildFvList.append(childfv)
+else:
+ffs.ParseFfs()
+self.FfsList.append(ffs)
offset += int(ffshdr.Size)
offset = AlignPtr(offset)
@@ -789,6 +812,13 @@ def SplitFspBin (fspfile, outdir, nametemplate):
hfsp.write(fv.FvData)
hfsp.close()
+def GetImageFromFv (fd, parentfvoffset, fv, imglist):
+for ffs in fv.FfsList:
+for sec in ffs.SecList:
+if sec.SecHdr.Type in [EFI_SECTION_TYPE.TE,
EFI_SECTION_TYPE.PE32]: # TE or PE32
+offset = fd.Offset + parentfvoffset + fv.Offset + ffs.Offset +
sec.Offset + sizeof(sec.SecHdr)
+imglist.append ((offset, len(sec.SecData) -
sizeof(sec.SecHdr)))
+
def RebaseFspBin (FspBinary, FspComponent, FspBase, OutputDir, OutputFile):
fd = FirmwareDevice(0, FspBinary)
fd.ParseFd ()
@@ -832,11 +862,11 @@ def RebaseFspBin (FspBinary, FspComponent, FspBase,
OutputDir, OutputFile):
imglist = []
for fvidx in fsp.FvIdxList:
fv = fd.FvList[fvidx]
-for ffs in fv.FfsList:
-for sec in ffs.SecList:
-if sec.SecHdr.Type in [EFI_SECTION_TYPE.TE,
EFI_SECTION_TYPE.PE32]: # TE or PE32
-offset = fd.Offset + fv.Offset + ffs.Offset +
sec.Offset + sizeof(sec.SecHdr)
-imglist.append ((offset, len(sec.SecData) -
sizeof(sec.SecHdr)))
+GetImageFromFv (fd, 0, fv, imglist)
+# get image from child fv
+for childfv in fv.ChildFvList:
+print ("Get image from child fv of fv%d, parent fv offset:
0x%x" % (fvidx, fv.Offset))
+GetImageFromFv (fd, fv.Offset, childfv, imglist)
fcount = 0
pcount = 0
--
2.40.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#107093): https://edk2.groups.io/g/devel/message/107093
Mute This Topic: https://groups.io/mt/100252890/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v1] SplitFspBin.py cannot support FSP binary with child FV included
https://bugzilla.tianocore.org/show_bug.cgi?id=4502
Update SplitFspBin.py to support child FV in FSP binary. Without the
patch, the tool won't be able to rebase the images in child FV in FSP
binary.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Ray Han Lim Ng
Cc: Susovan Mohapatra
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/Tools/SplitFspBin.py | 32 ---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py
b/IntelFsp2Pkg/Tools/SplitFspBin.py
index 419e5ba985..2e7550dbb2 100644
--- a/IntelFsp2Pkg/Tools/SplitFspBin.py
+++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
@@ -469,6 +469,7 @@ class FirmwareVolume:
else:
self.FvExtHdr = None
self.FfsList = []
+self.ChildFvList = []
def ParseFv(self):
fvsize = len(self.FvData)
@@ -483,8 +484,18 @@ class FirmwareVolume:
offset = fvsize
else:
ffs = FirmwareFile (offset, self.FvData[offset:offset +
int(ffshdr.Size)])
-ffs.ParseFfs()
-self.FfsList.append(ffs)
+csoffset = offset + sizeof (EFI_FFS_FILE_HEADER)
+cshdr = EFI_COMMON_SECTION_HEADER.from_buffer (self.FvData,
csoffset)
+# check if there is child fv
+if (ffs.FfsHdr.Type == EFI_FV_FILETYPE.FIRMWARE_VOLUME_IMAGE
and cshdr.Type == EFI_SECTION_TYPE.RAW):
+childfvoffset = csoffset + sizeof
(EFI_COMMON_SECTION_HEADER) + int(cshdr.Size)
+childfvhdr = EFI_FIRMWARE_VOLUME_HEADER.from_buffer
(self.FvData, childfvoffset)
+childfv = FirmwareVolume (childfvoffset,
self.FvData[childfvoffset:childfvoffset + int(childfvhdr.FvLength)])
+childfv.ParseFv ()
+self.ChildFvList.append(childfv)
+else:
+ffs.ParseFfs()
+self.FfsList.append(ffs)
offset += int(ffshdr.Size)
offset = AlignPtr(offset)
@@ -789,6 +800,13 @@ def SplitFspBin (fspfile, outdir, nametemplate):
hfsp.write(fv.FvData)
hfsp.close()
+def GetImageFromFv (fd, parentfvoffset, fv, imglist):
+for ffs in fv.FfsList:
+for sec in ffs.SecList:
+if sec.SecHdr.Type in [EFI_SECTION_TYPE.TE,
EFI_SECTION_TYPE.PE32]: # TE or PE32
+offset = fd.Offset + parentfvoffset + fv.Offset + ffs.Offset +
sec.Offset + sizeof(sec.SecHdr)
+imglist.append ((offset, len(sec.SecData) -
sizeof(sec.SecHdr)))
+
def RebaseFspBin (FspBinary, FspComponent, FspBase, OutputDir, OutputFile):
fd = FirmwareDevice(0, FspBinary)
fd.ParseFd ()
@@ -832,11 +850,11 @@ def RebaseFspBin (FspBinary, FspComponent, FspBase,
OutputDir, OutputFile):
imglist = []
for fvidx in fsp.FvIdxList:
fv = fd.FvList[fvidx]
-for ffs in fv.FfsList:
-for sec in ffs.SecList:
-if sec.SecHdr.Type in [EFI_SECTION_TYPE.TE,
EFI_SECTION_TYPE.PE32]: # TE or PE32
-offset = fd.Offset + fv.Offset + ffs.Offset +
sec.Offset + sizeof(sec.SecHdr)
-imglist.append ((offset, len(sec.SecData) -
sizeof(sec.SecHdr)))
+GetImageFromFv (fd, 0, fv, imglist)
+# get image from child fv
+for childfv in fv.ChildFvList:
+print ("Get image from child fv of fv%d, parent fv offset:
0x%x" % (fvidx, fv.Offset))
+GetImageFromFv (fd, fv.Offset, childfv, imglist)
fcount = 0
pcount = 0
--
2.40.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#107019): https://edk2.groups.io/g/devel/message/107019
Mute This Topic: https://groups.io/mt/100216127/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH] Maintainers.txt: Update for IntelFsp2Pkg and IntelFsp2WrapperPkg.
Reviewed-by: Kuo, Ted mailto:ted@intel.com>> From: Mohapatra, Susovan Sent: Thursday, April 27, 2023 11:20 AM To: Chiu, Chasel ; devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Duggapu, Chinni B ; Ng, Ray Han Lim ; Chen, Gang C ; Zeng, Star ; Kuo, Ted ; S, Ashraf Ali Subject: RE: [PATCH] Maintainers.txt: Update for IntelFsp2Pkg and IntelFsp2WrapperPkg. Reviewed-by: Mohapatra, Susovan mailto:susovan.mohapa...@intel.com>> From: S, Ashraf Ali mailto:ashraf.al...@intel.com>> Sent: Tuesday, April 25, 2023 12:22 AM To: Chiu, Chasel mailto:chasel.c...@intel.com>>; devel@edk2.groups.io<mailto:devel@edk2.groups.io> Cc: Chiu, Chasel mailto:chasel.c...@intel.com>>; Desimone, Nathaniel L mailto:nathaniel.l.desim...@intel.com>>; Duggapu, Chinni B mailto:chinni.b.dugg...@intel.com>>; Ng, Ray Han Lim mailto:ray.han.lim...@intel.com>>; Chen, Gang C mailto:gang.c.c...@intel.com>>; Zeng, Star mailto:star.z...@intel.com>>; Kuo, Ted mailto:ted@intel.com>>; Mohapatra, Susovan mailto:susovan.mohapa...@intel.com>> Subject: Re: [PATCH] Maintainers.txt: Update for IntelFsp2Pkg and IntelFsp2WrapperPkg. Reviewed-by: S, Ashraf Ali mailto:ashraf.al...@intel.com>> From: Chiu, Chasel mailto:chasel.c...@intel.com>> Sent: Monday, April 24, 2023 11:50:35 PM To: devel@edk2.groups.io<mailto:devel@edk2.groups.io> mailto:devel@edk2.groups.io>> Cc: Chiu, Chasel mailto:chasel.c...@intel.com>>; Desimone, Nathaniel L mailto:nathaniel.l.desim...@intel.com>>; Duggapu, Chinni B mailto:chinni.b.dugg...@intel.com>>; Ng, Ray Han Lim mailto:ray.han.lim...@intel.com>>; Chen, Gang C mailto:gang.c.c...@intel.com>>; Zeng, Star mailto:star.z...@intel.com>>; Kuo, Ted mailto:ted@intel.com>>; S, Ashraf Ali mailto:ashraf.al...@intel.com>>; Mohapatra, Susovan mailto:susovan.mohapa...@intel.com>> Subject: [PATCH] Maintainers.txt: Update for IntelFsp2Pkg and IntelFsp2WrapperPkg. Add more maintainers and reviewers for these 2 packages. Cc: Nate DeSimone mailto:nathaniel.l.desim...@intel.com>> Cc: Duggapu Chinni B mailto:chinni.b.dugg...@intel.com>> Cc: Ray Han Lim Ng mailto:ray.han.lim...@intel.com>> Cc: Chen Gang C mailto:gang.c.c...@intel.com>> Cc: Star Zeng mailto:star.z...@intel.com>> Cc: Ted Kuo mailto:ted@intel.com>> Cc: Ashraf Ali S mailto:ashraf.al...@intel.com>> Cc: Susovan Mohapatra mailto:susovan.mohapa...@intel.com>> Signed-off-by: Chasel Chiu mailto:chasel.c...@intel.com>> --- Maintainers.txt | 10 ++ 1 file changed, 10 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 455afdbc69..09d04af27a 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -237,14 +237,24 @@ F: IntelFsp2Pkg/ W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg M: Chasel Chiu mailto:chasel.c...@intel.com>> [ChaselChiu] M: Nate DeSimone mailto:nathaniel.l.desim...@intel.com>> [nate-desimone] +M: Duggapu Chinni B mailto:chinni.b.dugg...@intel.com>> [cbduggap] +M: Ray Han Lim Ng mailto:ray.han.lim...@intel.com>> [rayhanlimng] R: Star Zeng mailto:star.z...@intel.com>> [lzeng14] +R: Ted Kuo mailto:ted@intel.com>> [tedkuo1] +R: Ashraf Ali S mailto:ashraf.al...@intel.com>> [AshrafAliS] +R: Susovan Mohapatra mailto:susovan.mohapa...@intel.com>> [susovanmohapatra] IntelFsp2WrapperPkg F: IntelFsp2WrapperPkg/ W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg M: Chasel Chiu mailto:chasel.c...@intel.com>> [ChaselChiu] M: Nate DeSimone mailto:nathaniel.l.desim...@intel.com>> [nate-desimone] +M: Duggapu Chinni B mailto:chinni.b.dugg...@intel.com>> [cbduggap] +M: Chen Gang C mailto:gang.c.c...@intel.com>> [chengangc] R: Star Zeng mailto:star.z...@intel.com>> [lzeng14] +R: Ted Kuo mailto:ted@intel.com>> [tedkuo1] +R: Ashraf Ali S mailto:ashraf.al...@intel.com>> [AshrafAliS] +R: Susovan Mohapatra mailto:susovan.mohapa...@intel.com>> [susovanmohapatra] MdeModulePkg F: MdeModulePkg/ -- 2.35.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103688): https://edk2.groups.io/g/devel/message/103688 Mute This Topic: https://groups.io/mt/98477288/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file directly https://bugzilla.tianocore.org/show_bug.cgi?id=4412
Reviewed-by: Ted Kuo
Thanks,
Ted
-Original Message-
From: Duggapu, Chinni B
Sent: Friday, April 14, 2023 4:34 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L
; Zeng, Star ; Kuo, Ted
; Duggapu, Chinni B
Subject: [PATCH v2] IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file
directly https://bugzilla.tianocore.org/show_bug.cgi?id=4412
After shrinking the FSP (FV) component using FMMT, Image size in FSP info
header is not in sync with the FV length in FV header.
This enhancement helps to patch the FSP image size offset with correct length &
can be used to patch any offset directly on the FSP Component Fd .
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ted Kuo
Signed-off-by: Duggapu Chinni B
---
IntelFsp2Pkg/Tools/PatchFv.py | 14 -
.../Tools/UserManuals/PatchFvUserManual.md| 20 +++
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index eb130049b5..156c937abe 100644
--- a/IntelFsp2Pkg/Tools/PatchFv.py
+++ b/IntelFsp2Pkg/Tools/PatchFv.py
@@ -165,6 +165,17 @@ class Symbols:
if not os.path.isdir(fvDir): raise Exception ("'%s' is not
a valid directory!" % fvDir) +#+# if user provided fd name as a
input, skip rest of the flow to+# patch fd directly+# +
fdFile = os.path.join(fvDir,fvNames + ".fd")+if
os.path.exists(fdFile):+print("Tool identified Fd file as a input
to patch '%s'" %fdFile)+self.fdFile = fdFile+
self.fdSize = os.path.getsize(fdFile)+return 0+ # #
If the Guid.xref is not existing in fvDir, then raise an exception #@@
-848,8 +859,9 @@ class Symbols:
# Print out the usage # def Usage():-print ("PatchFv Version 0.50")+
print ("PatchFv Version 0.60") print ("Usage: \n\tPatchFv FvBuildDir
[FvFileBaseNames:]FdFileBaseNameToPatch \"Offset, Value\"")+print
("\tPatchFv FdFileDir FdFileName \"Offset, Value\"") def main(): #diff
--git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
index 5f1031e729..33bba38a3f 100644
--- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
+++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
@@ -1,6 +1,7 @@
#Name **_PatchFv.py_** - The python script that patches the firmware volumes
(**FV**) with in the flash device (**FD**) file post FSP build.+From version
0.60, script is capable of patching flash device (**FD**) directly. #Synopsis
@@ -10,6 +11,12 @@ PatchFv FvBuildDir [FvFileBaseNames:]FdFileBaseNameToPatch
["Offset, Value"]+
| ["Offset, Value, $Command"]+ | ["Offset, Value, $Command, @Comment"]+
```+```+PatchFv FdFileDir FdFileName ["Offset, Value"]++ | ["Offset, Value,
@Comment"]++ | ["Offset, Value, $Command"]++ | ["Offset, Value, $Command,
@Comment"]++``` #Description The **_PatchFv.py_** tool allows the developer to
fix up FD images to follow the@@ -102,6 +109,19 @@ ModuleGuid:Offset
< > Convert absolute address into an image offset (expr & FSP_SIZE)
```+From version 0.60 tool allows to pass flash device file path as Argument 1
and +flash device name as Argument 2 and rules for passing offset & value are
same+as explained in the previous sections.++Example usage:+Argument 1+```+
YouPlatformFspBinPkg\+```+Argument 2+```+ Fsp_Rebased_T+``` ###Special
Commands: Special commands must use the **$** symbol as a prefix to the command
itself.--
2.39.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#102990): https://edk2.groups.io/g/devel/message/102990
Mute This Topic: https://groups.io/mt/98258191/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.
Reviewed-by: Ted Kuo -Original Message- From: devel@edk2.groups.io On Behalf Of Chiu, Chasel Sent: Wednesday, March 29, 2023 11:44 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Zeng, Star ; Ni, Ray Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return. Cc: Nate DeSimone Cc: Star Zeng Cc: Ray Ni Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 18 ++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 16 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm index 2cff8b3643..b902d017ee 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -245,6 +245,19 @@ ASM_PFX(LoadMicrocodeDefault): cmpesp, 0jz ParamError + ;+ ; If microcode already loaded before this function, exit this function with SUCCESS.+ ;+ mov eax, 1+ cpuid+ mov ecx, MSR_IA32_BIOS_SIGN_ID+ rdmsr ; Get current microcode signature+ xor eax, eax+ test edx, edx+ jnz Exit2+++; skip loading Microcode if the MicrocodeCodeSize is zero; and report error if size is less than 2k; first check UPD header revision@@ -450,7 +463,7 @@ LoadCheck: ; Verify this microcode update is not already loadedcmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx- jeContinue+ jeDone ; if already one version microcode loaded, go to done LoadMicrocode:; EAX contains the linear address of the start of the Update Data@@ -465,9 +478,6 @@ LoadMicrocode: mov eax, 1cpuid -Continue:- jmp NextMicrocode- Done:mov eax, 1cpuiddiff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm index b32fa32a89..2a23c33c9b 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -141,6 +141,17 @@ ASM_PFX(LoadMicrocodeDefault): jz ParamErrormovrsp, rcx + ;+ ; If microcode already loaded before this function, exit this function with SUCCESS.+ ;+ mov eax, 1+ cpuid+ mov ecx, MSR_IA32_BIOS_SIGN_ID+ rdmsr ; Get current microcode signature+ xor rax, rax+ test edx, edx+ jnz Exit2+; skip loading Microcode if the MicrocodeCodeSize is zero; and report error if size is less than 2k; first check UPD header revision@@ -291,7 +302,7 @@ LoadCheck: ; Verify this microcode update is not already loadedcmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx- jeContinue+ jeDone ; if already one version microcode loaded, go to done LoadMicrocode:; EAX contains the linear address of the start of the Update Data@@ -306,9 +317,6 @@ LoadMicrocode: mov eax, 1cpuid -Continue:- jmp NextMicrocode- Done:mov eax, 1cpuid-- 2.35.0.windows.1 -=-=-=-=-=-= Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102124): https://edk2.groups.io/g/devel/message/102124 Mute This Topic: https://groups.io/mt/97931383/1862468 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [ted@intel.com] -=-=-=-=-=-= -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#102146): https://edk2.groups.io/g/devel/message/102146 Mute This Topic: https://groups.io/mt/97931383/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][PATCH v2 0/2] Supporting S3 in 64bit PEI
Only S3Resume.c is updated in patch v2 for the failure in UncrustifyCheck. Thanks, Ted -Original Message- From: devel@edk2.groups.io On Behalf Of Kuo, Ted Sent: Friday, December 16, 2022 8:46 PM To: devel@edk2.groups.io Subject: [edk2-devel][PATCH v2 0/2] Supporting S3 in 64bit PEI This patch set enables S3 in 64bit PEI. Ted Kuo (2): UefiCpuPkg: Supporting S3 in 64bit PEI MdeModulePkg: Supporting S3 in 64bit PEI .../BootScriptExecutorDxe/ScriptExecute.c | 21 ++-- .../BootScriptExecutorDxe/X64/SetIdtEntry.c | 4 +- .../Acpi/S3SaveStateDxe/AcpiS3ContextSave.c | 10 +- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 13 ++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 63 .../Universal/Acpi/S3Resume2Pei/S3Resume.c| 97 --- 7 files changed, 139 insertions(+), 70 deletions(-) -- 2.35.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97508): https://edk2.groups.io/g/devel/message/97508 Mute This Topic: https://groups.io/mt/95708648/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v2 2/2] MdeModulePkg: Supporting S3 in 64bit PEI
https://bugzilla.tianocore.org/show_bug.cgi?id=4195
Transfer from DXE to OS waking vector by calling SwitchStack() when
both are in the same execution mode.
Cc: Ray Ni
Cc: Zhiguang Liu
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Signed-off-by: Ted Kuo
---
.../BootScriptExecutorDxe/ScriptExecute.c | 21 +--
.../BootScriptExecutorDxe/X64/SetIdtEntry.c | 4 ++--
.../Acpi/S3SaveStateDxe/AcpiS3ContextSave.c | 10 -
3 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
index 82481aacd6..98c5abecf8 100644
--- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
+++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
@@ -4,7 +4,7 @@
This driver is dispatched by Dxe core and the driver will reload itself to
ACPI reserved memory
in the entry point. The functionality is to interpret and restore the S3
boot script
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -95,7 +95,7 @@ S3BootScriptExecutorEntryFunction (
PeiS3ResumeState->ReturnStatus = (UINT64)(UINTN)Status;
if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
//
- // X64 S3 Resume
+ // X64 DXE to IA32 PEI S3 Resume
//
DEBUG ((DEBUG_INFO, "Call AsmDisablePaging64() to return to S3 Resume in
PEI Phase\n"));
PeiS3ResumeState->AsmTransferControl =
(EFI_PHYSICAL_ADDRESS)(UINTN)AsmTransferControl32;
@@ -121,7 +121,7 @@ S3BootScriptExecutorEntryFunction (
);
} else {
//
- // IA32 S3 Resume
+ // IA32 DXE to IA32 PEI S3 Resume / X64 DXE to X64 PEI S3 Resume
//
DEBUG ((DEBUG_INFO, "Call SwitchStack() to return to S3 Resume in PEI
Phase\n"));
PeiS3ResumeState->AsmTransferControl =
(EFI_PHYSICAL_ADDRESS)(UINTN)AsmTransferControl;
@@ -156,8 +156,11 @@ S3BootScriptExecutorEntryFunction (
//
// X64 long mode waking vector
//
- DEBUG ((DEBUG_INFO, "Transfer to 64bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
- if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
+ DEBUG ((DEBUG_INFO, "Transfer from 64bit DXE to 64bit OS waking vector -
%x\r\n", (UINTN)Facs->XFirmwareWakingVector));
+ if (sizeof (UINTN) == sizeof (UINT64)) {
+//
+// 64bit DXE calls to 64bit OS S3 waking vector
+//
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)Facs->XFirmwareWakingVector,
NULL,
@@ -174,7 +177,10 @@ S3BootScriptExecutorEntryFunction (
// IA32 protected mode waking vector (Page disabled)
//
DEBUG ((DEBUG_INFO, "Transfer to 32bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
- if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
+ if (sizeof (UINTN) == sizeof (UINT64)) {
+//
+// 64bit DXE calls to 32bit OS S3 waking vector
+//
AsmDisablePaging64 (
0x10,
(UINT32)Facs->XFirmwareWakingVector,
@@ -183,6 +189,9 @@ S3BootScriptExecutorEntryFunction (
(UINT32)TempStackTop
);
} else {
+//
+// 32bit DXE calls to 32bit OS S3 waking vector
+//
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)Facs->XFirmwareWakingVector,
NULL,
diff --git
a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
index 6b44f50bac..7fc6cdcb4e 100644
--- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
+++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
@@ -3,7 +3,7 @@
Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
@@ -118,7 +118,7 @@ IsLongModeWakingVector (
((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0))
{
// Both BIOS and OS wants 64bit vector
- if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
+ if (sizeof (UINTN) == sizeof (UINT64)) {
return TRUE;
}
}
diff --git a/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
b/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
index 03f7a332d3..70bee7a67b 100644
--- a/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
+++ b/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
@@ -1,7 +1,7 @@
/** @file
This is the implementation to save ACPI S3 Context.
[edk2-devel][PATCH v2 1/2] UefiCpuPkg: Supporting S3 in 64bit PEI
https://bugzilla.tianocore.org/show_bug.cgi?id=4195
1.Updated the GDT table in VTF0 to align with the one in S3Resume2Pei.
By doing so can simplify the changes to enable S3 in 64bit PEI.
2.Use SwitchStack() between PEI and SMM in S3 resume path when both
are in the same execution mode.
3.Transfer from PEI to OS waking vector by calling SwitchStack() when
both are in the same execution mode.
4.Removed the debug assertion in S3Resume.c to support 64bit PEI.
Cc: Ray Ni
Cc: Zhiguang Liu
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Signed-off-by: Ted Kuo
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 13 ++-
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 +
.../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 63
.../Universal/Acpi/S3Resume2Pei/S3Resume.c| 97 ---
4 files changed, 117 insertions(+), 57 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 9b45c442c9..fb4a44eab6 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -1,7 +1,7 @@
/** @file
Code for Processor S3 restoration
-Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -783,7 +783,11 @@ SmmRestoreCpu (
SmmS3ResumeState = mSmmS3ResumeState;
ASSERT (SmmS3ResumeState != NULL);
- if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
+ //
+ // Setup 64bit IDT in 64bit SMM env when called from 32bit PEI.
+ // Note: 64bit PEI and 32bit DXE is not a supported combination.
+ //
+ if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) && (FeaturePcdGet
(PcdDxeIplSwitchToLongMode) == TRUE)) {
//
// Save the IA32 IDT Descriptor
//
@@ -846,9 +850,10 @@ SmmRestoreCpu (
DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n",
SmmS3ResumeState->ReturnStackPointer));
//
- // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
+ // If SMM is in 32-bit mode or PcdDxeIplSwitchToLongMode is FALSE, then use
SwitchStack() to resume PEI Phase.
+ // Note: 64bit PEI and 32bit DXE is not a supported combination.
//
- if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {
+ if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) || (FeaturePcdGet
(PcdDxeIplSwitchToLongMode) == FALSE)) {
DEBUG ((DEBUG_INFO, "Call SwitchStack() to return to S3 Resume in PEI
Phase\n"));
SwitchStack (
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
index deef00f9c6..b4b327f60c 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
@@ -124,6 +124,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode ## CONSUMES
[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber##
SOMETIMES_CONSUMES
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
index 0e79a3984b..f59fc6ead4 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
@@ -2,7 +2,7 @@
; @file
; Transition from 16 bit real mode into 32 bit flat protected mode
;
-; Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;--
@@ -92,7 +92,7 @@ ALIGN 16
GDT_BASE:
; null descriptor
-NULL_SELequ $-GDT_BASE
+NULL_SELequ $-GDT_BASE; Selector [0x0]
DW 0; limit 15:0
DW 0; base 15:0
DB 0; base 23:16
@@ -100,42 +100,67 @@ NULL_SELequ $-GDT_BASE
DB 0; limit 19:16, flags
DB 0; base 31:24
+; Spare segment descriptor
+SPARE1_SEL equ $-GDT_BASE; Selector [0x8]
+DW 0; limit 15:0
+DW 0; base 15:0
+DB 0; base 23:16
+DB 0; sys flag, dpl, type
+DB 0; limit 19:16, flags
+DB 0; base 31:24
+
+; linear code segment descriptor
+LINEAR_CODE_SEL equ $-GDT_BASE; Selector [0x10]
+DW 0x ; limit 15:0
+DW 0; base 15:0
+DB 0; base 23:16
+DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE)
; 09Bh
+DB
[edk2-devel][PATCH v2 0/2] Supporting S3 in 64bit PEI
This patch set enables S3 in 64bit PEI. Ted Kuo (2): UefiCpuPkg: Supporting S3 in 64bit PEI MdeModulePkg: Supporting S3 in 64bit PEI .../BootScriptExecutorDxe/ScriptExecute.c | 21 ++-- .../BootScriptExecutorDxe/X64/SetIdtEntry.c | 4 +- .../Acpi/S3SaveStateDxe/AcpiS3ContextSave.c | 10 +- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 13 ++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 63 .../Universal/Acpi/S3Resume2Pei/S3Resume.c| 97 --- 7 files changed, 139 insertions(+), 70 deletions(-) -- 2.35.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97505): https://edk2.groups.io/g/devel/message/97505 Mute This Topic: https://groups.io/mt/95708648/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v1 2/2] MdeModulePkg: Supporting S3 in 64bit PEI
https://bugzilla.tianocore.org/show_bug.cgi?id=4195
Transfer from DXE to OS waking vector by calling SwitchStack() when
both are in the same execution mode.
Cc: Ray Ni
Cc: Zhiguang Liu
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Signed-off-by: Ted Kuo
---
.../BootScriptExecutorDxe/ScriptExecute.c | 21 +--
.../BootScriptExecutorDxe/X64/SetIdtEntry.c | 4 ++--
.../Acpi/S3SaveStateDxe/AcpiS3ContextSave.c | 10 -
3 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
index 82481aacd6..98c5abecf8 100644
--- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
+++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
@@ -4,7 +4,7 @@
This driver is dispatched by Dxe core and the driver will reload itself to
ACPI reserved memory
in the entry point. The functionality is to interpret and restore the S3
boot script
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -95,7 +95,7 @@ S3BootScriptExecutorEntryFunction (
PeiS3ResumeState->ReturnStatus = (UINT64)(UINTN)Status;
if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
//
- // X64 S3 Resume
+ // X64 DXE to IA32 PEI S3 Resume
//
DEBUG ((DEBUG_INFO, "Call AsmDisablePaging64() to return to S3 Resume in
PEI Phase\n"));
PeiS3ResumeState->AsmTransferControl =
(EFI_PHYSICAL_ADDRESS)(UINTN)AsmTransferControl32;
@@ -121,7 +121,7 @@ S3BootScriptExecutorEntryFunction (
);
} else {
//
- // IA32 S3 Resume
+ // IA32 DXE to IA32 PEI S3 Resume / X64 DXE to X64 PEI S3 Resume
//
DEBUG ((DEBUG_INFO, "Call SwitchStack() to return to S3 Resume in PEI
Phase\n"));
PeiS3ResumeState->AsmTransferControl =
(EFI_PHYSICAL_ADDRESS)(UINTN)AsmTransferControl;
@@ -156,8 +156,11 @@ S3BootScriptExecutorEntryFunction (
//
// X64 long mode waking vector
//
- DEBUG ((DEBUG_INFO, "Transfer to 64bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
- if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
+ DEBUG ((DEBUG_INFO, "Transfer from 64bit DXE to 64bit OS waking vector -
%x\r\n", (UINTN)Facs->XFirmwareWakingVector));
+ if (sizeof (UINTN) == sizeof (UINT64)) {
+//
+// 64bit DXE calls to 64bit OS S3 waking vector
+//
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)Facs->XFirmwareWakingVector,
NULL,
@@ -174,7 +177,10 @@ S3BootScriptExecutorEntryFunction (
// IA32 protected mode waking vector (Page disabled)
//
DEBUG ((DEBUG_INFO, "Transfer to 32bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
- if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
+ if (sizeof (UINTN) == sizeof (UINT64)) {
+//
+// 64bit DXE calls to 32bit OS S3 waking vector
+//
AsmDisablePaging64 (
0x10,
(UINT32)Facs->XFirmwareWakingVector,
@@ -183,6 +189,9 @@ S3BootScriptExecutorEntryFunction (
(UINT32)TempStackTop
);
} else {
+//
+// 32bit DXE calls to 32bit OS S3 waking vector
+//
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)Facs->XFirmwareWakingVector,
NULL,
diff --git
a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
index 6b44f50bac..7fc6cdcb4e 100644
--- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
+++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
@@ -3,7 +3,7 @@
Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
@@ -118,7 +118,7 @@ IsLongModeWakingVector (
((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0))
{
// Both BIOS and OS wants 64bit vector
- if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
+ if (sizeof (UINTN) == sizeof (UINT64)) {
return TRUE;
}
}
diff --git a/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
b/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
index 03f7a332d3..70bee7a67b 100644
--- a/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
+++ b/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
@@ -1,7 +1,7 @@
/** @file
This is the implementation to save ACPI S3 Context.
[edk2-devel][PATCH v1 1/2] UefiCpuPkg: Supporting S3 in 64bit PEI
https://bugzilla.tianocore.org/show_bug.cgi?id=4195
1.Updated the GDT table in VTF0 to align with the one in S3Resume2Pei.
By doing so can simplify the changes to enable S3 in 64bit PEI.
2.Use SwitchStack() between PEI and SMM in S3 resume path when both
are in the same execution mode.
3.Transfer from PEI to OS waking vector by calling SwitchStack() when
both are in the same execution mode.
4.Removed the debug assertion in S3Resume.c to support 64bit PEI.
Cc: Ray Ni
Cc: Zhiguang Liu
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Signed-off-by: Ted Kuo
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 13 ++-
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 +
.../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 63
.../Universal/Acpi/S3Resume2Pei/S3Resume.c| 96 ---
4 files changed, 116 insertions(+), 57 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 9b45c442c9..fb4a44eab6 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -1,7 +1,7 @@
/** @file
Code for Processor S3 restoration
-Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -783,7 +783,11 @@ SmmRestoreCpu (
SmmS3ResumeState = mSmmS3ResumeState;
ASSERT (SmmS3ResumeState != NULL);
- if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
+ //
+ // Setup 64bit IDT in 64bit SMM env when called from 32bit PEI.
+ // Note: 64bit PEI and 32bit DXE is not a supported combination.
+ //
+ if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) && (FeaturePcdGet
(PcdDxeIplSwitchToLongMode) == TRUE)) {
//
// Save the IA32 IDT Descriptor
//
@@ -846,9 +850,10 @@ SmmRestoreCpu (
DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n",
SmmS3ResumeState->ReturnStackPointer));
//
- // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
+ // If SMM is in 32-bit mode or PcdDxeIplSwitchToLongMode is FALSE, then use
SwitchStack() to resume PEI Phase.
+ // Note: 64bit PEI and 32bit DXE is not a supported combination.
//
- if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {
+ if ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) || (FeaturePcdGet
(PcdDxeIplSwitchToLongMode) == FALSE)) {
DEBUG ((DEBUG_INFO, "Call SwitchStack() to return to S3 Resume in PEI
Phase\n"));
SwitchStack (
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
index deef00f9c6..b4b327f60c 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
@@ -124,6 +124,7 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode ## CONSUMES
[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber##
SOMETIMES_CONSUMES
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
index 0e79a3984b..f59fc6ead4 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
@@ -2,7 +2,7 @@
; @file
; Transition from 16 bit real mode into 32 bit flat protected mode
;
-; Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;--
@@ -92,7 +92,7 @@ ALIGN 16
GDT_BASE:
; null descriptor
-NULL_SELequ $-GDT_BASE
+NULL_SELequ $-GDT_BASE; Selector [0x0]
DW 0; limit 15:0
DW 0; base 15:0
DB 0; base 23:16
@@ -100,42 +100,67 @@ NULL_SELequ $-GDT_BASE
DB 0; limit 19:16, flags
DB 0; base 31:24
+; Spare segment descriptor
+SPARE1_SEL equ $-GDT_BASE; Selector [0x8]
+DW 0; limit 15:0
+DW 0; base 15:0
+DB 0; base 23:16
+DB 0; sys flag, dpl, type
+DB 0; limit 19:16, flags
+DB 0; base 31:24
+
+; linear code segment descriptor
+LINEAR_CODE_SEL equ $-GDT_BASE; Selector [0x10]
+DW 0x ; limit 15:0
+DW 0; base 15:0
+DB 0; base 23:16
+DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE)
; 09Bh
+DB
[edk2-devel][PATCH v1 0/2] Supporting S3 in 64bit PEI
This patch set enables S3 in 64bit PEI. Ted Kuo (2): UefiCpuPkg: Supporting S3 in 64bit PEI MdeModulePkg: Supporting S3 in 64bit PEI .../BootScriptExecutorDxe/ScriptExecute.c | 21 ++-- .../BootScriptExecutorDxe/X64/SetIdtEntry.c | 4 +- .../Acpi/S3SaveStateDxe/AcpiS3ContextSave.c | 10 +- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 13 ++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 1 + .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 63 .../Universal/Acpi/S3Resume2Pei/S3Resume.c| 96 --- 7 files changed, 138 insertions(+), 70 deletions(-) -- 2.35.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#97466): https://edk2.groups.io/g/devel/message/97466 Mute This Topic: https://groups.io/mt/95690179/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v1] IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-T
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4114 1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer respectively in TempRamInitApi in IA32 FspSecCoreT. 2.Correct inappropriate description in the return value of AsmGetFspInfoHeader. 3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in FspHeler.nasm. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Cc: Chinni B Duggapu Signed-off-by: Ted Kuo --- .../FspSecCore/Ia32/FspApiEntryT.nasm | 17 +++-- IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm | 4 +- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 74 ++- IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm| 4 +- 5 files changed, 55 insertions(+), 46 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm index 73821ad22a..2cff8b3643 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -594,37 +594,38 @@ ASM_PFX(TempRamInitApi): SAVE_EAX SAVE_EDX + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param + SAVE_ECX ; save UPD param to slot 3 in xmm6 + ; ; Sec Platform Init ; - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param CALL_MMX ASM_PFX(SecPlatformInit) cmp eax, 0 jnz TempRamInitExit ; Load microcode LOAD_ESP - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param + LOAD_ECX CALL_MMX ASM_PFX(LoadMicrocodeDefault) - SXMMN xmm6, 3, eax;Save microcode return status in ECX-SLOT 3 in xmm6. + SAVE_UCODE_STATUS ; Save microcode return status in slot 1 in xmm5. ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot. ; Call Sec CAR Init LOAD_ESP - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param + LOAD_ECX CALL_MMX ASM_PFX(SecCarInit) cmp eax, 0 jnz TempRamInitExit LOAD_ESP - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param - mov edi, ecx ; Save UPD param to EDI for later code use + LOAD_ECX + mov edi, ecx; Save UPD param to EDI for later code use CALL_MMX ASM_PFX(EstablishStackFsp) cmp eax, 0 jnz TempRamInitExit - LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6. - SXMMN xmm6, 3, edi ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 in xmm6. + LOAD_UCODE_STATUS ; Restore microcode status if no CAR init error from slot 1 in xmm5. TempRamInitExit: mov bl, al ; save al data in bl diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm index e3e1945473..3c63f6eea5 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm @@ -7,6 +7,8 @@ SECTION .text +FSP_HEADER_IMGBASE_OFFSETEQU 1Ch + global ASM_PFX(FspInfoHeaderRelativeOff) ASM_PFX(FspInfoHeaderRelativeOff): DD0x12345678 ; This value must be patched by the build script @@ -14,7 +16,7 @@ ASM_PFX(FspInfoHeaderRelativeOff): global ASM_PFX(AsmGetFspBaseAddress) ASM_PFX(AsmGetFspBaseAddress): call ASM_PFX(AsmGetFspInfoHeader) - add eax, 0x1C + add eax, FSP_HEADER_IMGBASE_OFFSET mov eax, dword [eax] ret diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 4c321cbece..a222f2e376 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -1,6 +1,6 @@ ;-- ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. +; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved. ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -16,21 +16,21 @@ ; ; Define SSE macros using SSE 4.1 instructions ; args 1:XMM, 2:IDX, 3:REG -%macro SXMMN 3 +%macro SXMMN3 pinsrd %1, %3, (%2 & 3) %endmacro ; ;args 1:XMM, 2:REG, 3:IDX ; -%macro LXMMN 3 +%macro LXMMN3 pextrd %2, %1, (%3 & 3) %endmacro %else ; ; Define SSE macros using SSE 2 instructions ; args 1:XMM, 2:IDX, 3:REG -%macro SXMMN 3 +%macro SXMMN3 pinsrw %1, %3, (%2 & 3) * 2 ror %3, 16 pinsrw %1, %3, (%2 & 3) * 2 + 1 @@ -38,19 +38,19 @@ %endmacro ; -;args 1:XMM, 2:REG, 3:IDX +;args 1:XMM, 2:REG, 3:IDX ; %macro LXMMN3 - pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh) + pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh) movd%2,
[edk2-devel][PATCH v1] IntelFsp2Pkg: Adding FspHelperLib
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4128
Adding FspHelperLib for platform code to consume. There will be
another patch raised later for FspSecCore to consume FspHelperLib.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Amy Chan
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecFsp.h | 25 +-
IntelFsp2Pkg/Include/Library/FspHelperLib.h | 35 +
IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +
.../BaseFspHelperLib/BaseFspHelperLib.inf | 50 +++
.../BaseFspHelperLib/Ia32/FspHelper.nasm | 35 +
.../BaseFspHelperLib/X64/FspHelper.nasm | 34 +
6 files changed, 157 insertions(+), 24 deletions(-)
create mode 100644 IntelFsp2Pkg/Include/Library/FspHelperLib.h
create mode 100644 IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
create mode 100644 IntelFsp2Pkg/Library/BaseFspHelperLib/Ia32/FspHelper.nasm
create mode 100644 IntelFsp2Pkg/Library/BaseFspHelperLib/X64/FspHelper.nasm
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/SecFsp.h
index d7a5976c12..f12769890f 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.h
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#define FSP_MCUD_SIGNATURE SIGNATURE_32 ('M', 'C', 'U', 'D')
#define FSP_PER0_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', '0')
@@ -64,28 +65,4 @@ FspDataPointerFixUp (
IN UINTN OffsetGap
);
-/**
- This interface returns the base address of FSP binary.
-
- @return FSP binary base address.
-
-**/
-UINTN
-EFIAPI
-AsmGetFspBaseAddress (
- VOID
- );
-
-/**
- This interface gets FspInfoHeader pointer
-
- @return FSP binary base address.
-
-**/
-UINTN
-EFIAPI
-AsmGetFspInfoHeader (
- VOID
- );
-
#endif
diff --git a/IntelFsp2Pkg/Include/Library/FspHelperLib.h
b/IntelFsp2Pkg/Include/Library/FspHelperLib.h
new file mode 100644
index 00..84b74fa7aa
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Library/FspHelperLib.h
@@ -0,0 +1,35 @@
+/** @file
+ Header file for FSP Helper Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FSP_HELPER_LIB_H_
+#define _FSP_HELPER_LIB_H_
+
+/**
+ This interface returns the base address of FSP binary.
+
+ @return FSP binary base address.
+
+**/
+UINTN
+EFIAPI
+AsmGetFspBaseAddress (
+ VOID
+ );
+
+/**
+ This interface gets FspInfoHeader pointer
+
+ @return FSP info header.
+**/
+UINTN
+EFIAPI
+AsmGetFspInfoHeader (
+ VOID
+ );
+
+#endif // _FSP_HELPER_LIB_H_
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc
index 0713f0028d..09893d70e8 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc
@@ -46,6 +46,7 @@
FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
FspSecPlatformLib|IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf
FspMultiPhaseLib|IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf
+ FspHelperLib|IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
[LibraryClasses.common.PEIM]
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
@@ -66,6 +67,7 @@
IntelFsp2Pkg/Library/BaseDebugDeviceLibNull/BaseDebugDeviceLibNull.inf
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf
IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf
+ IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
diff --git a/IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
b/IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
new file mode 100644
index 00..318ad65330
--- /dev/null
+++ b/IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf
@@ -0,0 +1,50 @@
+## @file
+# FSP Helper Library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+
+
+[Defines]
+ INF_VERSION= 0x00010005
+ BASE_NAME = FspHelperLib
+ FILE_GUID = 65746991-8a41-4b89-b0f4-eb4e24b5b471
+ MODULE_TYPE= BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FspHelperLib
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.
Reviewed-by: Ted Kuo
-Original Message-
From: Chiu, Chasel
Sent: Friday, November 4, 2022 1:02 AM
To: Kuo, Ted ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Zeng, Star
Subject: RE: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD
as NULL.
Hi Ted,
Please see my reply below inline.
Thanks,
Chasel
> -Original Message-
> From: Kuo, Ted
> Sent: Wednesday, November 2, 2022 7:32 PM
> To: devel@edk2.groups.io; Chiu, Chasel
> Cc: Desimone, Nathaniel L ; Zeng, Star
>
> Subject: RE: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support
> input UPD as NULL.
>
> Hi Chasel,
>
> I have few comments. Please find [Ted] inline.
>
> Thanks,
> Ted
>
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Chiu,
> Chasel
> Sent: Wednesday, November 2, 2022 1:46 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star
> Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support
> input UPD as NULL.
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114
>
> FSP specification supports input UPD as NULL cases which FSP will use
> built- in UPD region instead.
> FSP should not return INVALID_PARAMETER in such cases.
>
> In FSP-T entry point case, the valid FSP-T UPD region pointer will be
> passed to platform FSP code to consume.
> In FSP-M and FSP-S cases, valid UPD pointer will be decided when
> updating corresponding pointer field in FspGlobalData.
>
> Cc: Nate DeSimone
> Cc: Star Zeng
> Signed-off-by: Chasel Chiu
> ---
> IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 12 ++--
> IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73
> +++--
>
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 40
> ++--
> 3 files changed, 91 insertions(+), 34 deletions(-)
>
> diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> index a44fbf2a50..5f59938518 100644
> --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> @@ -44,6 +44,8 @@ FspApiCallingCheck (
> //
> if (((UINTN)FspData != MAX_ADDRESS) && ((UINTN)FspData !=
> MAX_UINT32)) {
>Status = EFI_UNSUPPORTED;
> +} else if (ApiParam == NULL) {
> + Status = EFI_SUCCESS;
> } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {
>Status = EFI_INVALID_PARAMETER;
> }
> @@ -67,9 +69,13 @@ FspApiCallingCheck (
> } else {
>if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
> Status = EFI_UNSUPPORTED;
> - } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex,
> ApiParam))) {
> -Status = EFI_INVALID_PARAMETER;
>} else if (ApiIdx == FspSiliconInitApiIndex) {
> +if (ApiParam == NULL) {
> + Status = EFI_SUCCESS;
> +} else if (EFI_ERROR (FspUpdSignatureCheck
> + (FspSiliconInitApiIndex,
> ApiParam))) {
> + Status = EFI_INVALID_PARAMETER;
> +}
> +
> //
> // Reset MultiPhase NumberOfPhases to zero
> //
> @@ -89,6 +95,8 @@ FspApiCallingCheck (
> } else {
>if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
> Status = EFI_UNSUPPORTED;
> + } else if (ApiParam == NULL) {
> +Status = EFI_SUCCESS;
>} else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex,
> ApiParam))) {
> Status = EFI_INVALID_PARAMETER;
>}
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> index 61030a843b..73821ad22a 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
> @@ -21,7 +21,7 @@ extern ASM_PFX(PcdGet32
> (PcdFspReservedBufferSize))
> ; Following functions will be provided in PlatformSecLib ; extern
> ASM_PFX(AsmGetFspBaseAddress) -extern
> ASM_PFX(AsmGetFspInfoHeader)
> +extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
> ;extern ASM_PFX(LoadMicrocode); @todo: needs a weak
> implementation
> extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation
> extern ASM_PFX(SecCarInit)
> @@ -160,6 +160,47 @@ endstruc
> RET_ESI_EXT mm7
> %endmacro
>
> +%macro CALL_EDI 1
> +
> + mov edi, %%ReturnAddress
> + jmp %1
> +%%ReturnAddress:
> +
> +%endmacro
> +
> +%macro CALL_EBP 1
> + mov ebp, %%ReturnAddress
> + jmp %1
> +%%ReturnAddress:
> +%endmacro
> +
> +%macro RET_EBP 0
> + jmp ebp
Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL.
Hi Chasel,
I have few comments. Please find [Ted] inline.
Thanks,
Ted
-Original Message-
From: devel@edk2.groups.io On Behalf Of Chiu, Chasel
Sent: Wednesday, November 2, 2022 1:46 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L
; Zeng, Star
Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as
NULL.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114
FSP specification supports input UPD as NULL cases which FSP will
use built-in UPD region instead.
FSP should not return INVALID_PARAMETER in such cases.
In FSP-T entry point case, the valid FSP-T UPD region pointer will be
passed to platform FSP code to consume.
In FSP-M and FSP-S cases, valid UPD pointer will be decided when
updating corresponding pointer field in FspGlobalData.
Cc: Nate DeSimone
Cc: Star Zeng
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 12 ++--
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73
+++--
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 40
++--
3 files changed, 91 insertions(+), 34 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index a44fbf2a50..5f59938518 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -44,6 +44,8 @@ FspApiCallingCheck (
//
if (((UINTN)FspData != MAX_ADDRESS) && ((UINTN)FspData != MAX_UINT32)) {
Status = EFI_UNSUPPORTED;
+} else if (ApiParam == NULL) {
+ Status = EFI_SUCCESS;
} else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {
Status = EFI_INVALID_PARAMETER;
}
@@ -67,9 +69,13 @@ FspApiCallingCheck (
} else {
if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
Status = EFI_UNSUPPORTED;
- } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex,
ApiParam))) {
-Status = EFI_INVALID_PARAMETER;
} else if (ApiIdx == FspSiliconInitApiIndex) {
+if (ApiParam == NULL) {
+ Status = EFI_SUCCESS;
+} else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex,
ApiParam))) {
+ Status = EFI_INVALID_PARAMETER;
+}
+
//
// Reset MultiPhase NumberOfPhases to zero
//
@@ -89,6 +95,8 @@ FspApiCallingCheck (
} else {
if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
Status = EFI_UNSUPPORTED;
+ } else if (ApiParam == NULL) {
+Status = EFI_SUCCESS;
} else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex,
ApiParam))) {
Status = EFI_INVALID_PARAMETER;
}
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 61030a843b..73821ad22a 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -21,7 +21,7 @@ extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
; Following functions will be provided in PlatformSecLib
;
extern ASM_PFX(AsmGetFspBaseAddress)
-extern ASM_PFX(AsmGetFspInfoHeader)
+extern ASM_PFX(AsmGetFspInfoHeaderNoStack)
;extern ASM_PFX(LoadMicrocode); @todo: needs a weak implementation
extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation
extern ASM_PFX(SecCarInit)
@@ -160,6 +160,47 @@ endstruc
RET_ESI_EXT mm7
%endmacro
+%macro CALL_EDI 1
+
+ mov edi, %%ReturnAddress
+ jmp %1
+%%ReturnAddress:
+
+%endmacro
+
+%macro CALL_EBP 1
+ mov ebp, %%ReturnAddress
+ jmp %1
+%%ReturnAddress:
+%endmacro
+
+%macro RET_EBP 0
+ jmp ebp ; restore EIP from EBP
+%endmacro
+
+;
+; Load UPD region pointer in ECX
+;
+global ASM_PFX(LoadUpdPointerToECX)
+ASM_PFX(LoadUpdPointerToECX):
+ ;
+ ; esp + 4 is input UPD parameter
+ ; If esp + 4 is NULL the default UPD should be used
+ ; ecx will be the UPD region that should be used
+ ;
+ mov ecx, dword [esp + 4]
+ cmp ecx, 0
+ jnz ParamValid
+
+ ;
+ ; Fall back to default UPD region
+ ;
+ CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack)
+ mov ecx, DWORD [eax + 01Ch] ; Read FsptImageBaseAddress
+ add ecx, DWORD [eax + 024h] ; Get Cfg Region base address =
FsptImageBaseAddress + CfgRegionOffset
+ParamValid:
+ RET_EBP
+
;
; @todo: The strong/weak implementation does not work.
;This needs to be reviewed later.
@@ -187,10 +228,9 @@ endstruc
global ASM_PFX(LoadMicrocodeDefault)
ASM_PFX(LoadMicrocodeDefault):
; Inputs:
- ; esp -> LoadMicrocodeParams pointer
+ ; ecx -> UPD region contains LoadMicrocodeParams pointer
; Register Usage:
- ; esp Preserved
- ; All others destroyed
+ ; All are destroyed
; Assumptions:
; No memory available, stack is hard-coded and used for return address
; Executed by SBSP and NBSP
@@
[edk2-devel][PATCH v2] IntelFsp2Pkg: NvsBufferPtr is missing in Fsp24ApiEntryM.nasm
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4063 Added NvsBufferPtr to FSPM_UPD_COMMON_FSP24 in Fsp24ApiEntryM.nasm to align with FSP 2.4 SPEC. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Cc: Chinni B Duggapu Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 3 ++- IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm index 997b9c0bff..15f8ecea83 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm @@ -40,12 +40,13 @@ struc FSPM_UPD_COMMON_FSP24 .Revision: resb 1 .Reserved: resb 3 .Length resd 1 +.NvsBufferPtr resq 1 .StackBase: resq 1 .StackSize: resq 1 .BootLoaderTolumSize: resd 1 .BootMode: resd 1 .FspEventHandlerresq 1 -.Reserved1: resb 24 +.Reserved1: resb 16 ; } .size: endstruc diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm index 8880721f29..a3b38e4585 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm @@ -22,12 +22,13 @@ struc FSPM_UPD_COMMON_FSP24 .Revision: resb 1 .Reserved: resb 3 .Length resd 1 +.NvsBufferPtr resq 1 .StackBase: resq 1 .StackSize: resq 1 .BootLoaderTolumSize: resd 1 .BootMode: resd 1 .FspEventHandlerresq 1 -.Reserved1: resb 24 +.Reserved1: resb 16 ; } .size: endstruc -- 2.35.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93832): https://edk2.groups.io/g/devel/message/93832 Mute This Topic: https://groups.io/mt/93699989/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v1] IntelFsp2Pkg: NvsBufferPtr is missing in Fsp24ApiEntryM.nasm
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4063 Added NvsBufferPtr to FSPM_UPD_COMMON_FSP24 in Fsp24ApiEntryM.nasm to align with FSP 2.4 SPEC. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Cc: Chinni B Duggapu Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm index 8880721f29..a3b38e4585 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm @@ -22,12 +22,13 @@ struc FSPM_UPD_COMMON_FSP24 .Revision: resb 1 .Reserved: resb 3 .Length resd 1 +.NvsBufferPtr resq 1 .StackBase: resq 1 .StackSize: resq 1 .BootLoaderTolumSize: resd 1 .BootMode: resd 1 .FspEventHandlerresq 1 -.Reserved1: resb 24 +.Reserved1: resb 16 ; } .size: endstruc -- 2.35.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93830): https://edk2.groups.io/g/devel/message/93830 Mute This Topic: https://groups.io/mt/93699556/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v1] BaseTools: 64bit FSP FV map file cannot be created correctly
https://bugzilla.tianocore.org/show_bug.cgi?id=4035
64bit FSP FV map file cannot be created correctly when using CLANG
compiler. When compiling 64bit FSP with CLANG, there is no prefix
symbol '_' added to function name. Hence FSP FV map file cannot be
created properly. Updated the if condition for CLANG in GenFv to
get the issue fixed.
Cc: Bob Feng
Cc: Liming Gao
Cc: Yuwei Chen
Cc: Lee Hamel
Signed-off-by: Ted Kuo
---
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index d650a527a5..d28ac8f6eb 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -1004,7 +1004,7 @@ Returns:
if (IsUseClang) {
sscanf (Line, "%llx %s %s %s", , KeyWord, KeyWord2,
FunctionTypeName);
FunctionAddress = (UINT64) TempLongAddress;
-if (FunctionTypeName [0] == '_' ) {
+if (FunctionTypeName [0] != '/' && FunctionTypeName [0] != '.' &&
FunctionTypeName [1] != ':') {
fprintf (FvMapFile, " 0x%010llx", (unsigned long long)
(ImageBaseAddress + FunctionAddress - LinkTimeBaseAddress));
fprintf (FvMapFile, "%s\n", FunctionTypeName);
}
--
2.35.3.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#92908): https://edk2.groups.io/g/devel/message/92908
Mute This Topic: https://groups.io/mt/93322647/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v2 2/2] IntelFsp2Pkg: Update SEC_IDT_TABLE struct
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957
The reserved IDT table size in SecCore is too small for X64. Changed the type
of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have
sufficient size reserved in IdtTable for X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecFsp.c | 9 +
IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +-
IntelFsp2Pkg/FspSecCore/SecMain.c | 16
IntelFsp2Pkg/FspSecCore/SecMain.h | 4 ++--
4 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 7fde6e7f41..e9b4091b20 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -16,19 +16,20 @@
@return FSP specific IDT gate descriptor.
**/
-UINT64
+IA32_IDT_GATE_DESCRIPTOR
FspGetExceptionHandler (
IN UINT64 IdtEntryTemplate
)
{
UINT32Entry;
- UINT64ExceptionHandler;
+ IA32_IDT_GATE_DESCRIPTOR ExceptionHandler;
IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor;
FSP_INFO_HEADER *FspInfoHeader;
+ ZeroMem ((VOID *), sizeof (IA32_IDT_GATE_DESCRIPTOR));
FspInfoHeader = (FSP_INFO_HEADER
*)(UINTN)AsmGetFspInfoHeader ();
- ExceptionHandler = IdtEntryTemplate;
- IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR
*)
+ *(UINT64 *) = IdtEntryTemplate;
+ IdtGateDescriptor =
Entry = (IdtGateDescriptor->Bits.OffsetHigh <<
16) | IdtGateDescriptor->Bits.OffsetLow;
Entry = FspInfoHeader->ImageBase +
FspInfoHeader->ImageSize - (~Entry + 1);
IdtGateDescriptor->Bits.OffsetHigh = (UINT16)(Entry >> 16);
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/SecFsp.h
index 41931a33dd..e84528b378 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.h
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h
@@ -30,7 +30,7 @@
@return FSP specific IDT gate descriptor.
**/
-UINT64
+IA32_IDT_GATE_DESCRIPTOR
FspGetExceptionHandler (
IN UINT64 IdtEntryTemplate
);
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index 8effe2225c..94ea3865b4 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -58,13 +58,13 @@ SecStartup (
IN UINT32 ApiIdx
)
{
- EFI_SEC_PEI_HAND_OFF SecCoreData;
- IA32_DESCRIPTOR IdtDescriptor;
- SEC_IDT_TABLE IdtTableInStack;
- UINT32Index;
- FSP_GLOBAL_DATA PeiFspData;
- UINT64ExceptionHandler;
- UINTN IdtSize;
+ EFI_SEC_PEI_HAND_OFF SecCoreData;
+ IA32_DESCRIPTOR IdtDescriptor;
+ SEC_IDT_TABLE IdtTableInStack;
+ UINT32Index;
+ FSP_GLOBAL_DATA PeiFspData;
+ IA32_IDT_GATE_DESCRIPTOR ExceptionHandler;
+ UINTN IdtSize;
//
// Process all libraries constructor function linked to SecCore.
@@ -119,7 +119,7 @@ SecStartup (
if (IdtDescriptor.Base == 0) {
ExceptionHandler = FspGetExceptionHandler (mIdtEntryTemplate);
for (Index = 0; Index < FixedPcdGet8 (PcdFspMaxInterruptSupported);
Index++) {
- CopyMem ((VOID *)[Index], (VOID
*), sizeof (UINT64));
+ CopyMem ((VOID *)[Index], (VOID
*), sizeof (IA32_IDT_GATE_DESCRIPTOR));
}
IdtSize = sizeof (IdtTableInStack.IdtTable);
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h
b/IntelFsp2Pkg/FspSecCore/SecMain.h
index 7c2642ad48..1fe7c15aeb 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.h
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.h
@@ -38,8 +38,8 @@ typedef struct _SEC_IDT_TABLE {
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to
store
// EFI_PEI_SERVICES**
//
- UINT64PeiService;
- UINT64IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];
+ UINT64PeiService;
+ IA32_IDT_GATE_DESCRIPTOR IdtTable[FixedPcdGet8
(PcdFspMaxInterruptSupported)];
} SEC_IDT_TABLE;
/**
--
2.35.3.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#91235): https://edk2.groups.io/g/devel/message/91235
Mute This Topic: https://groups.io/mt/92329473/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v2 0/2] Update SEC_IDT_TABLE struct to reserve sufficient size in IdtTable for both IA32 and X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957 The reserved IDT table size in SecCore is too small for X64. Changed the type of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have sufficient size reserved in IdtTable for X64. Ted Kuo (2): UefiCpuPkg: Update SEC_IDT_TABLE struct IntelFsp2Pkg: Update SEC_IDT_TABLE struct IntelFsp2Pkg/FspSecCore/SecFsp.c | 9 + IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- IntelFsp2Pkg/FspSecCore/SecMain.c | 16 IntelFsp2Pkg/FspSecCore/SecMain.h | 4 ++-- UefiCpuPkg/SecCore/SecMain.c | 1 + UefiCpuPkg/SecCore/SecMain.h | 4 ++-- 6 files changed, 19 insertions(+), 17 deletions(-) -- 2.35.3.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#91233): https://edk2.groups.io/g/devel/message/91233 Mute This Topic: https://groups.io/mt/92329471/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v2 1/2] UefiCpuPkg: Update SEC_IDT_TABLE struct
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957
The reserved IDT table size in SecCore is too small for X64. Changed the type
of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have
sufficient size reserved in IdtTable for X64. dff
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Ray Ni
Cc: Ashraf Ali S
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Signed-off-by: Ted Kuo
---
UefiCpuPkg/SecCore/SecMain.c | 1 +
UefiCpuPkg/SecCore/SecMain.h | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index 4edf0ce972..fe03d8019a 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -211,6 +211,7 @@ SecStartup (
IdtTableInStack.PeiService = 0;
for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index++) {
+ZeroMem ((VOID *)[Index], sizeof
(IA32_IDT_GATE_DESCRIPTOR));
CopyMem ((VOID *)[Index], (VOID
*), sizeof (UINT64));
}
diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h
index 189fcf9326..1be57c2248 100644
--- a/UefiCpuPkg/SecCore/SecMain.h
+++ b/UefiCpuPkg/SecCore/SecMain.h
@@ -43,8 +43,8 @@ typedef struct _SEC_IDT_TABLE {
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to
store
// EFI_PEI_SERVICES**
//
- UINT64PeiService;
- UINT64IdtTable[SEC_IDT_ENTRY_COUNT];
+ UINT64PeiService;
+ IA32_IDT_GATE_DESCRIPTOR IdtTable[SEC_IDT_ENTRY_COUNT];
} SEC_IDT_TABLE;
/**
--
2.35.3.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#91234): https://edk2.groups.io/g/devel/message/91234
Mute This Topic: https://groups.io/mt/92329472/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v1 1/2] UefiCpuPkg: Update SEC_IDT_TABLE struct
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957
The reserved IDT table size in SecCore is too small for X64. Changed the type
of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have
sufficient size reserved in IdtTable for X64. dff
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Ray Ni
Cc: Ashraf Ali S
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Signed-off-by: Ted Kuo
---
UefiCpuPkg/SecCore/SecMain.c | 1 +
UefiCpuPkg/SecCore/SecMain.h | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index a7526be9dd..d7140c2db3 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -202,6 +202,7 @@ SecStartup (
IdtTableInStack.PeiService = 0;
for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index++) {
+ZeroMem ((VOID *)[Index], sizeof
(IA32_IDT_GATE_DESCRIPTOR));
CopyMem ((VOID *)[Index], (VOID
*), sizeof (UINT64));
}
diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h
index 189fcf9326..1be57c2248 100644
--- a/UefiCpuPkg/SecCore/SecMain.h
+++ b/UefiCpuPkg/SecCore/SecMain.h
@@ -43,8 +43,8 @@ typedef struct _SEC_IDT_TABLE {
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to
store
// EFI_PEI_SERVICES**
//
- UINT64PeiService;
- UINT64IdtTable[SEC_IDT_ENTRY_COUNT];
+ UINT64PeiService;
+ IA32_IDT_GATE_DESCRIPTOR IdtTable[SEC_IDT_ENTRY_COUNT];
} SEC_IDT_TABLE;
/**
--
2.26.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#90785): https://edk2.groups.io/g/devel/message/90785
Mute This Topic: https://groups.io/mt/92015981/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v1 2/2] IntelFsp2Pkg: Update SEC_IDT_TABLE struct
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957
The reserved IDT table size in SecCore is too small for X64. Changed the type
of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have
sufficient size reserved in IdtTable for X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecMain.c | 19 ++-
IntelFsp2Pkg/FspSecCore/SecMain.h | 4 ++--
2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index 8effe2225c..6a23275afa 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -58,13 +58,13 @@ SecStartup (
IN UINT32 ApiIdx
)
{
- EFI_SEC_PEI_HAND_OFF SecCoreData;
- IA32_DESCRIPTOR IdtDescriptor;
- SEC_IDT_TABLE IdtTableInStack;
- UINT32Index;
- FSP_GLOBAL_DATA PeiFspData;
- UINT64ExceptionHandler;
- UINTN IdtSize;
+ EFI_SEC_PEI_HAND_OFF SecCoreData;
+ IA32_DESCRIPTOR IdtDescriptor;
+ SEC_IDT_TABLE IdtTableInStack;
+ UINT32Index;
+ FSP_GLOBAL_DATA PeiFspData;
+ IA32_IDT_GATE_DESCRIPTOR ExceptionHandler;
+ UINTN IdtSize;
//
// Process all libraries constructor function linked to SecCore.
@@ -117,9 +117,10 @@ SecStartup (
IdtTableInStack.PeiService = 0;
AsmReadIdtr ();
if (IdtDescriptor.Base == 0) {
-ExceptionHandler = FspGetExceptionHandler (mIdtEntryTemplate);
+ZeroMem ((VOID *), sizeof (IA32_IDT_GATE_DESCRIPTOR));
+*((UINT64 *) ) = FspGetExceptionHandler
(mIdtEntryTemplate);
for (Index = 0; Index < FixedPcdGet8 (PcdFspMaxInterruptSupported);
Index++) {
- CopyMem ((VOID *)[Index], (VOID
*), sizeof (UINT64));
+ CopyMem ((VOID *)[Index], (VOID
*), sizeof (IA32_IDT_GATE_DESCRIPTOR));
}
IdtSize = sizeof (IdtTableInStack.IdtTable);
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.h
b/IntelFsp2Pkg/FspSecCore/SecMain.h
index 7c2642ad48..1fe7c15aeb 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.h
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.h
@@ -38,8 +38,8 @@ typedef struct _SEC_IDT_TABLE {
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to
store
// EFI_PEI_SERVICES**
//
- UINT64PeiService;
- UINT64IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];
+ UINT64PeiService;
+ IA32_IDT_GATE_DESCRIPTOR IdtTable[FixedPcdGet8
(PcdFspMaxInterruptSupported)];
} SEC_IDT_TABLE;
/**
--
2.26.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#90786): https://edk2.groups.io/g/devel/message/90786
Mute This Topic: https://groups.io/mt/92015982/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v1 0/2] Update SEC_IDT_TABLE struct to reserve sufficient size in IdtTable for both IA32 and X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957 The reserved IDT table size in SecCore is too small for X64. Changed the type of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have sufficient size reserved in IdtTable for X64. Ted Kuo (2): UefiCpuPkg: Update SEC_IDT_TABLE struct IntelFsp2Pkg: Update SEC_IDT_TABLE struct IntelFsp2Pkg/FspSecCore/SecMain.c | 19 ++- IntelFsp2Pkg/FspSecCore/SecMain.h | 4 ++-- UefiCpuPkg/SecCore/SecMain.c | 1 + UefiCpuPkg/SecCore/SecMain.h | 4 ++-- 4 files changed, 15 insertions(+), 13 deletions(-) -- 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90784): https://edk2.groups.io/g/devel/message/90784 Mute This Topic: https://groups.io/mt/92015980/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH v5 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention
Looks good to me except one typo. Please see my inline comment. Thanks, Ted -Original Message- From: devel@edk2.groups.io On Behalf Of Chiu, Chasel Sent: Wednesday, May 18, 2022 9:41 AM To: Duggapu, Chinni B ; devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Zeng, Star ; S, Ashraf Ali Subject: Re: [edk2-devel] [PATCH v5 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention Thanks Chinni! Reviewed-by: Chasel Chiu > -Original Message- > From: Duggapu, Chinni B > Sent: Tuesday, May 17, 2022 4:44 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star ; S, > Ashraf Ali > Subject: [PATCH v5 2/2] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call > must follow X64 Calling Convention > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 > Pass Input parameters using RCX. > > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Star Zeng > Cc: Ashraf Ali S > Signed-off-by: cbduggap > --- > .../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git > a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > index dbbf63336e..065d80d0e2 100644 > --- > a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > +++ > b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64 > /SecEntry.nasm > @@ -130,6 +130,9 @@ FspHeaderFound: >mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] > >add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] > > > > + ; Pass Fsp T Udp pointer as Input parameter [Ted]: It should be Upd not Udp. > > + mov rcx, ASM_PFX(FsptUpdDataPtr) > > + > >; Setup the hardcode stack > >mov rsp, TempRamInitStack > > > > @@ -167,5 +170,4 @@ FspApiFailed: > align 10h > > TempRamInitStack: > > DQ TempRamInitDone > > -DQ ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams > > > > -- > 2.36.0.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89874): https://edk2.groups.io/g/devel/message/89874 Mute This Topic: https://groups.io/mt/91159382/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v5 8/8] IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added SecFspWrapperPlatformSecLibSample support for X64.
2.Adopted FSPT_ARCH2_UPD in SecFspWrapperPlatformSecLibSample.
3.Moved Fsp.h up one level to be shared across IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../{Ia32 => }/Fsp.h | 0
.../Ia32/Stack.nasm| 8 +-
.../SecFspWrapperPlatformSecLibSample.inf | 9 +-
.../SecRamInitData.c | 24 +--
.../X64/PeiCoreEntry.nasm | 149 ++
.../X64/SecEntry.nasm | 171 +
.../X64/Stack.nasm | 73 +
7 files changed, 418 insertions(+), 16 deletions(-)
rename IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/{Ia32 =>
}/Fsp.h (100%)
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/PeiCoreEntry.nasm
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/Stack.nasm
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Fsp.h
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.h
similarity index 100%
rename from
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Fsp.h
rename to IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.h
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
index d7394cf286..eb5b120816 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
@@ -1,6 +1,6 @@
;--
;
-; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -22,7 +22,7 @@
global ASM_PFX(SecSwitchStack)
ASM_PFX(SecSwitchStack):
;
-; Save three register: eax, ebx, ecx
+; Save four register: eax, ebx, ecx, edx
;
push eax
push ebx
@@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack):
mov dword [eax + 12], edx
mov edx, dword [esp + 16]; Update this function's return address
into permanent memory
mov dword [eax + 16], edx
-mov esp, eax ; From now, esp is pointed to permanent
memory
+mov esp, eax ; From now, esp is pointed to permanent
memory
;
; Fixup the ebp point to permanent memory
@@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack):
mov eax, ebp
sub eax, ebx
add eax, ecx
-mov ebp, eax; From now, ebp is pointed to permanent
memory
+mov ebp, eax ; From now, ebp is pointed to permanent
memory
pop edx
pop ecx
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
index 027b127724..28a8602b03 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
@@ -1,7 +1,7 @@
## @file
# Sample to provide FSP wrapper platform sec related function.
#
-# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -39,13 +39,18 @@
SecGetPerformance.c
SecTempRamDone.c
PlatformInit.c
+ Fsp.h
[Sources.IA32]
- Ia32/Fsp.h
Ia32/SecEntry.nasm
Ia32/PeiCoreEntry.nasm
Ia32/Stack.nasm
+[Sources.X64]
+ X64/SecEntry.nasm
+ X64/PeiCoreEntry.nasm
+ X64/Stack.nasm
+
#
# Package Dependency Section - list of Package files that are required for
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
index 03616cb418..d2acb2fd46 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
@@ -1,7 +1,7 @@
/** @file
Sample to provide TempRamInitParams data.
- Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2022, Intel Corporation. All
[edk2-devel][PATCH v5 7/8] IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Add Execute64BitCode to execute 64bit code from long mode directly
in PEI 64bit.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../BaseFspWrapperApiLib/FspWrapperApiLib.c| 44 +---
.../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 23 ++-
.../BaseFspWrapperApiLib/X64/DispatchExecute.c | 47 --
3 files changed, 104 insertions(+), 10 deletions(-)
diff --git
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
index 67faad927c..5b5beb5c65 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
@@ -1,7 +1,7 @@
/** @file
Provide FSP API related function.
- Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -13,7 +13,7 @@
#include
/**
- Wrapper for a thunk to transition from long mode to compatibility mode to
execute 32-bit code and then transit back to
+ Wrapper for a thunk to transition from long mode to compatibility mode to
execute 32-bit code and then transit back to
long mode.
@param[in] Function The 32bit code entry to be executed.
@@ -29,6 +29,22 @@ Execute32BitCode (
IN UINT64 Param2
);
+/**
+ Wrapper to execute 64-bit code directly from long mode.
+
+ @param[in] Function The 64bit code entry to be executed.
+ @param[in] Param1 The first parameter to pass to 64bit code.
+ @param[in] Param2 The second parameter to pass to 64bit code.
+
+ @return EFI_STATUS.
+**/
+EFI_STATUS
+Execute64BitCode (
+ IN UINT64 Function,
+ IN UINT64 Param1,
+ IN UINT64 Param2
+ );
+
/**
Find FSP header pointer.
@@ -94,7 +110,11 @@ CallFspNotifyPhase (
NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase +
FspHeader->NotifyPhaseEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -127,7 +147,11 @@ CallFspMemoryInit (
FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase +
FspHeader->FspMemoryInitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)FspMemoryInitApi,
(UINTN)FspmUpdDataPtr, (UINTN)HobListPtr);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr,
(UINTN)HobListPtr);
+ } else {
+Status = Execute64BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr,
(UINTN)HobListPtr);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -158,7 +182,11 @@ CallTempRamExit (
TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase +
FspHeader->TempRamExitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)TempRamExitApi,
(UINTN)TempRamExitParam, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam,
(UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam,
(UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -189,7 +217,11 @@ CallFspSiliconInit (
FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase +
FspHeader->FspSiliconInitEntryOffset);
InterruptState= SaveAndDisableInterrupts ();
- Status= Execute32BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
diff --git
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
index 4f6a8dd1a7..a17ca7dcab 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
@@
[edk2-devel][PATCH v5 6/8] IntelFsp2WrapperPkg: Adopt FSPM_UPD_COMMON_FSP24 for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Adopt FSPM_UPD_COMMON_FSP24 in FspmWrapperPeim to support X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 27 ++
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index b0c6b2f8a6..047c2965a3 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register
MemoryDiscoveredPpi
notify to call FspSiliconInit API.
- Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -71,7 +71,7 @@ PeiFspMemoryInit (
UINT64 TimeStampCounterStart;
VOID *FspHobListPtr;
VOID *HobData;
- FSPM_UPD_COMMON *FspmUpdDataPtr;
+ VOID *FspmUpdDataPtr;
UINTN*SourceData;
DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
@@ -89,7 +89,7 @@ PeiFspMemoryInit (
//
// Copy default FSP-M UPD data from Flash
//
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)AllocateZeroPool
((UINTN)FspmHeaderPtr->CfgRegionSize);
+FspmUpdDataPtr = AllocateZeroPool ((UINTN)FspmHeaderPtr->CfgRegionSize);
ASSERT (FspmUpdDataPtr != NULL);
SourceData = (UINTN *)((UINTN)FspmHeaderPtr->ImageBase +
(UINTN)FspmHeaderPtr->CfgRegionOffset);
CopyMem (FspmUpdDataPtr, SourceData, (UINTN)FspmHeaderPtr->CfgRegionSize);
@@ -97,17 +97,24 @@ PeiFspMemoryInit (
//
// External UPD is ready, get the buffer from PCD pointer.
//
-FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress();
+FspmUpdDataPtr = (VOID *) GetFspmUpdDataAddress();
ASSERT (FspmUpdDataPtr != NULL);
}
DEBUG ((DEBUG_INFO, "UpdateFspmUpdData enter\n"));
- UpdateFspmUpdData ((VOID *)FspmUpdDataPtr);
- DEBUG ((DEBUG_INFO, " NvsBufferPtr- 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.NvsBufferPtr));
- DEBUG ((DEBUG_INFO, " StackBase - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.StackBase));
- DEBUG ((DEBUG_INFO, " StackSize - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.StackSize));
- DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.BootLoaderTolumSize));
- DEBUG ((DEBUG_INFO, " BootMode- 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.BootMode));
+ UpdateFspmUpdData (FspmUpdDataPtr);
+ if (((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.Revision >= 3) {
+DEBUG ((DEBUG_INFO, " StackBase - 0x%lx\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.StackBase));
+DEBUG ((DEBUG_INFO, " StackSize - 0x%lx\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.StackSize));
+DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize));
+DEBUG ((DEBUG_INFO, " BootMode- 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.BootMode));
+ } else {
+DEBUG ((DEBUG_INFO, " NvsBufferPtr- 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.NvsBufferPtr));
+DEBUG ((DEBUG_INFO, " StackBase - 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.StackBase));
+DEBUG ((DEBUG_INFO, " StackSize - 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.StackSize));
+DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize));
+DEBUG ((DEBUG_INFO, " BootMode- 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.BootMode));
+ }
DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", ));
TimeStampCounterStart = AsmReadTsc ();
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#88934): https://edk2.groups.io/g/devel/message/88934
Mute This Topic: https://groups.io/mt/90482853/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v5 5/8] IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspSecPlatformLibNull support for X64. 2.Added X64 support to IntelFsp2Pkg.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 4 +-- .../SecFspSecPlatformLibNull.inf | 8 +++-- .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 + .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++ 4 files changed, 79 insertions(+), 4 deletions(-) create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index c1414f7e75..7cf7e88245 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -1,7 +1,7 @@ ## @file # Provides driver and definitions to build fsp. # -# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved. +# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved. # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -12,7 +12,7 @@ PLATFORM_VERSION = 0.1 DSC_SPECIFICATION = 0x00010005 OUTPUT_DIRECTORY = Build/IntelFsp2Pkg - SUPPORTED_ARCHITECTURES= IA32 + SUPPORTED_ARCHITECTURES= IA32|X64 BUILD_TARGETS = DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER = DEFAULT diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf index 42e7d83c32..55ee1b98a2 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf @@ -1,7 +1,7 @@ ## @file # NULL instance of Platform Sec Lib. # -# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved. +# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -23,7 +23,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # @@ -39,6 +39,10 @@ Ia32/Flat32.nasm Ia32/SecCarInit.nasm +[Sources.X64] + X64/Long64.nasm + X64/SecCarInit.nasm + # # Package Dependency Section - list of Package files that are required for diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm new file mode 100644 index 00..836257f962 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm @@ -0,0 +1,31 @@ +;; @file +; This is the code that performs early platform initialization. +; It consumes the reset vector, configures the stack. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +extern ASM_PFX(TempRamInitApi) + +SECTION .text + +%macro RET_RSI 0 + + movdrsi, mm7 ; restore RSI from MM7 + jmp rsi + +%endmacro + +; +; Perform early platform initialization +; +global ASM_PFX(SecPlatformInit) +ASM_PFX(SecPlatformInit): + + RET_RSI + diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm new file mode 100644 index 00..e64c77ed18 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm @@ -0,0 +1,40 @@ +;; @file +; SEC CAR function +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +%macro RET_RSI 0 + + movdrsi, mm7 ; move ReturnAddress from MM7 to RSI + jmp rsi + +%endmacro + +SECTION .text + +;- +; +; Section: SecCarInit +; +; Description: This function initializes the Cache for Data, Stack, and Code +; +;- +global ASM_PFX(SecCarInit) +ASM_PFX(SecCarInit): + + ; + ; Set up CAR + ; + + xorrax, rax + +SecCarInitExit: + + RET_RSI + -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88933): https://edk2.groups.io/g/devel/message/88933 Mute This Topic: https://groups.io/mt/90482852/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe:
[edk2-devel][PATCH v5 3/8] IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support
both IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +-
IntelFsp2Pkg/Include/FspGlobalData.h | 53 +---
2 files changed, 38 insertions(+), 17 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 04b43c10d0..7fde6e7f41 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -130,7 +130,7 @@ FspGlobalDataInit (
ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA));
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;
- PeiFspData->Version = 0;
+ PeiFspData->Version = FSP_GLOBAL_DATA_VERSION;
PeiFspData->CoreStack = BootLoaderStack;
PeiFspData->PerfIdx = 2;
PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;
diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h
b/IntelFsp2Pkg/Include/FspGlobalData.h
index 2b534075ae..445540abfa 100644
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,8 +10,9 @@
#include
-#define FSP_IN_API_MODE 0
-#define FSP_IN_DISPATCH_MODE 1
+#define FSP_IN_API_MODE 0
+#define FSP_IN_DISPATCH_MODE1
+#define FSP_GLOBAL_DATA_VERSION 1
#pragma pack(1)
@@ -28,10 +29,11 @@ typedef enum {
typedef struct {
VOID *DataPtr;
- UINT32MicrocodeRegionBase;
- UINT32MicrocodeRegionSize;
- UINT32CodeRegionBase;
- UINT32CodeRegionSize;
+ UINTN MicrocodeRegionBase;
+ UINTN MicrocodeRegionSize;
+ UINTN CodeRegionBase;
+ UINTN CodeRegionSize;
+ UINTN Reserved;
} FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURESIGNATURE_32 ('F', 'S', 'P', 'D')
@@ -42,15 +44,15 @@ typedef struct {
UINT32 Signature;
UINT8 Version;
UINT8 Reserved1[3];
+ ///
+ /// Offset 0x08
+ ///
UINTN CoreStack;
+ UINTN Reserved2;
+ ///
+ /// IA32: Offset 0x10; X64: Offset 0x18
+ ///
UINT32 StatusCode;
- UINT32 Reserved2[8];
- FSP_PLAT_DATA PlatformData;
- FSP_INFO_HEADER*FspInfoHeader;
- VOID *UpdDataPtr;
- VOID *TempRamInitUpdPtr;
- VOID *MemoryInitUpdPtr;
- VOID *SiliconInitUpdPtr;
UINT8 ApiIdx;
///
/// 0: FSP in API mode; 1: FSP in DISPATCH mode
@@ -60,15 +62,34 @@ typedef struct {
UINT8 Reserved3;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
+ UINT32 Reserved4[8];
///
+ /// IA32: Offset 0x40; X64: Offset 0x48
+ /// Start of UINTN and pointer section
+ /// All UINTN and pointer members must be put in this section
+ /// except CoreStack and Reserved2. In addition, the number of
+ /// UINTN and pointer members must be even for natural alignment
+ /// in both IA32 and X64.
+ ///
+ FSP_PLAT_DATA PlatformData;
+ VOID *TempRamInitUpdPtr;
+ VOID *MemoryInitUpdPtr;
+ VOID *SiliconInitUpdPtr;
+ ///
+ /// IA32: Offset 0x64; X64: Offset 0x90
/// To store function parameters pointer
/// so it can be retrieved after stack switched.
///
VOID *FunctionParameterPtr;
- UINT8 Reserved4[16];
+ FSP_INFO_HEADER*FspInfoHeader;
+ VOID *UpdDataPtr;
+ ///
+ /// End of UINTN and pointer section
+ ///
+ UINT8 Reserved5[16];
UINT32 PerfSig;
UINT16 PerfLen;
- UINT16 Reserved5;
+ UINT16 Reserved6;
UINT32 PerfIdx;
UINT64 PerfData[32];
} FSP_GLOBAL_DATA;
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#88932): https://edk2.groups.io/g/devel/message/88932
Mute This Topic: https://groups.io/mt/90482851/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v5 4/8] IntelFsp2Pkg: FspSecCore support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. 3.Corrected few typos. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 10 +- IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 11 +- IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 10 +- IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 12 +- .../FspSecCore/Ia32/FspApiEntryCommon.nasm | 6 +- IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 + IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 271 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 495 + IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++ IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 + IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 + IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++ IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 16 +- IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284 .../Library/BaseFspCommonLib/FspCommonLib.c| 6 +- .../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +- 18 files changed, 1493 insertions(+), 19 deletions(-) create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc create mode 100644 IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Stack.nasm create mode 100644 IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf index 0a24eb2a8b..4a67388ddf 100644 --- a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf @@ -1,7 +1,7 @@ ## @file # Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization. # -# Copyright (c) 2020, Intel Corporation. All rights reserved. +# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/Fsp22ApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf index 7b05cae641..a7fc07dc61 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -1,7 +1,7 @@ ## @file # Sec Core for FSP # -# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved. +# Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -34,6 +34,13 @@ Ia32/FspHelper.nasm Ia32/ReadEsp.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryM.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + X64/ReadRsp.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf index 1d9c2554d1..fb80c0e339 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf @@ -1,7 +1,7 @@ ## @file # Sec Core for FSP # -# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved. +# Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
[edk2-devel][PATCH v5 2/8] IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64.
2.Added FSPx_UPD_COMMON_FSP24 structures.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 32 +-
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 98 ++---
IntelFsp2Pkg/Include/FspEas/FspApi.h | 139 -
IntelFsp2Pkg/Tools/GenCfgOpt.py| 7 +-
4 files changed, 252 insertions(+), 24 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index e7261b41cd..5dada2af54 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -1,7 +1,7 @@
;; @file
; Provide FSP API entry points.
;
-; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
@@ -32,6 +32,24 @@ struc FSPM_UPD_COMMON
.size:
endstruc
+struc FSPM_UPD_COMMON_FSP24
+; FSP_UPD_HEADER {
+.FspUpdHeader: resd 8
+; }
+; FSPM_ARCH2_UPD {
+.Revision: resb 1
+.Reserved: resb 3
+.Length resd 1
+.StackBase: resq 1
+.StackSize: resq 1
+.BootLoaderTolumSize: resd 1
+.BootMode: resd 1
+.FspEventHandlerresq 1
+.Reserved1: resb 24
+; }
+.size:
+endstruc
+
;
; Following functions will be provided in C
;
@@ -124,12 +142,22 @@ ASM_PFX(FspApiCommonContinue):
popeax
FspStackSetup:
+ movecx, [edx + FSPM_UPD_COMMON.Revision]
+ cmpecx, 3
+ jaeFspmUpdCommon2
+
;
; StackBase = temp memory base, StackSize = temp memory size
;
movedi, [edx + FSPM_UPD_COMMON.StackBase]
movecx, [edx + FSPM_UPD_COMMON.StackSize]
+ jmpChkFspHeapSize
+
+FspmUpdCommon2:
+ movedi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]
+ movecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]
+ChkFspHeapSize:
;
; Keep using bootloader stack if heap size % is 0
;
@@ -219,7 +247,7 @@ exit:
global ASM_PFX(FspPeiCoreEntryOff)
ASM_PFX(FspPeiCoreEntryOff):
;
- ; This value will be pached by the build script
+ ; This value will be patched by the build script
;
DD0x12345678
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 7fd3d6d843..61030a843b 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -1,7 +1,7 @@
;; @file
; Provide FSP API entry points.
;
-; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
@@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22
.FspUpdHeaderRevision:resb1
.FspUpdHeaderReserved:resb 23
; }
-; FSPT_ARCH_UPD{
-.FsptArchUpd: resd8
+; FSPT_ARCH_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchUpd: resd7
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resd1
@@ -96,6 +98,28 @@ struc LoadMicrocodeParamsFsp22
.size:
endstruc
+struc LoadMicrocodeParamsFsp24
+; FSP_UPD_HEADER {
+.FspUpdHeaderSignature: resd2
+.FspUpdHeaderRevision:resb1
+.FspUpdHeaderReserved:resb 23
+; }
+; FSPT_ARCH2_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchLength: resd1
+.FspDebugHandler resq1
+.FsptArchUpd: resd4
+; }
+; FSPT_CORE_UPD {
+.MicrocodeCodeAddr: resq1
+.MicrocodeCodeSize: resq1
+.CodeRegionBase: resq1
+.CodeRegionSize: resq1
+; }
+.size:
+endstruc
+
;
; Define SSE macros
;
@@ -172,9 +196,9 @@ ASM_PFX(LoadMicrocodeDefault):
; Executed by SBSP and NBSP
; Beginning of microcode update region starts on paragraph boundary
- ;
;
; Save return address to EBP
+ ;
movd ebp, mm7
cmpesp, 0
@@ -188,8 +212,12 @@ ASM_PFX(LoadMicrocodeDefault):
; and report error if size is less than 2k
; first check UPD header revision
cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
- jaeFsp22UpdHeader
+ jb Fsp20UpdHeader
+ cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
+ je Fsp24UpdHeader
+ jmpFsp22UpdHeader
+Fsp20UpdHeader:
; UPD structure is compliant with FSP spec 2.0/2.1
moveax, dword [esp +
[edk2-devel][PATCH v5 0/8] Support PEI 64bit in IntelFsp2Pkg and IntelFsp2WrapperPkg
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Currently PEI drivers/libraries only support 32bit in IntelFsp2Pkg and
IntelFsp2WrapperPkg. The patches below are needed to support these
drivers/libraries in 64bit.
V2 changes:
1.Change FSPM_UPD_COMMON2 to FSPM_UPD_COMMON_FSP24 in FspApiEntryM.nasm.
2.Add FSPx_UPD_COMMON_FSP24 in FspApi.h.
3.Add 3 additional patches for supporting X64 in IntelFsp2WrapperPkg.
V3 changes:
1.Update FSPT_ARCH2_UPD and add FSPT_CORE_UPD back.
2.Use 0x instead of MAX_ADDRESS to reflect the default of FspData.
3.Remove EnableMultiPhaseMemoryInit from FSPM_ARCH2_UPD.
4.Bump GenCfgOpt version to 0.57.
V4 changes:
1.Added EFIAPI to SwapStack and PEI_CORE_ENTRY.
2.Cast FspData from pointer to UINTN and then from UINTN to UINT32.
3.Corrected few typos.
Ted Kuo (8):
IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
IntelFsp2Pkg: FspSecCore support for X64
IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
IntelFsp2WrapperPkg: Adopt FSPM_UPD_COMMON_FSP24 for X64
IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
V5
1.Extend Copyright year to 2022 for the modified files
2.Check FSPM_UPD_COMMON_FSP24.Revision before configuring FSP stack.
3.Treat both MAX_ADDRESS and MAX_UINT32 as invalid address for FSP global data
in FspApiCallingCheck().
4.Remove EnableMultiPhaseSiliconInit from FSPS_ARCH2_UPD.
5.Add an additional ExcludedSpecificUpd1 to exclude FSPx_ARCH2_UPD in
GenCfgOpt.py tool.
IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 3 +-
IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 10 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 11 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 10 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 12 +-
.../FspSecCore/Ia32/FspApiEntryCommon.nasm | 6 +-
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 32 +-
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 98 +++-
IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 10 +-
IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 12 +-
IntelFsp2Pkg/FspSecCore/SecFsp.c | 12 +-
IntelFsp2Pkg/FspSecCore/SecFsp.h | 4 +-
IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 10 +-
IntelFsp2Pkg/FspSecCore/SecMain.c | 10 +-
IntelFsp2Pkg/FspSecCore/SecMain.h | 20 +-
IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 +
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 271 +++
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 495 +
IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++
IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 +
IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 +
IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++
IntelFsp2Pkg/Include/FspEas/FspApi.h | 139 +-
IntelFsp2Pkg/Include/FspGlobalData.h | 53 ++-
IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 16 +-
IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284
IntelFsp2Pkg/IntelFsp2Pkg.dsc | 4 +-
.../Library/BaseFspCommonLib/FspCommonLib.c| 6 +-
.../BaseFspSwitchStackLib/FspSwitchStackLib.c | 3 +-
.../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +-
.../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 4 +-
.../SecFspSecPlatformLibNull.inf | 8 +-
.../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 ++
.../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++
IntelFsp2Pkg/Tools/GenCfgOpt.py| 7 +-
.../FspmWrapperPeim/FspmWrapperPeim.c | 27 +-
.../BaseFspWrapperApiLib/FspWrapperApiLib.c| 44 +-
.../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 23 +-
.../BaseFspWrapperApiLib/X64/DispatchExecute.c | 47 +-
.../{Ia32 => }/Fsp.h | 0
.../Ia32/Stack.nasm| 8 +-
.../SecFspWrapperPlatformSecLibSample.inf | 9 +-
.../SecRamInitData.c | 24 +-
.../X64/PeiCoreEntry.nasm | 149 +++
.../X64/SecEntry.nasm | 171 +++
.../X64/Stack.nasm | 73 +++
48 files changed, 2446 insertions(+), 141 deletions(-)
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm
create mode
[edk2-devel][PATCH v5 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added EFIAPI to FspNotifyPhasePeimEntryPoint, SwapStack and PEI_CORE_ENTRY. 2.Treat both MAX_ADDRESS and MAX_UINT32 as invalid address for FSP global data in FspApiCallingCheck(). 3.Changed AsmReadEsp to AsmReadStackPointer. 4.Changed the type of the return value of AsmReadStackPointer from UINT32 to UINTN. 5.Changed the type of TemporaryMemoryBase, PermenentMemoryBase and BootLoaderStack from UINT32 to UINTN. 6.Some type casting to pointers are UINT32. Changed them to UINTN to accommodate both IA32 and X64. 7.Corrected some typos. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 3 ++- IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm| 10 +- IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 12 ++-- IntelFsp2Pkg/FspSecCore/SecFsp.c | 10 +- IntelFsp2Pkg/FspSecCore/SecFsp.h | 4 ++-- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 10 +- IntelFsp2Pkg/FspSecCore/SecMain.c| 10 +- IntelFsp2Pkg/FspSecCore/SecMain.h| 20 +++- .../BaseFspSwitchStackLib/FspSwitchStackLib.c| 3 ++- .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm| 4 ++-- 10 files changed, 45 insertions(+), 41 deletions(-) diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c index 88f5540fef..c3ba9f168c 100644 --- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c +++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c @@ -1,7 +1,7 @@ /** @file Source file for FSP notify phase PEI module - Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved. + Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -112,6 +112,7 @@ WaitForNotify ( @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database **/ EFI_STATUS +EFIAPI FspNotifyPhasePeimEntryPoint ( IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm index 8046b43745..d6bbf9cc75 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm @@ -1,7 +1,7 @@ ;; @file ; Provide read ESP function ; -; Copyright (c) 2019, Intel Corporation. All rights reserved. +; Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved. ; SPDX-License-Identifier: BSD-2-Clause-Patent ;; ;-- @@ -9,14 +9,14 @@ SECTION .text ;-- -; UINT32 +; UINTN ; EFIAPI -; AsmReadEsp ( +; AsmReadStackPointer ( ; VOID ; ); ;-- -global ASM_PFX(AsmReadEsp) -ASM_PFX(AsmReadEsp): +global ASM_PFX(AsmReadStackPointer) +ASM_PFX(AsmReadStackPointer): mov eax, esp ret diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm index 5a7e27c240..5cb2424bc8 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -1,6 +1,6 @@ ;-- ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. +; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved. ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -9,20 +9,20 @@ ; ;-- -SECTION .text +SECTION .text ;-- ; VOID ; EFIAPI ; SecSwitchStack ( ; UINT32 TemporaryMemoryBase, -; UINT32 PermenentMemoryBase +; UINT32 PermanentMemoryBase ; ); ;-- global ASM_PFX(SecSwitchStack) ASM_PFX(SecSwitchStack): ; -; Save three register: eax, ebx, ecx +; Save four register: eax, ebx, ecx, edx ; push eax push ebx @@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack): mov dword [eax + 12], edx mov edx, dword [esp + 16]; Update this function's return address into permanent memory mov dword [eax + 16], edx -mov esp, eax ; From now, esp is pointed to permanent memory +mov esp, eax ; From now, esp is pointed to permanent memory ; ; Fixup the ebp point to permanent memory @@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack): mov eax, ebp sub eax, ebx add eax, ecx -mov ebp, eax; From now, ebp is
[edk2-devel][PATCH v4 8/8] IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added SecFspWrapperPlatformSecLibSample support for X64.
2.Adopted FSPT_ARCH2_UPD in SecFspWrapperPlatformSecLibSample.
3.Moved Fsp.h up one level to be shared across IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../{Ia32 => }/Fsp.h | 0
.../Ia32/Stack.nasm| 6 +-
.../SecFspWrapperPlatformSecLibSample.inf | 7 +-
.../SecRamInitData.c | 22 +--
.../X64/PeiCoreEntry.nasm | 149 ++
.../X64/SecEntry.nasm | 171 +
.../X64/Stack.nasm | 73 +
7 files changed, 415 insertions(+), 13 deletions(-)
rename IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/{Ia32 =>
}/Fsp.h (100%)
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/PeiCoreEntry.nasm
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/Stack.nasm
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Fsp.h
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.h
similarity index 100%
rename from
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Fsp.h
rename to IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.h
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
index d7394cf286..65e9c2e895 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
@@ -22,7 +22,7 @@
global ASM_PFX(SecSwitchStack)
ASM_PFX(SecSwitchStack):
;
-; Save three register: eax, ebx, ecx
+; Save four register: eax, ebx, ecx, edx
;
push eax
push ebx
@@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack):
mov dword [eax + 12], edx
mov edx, dword [esp + 16]; Update this function's return address
into permanent memory
mov dword [eax + 16], edx
-mov esp, eax ; From now, esp is pointed to permanent
memory
+mov esp, eax ; From now, esp is pointed to permanent
memory
;
; Fixup the ebp point to permanent memory
@@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack):
mov eax, ebp
sub eax, ebx
add eax, ecx
-mov ebp, eax; From now, ebp is pointed to permanent
memory
+mov ebp, eax ; From now, ebp is pointed to permanent
memory
pop edx
pop ecx
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
index 027b127724..7aa4297bcc 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
@@ -39,13 +39,18 @@
SecGetPerformance.c
SecTempRamDone.c
PlatformInit.c
+ Fsp.h
[Sources.IA32]
- Ia32/Fsp.h
Ia32/SecEntry.nasm
Ia32/PeiCoreEntry.nasm
Ia32/Stack.nasm
+[Sources.X64]
+ X64/SecEntry.nasm
+ X64/PeiCoreEntry.nasm
+ X64/Stack.nasm
+
#
# Package Dependency Section - list of Package files that are required for
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
index 03616cb418..4a7478c2c3 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
@@ -10,18 +10,20 @@
#include
typedef struct {
- UINT32MicrocodeRegionBase;
- UINT32MicrocodeRegionSize;
- UINT32CodeRegionBase;
- UINT32CodeRegionSize;
+ EFI_PHYSICAL_ADDRESS MicrocodeRegionBase;
+ UINT64MicrocodeRegionSize;
+ EFI_PHYSICAL_ADDRESS CodeRegionBase;
+ UINT64CodeRegionSize;
} FSPT_CORE_UPD;
typedef struct {
FSP_UPD_HEADERFspUpdHeader;
//
- // If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD structure.
+ // If FSP spec version < 2.2, remove FSPT_ARCH_UPD structure.
+ // Else If FSP spec version >= 2.2 and FSP spec version < 2.4, use
FSPT_ARCH_UPD structure.
+ // Else, use FSPT_ARCH2_UPD structure.
//
- FSPT_ARCH_UPD FsptArchUpd;
+ FSPT_ARCH2_UPDFsptArchUpd;
[edk2-devel][PATCH v4 7/8] IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Add Execute64BitCode to execute 64bit code from long mode directly
in PEI 64bit.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../BaseFspWrapperApiLib/FspWrapperApiLib.c| 42 +---
.../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 21 ++
.../BaseFspWrapperApiLib/X64/DispatchExecute.c | 45 +-
3 files changed, 101 insertions(+), 7 deletions(-)
diff --git
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
index 67faad927c..ba4fe3903e 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
@@ -13,7 +13,7 @@
#include
/**
- Wrapper for a thunk to transition from long mode to compatibility mode to
execute 32-bit code and then transit back to
+ Wrapper for a thunk to transition from long mode to compatibility mode to
execute 32-bit code and then transit back to
long mode.
@param[in] Function The 32bit code entry to be executed.
@@ -29,6 +29,22 @@ Execute32BitCode (
IN UINT64 Param2
);
+/**
+ Wrapper to execute 64-bit code directly from long mode.
+
+ @param[in] Function The 64bit code entry to be executed.
+ @param[in] Param1 The first parameter to pass to 64bit code.
+ @param[in] Param2 The second parameter to pass to 64bit code.
+
+ @return EFI_STATUS.
+**/
+EFI_STATUS
+Execute64BitCode (
+ IN UINT64 Function,
+ IN UINT64 Param1,
+ IN UINT64 Param2
+ );
+
/**
Find FSP header pointer.
@@ -94,7 +110,11 @@ CallFspNotifyPhase (
NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase +
FspHeader->NotifyPhaseEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -127,7 +147,11 @@ CallFspMemoryInit (
FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase +
FspHeader->FspMemoryInitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)FspMemoryInitApi,
(UINTN)FspmUpdDataPtr, (UINTN)HobListPtr);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr,
(UINTN)HobListPtr);
+ } else {
+Status = Execute64BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr,
(UINTN)HobListPtr);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -158,7 +182,11 @@ CallTempRamExit (
TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase +
FspHeader->TempRamExitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)TempRamExitApi,
(UINTN)TempRamExitParam, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam,
(UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam,
(UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -189,7 +217,11 @@ CallFspSiliconInit (
FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase +
FspHeader->FspSiliconInitEntryOffset);
InterruptState= SaveAndDisableInterrupts ();
- Status= Execute32BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
diff --git
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
index 4f6a8dd1a7..a22ed2d539 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
@@ -49,3 +49,24 @@ Execute32BitCode (
return Status;
}
+
+/**
+ Wrapper for a thunk to transition from compatibility mode to long mode to
execute 64-bit code and then transit back to
+ compatibility mode.
+
+ @param[in] Function The 64bit code entry to
[edk2-devel][PATCH v4 5/8] IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspSecPlatformLibNull support for X64. 2.Added X64 support to IntelFsp2Pkg.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +- .../SecFspSecPlatformLibNull.inf | 6 +++- .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 + .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++ 4 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index c1414f7e75..1284aa042c 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -12,7 +12,7 @@ PLATFORM_VERSION = 0.1 DSC_SPECIFICATION = 0x00010005 OUTPUT_DIRECTORY = Build/IntelFsp2Pkg - SUPPORTED_ARCHITECTURES= IA32 + SUPPORTED_ARCHITECTURES= IA32|X64 BUILD_TARGETS = DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER = DEFAULT diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf index 42e7d83c32..ef859d5ea5 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf @@ -23,7 +23,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # @@ -39,6 +39,10 @@ Ia32/Flat32.nasm Ia32/SecCarInit.nasm +[Sources.X64] + X64/Long64.nasm + X64/SecCarInit.nasm + # # Package Dependency Section - list of Package files that are required for diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm new file mode 100644 index 00..836257f962 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm @@ -0,0 +1,31 @@ +;; @file +; This is the code that performs early platform initialization. +; It consumes the reset vector, configures the stack. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +extern ASM_PFX(TempRamInitApi) + +SECTION .text + +%macro RET_RSI 0 + + movdrsi, mm7 ; restore RSI from MM7 + jmp rsi + +%endmacro + +; +; Perform early platform initialization +; +global ASM_PFX(SecPlatformInit) +ASM_PFX(SecPlatformInit): + + RET_RSI + diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm new file mode 100644 index 00..e64c77ed18 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm @@ -0,0 +1,40 @@ +;; @file +; SEC CAR function +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +%macro RET_RSI 0 + + movdrsi, mm7 ; move ReturnAddress from MM7 to RSI + jmp rsi + +%endmacro + +SECTION .text + +;- +; +; Section: SecCarInit +; +; Description: This function initializes the Cache for Data, Stack, and Code +; +;- +global ASM_PFX(SecCarInit) +ASM_PFX(SecCarInit): + + ; + ; Set up CAR + ; + + xorrax, rax + +SecCarInitExit: + + RET_RSI + -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88830): https://edk2.groups.io/g/devel/message/88830 Mute This Topic: https://groups.io/mt/90433374/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v4 4/8] IntelFsp2Pkg: FspSecCore support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. 3.Corrected few typos. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 9 +- IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 10 +- .../FspSecCore/Ia32/FspApiEntryCommon.nasm | 4 +- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 2 +- IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 + IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 262 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 495 + IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++ IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 + IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 + IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++ IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 14 +- IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284 .../Library/BaseFspCommonLib/FspCommonLib.c| 4 +- .../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +- 19 files changed, 1478 insertions(+), 13 deletions(-) create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc create mode 100644 IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Stack.nasm create mode 100644 IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf index 0a24eb2a8b..d64ec12499 100644 --- a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/Fsp22ApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf index 7b05cae641..34794dd16e 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -34,6 +34,13 @@ Ia32/FspHelper.nasm Ia32/ReadEsp.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryM.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + X64/ReadRsp.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf index 1d9c2554d1..79d4e0674e 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf index 664bde5678..f08a3b2c2b 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf @@ -17,17 +17,19 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # -[Sources] - - [Sources.IA32] Ia32/Stack.nasm Ia32/FspApiEntryT.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryT.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git
[edk2-devel][PATCH v4 3/8] IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support
both IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +-
IntelFsp2Pkg/Include/FspGlobalData.h | 51 +---
2 files changed, 37 insertions(+), 16 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 85fbc7664c..1ead3c9ce6 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -130,7 +130,7 @@ FspGlobalDataInit (
ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA));
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;
- PeiFspData->Version = 0;
+ PeiFspData->Version = FSP_GLOBAL_DATA_VERSION;
PeiFspData->CoreStack = BootLoaderStack;
PeiFspData->PerfIdx = 2;
PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;
diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h
b/IntelFsp2Pkg/Include/FspGlobalData.h
index 2b534075ae..dcfeed7501 100644
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -10,8 +10,9 @@
#include
-#define FSP_IN_API_MODE 0
-#define FSP_IN_DISPATCH_MODE 1
+#define FSP_IN_API_MODE 0
+#define FSP_IN_DISPATCH_MODE1
+#define FSP_GLOBAL_DATA_VERSION 1
#pragma pack(1)
@@ -28,10 +29,11 @@ typedef enum {
typedef struct {
VOID *DataPtr;
- UINT32MicrocodeRegionBase;
- UINT32MicrocodeRegionSize;
- UINT32CodeRegionBase;
- UINT32CodeRegionSize;
+ UINTN MicrocodeRegionBase;
+ UINTN MicrocodeRegionSize;
+ UINTN CodeRegionBase;
+ UINTN CodeRegionSize;
+ UINTN Reserved;
} FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURESIGNATURE_32 ('F', 'S', 'P', 'D')
@@ -42,15 +44,15 @@ typedef struct {
UINT32 Signature;
UINT8 Version;
UINT8 Reserved1[3];
+ ///
+ /// Offset 0x08
+ ///
UINTN CoreStack;
+ UINTN Reserved2;
+ ///
+ /// IA32: Offset 0x10; X64: Offset 0x18
+ ///
UINT32 StatusCode;
- UINT32 Reserved2[8];
- FSP_PLAT_DATA PlatformData;
- FSP_INFO_HEADER*FspInfoHeader;
- VOID *UpdDataPtr;
- VOID *TempRamInitUpdPtr;
- VOID *MemoryInitUpdPtr;
- VOID *SiliconInitUpdPtr;
UINT8 ApiIdx;
///
/// 0: FSP in API mode; 1: FSP in DISPATCH mode
@@ -60,15 +62,34 @@ typedef struct {
UINT8 Reserved3;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
+ UINT32 Reserved4[8];
///
+ /// IA32: Offset 0x40; X64: Offset 0x48
+ /// Start of UINTN and pointer section
+ /// All UINTN and pointer members must be put in this section
+ /// except CoreStack and Reserved2. In addition, the number of
+ /// UINTN and pointer members must be even for natural alignment
+ /// in both IA32 and X64.
+ ///
+ FSP_PLAT_DATA PlatformData;
+ VOID *TempRamInitUpdPtr;
+ VOID *MemoryInitUpdPtr;
+ VOID *SiliconInitUpdPtr;
+ ///
+ /// IA32: Offset 0x64; X64: Offset 0x90
/// To store function parameters pointer
/// so it can be retrieved after stack switched.
///
VOID *FunctionParameterPtr;
- UINT8 Reserved4[16];
+ FSP_INFO_HEADER*FspInfoHeader;
+ VOID *UpdDataPtr;
+ ///
+ /// End of UINTN and pointer section
+ ///
+ UINT8 Reserved5[16];
UINT32 PerfSig;
UINT16 PerfLen;
- UINT16 Reserved5;
+ UINT16 Reserved6;
UINT32 PerfIdx;
UINT64 PerfData[32];
} FSP_GLOBAL_DATA;
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#88828): https://edk2.groups.io/g/devel/message/88828
Mute This Topic: https://groups.io/mt/90433371/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v4 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added EFIAPI to FspNotifyPhasePeimEntryPoint, SwapStack and PEI_CORE_ENTRY. 2.Cast FspData from pointer to UINTN and then from UINTN to UINT32. 3.Changed AsmReadEsp to AsmReadStackPointer. 4.Changed the type of the return value of AsmReadStackPointer from UINT32 to UINTN. 5.Changed the type of TemporaryMemoryBase, PermenentMemoryBase and BootLoaderStack from UINT32 to UINTN. 6..Some type casting to pointers are UINT32. Changed them to UINTN to accommodate both IA32 and X64. 7.Corrected some typos. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 + IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +- IntelFsp2Pkg/FspSecCore/SecFsp.c | 8 IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 IntelFsp2Pkg/FspSecCore/SecMain.c | 8 IntelFsp2Pkg/FspSecCore/SecMain.h | 18 ++ .../Library/BaseFspSwitchStackLib/FspSwitchStackLib.c | 1 + .../Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- 10 files changed, 35 insertions(+), 31 deletions(-) diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c index 88f5540fef..66d39cc70c 100644 --- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c +++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c @@ -112,6 +112,7 @@ WaitForNotify ( @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database **/ EFI_STATUS +EFIAPI FspNotifyPhasePeimEntryPoint ( IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm index 8046b43745..d40dad5a52 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm @@ -9,14 +9,14 @@ SECTION .text ;-- -; UINT32 +; UINTN ; EFIAPI -; AsmReadEsp ( +; AsmReadStackPointer ( ; VOID ; ); ;-- -global ASM_PFX(AsmReadEsp) -ASM_PFX(AsmReadEsp): +global ASM_PFX(AsmReadStackPointer) +ASM_PFX(AsmReadStackPointer): mov eax, esp ret diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm index 5a7e27c240..ce20639890 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -9,20 +9,20 @@ ; ;-- -SECTION .text +SECTION .text ;-- ; VOID ; EFIAPI ; SecSwitchStack ( ; UINT32 TemporaryMemoryBase, -; UINT32 PermenentMemoryBase +; UINT32 PermanentMemoryBase ; ); ;-- global ASM_PFX(SecSwitchStack) ASM_PFX(SecSwitchStack): ; -; Save three register: eax, ebx, ecx +; Save four register: eax, ebx, ecx, edx ; push eax push ebx @@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack): mov dword [eax + 12], edx mov edx, dword [esp + 16]; Update this function's return address into permanent memory mov dword [eax + 16], edx -mov esp, eax ; From now, esp is pointed to permanent memory +mov esp, eax ; From now, esp is pointed to permanent memory ; ; Fixup the ebp point to permanent memory @@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack): mov eax, ebp sub eax, ebx add eax, ecx -mov ebp, eax; From now, ebp is pointed to permanent memory +mov ebp, eax ; From now, ebp is pointed to permanent memory pop edx pop ecx diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c index 68e588dd41..85fbc7664c 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -26,7 +26,7 @@ FspGetExceptionHandler ( IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor; FSP_INFO_HEADER *FspInfoHeader; - FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader (); + FspInfoHeader = (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHeader (); ExceptionHandler = IdtEntryTemplate; IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *) Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow; @@ -115,7 +115,7 @@
[edk2-devel][PATCH v4 0/8] Support PEI 64bit in IntelFsp2Pkg and IntelFsp2WrapperPkg
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Currently PEI drivers/libraries only support 32bit in IntelFsp2Pkg and
IntelFsp2WrapperPkg. The patches below are needed to support these
drivers/libraries in 64bit.
V2 changes:
1.Change FSPM_UPD_COMMON2 to FSPM_UPD_COMMON_FSP24 in FspApiEntryM.nasm.
2.Add FSPx_UPD_COMMON_FSP24 in FspApi.h.
3.Add 3 additional patches for supporting X64 in IntelFsp2WrapperPkg.
V3 changes:
1.Update FSPT_ARCH2_UPD and add FSPT_CORE_UPD back.
2.Use 0x instead of MAX_ADDRESS to reflect the default of FspData.
3.Remove EnableMultiPhaseMemoryInit from FSPM_ARCH2_UPD.
4.Bump GenCfgOpt version to 0.57.
V4 changes:
1.Added EFIAPI to SwapStack and PEI_CORE_ENTRY.
2.Cast FspData from pointer to UINTN and then from UINTN to UINT32.
3.Corrected few typos.
Ted Kuo (8):
IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
IntelFsp2Pkg: FspSecCore support for X64
IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
IntelFsp2WrapperPkg: Adopt FSPM_UPD_COMMON_FSP24 for X64
IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 +
IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 8 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 9 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 8 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 10 +-
.../FspSecCore/Ia32/FspApiEntryCommon.nasm | 4 +-
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 30 +-
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 96 +++-
IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 +-
IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +-
IntelFsp2Pkg/FspSecCore/SecFsp.c | 10 +-
IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +-
IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 +-
IntelFsp2Pkg/FspSecCore/SecMain.c | 8 +-
IntelFsp2Pkg/FspSecCore/SecMain.h | 18 +-
IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 +
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 262 +++
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 495 +
IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++
IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 +
IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 +
IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++
IntelFsp2Pkg/Include/FspEas/FspApi.h | 145 +-
IntelFsp2Pkg/Include/FspGlobalData.h | 51 ++-
IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 14 +-
IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284
IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +-
.../Library/BaseFspCommonLib/FspCommonLib.c| 4 +-
.../BaseFspSwitchStackLib/FspSwitchStackLib.c | 1 +
.../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +-
.../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +-
.../SecFspSecPlatformLibNull.inf | 6 +-
.../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 ++
.../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++
IntelFsp2Pkg/Tools/GenCfgOpt.py| 4 +-
.../FspmWrapperPeim/FspmWrapperPeim.c | 25 +-
.../BaseFspWrapperApiLib/FspWrapperApiLib.c| 42 +-
.../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 21 +
.../BaseFspWrapperApiLib/X64/DispatchExecute.c | 45 +-
.../{Ia32 => }/Fsp.h | 0
.../Ia32/Stack.nasm| 6 +-
.../SecFspWrapperPlatformSecLibSample.inf | 7 +-
.../SecRamInitData.c | 22 +-
.../X64/PeiCoreEntry.nasm | 149 +++
.../X64/SecEntry.nasm | 171 +++
.../X64/Stack.nasm | 73 +++
48 files changed, 2413 insertions(+), 110 deletions(-)
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Stack.nasm
create mode 100644 IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
create mode
[edk2-devel][PATCH v4 2/8] IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64.
2.Added FSPx_UPD_COMMON_FSP24 structures.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 28 +
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 96 +---
IntelFsp2Pkg/Include/FspEas/FspApi.h | 145 -
IntelFsp2Pkg/Tools/GenCfgOpt.py| 4 +-
4 files changed, 254 insertions(+), 19 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index e7261b41cd..9fa9f28030 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -32,6 +32,24 @@ struc FSPM_UPD_COMMON
.size:
endstruc
+struc FSPM_UPD_COMMON_FSP24
+; FSP_UPD_HEADER {
+.FspUpdHeader: resd 8
+; }
+; FSPM_ARCH2_UPD {
+.Revision: resb 1
+.Reserved: resb 3
+.Length resd 1
+.StackBase: resq 1
+.StackSize: resq 1
+.BootLoaderTolumSize: resd 1
+.BootMode: resd 1
+.FspEventHandlerresq 1
+.Reserved1: resb 24
+; }
+.size:
+endstruc
+
;
; Following functions will be provided in C
;
@@ -124,12 +142,22 @@ ASM_PFX(FspApiCommonContinue):
popeax
FspStackSetup:
+ movecx, [edx + FSPM_UPD_COMMON.Revision]
+ cmpecx, 3
+ jaeFspmUpdCommon2
+
;
; StackBase = temp memory base, StackSize = temp memory size
;
movedi, [edx + FSPM_UPD_COMMON.StackBase]
movecx, [edx + FSPM_UPD_COMMON.StackSize]
+ jmpChkFspHeapSize
+
+FspmUpdCommon2:
+ movedi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]
+ movecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]
+ChkFspHeapSize:
;
; Keep using bootloader stack if heap size % is 0
;
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 7fd3d6d843..554b143ffa 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22
.FspUpdHeaderRevision:resb1
.FspUpdHeaderReserved:resb 23
; }
-; FSPT_ARCH_UPD{
-.FsptArchUpd: resd8
+; FSPT_ARCH_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchUpd: resd7
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resd1
@@ -96,6 +98,28 @@ struc LoadMicrocodeParamsFsp22
.size:
endstruc
+struc LoadMicrocodeParamsFsp24
+; FSP_UPD_HEADER {
+.FspUpdHeaderSignature: resd2
+.FspUpdHeaderRevision:resb1
+.FspUpdHeaderReserved:resb 23
+; }
+; FSPT_ARCH2_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchLength: resd1
+.FspDebugHandler resq1
+.FsptArchUpd: resd4
+; }
+; FSPT_CORE_UPD {
+.MicrocodeCodeAddr: resq1
+.MicrocodeCodeSize: resq1
+.CodeRegionBase: resq1
+.CodeRegionSize: resq1
+; }
+.size:
+endstruc
+
;
; Define SSE macros
;
@@ -172,9 +196,9 @@ ASM_PFX(LoadMicrocodeDefault):
; Executed by SBSP and NBSP
; Beginning of microcode update region starts on paragraph boundary
- ;
;
; Save return address to EBP
+ ;
movd ebp, mm7
cmpesp, 0
@@ -188,8 +212,12 @@ ASM_PFX(LoadMicrocodeDefault):
; and report error if size is less than 2k
; first check UPD header revision
cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
- jaeFsp22UpdHeader
+ jb Fsp20UpdHeader
+ cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
+ je Fsp24UpdHeader
+ jmpFsp22UpdHeader
+Fsp20UpdHeader:
; UPD structure is compliant with FSP spec 2.0/2.1
moveax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
cmpeax, 0
@@ -213,6 +241,19 @@ Fsp22UpdHeader:
movesi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
cmpesi, 0
jnzCheckMainHeader
+ jmpParamError
+
+Fsp24UpdHeader:
+ ; UPD structure is compliant with FSP spec 2.4
+ moveax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
+ cmpeax, 0
+ jz Exit2
+ cmpeax, 0800h
+ jl ParamError
+
+ movesi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
+ cmpesi, 0
+ jnzCheckMainHeader
ParamError:
moveax, 08002h
@@ -308,9 +349,13 @@ AdvanceFixedSize:
CheckAddress:
; Check UPD header revision
- cmpbyte [esp +
Re: [edk2-devel][PATCH v3 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
Hi Andrew, Please see my inline comment. Thanks, Ted -Original Message- From: Andrew Fish Sent: Thursday, April 7, 2022 8:06 AM To: devel@edk2.groups.io; Ni, Ray Cc: Kuo, Ted ; Chiu, Chasel ; Desimone, Nathaniel L ; Zeng, Star ; S, Ashraf Ali Subject: Re: [edk2-devel][PATCH v3 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit > On Apr 6, 2022, at 4:57 PM, Ni, Ray wrote: > >> -; UINT32 >> +; UINTN >> ; EFIAPI >> -; AsmReadEsp ( >> +; AsmReadStackPointer ( >> ; VOID >> ; ); >> ;-- >> -global ASM_PFX(AsmReadEsp) >> -ASM_PFX(AsmReadEsp): >> +global ASM_PFX(AsmReadStackPointer) >> +ASM_PFX(AsmReadStackPointer): >> mov eax, esp >> ret >> > > I guess it's possible that bootloader sets up the stack above 4G. > If that's the case, above code doesn't work. > > Is there an issue with the SecSwitchStack too? [Ted]: I believe we already handled it in IntelFsp2Pkg/FspSecCore/X64/Stack.nasm in the patch [edk2-devel][PATCH v3 4/8] IntelFsp2Pkg: FspSecCore support for X64. Thanks, Andrew Fish > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88495): https://edk2.groups.io/g/devel/message/88495 Mute This Topic: https://groups.io/mt/90294483/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][PATCH v3 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
Hi Ray, Please see my inline comment. Thanks, Ted -Original Message- From: Ni, Ray Sent: Thursday, April 7, 2022 7:58 AM To: devel@edk2.groups.io; Kuo, Ted Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Zeng, Star ; S, Ashraf Ali Subject: RE: [edk2-devel][PATCH v3 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit > -; UINT32 > +; UINTN > ; EFIAPI > -; AsmReadEsp ( > +; AsmReadStackPointer ( > ; VOID > ; ); > > ;-- > -global ASM_PFX(AsmReadEsp) > -ASM_PFX(AsmReadEsp): > +global ASM_PFX(AsmReadStackPointer) > +ASM_PFX(AsmReadStackPointer): > mov eax, esp > ret > I guess it's possible that bootloader sets up the stack above 4G. If that's the case, above code doesn't work. [Ted]: The above code is for IA32 only. We have a separate ReadRsp.nasm for X64. You can find it in the patch [edk2-devel][PATCH v3 4/8] IntelFsp2Pkg: FspSecCore support for X64. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88494): https://edk2.groups.io/g/devel/message/88494 Mute This Topic: https://groups.io/mt/90294483/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v3 7/8] IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Add Execute64BitCode to execute 64bit code from long mode directly
in PEI 64bit.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../BaseFspWrapperApiLib/FspWrapperApiLib.c| 42 +---
.../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 21 ++
.../BaseFspWrapperApiLib/X64/DispatchExecute.c | 45 +-
3 files changed, 101 insertions(+), 7 deletions(-)
diff --git
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
index 67faad927c..ba4fe3903e 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
@@ -13,7 +13,7 @@
#include
/**
- Wrapper for a thunk to transition from long mode to compatibility mode to
execute 32-bit code and then transit back to
+ Wrapper for a thunk to transition from long mode to compatibility mode to
execute 32-bit code and then transit back to
long mode.
@param[in] Function The 32bit code entry to be executed.
@@ -29,6 +29,22 @@ Execute32BitCode (
IN UINT64 Param2
);
+/**
+ Wrapper to execute 64-bit code directly from long mode.
+
+ @param[in] Function The 64bit code entry to be executed.
+ @param[in] Param1 The first parameter to pass to 64bit code.
+ @param[in] Param2 The second parameter to pass to 64bit code.
+
+ @return EFI_STATUS.
+**/
+EFI_STATUS
+Execute64BitCode (
+ IN UINT64 Function,
+ IN UINT64 Param1,
+ IN UINT64 Param2
+ );
+
/**
Find FSP header pointer.
@@ -94,7 +110,11 @@ CallFspNotifyPhase (
NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase +
FspHeader->NotifyPhaseEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -127,7 +147,11 @@ CallFspMemoryInit (
FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase +
FspHeader->FspMemoryInitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)FspMemoryInitApi,
(UINTN)FspmUpdDataPtr, (UINTN)HobListPtr);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr,
(UINTN)HobListPtr);
+ } else {
+Status = Execute64BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr,
(UINTN)HobListPtr);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -158,7 +182,11 @@ CallTempRamExit (
TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase +
FspHeader->TempRamExitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)TempRamExitApi,
(UINTN)TempRamExitParam, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam,
(UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam,
(UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -189,7 +217,11 @@ CallFspSiliconInit (
FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase +
FspHeader->FspSiliconInitEntryOffset);
InterruptState= SaveAndDisableInterrupts ();
- Status= Execute32BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
diff --git
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
index 4f6a8dd1a7..a22ed2d539 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
@@ -49,3 +49,24 @@ Execute32BitCode (
return Status;
}
+
+/**
+ Wrapper for a thunk to transition from compatibility mode to long mode to
execute 64-bit code and then transit back to
+ compatibility mode.
+
+ @param[in] Function The 64bit code entry to
[edk2-devel][PATCH v3 8/8] IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added SecFspWrapperPlatformSecLibSample support for X64.
2.Adopted FSPT_ARCH2_UPD in SecFspWrapperPlatformSecLibSample.
3.Moved Fsp.h up one level to be shared across IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../{Ia32 => }/Fsp.h | 0
.../Ia32/Stack.nasm| 6 +-
.../SecFspWrapperPlatformSecLibSample.inf | 7 +-
.../SecRamInitData.c | 22 +--
.../X64/PeiCoreEntry.nasm | 149 ++
.../X64/SecEntry.nasm | 171 +
.../X64/Stack.nasm | 73 +
7 files changed, 415 insertions(+), 13 deletions(-)
rename IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/{Ia32 =>
}/Fsp.h (100%)
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/PeiCoreEntry.nasm
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/Stack.nasm
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Fsp.h
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.h
similarity index 100%
rename from
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Fsp.h
rename to IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.h
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
index d7394cf286..65e9c2e895 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
@@ -22,7 +22,7 @@
global ASM_PFX(SecSwitchStack)
ASM_PFX(SecSwitchStack):
;
-; Save three register: eax, ebx, ecx
+; Save four register: eax, ebx, ecx, edx
;
push eax
push ebx
@@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack):
mov dword [eax + 12], edx
mov edx, dword [esp + 16]; Update this function's return address
into permanent memory
mov dword [eax + 16], edx
-mov esp, eax ; From now, esp is pointed to permanent
memory
+mov esp, eax ; From now, esp is pointed to permanent
memory
;
; Fixup the ebp point to permanent memory
@@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack):
mov eax, ebp
sub eax, ebx
add eax, ecx
-mov ebp, eax; From now, ebp is pointed to permanent
memory
+mov ebp, eax ; From now, ebp is pointed to permanent
memory
pop edx
pop ecx
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
index 027b127724..7aa4297bcc 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
@@ -39,13 +39,18 @@
SecGetPerformance.c
SecTempRamDone.c
PlatformInit.c
+ Fsp.h
[Sources.IA32]
- Ia32/Fsp.h
Ia32/SecEntry.nasm
Ia32/PeiCoreEntry.nasm
Ia32/Stack.nasm
+[Sources.X64]
+ X64/SecEntry.nasm
+ X64/PeiCoreEntry.nasm
+ X64/Stack.nasm
+
#
# Package Dependency Section - list of Package files that are required for
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
index 03616cb418..4a7478c2c3 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
@@ -10,18 +10,20 @@
#include
typedef struct {
- UINT32MicrocodeRegionBase;
- UINT32MicrocodeRegionSize;
- UINT32CodeRegionBase;
- UINT32CodeRegionSize;
+ EFI_PHYSICAL_ADDRESS MicrocodeRegionBase;
+ UINT64MicrocodeRegionSize;
+ EFI_PHYSICAL_ADDRESS CodeRegionBase;
+ UINT64CodeRegionSize;
} FSPT_CORE_UPD;
typedef struct {
FSP_UPD_HEADERFspUpdHeader;
//
- // If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD structure.
+ // If FSP spec version < 2.2, remove FSPT_ARCH_UPD structure.
+ // Else If FSP spec version >= 2.2 and FSP spec version < 2.4, use
FSPT_ARCH_UPD structure.
+ // Else, use FSPT_ARCH2_UPD structure.
//
- FSPT_ARCH_UPD FsptArchUpd;
+ FSPT_ARCH2_UPDFsptArchUpd;
[edk2-devel][PATCH v3 5/8] IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspSecPlatformLibNull support for X64. 2.Added X64 support to IntelFsp2Pkg.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +- .../SecFspSecPlatformLibNull.inf | 6 +++- .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 + .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++ 4 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index c1414f7e75..1284aa042c 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -12,7 +12,7 @@ PLATFORM_VERSION = 0.1 DSC_SPECIFICATION = 0x00010005 OUTPUT_DIRECTORY = Build/IntelFsp2Pkg - SUPPORTED_ARCHITECTURES= IA32 + SUPPORTED_ARCHITECTURES= IA32|X64 BUILD_TARGETS = DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER = DEFAULT diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf index 42e7d83c32..ef859d5ea5 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf @@ -23,7 +23,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # @@ -39,6 +39,10 @@ Ia32/Flat32.nasm Ia32/SecCarInit.nasm +[Sources.X64] + X64/Long64.nasm + X64/SecCarInit.nasm + # # Package Dependency Section - list of Package files that are required for diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm new file mode 100644 index 00..836257f962 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm @@ -0,0 +1,31 @@ +;; @file +; This is the code that performs early platform initialization. +; It consumes the reset vector, configures the stack. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +extern ASM_PFX(TempRamInitApi) + +SECTION .text + +%macro RET_RSI 0 + + movdrsi, mm7 ; restore RSI from MM7 + jmp rsi + +%endmacro + +; +; Perform early platform initialization +; +global ASM_PFX(SecPlatformInit) +ASM_PFX(SecPlatformInit): + + RET_RSI + diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm new file mode 100644 index 00..e64c77ed18 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm @@ -0,0 +1,40 @@ +;; @file +; SEC CAR function +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +%macro RET_RSI 0 + + movdrsi, mm7 ; move ReturnAddress from MM7 to RSI + jmp rsi + +%endmacro + +SECTION .text + +;- +; +; Section: SecCarInit +; +; Description: This function initializes the Cache for Data, Stack, and Code +; +;- +global ASM_PFX(SecCarInit) +ASM_PFX(SecCarInit): + + ; + ; Set up CAR + ; + + xorrax, rax + +SecCarInitExit: + + RET_RSI + -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88470): https://edk2.groups.io/g/devel/message/88470 Mute This Topic: https://groups.io/mt/90294486/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v3 6/8] IntelFsp2WrapperPkg: Adopt FSPM_UPD_COMMON_FSP24 for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Adopt FSPM_UPD_COMMON_FSP24 in FspmWrapperPeim to support X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 25 ++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index b0c6b2f8a6..62a34467e0 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -71,7 +71,7 @@ PeiFspMemoryInit (
UINT64 TimeStampCounterStart;
VOID *FspHobListPtr;
VOID *HobData;
- FSPM_UPD_COMMON *FspmUpdDataPtr;
+ VOID *FspmUpdDataPtr;
UINTN*SourceData;
DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
@@ -89,7 +89,7 @@ PeiFspMemoryInit (
//
// Copy default FSP-M UPD data from Flash
//
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)AllocateZeroPool
((UINTN)FspmHeaderPtr->CfgRegionSize);
+FspmUpdDataPtr = AllocateZeroPool ((UINTN)FspmHeaderPtr->CfgRegionSize);
ASSERT (FspmUpdDataPtr != NULL);
SourceData = (UINTN *)((UINTN)FspmHeaderPtr->ImageBase +
(UINTN)FspmHeaderPtr->CfgRegionOffset);
CopyMem (FspmUpdDataPtr, SourceData, (UINTN)FspmHeaderPtr->CfgRegionSize);
@@ -97,17 +97,24 @@ PeiFspMemoryInit (
//
// External UPD is ready, get the buffer from PCD pointer.
//
-FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress();
+FspmUpdDataPtr = (VOID *) GetFspmUpdDataAddress();
ASSERT (FspmUpdDataPtr != NULL);
}
DEBUG ((DEBUG_INFO, "UpdateFspmUpdData enter\n"));
- UpdateFspmUpdData ((VOID *)FspmUpdDataPtr);
- DEBUG ((DEBUG_INFO, " NvsBufferPtr- 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.NvsBufferPtr));
- DEBUG ((DEBUG_INFO, " StackBase - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.StackBase));
- DEBUG ((DEBUG_INFO, " StackSize - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.StackSize));
- DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.BootLoaderTolumSize));
- DEBUG ((DEBUG_INFO, " BootMode- 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.BootMode));
+ UpdateFspmUpdData (FspmUpdDataPtr);
+ if (((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.Revision >= 3) {
+DEBUG ((DEBUG_INFO, " StackBase - 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.StackBase));
+DEBUG ((DEBUG_INFO, " StackSize - 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.StackSize));
+DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize));
+DEBUG ((DEBUG_INFO, " BootMode- 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.BootMode));
+ } else {
+DEBUG ((DEBUG_INFO, " NvsBufferPtr- 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.NvsBufferPtr));
+DEBUG ((DEBUG_INFO, " StackBase - 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.StackBase));
+DEBUG ((DEBUG_INFO, " StackSize - 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.StackSize));
+DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize));
+DEBUG ((DEBUG_INFO, " BootMode- 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.BootMode));
+ }
DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", ));
TimeStampCounterStart = AsmReadTsc ();
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#88471): https://edk2.groups.io/g/devel/message/88471
Mute This Topic: https://groups.io/mt/90294487/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v3 4/8] IntelFsp2Pkg: FspSecCore support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 9 +- IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 10 +- .../FspSecCore/Ia32/FspApiEntryCommon.nasm | 4 +- IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 + IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 262 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 495 + IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++ IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 + IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 + IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++ IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 14 +- IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284 .../Library/BaseFspCommonLib/FspCommonLib.c| 1 + .../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +- 18 files changed, 1475 insertions(+), 11 deletions(-) create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc create mode 100644 IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Stack.nasm create mode 100644 IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf index 0a24eb2a8b..d64ec12499 100644 --- a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/Fsp22ApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf index 7b05cae641..34794dd16e 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -34,6 +34,13 @@ Ia32/FspHelper.nasm Ia32/ReadEsp.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryM.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + X64/ReadRsp.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf index 1d9c2554d1..79d4e0674e 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf index 664bde5678..f08a3b2c2b 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf @@ -17,17 +17,19 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # -[Sources] - - [Sources.IA32] Ia32/Stack.nasm Ia32/FspApiEntryT.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryT.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm index
[edk2-devel][PATCH v3 3/8] IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support
both IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +-
IntelFsp2Pkg/Include/FspGlobalData.h | 51 +---
2 files changed, 37 insertions(+), 16 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 85fbc7664c..1ead3c9ce6 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -130,7 +130,7 @@ FspGlobalDataInit (
ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA));
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;
- PeiFspData->Version = 0;
+ PeiFspData->Version = FSP_GLOBAL_DATA_VERSION;
PeiFspData->CoreStack = BootLoaderStack;
PeiFspData->PerfIdx = 2;
PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;
diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h
b/IntelFsp2Pkg/Include/FspGlobalData.h
index 2b534075ae..dcfeed7501 100644
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -10,8 +10,9 @@
#include
-#define FSP_IN_API_MODE 0
-#define FSP_IN_DISPATCH_MODE 1
+#define FSP_IN_API_MODE 0
+#define FSP_IN_DISPATCH_MODE1
+#define FSP_GLOBAL_DATA_VERSION 1
#pragma pack(1)
@@ -28,10 +29,11 @@ typedef enum {
typedef struct {
VOID *DataPtr;
- UINT32MicrocodeRegionBase;
- UINT32MicrocodeRegionSize;
- UINT32CodeRegionBase;
- UINT32CodeRegionSize;
+ UINTN MicrocodeRegionBase;
+ UINTN MicrocodeRegionSize;
+ UINTN CodeRegionBase;
+ UINTN CodeRegionSize;
+ UINTN Reserved;
} FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURESIGNATURE_32 ('F', 'S', 'P', 'D')
@@ -42,15 +44,15 @@ typedef struct {
UINT32 Signature;
UINT8 Version;
UINT8 Reserved1[3];
+ ///
+ /// Offset 0x08
+ ///
UINTN CoreStack;
+ UINTN Reserved2;
+ ///
+ /// IA32: Offset 0x10; X64: Offset 0x18
+ ///
UINT32 StatusCode;
- UINT32 Reserved2[8];
- FSP_PLAT_DATA PlatformData;
- FSP_INFO_HEADER*FspInfoHeader;
- VOID *UpdDataPtr;
- VOID *TempRamInitUpdPtr;
- VOID *MemoryInitUpdPtr;
- VOID *SiliconInitUpdPtr;
UINT8 ApiIdx;
///
/// 0: FSP in API mode; 1: FSP in DISPATCH mode
@@ -60,15 +62,34 @@ typedef struct {
UINT8 Reserved3;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
+ UINT32 Reserved4[8];
///
+ /// IA32: Offset 0x40; X64: Offset 0x48
+ /// Start of UINTN and pointer section
+ /// All UINTN and pointer members must be put in this section
+ /// except CoreStack and Reserved2. In addition, the number of
+ /// UINTN and pointer members must be even for natural alignment
+ /// in both IA32 and X64.
+ ///
+ FSP_PLAT_DATA PlatformData;
+ VOID *TempRamInitUpdPtr;
+ VOID *MemoryInitUpdPtr;
+ VOID *SiliconInitUpdPtr;
+ ///
+ /// IA32: Offset 0x64; X64: Offset 0x90
/// To store function parameters pointer
/// so it can be retrieved after stack switched.
///
VOID *FunctionParameterPtr;
- UINT8 Reserved4[16];
+ FSP_INFO_HEADER*FspInfoHeader;
+ VOID *UpdDataPtr;
+ ///
+ /// End of UINTN and pointer section
+ ///
+ UINT8 Reserved5[16];
UINT32 PerfSig;
UINT16 PerfLen;
- UINT16 Reserved5;
+ UINT16 Reserved6;
UINT32 PerfIdx;
UINT64 PerfData[32];
} FSP_GLOBAL_DATA;
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#88468): https://edk2.groups.io/g/devel/message/88468
Mute This Topic: https://groups.io/mt/90294484/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v3 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added EFIAPI to FspNotifyPhasePeimEntryPoint. 2.Changed AsmReadEsp to AsmReadStackPointer. 3.Changed the type of the return value of AsmReadStackPointer from UINT32 to UINTN. 4.Changed the type of TemporaryMemoryBase, PermenentMemoryBase and BootLoaderStack from UINT32 to UINTN. 5.Some type casting to pointers are UINT32. Changed them to UINTN to accommodate both IA32 and X64. 6.Corrected some typos. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 + IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +- IntelFsp2Pkg/FspSecCore/SecFsp.c | 8 IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 IntelFsp2Pkg/FspSecCore/SecMain.c | 8 IntelFsp2Pkg/FspSecCore/SecMain.h | 10 +- IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- 9 files changed, 29 insertions(+), 28 deletions(-) diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c index 88f5540fef..66d39cc70c 100644 --- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c +++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c @@ -112,6 +112,7 @@ WaitForNotify ( @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database **/ EFI_STATUS +EFIAPI FspNotifyPhasePeimEntryPoint ( IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm index 8046b43745..d40dad5a52 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm @@ -9,14 +9,14 @@ SECTION .text ;-- -; UINT32 +; UINTN ; EFIAPI -; AsmReadEsp ( +; AsmReadStackPointer ( ; VOID ; ); ;-- -global ASM_PFX(AsmReadEsp) -ASM_PFX(AsmReadEsp): +global ASM_PFX(AsmReadStackPointer) +ASM_PFX(AsmReadStackPointer): mov eax, esp ret diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm index 5a7e27c240..ce20639890 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -9,20 +9,20 @@ ; ;-- -SECTION .text +SECTION .text ;-- ; VOID ; EFIAPI ; SecSwitchStack ( ; UINT32 TemporaryMemoryBase, -; UINT32 PermenentMemoryBase +; UINT32 PermanentMemoryBase ; ); ;-- global ASM_PFX(SecSwitchStack) ASM_PFX(SecSwitchStack): ; -; Save three register: eax, ebx, ecx +; Save four register: eax, ebx, ecx, edx ; push eax push ebx @@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack): mov dword [eax + 12], edx mov edx, dword [esp + 16]; Update this function's return address into permanent memory mov dword [eax + 16], edx -mov esp, eax ; From now, esp is pointed to permanent memory +mov esp, eax ; From now, esp is pointed to permanent memory ; ; Fixup the ebp point to permanent memory @@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack): mov eax, ebp sub eax, ebx add eax, ecx -mov ebp, eax; From now, ebp is pointed to permanent memory +mov ebp, eax ; From now, ebp is pointed to permanent memory pop edx pop ecx diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c index 68e588dd41..85fbc7664c 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -26,7 +26,7 @@ FspGetExceptionHandler ( IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor; FSP_INFO_HEADER *FspInfoHeader; - FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader (); + FspInfoHeader = (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHeader (); ExceptionHandler = IdtEntryTemplate; IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *) Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow; @@ -115,7 +115,7 @@ SecGetPlatformData ( VOID FspGlobalDataInit ( IN OUT FSP_GLOBAL_DATA *PeiFspData, - IN UINT32
[edk2-devel][PATCH v3 2/8] IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64.
2.Added FSPx_UPD_COMMON_FSP24 structures.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 28 +
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 96 +---
IntelFsp2Pkg/Include/FspEas/FspApi.h | 145 -
IntelFsp2Pkg/Tools/GenCfgOpt.py| 4 +-
4 files changed, 254 insertions(+), 19 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index e7261b41cd..9fa9f28030 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -32,6 +32,24 @@ struc FSPM_UPD_COMMON
.size:
endstruc
+struc FSPM_UPD_COMMON_FSP24
+; FSP_UPD_HEADER {
+.FspUpdHeader: resd 8
+; }
+; FSPM_ARCH2_UPD {
+.Revision: resb 1
+.Reserved: resb 3
+.Length resd 1
+.StackBase: resq 1
+.StackSize: resq 1
+.BootLoaderTolumSize: resd 1
+.BootMode: resd 1
+.FspEventHandlerresq 1
+.Reserved1: resb 24
+; }
+.size:
+endstruc
+
;
; Following functions will be provided in C
;
@@ -124,12 +142,22 @@ ASM_PFX(FspApiCommonContinue):
popeax
FspStackSetup:
+ movecx, [edx + FSPM_UPD_COMMON.Revision]
+ cmpecx, 3
+ jaeFspmUpdCommon2
+
;
; StackBase = temp memory base, StackSize = temp memory size
;
movedi, [edx + FSPM_UPD_COMMON.StackBase]
movecx, [edx + FSPM_UPD_COMMON.StackSize]
+ jmpChkFspHeapSize
+
+FspmUpdCommon2:
+ movedi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]
+ movecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]
+ChkFspHeapSize:
;
; Keep using bootloader stack if heap size % is 0
;
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 7fd3d6d843..554b143ffa 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22
.FspUpdHeaderRevision:resb1
.FspUpdHeaderReserved:resb 23
; }
-; FSPT_ARCH_UPD{
-.FsptArchUpd: resd8
+; FSPT_ARCH_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchUpd: resd7
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resd1
@@ -96,6 +98,28 @@ struc LoadMicrocodeParamsFsp22
.size:
endstruc
+struc LoadMicrocodeParamsFsp24
+; FSP_UPD_HEADER {
+.FspUpdHeaderSignature: resd2
+.FspUpdHeaderRevision:resb1
+.FspUpdHeaderReserved:resb 23
+; }
+; FSPT_ARCH2_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchLength: resd1
+.FspDebugHandler resq1
+.FsptArchUpd: resd4
+; }
+; FSPT_CORE_UPD {
+.MicrocodeCodeAddr: resq1
+.MicrocodeCodeSize: resq1
+.CodeRegionBase: resq1
+.CodeRegionSize: resq1
+; }
+.size:
+endstruc
+
;
; Define SSE macros
;
@@ -172,9 +196,9 @@ ASM_PFX(LoadMicrocodeDefault):
; Executed by SBSP and NBSP
; Beginning of microcode update region starts on paragraph boundary
- ;
;
; Save return address to EBP
+ ;
movd ebp, mm7
cmpesp, 0
@@ -188,8 +212,12 @@ ASM_PFX(LoadMicrocodeDefault):
; and report error if size is less than 2k
; first check UPD header revision
cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
- jaeFsp22UpdHeader
+ jb Fsp20UpdHeader
+ cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
+ je Fsp24UpdHeader
+ jmpFsp22UpdHeader
+Fsp20UpdHeader:
; UPD structure is compliant with FSP spec 2.0/2.1
moveax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
cmpeax, 0
@@ -213,6 +241,19 @@ Fsp22UpdHeader:
movesi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
cmpesi, 0
jnzCheckMainHeader
+ jmpParamError
+
+Fsp24UpdHeader:
+ ; UPD structure is compliant with FSP spec 2.4
+ moveax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
+ cmpeax, 0
+ jz Exit2
+ cmpeax, 0800h
+ jl ParamError
+
+ movesi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
+ cmpesi, 0
+ jnzCheckMainHeader
ParamError:
moveax, 08002h
@@ -308,9 +349,13 @@ AdvanceFixedSize:
CheckAddress:
; Check UPD header revision
- cmpbyte [esp +
[edk2-devel][PATCH v3 0/8] Support PEI 64bit in IntelFsp2Pkg and IntelFsp2WrapperPkg
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Currently PEI drivers/libraries only support 32bit in IntelFsp2Pkg and
IntelFsp2WrapperPkg. The patches below are needed to support these
drivers/libraries in 64bit.
V2 changes:
1.Change FSPM_UPD_COMMON2 to FSPM_UPD_COMMON_FSP24 in FspApiEntryM.nasm.
2.Add FSPx_UPD_COMMON_FSP24 in FspApi.h.
3.Add 3 additional patches for supporting X64 in IntelFsp2WrapperPkg.
V3 changes:
1.Update FSPT_ARCH2_UPD and add FSPT_CORE_UPD back.
2.Use 0x instead of MAX_ADDRESS to reflect the default of FspData.
3.Remove EnableMultiPhaseMemoryInit from FSPM_ARCH2_UPD.
4.Bump GenCfgOpt version to 0.57.
Ted Kuo (8):
IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
IntelFsp2Pkg: FspSecCore support for X64
IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
IntelFsp2WrapperPkg: Adopt FSPM_UPD_COMMON_FSP24 for X64
IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 +
IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 8 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 9 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 8 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 10 +-
.../FspSecCore/Ia32/FspApiEntryCommon.nasm | 4 +-
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 28 ++
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 96 +++-
IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 +-
IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +-
IntelFsp2Pkg/FspSecCore/SecFsp.c | 10 +-
IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +-
IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 +-
IntelFsp2Pkg/FspSecCore/SecMain.c | 8 +-
IntelFsp2Pkg/FspSecCore/SecMain.h | 10 +-
IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 +
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 262 +++
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 495 +
IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++
IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 +
IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 +
IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++
IntelFsp2Pkg/Include/FspEas/FspApi.h | 145 +-
IntelFsp2Pkg/Include/FspGlobalData.h | 51 ++-
IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 14 +-
IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284
IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +-
.../Library/BaseFspCommonLib/FspCommonLib.c| 1 +
.../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +-
.../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +-
.../SecFspSecPlatformLibNull.inf | 6 +-
.../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 ++
.../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++
IntelFsp2Pkg/Tools/GenCfgOpt.py| 4 +-
.../FspmWrapperPeim/FspmWrapperPeim.c | 25 +-
.../BaseFspWrapperApiLib/FspWrapperApiLib.c| 42 +-
.../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 21 +
.../BaseFspWrapperApiLib/X64/DispatchExecute.c | 45 +-
.../{Ia32 => }/Fsp.h | 0
.../Ia32/Stack.nasm| 6 +-
.../SecFspWrapperPlatformSecLibSample.inf | 7 +-
.../SecRamInitData.c | 22 +-
.../X64/PeiCoreEntry.nasm | 149 +++
.../X64/SecEntry.nasm | 171 +++
.../X64/Stack.nasm | 73 +++
47 files changed, 2404 insertions(+), 105 deletions(-)
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Stack.nasm
create mode 100644 IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
create mode 100644
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm
create mode 100644
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm
rename
[edk2-devel][PATCH v2 8/8] IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added SecFspWrapperPlatformSecLibSample support for X64.
2.Adopted FSPT_ARCH2_UPD in SecFspWrapperPlatformSecLibSample.
3.Moved Fsp.h up one level to be shared across IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../{Ia32 => }/Fsp.h | 0
.../Ia32/Stack.nasm| 6 +-
.../SecFspWrapperPlatformSecLibSample.inf | 7 +-
.../SecRamInitData.c | 32 ++--
.../X64/PeiCoreEntry.nasm | 149 ++
.../X64/SecEntry.nasm | 171 +
.../X64/Stack.nasm | 73 +
7 files changed, 415 insertions(+), 23 deletions(-)
rename IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/{Ia32 =>
}/Fsp.h (100%)
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/PeiCoreEntry.nasm
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/Stack.nasm
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Fsp.h
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.h
similarity index 100%
rename from
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Fsp.h
rename to IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Fsp.h
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
index d7394cf286..65e9c2e895 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/Stack.nasm
@@ -22,7 +22,7 @@
global ASM_PFX(SecSwitchStack)
ASM_PFX(SecSwitchStack):
;
-; Save three register: eax, ebx, ecx
+; Save four register: eax, ebx, ecx, edx
;
push eax
push ebx
@@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack):
mov dword [eax + 12], edx
mov edx, dword [esp + 16]; Update this function's return address
into permanent memory
mov dword [eax + 16], edx
-mov esp, eax ; From now, esp is pointed to permanent
memory
+mov esp, eax ; From now, esp is pointed to permanent
memory
;
; Fixup the ebp point to permanent memory
@@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack):
mov eax, ebp
sub eax, ebx
add eax, ecx
-mov ebp, eax; From now, ebp is pointed to permanent
memory
+mov ebp, eax ; From now, ebp is pointed to permanent
memory
pop edx
pop ecx
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
index 027b127724..7aa4297bcc 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecFspWrapperPlatformSecLibSample.inf
@@ -39,13 +39,18 @@
SecGetPerformance.c
SecTempRamDone.c
PlatformInit.c
+ Fsp.h
[Sources.IA32]
- Ia32/Fsp.h
Ia32/SecEntry.nasm
Ia32/PeiCoreEntry.nasm
Ia32/Stack.nasm
+[Sources.X64]
+ X64/SecEntry.nasm
+ X64/PeiCoreEntry.nasm
+ X64/Stack.nasm
+
#
# Package Dependency Section - list of Package files that are required for
diff --git
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
index 03616cb418..4464abaca0 100644
---
a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
+++
b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamInitData.c
@@ -9,20 +9,14 @@
#include
#include
-typedef struct {
- UINT32MicrocodeRegionBase;
- UINT32MicrocodeRegionSize;
- UINT32CodeRegionBase;
- UINT32CodeRegionSize;
-} FSPT_CORE_UPD;
-
typedef struct {
FSP_UPD_HEADERFspUpdHeader;
//
- // If platform does not support FSP spec 2.2 remove FSPT_ARCH_UPD structure.
+ // If FSP spec version < 2.2, remove FSPT_ARCH_UPD structure.
+ // Else If FSP spec version >= 2.2 and FSP spec version < 2.4, use
FSPT_ARCH_UPD structure.
+ // Else, use FSPT_ARCH2_UPD structure.
//
- FSPT_ARCH_UPD FsptArchUpd;
- FSPT_CORE_UPD FsptCoreUpd;
+ FSPT_ARCH2_UPDFsptArchUpd;
} FSPT_UPD_CORE_DATA;
GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr = {
@@ -36,24 +30,24 @@
[edk2-devel][PATCH v2 7/8] IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Add Execute64BitCode to execute 64bit code from long mode directly
in PEI 64bit.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../BaseFspWrapperApiLib/FspWrapperApiLib.c| 42 +---
.../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 21 ++
.../BaseFspWrapperApiLib/X64/DispatchExecute.c | 45 +-
3 files changed, 101 insertions(+), 7 deletions(-)
diff --git
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
index 67faad927c..ba4fe3903e 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c
@@ -13,7 +13,7 @@
#include
/**
- Wrapper for a thunk to transition from long mode to compatibility mode to
execute 32-bit code and then transit back to
+ Wrapper for a thunk to transition from long mode to compatibility mode to
execute 32-bit code and then transit back to
long mode.
@param[in] Function The 32bit code entry to be executed.
@@ -29,6 +29,22 @@ Execute32BitCode (
IN UINT64 Param2
);
+/**
+ Wrapper to execute 64-bit code directly from long mode.
+
+ @param[in] Function The 64bit code entry to be executed.
+ @param[in] Param1 The first parameter to pass to 64bit code.
+ @param[in] Param2 The second parameter to pass to 64bit code.
+
+ @return EFI_STATUS.
+**/
+EFI_STATUS
+Execute64BitCode (
+ IN UINT64 Function,
+ IN UINT64 Param1,
+ IN UINT64 Param2
+ );
+
/**
Find FSP header pointer.
@@ -94,7 +110,11 @@ CallFspNotifyPhase (
NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase +
FspHeader->NotifyPhaseEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)NotifyPhaseApi,
(UINTN)NotifyPhaseParams, (UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -127,7 +147,11 @@ CallFspMemoryInit (
FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase +
FspHeader->FspMemoryInitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)FspMemoryInitApi,
(UINTN)FspmUpdDataPtr, (UINTN)HobListPtr);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr,
(UINTN)HobListPtr);
+ } else {
+Status = Execute64BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDataPtr,
(UINTN)HobListPtr);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -158,7 +182,11 @@ CallTempRamExit (
TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase +
FspHeader->TempRamExitEntryOffset);
InterruptState = SaveAndDisableInterrupts ();
- Status = Execute32BitCode ((UINTN)TempRamExitApi,
(UINTN)TempRamExitParam, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam,
(UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam,
(UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
@@ -189,7 +217,11 @@ CallFspSiliconInit (
FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase +
FspHeader->FspSiliconInitEntryOffset);
InterruptState= SaveAndDisableInterrupts ();
- Status= Execute32BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) ==
FSP_IA32) {
+Status = Execute32BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ } else {
+Status = Execute64BitCode ((UINTN)FspSiliconInitApi,
(UINTN)FspsUpdDataPtr, (UINTN)NULL);
+ }
SetInterruptState (InterruptState);
return Status;
diff --git
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
index 4f6a8dd1a7..a22ed2d539 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute.c
@@ -49,3 +49,24 @@ Execute32BitCode (
return Status;
}
+
+/**
+ Wrapper for a thunk to transition from compatibility mode to long mode to
execute 64-bit code and then transit back to
+ compatibility mode.
+
+ @param[in] Function The 64bit code entry to
[edk2-devel][PATCH v2 6/8] IntelFsp2WrapperPkg: Adopt FSPM_UPD_COMMON_FSP24 for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Adopt FSPM_UPD_COMMON_FSP24 in FspmWrapperPeim to support X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 25 ++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index b0c6b2f8a6..62a34467e0 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -71,7 +71,7 @@ PeiFspMemoryInit (
UINT64 TimeStampCounterStart;
VOID *FspHobListPtr;
VOID *HobData;
- FSPM_UPD_COMMON *FspmUpdDataPtr;
+ VOID *FspmUpdDataPtr;
UINTN*SourceData;
DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
@@ -89,7 +89,7 @@ PeiFspMemoryInit (
//
// Copy default FSP-M UPD data from Flash
//
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)AllocateZeroPool
((UINTN)FspmHeaderPtr->CfgRegionSize);
+FspmUpdDataPtr = AllocateZeroPool ((UINTN)FspmHeaderPtr->CfgRegionSize);
ASSERT (FspmUpdDataPtr != NULL);
SourceData = (UINTN *)((UINTN)FspmHeaderPtr->ImageBase +
(UINTN)FspmHeaderPtr->CfgRegionOffset);
CopyMem (FspmUpdDataPtr, SourceData, (UINTN)FspmHeaderPtr->CfgRegionSize);
@@ -97,17 +97,24 @@ PeiFspMemoryInit (
//
// External UPD is ready, get the buffer from PCD pointer.
//
-FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress();
+FspmUpdDataPtr = (VOID *) GetFspmUpdDataAddress();
ASSERT (FspmUpdDataPtr != NULL);
}
DEBUG ((DEBUG_INFO, "UpdateFspmUpdData enter\n"));
- UpdateFspmUpdData ((VOID *)FspmUpdDataPtr);
- DEBUG ((DEBUG_INFO, " NvsBufferPtr- 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.NvsBufferPtr));
- DEBUG ((DEBUG_INFO, " StackBase - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.StackBase));
- DEBUG ((DEBUG_INFO, " StackSize - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.StackSize));
- DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.BootLoaderTolumSize));
- DEBUG ((DEBUG_INFO, " BootMode- 0x%x\n",
FspmUpdDataPtr->FspmArchUpd.BootMode));
+ UpdateFspmUpdData (FspmUpdDataPtr);
+ if (((FSPM_UPD_COMMON *)FspmUpdDataPtr)->FspmArchUpd.Revision >= 3) {
+DEBUG ((DEBUG_INFO, " StackBase - 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.StackBase));
+DEBUG ((DEBUG_INFO, " StackSize - 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.StackSize));
+DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize));
+DEBUG ((DEBUG_INFO, " BootMode- 0x%x\n",
((FSPM_UPD_COMMON_FSP24 *)FspmUpdDataPtr)->FspmArchUpd.BootMode));
+ } else {
+DEBUG ((DEBUG_INFO, " NvsBufferPtr- 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.NvsBufferPtr));
+DEBUG ((DEBUG_INFO, " StackBase - 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.StackBase));
+DEBUG ((DEBUG_INFO, " StackSize - 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.StackSize));
+DEBUG ((DEBUG_INFO, " BootLoaderTolumSize - 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.BootLoaderTolumSize));
+DEBUG ((DEBUG_INFO, " BootMode- 0x%x\n", ((FSPM_UPD_COMMON
*)FspmUpdDataPtr)->FspmArchUpd.BootMode));
+ }
DEBUG ((DEBUG_INFO, " HobListPtr - 0x%x\n", ));
TimeStampCounterStart = AsmReadTsc ();
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#88399): https://edk2.groups.io/g/devel/message/88399
Mute This Topic: https://groups.io/mt/90235999/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v2 5/8] IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspSecPlatformLibNull support for X64. 2.Added X64 support to IntelFsp2Pkg.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +- .../SecFspSecPlatformLibNull.inf | 6 +++- .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 + .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++ 4 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index c1414f7e75..1284aa042c 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -12,7 +12,7 @@ PLATFORM_VERSION = 0.1 DSC_SPECIFICATION = 0x00010005 OUTPUT_DIRECTORY = Build/IntelFsp2Pkg - SUPPORTED_ARCHITECTURES= IA32 + SUPPORTED_ARCHITECTURES= IA32|X64 BUILD_TARGETS = DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER = DEFAULT diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf index 42e7d83c32..ef859d5ea5 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf @@ -23,7 +23,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # @@ -39,6 +39,10 @@ Ia32/Flat32.nasm Ia32/SecCarInit.nasm +[Sources.X64] + X64/Long64.nasm + X64/SecCarInit.nasm + # # Package Dependency Section - list of Package files that are required for diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm new file mode 100644 index 00..836257f962 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm @@ -0,0 +1,31 @@ +;; @file +; This is the code that performs early platform initialization. +; It consumes the reset vector, configures the stack. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +extern ASM_PFX(TempRamInitApi) + +SECTION .text + +%macro RET_RSI 0 + + movdrsi, mm7 ; restore RSI from MM7 + jmp rsi + +%endmacro + +; +; Perform early platform initialization +; +global ASM_PFX(SecPlatformInit) +ASM_PFX(SecPlatformInit): + + RET_RSI + diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm new file mode 100644 index 00..e64c77ed18 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm @@ -0,0 +1,40 @@ +;; @file +; SEC CAR function +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +%macro RET_RSI 0 + + movdrsi, mm7 ; move ReturnAddress from MM7 to RSI + jmp rsi + +%endmacro + +SECTION .text + +;- +; +; Section: SecCarInit +; +; Description: This function initializes the Cache for Data, Stack, and Code +; +;- +global ASM_PFX(SecCarInit) +ASM_PFX(SecCarInit): + + ; + ; Set up CAR + ; + + xorrax, rax + +SecCarInitExit: + + RET_RSI + -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88398): https://edk2.groups.io/g/devel/message/88398 Mute This Topic: https://groups.io/mt/90235998/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v2 3/8] IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support
both IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +-
IntelFsp2Pkg/Include/FspGlobalData.h | 51 +---
2 files changed, 37 insertions(+), 16 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 85fbc7664c..1ead3c9ce6 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -130,7 +130,7 @@ FspGlobalDataInit (
ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA));
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;
- PeiFspData->Version = 0;
+ PeiFspData->Version = FSP_GLOBAL_DATA_VERSION;
PeiFspData->CoreStack = BootLoaderStack;
PeiFspData->PerfIdx = 2;
PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;
diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h
b/IntelFsp2Pkg/Include/FspGlobalData.h
index 2b534075ae..dcfeed7501 100644
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -10,8 +10,9 @@
#include
-#define FSP_IN_API_MODE 0
-#define FSP_IN_DISPATCH_MODE 1
+#define FSP_IN_API_MODE 0
+#define FSP_IN_DISPATCH_MODE1
+#define FSP_GLOBAL_DATA_VERSION 1
#pragma pack(1)
@@ -28,10 +29,11 @@ typedef enum {
typedef struct {
VOID *DataPtr;
- UINT32MicrocodeRegionBase;
- UINT32MicrocodeRegionSize;
- UINT32CodeRegionBase;
- UINT32CodeRegionSize;
+ UINTN MicrocodeRegionBase;
+ UINTN MicrocodeRegionSize;
+ UINTN CodeRegionBase;
+ UINTN CodeRegionSize;
+ UINTN Reserved;
} FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURESIGNATURE_32 ('F', 'S', 'P', 'D')
@@ -42,15 +44,15 @@ typedef struct {
UINT32 Signature;
UINT8 Version;
UINT8 Reserved1[3];
+ ///
+ /// Offset 0x08
+ ///
UINTN CoreStack;
+ UINTN Reserved2;
+ ///
+ /// IA32: Offset 0x10; X64: Offset 0x18
+ ///
UINT32 StatusCode;
- UINT32 Reserved2[8];
- FSP_PLAT_DATA PlatformData;
- FSP_INFO_HEADER*FspInfoHeader;
- VOID *UpdDataPtr;
- VOID *TempRamInitUpdPtr;
- VOID *MemoryInitUpdPtr;
- VOID *SiliconInitUpdPtr;
UINT8 ApiIdx;
///
/// 0: FSP in API mode; 1: FSP in DISPATCH mode
@@ -60,15 +62,34 @@ typedef struct {
UINT8 Reserved3;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
+ UINT32 Reserved4[8];
///
+ /// IA32: Offset 0x40; X64: Offset 0x48
+ /// Start of UINTN and pointer section
+ /// All UINTN and pointer members must be put in this section
+ /// except CoreStack and Reserved2. In addition, the number of
+ /// UINTN and pointer members must be even for natural alignment
+ /// in both IA32 and X64.
+ ///
+ FSP_PLAT_DATA PlatformData;
+ VOID *TempRamInitUpdPtr;
+ VOID *MemoryInitUpdPtr;
+ VOID *SiliconInitUpdPtr;
+ ///
+ /// IA32: Offset 0x64; X64: Offset 0x90
/// To store function parameters pointer
/// so it can be retrieved after stack switched.
///
VOID *FunctionParameterPtr;
- UINT8 Reserved4[16];
+ FSP_INFO_HEADER*FspInfoHeader;
+ VOID *UpdDataPtr;
+ ///
+ /// End of UINTN and pointer section
+ ///
+ UINT8 Reserved5[16];
UINT32 PerfSig;
UINT16 PerfLen;
- UINT16 Reserved5;
+ UINT16 Reserved6;
UINT32 PerfIdx;
UINT64 PerfData[32];
} FSP_GLOBAL_DATA;
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#88396): https://edk2.groups.io/g/devel/message/88396
Mute This Topic: https://groups.io/mt/90235996/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v2 2/8] IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64.
2.Added FSPx_UPD_COMMON_FSP24 structures.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 29 +
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 93 +++--
IntelFsp2Pkg/Include/FspEas/FspApi.h | 172 -
IntelFsp2Pkg/Tools/GenCfgOpt.py| 2 +-
4 files changed, 278 insertions(+), 18 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index e7261b41cd..de7f916070 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -32,6 +32,25 @@ struc FSPM_UPD_COMMON
.size:
endstruc
+struc FSPM_UPD_COMMON_FSP24
+; FSP_UPD_HEADER {
+.FspUpdHeader: resd 8
+; }
+; FSPM_ARCH2_UPD {
+.Revision: resb 1
+.Reserved: resb 3
+.Length resd 1
+.StackBase: resq 1
+.StackSize: resq 1
+.BootLoaderTolumSize: resd 1
+.BootMode: resd 1
+.FspEventHandlerresq 1
+.EnableMultiPhaseMemoryInit resb 1
+.Reserved1: resb 23
+; }
+.size:
+endstruc
+
;
; Following functions will be provided in C
;
@@ -124,12 +143,22 @@ ASM_PFX(FspApiCommonContinue):
popeax
FspStackSetup:
+ movecx, [edx + FSPM_UPD_COMMON.Revision]
+ cmpecx, 3
+ jaeFspmUpdCommon2
+
;
; StackBase = temp memory base, StackSize = temp memory size
;
movedi, [edx + FSPM_UPD_COMMON.StackBase]
movecx, [edx + FSPM_UPD_COMMON.StackSize]
+ jmpChkFspHeapSize
+
+FspmUpdCommon2:
+ movedi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]
+ movecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]
+ChkFspHeapSize:
;
; Keep using bootloader stack if heap size % is 0
;
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 7fd3d6d843..25ef99b798 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22
.FspUpdHeaderRevision:resb1
.FspUpdHeaderReserved:resb 23
; }
-; FSPT_ARCH_UPD{
-.FsptArchUpd: resd8
+; FSPT_ARCH_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchUpd: resd7
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resd1
@@ -96,6 +98,25 @@ struc LoadMicrocodeParamsFsp22
.size:
endstruc
+struc LoadMicrocodeParamsFsp24
+; FSP_UPD_HEADER {
+.FspUpdHeaderSignature: resd2
+.FspUpdHeaderRevision:resb1
+.FspUpdHeaderReserved:resb 23
+; }
+; FSPT_ARCH2_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchLength: resd1
+.FspDebugHandler resq1
+.MicrocodeCodeAddr: resq1
+.MicrocodeCodeSize: resq1
+.CodeRegionBase: resq1
+.CodeRegionSize: resq1
+; }
+.size:
+endstruc
+
;
; Define SSE macros
;
@@ -172,9 +193,9 @@ ASM_PFX(LoadMicrocodeDefault):
; Executed by SBSP and NBSP
; Beginning of microcode update region starts on paragraph boundary
- ;
;
; Save return address to EBP
+ ;
movd ebp, mm7
cmpesp, 0
@@ -188,8 +209,12 @@ ASM_PFX(LoadMicrocodeDefault):
; and report error if size is less than 2k
; first check UPD header revision
cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
- jaeFsp22UpdHeader
+ jb Fsp20UpdHeader
+ cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
+ je Fsp24UpdHeader
+ jmpFsp22UpdHeader
+Fsp20UpdHeader:
; UPD structure is compliant with FSP spec 2.0/2.1
moveax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
cmpeax, 0
@@ -213,6 +238,19 @@ Fsp22UpdHeader:
movesi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
cmpesi, 0
jnzCheckMainHeader
+ jmpParamError
+
+Fsp24UpdHeader:
+ ; UPD structure is compliant with FSP spec 2.4
+ moveax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
+ cmpeax, 0
+ jz Exit2
+ cmpeax, 0800h
+ jl ParamError
+
+ movesi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
+ cmpesi, 0
+ jnzCheckMainHeader
ParamError:
moveax, 08002h
@@ -308,9 +346,13 @@ AdvanceFixedSize:
CheckAddress:
; Check UPD header revision
- cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
- jaeFsp22UpdHeader1
[edk2-devel][PATCH v2 4/8] IntelFsp2Pkg: FspSecCore support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 9 +- IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 10 +- .../FspSecCore/Ia32/FspApiEntryCommon.nasm | 4 +- IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 + IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 263 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 492 + IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++ IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 + IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 + IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++ IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 14 +- IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284 .../Library/BaseFspCommonLib/FspCommonLib.c| 1 + .../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +- 18 files changed, 1473 insertions(+), 11 deletions(-) create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc create mode 100644 IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Stack.nasm create mode 100644 IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf index 0a24eb2a8b..d64ec12499 100644 --- a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/Fsp22ApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf index 7b05cae641..34794dd16e 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -34,6 +34,13 @@ Ia32/FspHelper.nasm Ia32/ReadEsp.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryM.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + X64/ReadRsp.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf index 1d9c2554d1..79d4e0674e 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf index 664bde5678..f08a3b2c2b 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf @@ -17,17 +17,19 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # -[Sources] - - [Sources.IA32] Ia32/Stack.nasm Ia32/FspApiEntryT.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryT.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm index
[edk2-devel][PATCH v2 0/8] Support PEI 64bit in IntelFsp2Pkg and IntelFsp2WrapperPkg
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Currently PEI drivers/libraries only support 32bit in IntelFsp2Pkg and
IntelFsp2WrapperPkg. The patches below are needed to support these
drivers/libraries in 64bit.
V2 changes:
1.Change FSPM_UPD_COMMON2 to FSPM_UPD_COMMON_FSP24 in FspApiEntryM.nasm.
2.Add FSPx_UPD_COMMON_FSP24 in FspApi.h.
3.Add 3 additional patches for supporting X64 in IntelFsp2WrapperPkg.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
Ted Kuo (8):
IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
IntelFsp2Pkg: FspSecCore support for X64
IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
IntelFsp2WrapperPkg: Adopt FSPM_UPD_COMMON_FSP24 for X64
IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64
IntelFsp2WrapperPkg: SecFspWrapperPlatformSecLibSample support for X64
IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 +
IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 8 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 9 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 8 +-
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 10 +-
.../FspSecCore/Ia32/FspApiEntryCommon.nasm | 4 +-
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 29 ++
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 93 +++-
IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 +-
IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +-
IntelFsp2Pkg/FspSecCore/SecFsp.c | 10 +-
IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +-
IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 +-
IntelFsp2Pkg/FspSecCore/SecMain.c | 8 +-
IntelFsp2Pkg/FspSecCore/SecMain.h | 10 +-
IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 +
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 263 +++
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 492 +
IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++
IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 +
IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 +
IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++
IntelFsp2Pkg/Include/FspEas/FspApi.h | 172 ++-
IntelFsp2Pkg/Include/FspGlobalData.h | 51 ++-
IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 14 +-
IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284
IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +-
.../Library/BaseFspCommonLib/FspCommonLib.c| 1 +
.../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +-
.../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +-
.../SecFspSecPlatformLibNull.inf | 6 +-
.../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 ++
.../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++
IntelFsp2Pkg/Tools/GenCfgOpt.py| 2 +-
.../FspmWrapperPeim/FspmWrapperPeim.c | 25 +-
.../BaseFspWrapperApiLib/FspWrapperApiLib.c| 42 +-
.../BaseFspWrapperApiLib/IA32/DispatchExecute.c| 21 +
.../BaseFspWrapperApiLib/X64/DispatchExecute.c | 45 +-
.../{Ia32 => }/Fsp.h | 0
.../Ia32/Stack.nasm| 6 +-
.../SecFspWrapperPlatformSecLibSample.inf | 7 +-
.../SecRamInitData.c | 32 +-
.../X64/PeiCoreEntry.nasm | 149 +++
.../X64/SecEntry.nasm | 171 +++
.../X64/Stack.nasm | 73 +++
47 files changed, 2426 insertions(+), 114 deletions(-)
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm
create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Stack.nasm
create mode 100644 IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
create mode 100644
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm
create mode 100644
IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm
rename IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/{Ia32 =>
}/Fsp.h (100%)
create mode 100644
IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSamp
[edk2-devel][PATCH v2 1/8] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added EFIAPI to FspNotifyPhasePeimEntryPoint. 2.Changed AsmReadEsp to AsmReadStackPointer. 3.Changed the type of the return value of AsmReadStackPointer from UINT32 to UINTN. 4.Changed the type of TemporaryMemoryBase, PermenentMemoryBase and BootLoaderStack from UINT32 to UINTN. 5.Some type casting to pointers are UINT32. Changed them to UINTN to accommodate both IA32 and X64. 6.Corrected some typos. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 + IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +- IntelFsp2Pkg/FspSecCore/SecFsp.c | 8 IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 IntelFsp2Pkg/FspSecCore/SecMain.c | 8 IntelFsp2Pkg/FspSecCore/SecMain.h | 10 +- IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- 9 files changed, 29 insertions(+), 28 deletions(-) diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c index 88f5540fef..66d39cc70c 100644 --- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c +++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c @@ -112,6 +112,7 @@ WaitForNotify ( @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database **/ EFI_STATUS +EFIAPI FspNotifyPhasePeimEntryPoint ( IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm index 8046b43745..d40dad5a52 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm @@ -9,14 +9,14 @@ SECTION .text ;-- -; UINT32 +; UINTN ; EFIAPI -; AsmReadEsp ( +; AsmReadStackPointer ( ; VOID ; ); ;-- -global ASM_PFX(AsmReadEsp) -ASM_PFX(AsmReadEsp): +global ASM_PFX(AsmReadStackPointer) +ASM_PFX(AsmReadStackPointer): mov eax, esp ret diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm index 5a7e27c240..ce20639890 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -9,20 +9,20 @@ ; ;-- -SECTION .text +SECTION .text ;-- ; VOID ; EFIAPI ; SecSwitchStack ( ; UINT32 TemporaryMemoryBase, -; UINT32 PermenentMemoryBase +; UINT32 PermanentMemoryBase ; ); ;-- global ASM_PFX(SecSwitchStack) ASM_PFX(SecSwitchStack): ; -; Save three register: eax, ebx, ecx +; Save four register: eax, ebx, ecx, edx ; push eax push ebx @@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack): mov dword [eax + 12], edx mov edx, dword [esp + 16]; Update this function's return address into permanent memory mov dword [eax + 16], edx -mov esp, eax ; From now, esp is pointed to permanent memory +mov esp, eax ; From now, esp is pointed to permanent memory ; ; Fixup the ebp point to permanent memory @@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack): mov eax, ebp sub eax, ebx add eax, ecx -mov ebp, eax; From now, ebp is pointed to permanent memory +mov ebp, eax ; From now, ebp is pointed to permanent memory pop edx pop ecx diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c index 68e588dd41..85fbc7664c 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -26,7 +26,7 @@ FspGetExceptionHandler ( IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor; FSP_INFO_HEADER *FspInfoHeader; - FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader (); + FspInfoHeader = (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHeader (); ExceptionHandler = IdtEntryTemplate; IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *) Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow; @@ -115,7 +115,7 @@ SecGetPlatformData ( VOID FspGlobalDataInit ( IN OUT FSP_GLOBAL_DATA *PeiFspData, - IN UINT32
[edk2-devel][PATCH 5/5] IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspSecPlatformLibNull support for X64. 2.Added X64 support to IntelFsp2Pkg.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +- .../SecFspSecPlatformLibNull.inf | 6 +++- .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 + .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++ 4 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index c1414f7e75..1284aa042c 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -12,7 +12,7 @@ PLATFORM_VERSION = 0.1 DSC_SPECIFICATION = 0x00010005 OUTPUT_DIRECTORY = Build/IntelFsp2Pkg - SUPPORTED_ARCHITECTURES= IA32 + SUPPORTED_ARCHITECTURES= IA32|X64 BUILD_TARGETS = DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER = DEFAULT diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf index 42e7d83c32..ef859d5ea5 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf @@ -23,7 +23,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # @@ -39,6 +39,10 @@ Ia32/Flat32.nasm Ia32/SecCarInit.nasm +[Sources.X64] + X64/Long64.nasm + X64/SecCarInit.nasm + # # Package Dependency Section - list of Package files that are required for diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm new file mode 100644 index 00..836257f962 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm @@ -0,0 +1,31 @@ +;; @file +; This is the code that performs early platform initialization. +; It consumes the reset vector, configures the stack. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +extern ASM_PFX(TempRamInitApi) + +SECTION .text + +%macro RET_RSI 0 + + movdrsi, mm7 ; restore RSI from MM7 + jmp rsi + +%endmacro + +; +; Perform early platform initialization +; +global ASM_PFX(SecPlatformInit) +ASM_PFX(SecPlatformInit): + + RET_RSI + diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm new file mode 100644 index 00..e64c77ed18 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm @@ -0,0 +1,40 @@ +;; @file +; SEC CAR function +; +; Copyright (c) 2022, Intel Corporation. All rights reserved. +; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +%macro RET_RSI 0 + + movdrsi, mm7 ; move ReturnAddress from MM7 to RSI + jmp rsi + +%endmacro + +SECTION .text + +;- +; +; Section: SecCarInit +; +; Description: This function initializes the Cache for Data, Stack, and Code +; +;- +global ASM_PFX(SecCarInit) +ASM_PFX(SecCarInit): + + ; + ; Set up CAR + ; + + xorrax, rax + +SecCarInitExit: + + RET_RSI + -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88392): https://edk2.groups.io/g/devel/message/88392 Mute This Topic: https://groups.io/mt/90234877/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH 3/5] IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support
both IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +-
IntelFsp2Pkg/Include/FspGlobalData.h | 51 +---
2 files changed, 37 insertions(+), 16 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 85fbc7664c..1ead3c9ce6 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -130,7 +130,7 @@ FspGlobalDataInit (
ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA));
PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;
- PeiFspData->Version = 0;
+ PeiFspData->Version = FSP_GLOBAL_DATA_VERSION;
PeiFspData->CoreStack = BootLoaderStack;
PeiFspData->PerfIdx = 2;
PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;
diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h
b/IntelFsp2Pkg/Include/FspGlobalData.h
index 2b534075ae..dcfeed7501 100644
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -10,8 +10,9 @@
#include
-#define FSP_IN_API_MODE 0
-#define FSP_IN_DISPATCH_MODE 1
+#define FSP_IN_API_MODE 0
+#define FSP_IN_DISPATCH_MODE1
+#define FSP_GLOBAL_DATA_VERSION 1
#pragma pack(1)
@@ -28,10 +29,11 @@ typedef enum {
typedef struct {
VOID *DataPtr;
- UINT32MicrocodeRegionBase;
- UINT32MicrocodeRegionSize;
- UINT32CodeRegionBase;
- UINT32CodeRegionSize;
+ UINTN MicrocodeRegionBase;
+ UINTN MicrocodeRegionSize;
+ UINTN CodeRegionBase;
+ UINTN CodeRegionSize;
+ UINTN Reserved;
} FSP_PLAT_DATA;
#define FSP_GLOBAL_DATA_SIGNATURESIGNATURE_32 ('F', 'S', 'P', 'D')
@@ -42,15 +44,15 @@ typedef struct {
UINT32 Signature;
UINT8 Version;
UINT8 Reserved1[3];
+ ///
+ /// Offset 0x08
+ ///
UINTN CoreStack;
+ UINTN Reserved2;
+ ///
+ /// IA32: Offset 0x10; X64: Offset 0x18
+ ///
UINT32 StatusCode;
- UINT32 Reserved2[8];
- FSP_PLAT_DATA PlatformData;
- FSP_INFO_HEADER*FspInfoHeader;
- VOID *UpdDataPtr;
- VOID *TempRamInitUpdPtr;
- VOID *MemoryInitUpdPtr;
- VOID *SiliconInitUpdPtr;
UINT8 ApiIdx;
///
/// 0: FSP in API mode; 1: FSP in DISPATCH mode
@@ -60,15 +62,34 @@ typedef struct {
UINT8 Reserved3;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
+ UINT32 Reserved4[8];
///
+ /// IA32: Offset 0x40; X64: Offset 0x48
+ /// Start of UINTN and pointer section
+ /// All UINTN and pointer members must be put in this section
+ /// except CoreStack and Reserved2. In addition, the number of
+ /// UINTN and pointer members must be even for natural alignment
+ /// in both IA32 and X64.
+ ///
+ FSP_PLAT_DATA PlatformData;
+ VOID *TempRamInitUpdPtr;
+ VOID *MemoryInitUpdPtr;
+ VOID *SiliconInitUpdPtr;
+ ///
+ /// IA32: Offset 0x64; X64: Offset 0x90
/// To store function parameters pointer
/// so it can be retrieved after stack switched.
///
VOID *FunctionParameterPtr;
- UINT8 Reserved4[16];
+ FSP_INFO_HEADER*FspInfoHeader;
+ VOID *UpdDataPtr;
+ ///
+ /// End of UINTN and pointer section
+ ///
+ UINT8 Reserved5[16];
UINT32 PerfSig;
UINT16 PerfLen;
- UINT16 Reserved5;
+ UINT16 Reserved6;
UINT32 PerfIdx;
UINT64 PerfData[32];
} FSP_GLOBAL_DATA;
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#88390): https://edk2.groups.io/g/devel/message/88390
Mute This Topic: https://groups.io/mt/90234871/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH 4/5] IntelFsp2Pkg: FspSecCore support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 9 +- IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 10 +- .../FspSecCore/Ia32/FspApiEntryCommon.nasm | 4 +- IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 + IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 263 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 492 + IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++ IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 + IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 + IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++ IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 14 +- IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284 .../Library/BaseFspCommonLib/FspCommonLib.c| 1 + .../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +- 18 files changed, 1473 insertions(+), 11 deletions(-) create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc create mode 100644 IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Stack.nasm create mode 100644 IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf index 0a24eb2a8b..d64ec12499 100644 --- a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/Fsp22ApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf index 7b05cae641..34794dd16e 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -34,6 +34,13 @@ Ia32/FspHelper.nasm Ia32/ReadEsp.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryM.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + X64/ReadRsp.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf index 1d9c2554d1..79d4e0674e 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf @@ -17,7 +17,7 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # [Sources] @@ -30,6 +30,12 @@ Ia32/FspApiEntryCommon.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryS.nasm + X64/FspApiEntryCommon.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf index 664bde5678..f08a3b2c2b 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf @@ -17,17 +17,19 @@ # # The following information is for reference only and not required by the build tools. # -# VALID_ARCHITECTURES = IA32 +# VALID_ARCHITECTURES = IA32 X64 # -[Sources] - - [Sources.IA32] Ia32/Stack.nasm Ia32/FspApiEntryT.nasm Ia32/FspHelper.nasm +[Sources.X64] + X64/Stack.nasm + X64/FspApiEntryT.nasm + X64/FspHelper.nasm + [Binaries.Ia32] RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm index
[edk2-devel][PATCH 2/5] IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
Added FSPx_ARCH2_UPD structures which support both IA32 and X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 29 ++
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 93 +++---
IntelFsp2Pkg/Include/FspEas/FspApi.h | 128 -
IntelFsp2Pkg/Tools/GenCfgOpt.py| 2 +-
4 files changed, 234 insertions(+), 18 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index e7261b41cd..2fe235a237 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -32,6 +32,25 @@ struc FSPM_UPD_COMMON
.size:
endstruc
+struc FSPM_UPD_COMMON2
+; FSP_UPD_HEADER {
+.FspUpdHeader: resd 8
+; }
+; FSPM_ARCH2_UPD {
+.Revision: resb 1
+.Reserved: resb 3
+.Length resd 1
+.StackBase: resq 1
+.StackSize: resq 1
+.BootLoaderTolumSize: resd 1
+.BootMode: resd 1
+.FspEventHandlerresq 1
+.EnableMultiPhaseMemoryInit resb 1
+.Reserved1: resb 23
+; }
+.size:
+endstruc
+
;
; Following functions will be provided in C
;
@@ -124,12 +143,22 @@ ASM_PFX(FspApiCommonContinue):
popeax
FspStackSetup:
+ movecx, [edx + FSPM_UPD_COMMON.Revision]
+ cmpecx, 3
+ jaeFspmUpdCommon2
+
;
; StackBase = temp memory base, StackSize = temp memory size
;
movedi, [edx + FSPM_UPD_COMMON.StackBase]
movecx, [edx + FSPM_UPD_COMMON.StackSize]
+ jmpChkFspHeapSize
+
+FspmUpdCommon2:
+ movedi, [edx + FSPM_UPD_COMMON2.StackBase]
+ movecx, [edx + FSPM_UPD_COMMON2.StackSize]
+ChkFspHeapSize:
;
; Keep using bootloader stack if heap size % is 0
;
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 7fd3d6d843..25ef99b798 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22
.FspUpdHeaderRevision:resb1
.FspUpdHeaderReserved:resb 23
; }
-; FSPT_ARCH_UPD{
-.FsptArchUpd: resd8
+; FSPT_ARCH_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchUpd: resd7
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resd1
@@ -96,6 +98,25 @@ struc LoadMicrocodeParamsFsp22
.size:
endstruc
+struc LoadMicrocodeParamsFsp24
+; FSP_UPD_HEADER {
+.FspUpdHeaderSignature: resd2
+.FspUpdHeaderRevision:resb1
+.FspUpdHeaderReserved:resb 23
+; }
+; FSPT_ARCH2_UPD {
+.FsptArchRevision:resb1
+.FsptArchReserved:resb3
+.FsptArchLength: resd1
+.FspDebugHandler resq1
+.MicrocodeCodeAddr: resq1
+.MicrocodeCodeSize: resq1
+.CodeRegionBase: resq1
+.CodeRegionSize: resq1
+; }
+.size:
+endstruc
+
;
; Define SSE macros
;
@@ -172,9 +193,9 @@ ASM_PFX(LoadMicrocodeDefault):
; Executed by SBSP and NBSP
; Beginning of microcode update region starts on paragraph boundary
- ;
;
; Save return address to EBP
+ ;
movd ebp, mm7
cmpesp, 0
@@ -188,8 +209,12 @@ ASM_PFX(LoadMicrocodeDefault):
; and report error if size is less than 2k
; first check UPD header revision
cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
- jaeFsp22UpdHeader
+ jb Fsp20UpdHeader
+ cmpbyte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
+ je Fsp24UpdHeader
+ jmpFsp22UpdHeader
+Fsp20UpdHeader:
; UPD structure is compliant with FSP spec 2.0/2.1
moveax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]
cmpeax, 0
@@ -213,6 +238,19 @@ Fsp22UpdHeader:
movesi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]
cmpesi, 0
jnzCheckMainHeader
+ jmpParamError
+
+Fsp24UpdHeader:
+ ; UPD structure is compliant with FSP spec 2.4
+ moveax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
+ cmpeax, 0
+ jz Exit2
+ cmpeax, 0800h
+ jl ParamError
+
+ movesi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]
+ cmpesi, 0
+ jnzCheckMainHeader
ParamError:
moveax, 08002h
@@ -308,9 +346,13 @@ AdvanceFixedSize:
CheckAddress:
; Check UPD header revision
- cmpbyte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
- jaeFsp22UpdHeader1
+ cmp byte [esp +
[edk2-devel][PATCH 1/5] IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added EFIAPI to FspNotifyPhasePeimEntryPoint. 2.Changed AsmReadEsp to AsmReadStackPointer. 3.Changed the type of the return value of AsmReadStackPointer from UINT32 to UINTN. 4.Changed the type of TemporaryMemoryBase, PermenentMemoryBase and BootLoaderStack from UINT32 to UINTN. 5.Some type casting to pointers are UINT32. Changed them to UINTN to accommodate both IA32 and X64. 6.Corrected some typos. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 + IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +- IntelFsp2Pkg/FspSecCore/SecFsp.c | 8 IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 IntelFsp2Pkg/FspSecCore/SecMain.c | 8 IntelFsp2Pkg/FspSecCore/SecMain.h | 10 +- IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- 9 files changed, 29 insertions(+), 28 deletions(-) diff --git a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c index 88f5540fef..66d39cc70c 100644 --- a/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c +++ b/IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c @@ -112,6 +112,7 @@ WaitForNotify ( @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database **/ EFI_STATUS +EFIAPI FspNotifyPhasePeimEntryPoint ( IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm index 8046b43745..d40dad5a52 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm @@ -9,14 +9,14 @@ SECTION .text ;-- -; UINT32 +; UINTN ; EFIAPI -; AsmReadEsp ( +; AsmReadStackPointer ( ; VOID ; ); ;-- -global ASM_PFX(AsmReadEsp) -ASM_PFX(AsmReadEsp): +global ASM_PFX(AsmReadStackPointer) +ASM_PFX(AsmReadStackPointer): mov eax, esp ret diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm index 5a7e27c240..ce20639890 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -9,20 +9,20 @@ ; ;-- -SECTION .text +SECTION .text ;-- ; VOID ; EFIAPI ; SecSwitchStack ( ; UINT32 TemporaryMemoryBase, -; UINT32 PermenentMemoryBase +; UINT32 PermanentMemoryBase ; ); ;-- global ASM_PFX(SecSwitchStack) ASM_PFX(SecSwitchStack): ; -; Save three register: eax, ebx, ecx +; Save four register: eax, ebx, ecx, edx ; push eax push ebx @@ -55,7 +55,7 @@ ASM_PFX(SecSwitchStack): mov dword [eax + 12], edx mov edx, dword [esp + 16]; Update this function's return address into permanent memory mov dword [eax + 16], edx -mov esp, eax ; From now, esp is pointed to permanent memory +mov esp, eax ; From now, esp is pointed to permanent memory ; ; Fixup the ebp point to permanent memory @@ -63,7 +63,7 @@ ASM_PFX(SecSwitchStack): mov eax, ebp sub eax, ebx add eax, ecx -mov ebp, eax; From now, ebp is pointed to permanent memory +mov ebp, eax ; From now, ebp is pointed to permanent memory pop edx pop ecx diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c index 68e588dd41..85fbc7664c 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -26,7 +26,7 @@ FspGetExceptionHandler ( IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor; FSP_INFO_HEADER *FspInfoHeader; - FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader (); + FspInfoHeader = (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHeader (); ExceptionHandler = IdtEntryTemplate; IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *) Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow; @@ -115,7 +115,7 @@ SecGetPlatformData ( VOID FspGlobalDataInit ( IN OUT FSP_GLOBAL_DATA *PeiFspData, - IN UINT32
[edk2-devel][PATCH 0/5] To support PEI 64bit in IntelFsp2Pkg
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 Currently PEI drivers/libraries only support 32bit in IntelFsp2Pkg. The patches below are needed to support these drivers/libraries in 64bit. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo Ted Kuo (5): IntelFsp2Pkg: X64 compatible changes to support PEI in 64bit IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64 IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64 IntelFsp2Pkg: FspSecCore support for X64 IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64 IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.c | 1 + IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf | 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf| 9 +- IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf| 8 +- IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf| 10 +- .../FspSecCore/Ia32/FspApiEntryCommon.nasm | 4 +- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 29 ++ IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 93 +++- IntelFsp2Pkg/FspSecCore/Ia32/ReadEsp.nasm | 8 +- IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm| 10 +- IntelFsp2Pkg/FspSecCore/SecFsp.c | 10 +- IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 8 +- IntelFsp2Pkg/FspSecCore/SecMain.c | 8 +- IntelFsp2Pkg/FspSecCore/SecMain.h | 10 +- IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm| 103 + IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 76 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 263 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm | 67 +++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 492 + IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 34 ++ IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc | 11 + IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm | 22 + IntelFsp2Pkg/FspSecCore/X64/Stack.nasm | 73 +++ IntelFsp2Pkg/Include/FspEas/FspApi.h | 128 +- IntelFsp2Pkg/Include/FspGlobalData.h | 51 ++- IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 14 +- IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 284 IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +- .../Library/BaseFspCommonLib/FspCommonLib.c| 1 + .../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 5 +- .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- .../SecFspSecPlatformLibNull.inf | 6 +- .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 ++ .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++ IntelFsp2Pkg/Tools/GenCfgOpt.py| 2 +- 36 files changed, 1850 insertions(+), 75 deletions(-) create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Fsp22ApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryS.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/MicrocodeLoadNasm.inc create mode 100644 IntelFsp2Pkg/FspSecCore/X64/ReadRsp.nasm create mode 100644 IntelFsp2Pkg/FspSecCore/X64/Stack.nasm create mode 100644 IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88387): https://edk2.groups.io/g/devel/message/88387 Mute This Topic: https://groups.io/mt/90234850/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][PATCH 1/2] MdeModulePkg: StackOffset must be aligned to a 16-byte boundary in X64
Hi Marvin,
Please find my inline comments with [Ted2].
Thanks,
Ted
-Original Message-
From: Marvin Häuser
Sent: Tuesday, March 22, 2022 5:27 PM
To: Kuo, Ted
Cc: devel@edk2.groups.io; Kinney, Michael D ; Bi,
Dandan ; Gao, Liming ; De,
Debkumar ; Han, Harry ; West,
Catharine ; Wang, Jian J
Subject: Re: [edk2-devel][PATCH 1/2] MdeModulePkg: StackOffset must be aligned
to a 16-byte boundary in X64
Good day,
Thanks for the updates!
> On 22. Mar 2022, at 08:23, Kuo, Ted wrote:
>
> Hi Marvin,
>
> Good day. Thanks for your valuable comments. After checking all of your
> comments, I decide to drop the patches and close the bugzilla ticket since
> the changes should be specific to X64 in IntelFspPkg. You still can find my
> inline comments with [Ted] for your questions.
>
> Thanks,
> Ted
>
> -Original Message-
> From: Marvin Häuser
> Sent: Tuesday, March 22, 2022 3:46 AM
> To: devel@edk2.groups.io; Kuo, Ted
> Cc: Kinney, Michael D ; Bi, Dandan
> ; Gao, Liming ; De,
> Debkumar ; Han, Harry ;
> West, Catharine ; Wang, Jian J
>
> Subject: Re: [edk2-devel][PATCH 1/2] MdeModulePkg: StackOffset must be
> aligned to a 16-byte boundary in X64
>
> Good day,
>
> Thanks for the update!
>
>> On 21.03.22 13:43, Kuo, Ted wrote:
>> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3865
>> For X64, StackOffset must be aligned to a 16-byte boundary as well as
>> old stack and new stack. Otherwise, it'll get wrong data from Private
>> pointer after switching from old stack to new stack.
>>
>> Cc: Michael D Kinney
>> Cc: Dandan Bi
>> Cc: Liming Gao
>> Cc: Debkumar De
>> Cc: Harry Han
>> Cc: Catharine West
>> Cc: Jian J Wang
>> Cc: Marvin Häuser
>> Signed-off-by: Ted Kuo
>> ---
>> MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c | 18
>> +-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
>> b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
>> index 3552feda8f..8a2c1ec779 100644
>> --- a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
>> +++ b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
>> @@ -823,6 +823,19 @@ PeiCheckAndSwitchStack (
>> (VOID **)
>> );
>> if (!EFI_ERROR (Status)) {
>> + //
>> + // For X64, StackOffset must be aligned to a 16-byte boundary.
>> Otherwise, it'll get wrong data
>> + // from Private pointer after switching to new stack.
>> + //
>> + if ((sizeof (UINTN) == sizeof (UINT64)) && ((StackOffset & 0x0F) ==
>> 8)) {
>> +if (StackOffsetPositive == TRUE) {
>> + StackOffset -= 8;
>> +} else {
>> + StackOffset += 8;
>> +}
>> +Private->StackOffset = StackOffset;
>> + }
>> +
>
> Hmm, the overall design (not your patch) looks very broken to me. So, if the
> PPI exists, it's responsible for the migration of the stack, but it is
> neither passed where to migrate the stack to, nor does it return where it did
> migrate it to. This means the StackOffset calculated here may be out-of-sync
> with what actually happens in the PPI, e.g., if the PPI code is changed.
> There also is no detailed explanation for the memory layout with FSP separate
> stack vs bootloader shared stack, so I cannot really give detailed comments
> quickly. *Sigh*.
>
> Anyhow, as for the patch, I do not understand a few things:
>
> 1) Maybe most important of all, what even is broken? Which address is not
> 16-Byte-aligned to cause this issue in the first place?
> [Ted]: CPU will generate exception when running some X64 instructions which
> need input/output memory address to be 16-Byte-aligned.
Yes, I understood as much. I built a chain of reasoning for alignment in the
response for the first revision, because a proper fix needs knowledge of which
assumption is wrong in the first place. The question is, which *exact* value in
the chain is not 16-Byte aligned, and should it be? Did you ever print all
involved values, like PhysicalMemoryBegin (or whatever its name was, sorry, I’m
responding from mobile)?
[Ted2]: Yes, I confirmed that no issue with the current design in Dispatcher.c.
The unaligned stack offset I observed was caused by the unaligned TopOfOldStack
which is produced by sum of SecCoreData->StackBase and SecCoreData->StackSize.
In my case, SecCoreData is provided by FspSecCore. Hence we need to ensure
SecCoreData->StackBase and SecCoreData->StackSize provided by FspSecCore are
16-byte-aligned instead of making changes in Dispatcher.c in MdeMod
Re: [edk2-devel][PATCH 1/2] MdeModulePkg: StackOffset must be aligned to a 16-byte boundary in X64
Hi Marvin,
Good day. Thanks for your valuable comments. After checking all of your
comments, I decide to drop the patches and close the bugzilla ticket since the
changes should be specific to X64 in IntelFspPkg. You still can find my inline
comments with [Ted] for your questions.
Thanks,
Ted
-Original Message-
From: Marvin Häuser
Sent: Tuesday, March 22, 2022 3:46 AM
To: devel@edk2.groups.io; Kuo, Ted
Cc: Kinney, Michael D ; Bi, Dandan
; Gao, Liming ; De, Debkumar
; Han, Harry ; West, Catharine
; Wang, Jian J
Subject: Re: [edk2-devel][PATCH 1/2] MdeModulePkg: StackOffset must be aligned
to a 16-byte boundary in X64
Good day,
Thanks for the update!
On 21.03.22 13:43, Kuo, Ted wrote:
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3865
> For X64, StackOffset must be aligned to a 16-byte boundary as well as
> old stack and new stack. Otherwise, it'll get wrong data from Private
> pointer after switching from old stack to new stack.
>
> Cc: Michael D Kinney
> Cc: Dandan Bi
> Cc: Liming Gao
> Cc: Debkumar De
> Cc: Harry Han
> Cc: Catharine West
> Cc: Jian J Wang
> Cc: Marvin Häuser
> Signed-off-by: Ted Kuo
> ---
> MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c | 18 +-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
> b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
> index 3552feda8f..8a2c1ec779 100644
> --- a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
> +++ b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
> @@ -823,6 +823,19 @@ PeiCheckAndSwitchStack (
> (VOID **)
> );
> if (!EFI_ERROR (Status)) {
> + //
> + // For X64, StackOffset must be aligned to a 16-byte boundary.
> Otherwise, it'll get wrong data
> + // from Private pointer after switching to new stack.
> + //
> + if ((sizeof (UINTN) == sizeof (UINT64)) && ((StackOffset & 0x0F) ==
> 8)) {
> +if (StackOffsetPositive == TRUE) {
> + StackOffset -= 8;
> +} else {
> + StackOffset += 8;
> +}
> +Private->StackOffset = StackOffset;
> + }
> +
Hmm, the overall design (not your patch) looks very broken to me. So, if the
PPI exists, it's responsible for the migration of the stack, but it is neither
passed where to migrate the stack to, nor does it return where it did migrate
it to. This means the StackOffset calculated here may be out-of-sync with what
actually happens in the PPI, e.g., if the PPI code is changed. There also is no
detailed explanation for the memory layout with FSP separate stack vs
bootloader shared stack, so I cannot really give detailed comments quickly.
*Sigh*.
Anyhow, as for the patch, I do not understand a few things:
1) Maybe most important of all, what even is broken? Which address is not
16-Byte-aligned to cause this issue in the first place?
[Ted]: CPU will generate exception when running some X64 instructions which
need input/output memory address to be 16-Byte-aligned.
2) Why do you align StackOffset? Like yes, if the old top of the stack and the
offset to the new top of the stack are both 16-Byte-aligned, then the new top
of the stack is 16-Byte-aligned too. However, StackOffset is more of a
by-product and TopOfNewStack remains holding the old value. I just don't really
understand the idea of this approach.
[Ted]: Since new stack must keep the original stack alignment as old stack, it
means stack offset must be 16-Byte-aligned too. And the OldStack/NewStack in
the fsp patch indicates the *current* old/new stack. The fsp patch just makes
left shift 8-byte of whole used stack data when new stack not aligning with old
stack. Hence I think no need to update TopOfNewStack.
e.g.
case1:
old stack: 0xfef5e000
new stack: 0x49c8f3b0
stack: 0x9c8f3b0 -> 16-Byte-aligned
case2:
old stack: 0xfef5e008
new stack: 0x49c8f3b8
stack: 0x9c8f3b0 -> 16-Byte-aligned
3) This only works when StackOffset is guaranteed to be 8-Byte-aligned (is
it?). As we are dealing with the *top* of the stack (which should be 4K-aligned
even for memory protection!), what would be wrong with just aligning down and
up instead?
(Same question for the second patch to the FSP code)
As my answer in Q2, what we adjust in the fsp patch is the new "current" stack
in order to keep the same stack alignment as old stack after switching stack.
Top of the new stack remains unchanged. If StackOffset is not adjusted
accordingly, bios will get wrong data from Private pointer after switching to
new stack.
4) The next patch performs a similar alignment operation (as mentioned before).
However, while this patch aligns the *top* of the stack, the FSP patch aligns
the *bottom* of the stack. This may or may not be correct based on your
premises. Can you maybe d
[edk2-devel][PATCH 2/2] IntelFsp2Pkg: Ensure new stack is aligned to old stack for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3865
Ensure bit3:0 of NewStack is aligned with bit3:0 of OldStack for X64
before switching stack. Otherwise, RSP may not be aligned to a 16-byte
boundary after returning from SecTemporaryRamSupport.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecMain.c | 8
1 file changed, 8 insertions(+)
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c
b/IntelFsp2Pkg/FspSecCore/SecMain.c
index d376fb8361..f93e2d2ff7 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -258,6 +258,14 @@ SecTemporaryRamSupport (
NewStack = (VOID *)(UINTN)PermanentMemoryBase;
}
+ //
+ // Ensure bit3:0 of NewStack is aligned with bit3:0 of OldStack for X64
before switching stack.
+ // Otherwise, RSP may not be aligned to a 16-byte boundary after returning
from SecTemporaryRamSupport.
+ //
+ if ((sizeof (UINTN) == sizeof (UINT64)) && (((UINTN)NewStack & 0x0F) !=
((UINTN)OldStack & 0x0F))) {
+NewStack = (VOID *)((UINTN)NewStack - 8);
+ }
+
//
// Migrate Heap
//
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#87793): https://edk2.groups.io/g/devel/message/87793
Mute This Topic: https://groups.io/mt/89926608/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH 1/2] MdeModulePkg: StackOffset must be aligned to a 16-byte boundary in X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3865
For X64, StackOffset must be aligned to a 16-byte boundary as well as
old stack and new stack. Otherwise, it'll get wrong data from Private
pointer after switching from old stack to new stack.
Cc: Michael D Kinney
Cc: Dandan Bi
Cc: Liming Gao
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Jian J Wang
Cc: Marvin Häuser
Signed-off-by: Ted Kuo
---
MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
index 3552feda8f..8a2c1ec779 100644
--- a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
+++ b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
@@ -823,6 +823,19 @@ PeiCheckAndSwitchStack (
(VOID **)
);
if (!EFI_ERROR (Status)) {
+ //
+ // For X64, StackOffset must be aligned to a 16-byte boundary.
Otherwise, it'll get wrong data
+ // from Private pointer after switching to new stack.
+ //
+ if ((sizeof (UINTN) == sizeof (UINT64)) && ((StackOffset & 0x0F) == 8)) {
+if (StackOffsetPositive == TRUE) {
+ StackOffset -= 8;
+} else {
+ StackOffset += 8;
+}
+Private->StackOffset = StackOffset;
+ }
+
//
// Heap Offset
//
@@ -852,7 +865,10 @@ PeiCheckAndSwitchStack (
// Temporary Ram Support PPI is provided by platform, it will copy
// temporary memory to permanent memory and do stack switching.
// After invoking Temporary Ram Support PPI, the following code's
- // stack is in permanent memory.
+ // stack is in permanent memory. For X64, the bit3:0 of the new stack
+ // produced by TemporaryRamMigration must be aligned with the bit3:0 of
+ // the old stack. Otherwise, it'll break the original stack alignment
+ // after switching to new stack.
//
TemporaryRamSupportPpi->TemporaryRamMigration (
PeiServices,
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#87792): https://edk2.groups.io/g/devel/message/87792
Mute This Topic: https://groups.io/mt/89926603/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH 0/2] Ensure RSP is aligned to a 16-byte boundary for PEI 64bit
The changes ensure the same stack alignment is kept before and after swithing stack in X64. Ted Kuo (2): MdeModulePkg: StackOffset must be aligned to a 16-byte boundary in X64 IntelFsp2Pkg: Ensure new stack is aligned to old stack for X64 IntelFsp2Pkg/FspSecCore/SecMain.c | 8 MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c | 18 +- 2 files changed, 25 insertions(+), 1 deletion(-) -- 2.16.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87791): https://edk2.groups.io/g/devel/message/87791 Mute This Topic: https://groups.io/mt/89926595/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel][PATCH] MdeModulePkg: Make RSP 16-byte boundary aligned for PEI 64bit
Thanks Marvin for your feedback. I think your direction is right. The original
stack alignment is correct before switching to new stack but the current
implementation in SecCore's SecTemporaryRamSupport() will break the stack
alignment after switching to new stack. We need to ensure the new stack and
stack offset have same alignment as well as the old stack. I'll resend a new
patch to keep the stack alignment aligned before and after switching stack.
Thanks,
Ted
-Original Message-
From: Marvin Häuser
Sent: Thursday, March 17, 2022 7:09 PM
To: devel@edk2.groups.io; Kuo, Ted
Cc: Bi, Dandan ; Gao, Liming ;
De, Debkumar ; Han, Harry ; West,
Catharine ; Wang, Jian J ; S,
Ashraf Ali ; Kinney, Michael D
Subject: Re: [edk2-devel][PATCH] MdeModulePkg: Make RSP 16-byte boundary
aligned for PEI 64bit
Good day,
> On 17. Mar 2022, at 02:05, Kuo, Ted wrote:
>
> Hi Liming and Mike,
>
> Can you please review the change?
>
> Thanks,
> Ted
>
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Kuo,
> Ted
> Sent: Thursday, March 10, 2022 2:21 PM
> To: devel@edk2.groups.io
> Cc: Bi, Dandan ; Gao, Liming
> ; De, Debkumar ; Han,
> Harry ; West, Catharine
> ; Wang, Jian J ; S,
> Ashraf Ali
> Subject: [edk2-devel][PATCH] MdeModulePkg: Make RSP 16-byte boundary
> aligned for PEI 64bit
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3865
> Use SwitchPeiCore instead of calling PeiCore directly when switching
> PeiCore from temporary memory to permanent memory. For PEI 32bit,
> SwitchPeiCore always calls PeiCore without any additional step. For
> PEI 64bit, SwitchPeiCore makes RSP 16-byte boundary aligned and then
> allocate 32 bytes as a shadow store on call stack before calling PeiCore.
>
> Cc: Dandan Bi
> Cc: Liming Gao
> Cc: Debkumar De
> Cc: Harry Han
> Cc: Catharine West
> Cc: Jian J Wang
> Cc: Ashraf Ali S
> Signed-off-by: Ted Kuo
> ---
> MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c | Â 2 +-
> Â MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm | 33
> +++
> MdeModulePkg/Core/Pei/PeiMain.h   | 25 ++
> MdeModulePkg/Core/Pei/PeiMain.inf | Â 6 +
> MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm  | 38
> +++
> 5 files changed, 103 insertions(+), 1 deletion(-) Â create mode 100644
> MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
> create mode 100644 MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm
>
> diff --git a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
> b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
> index 3552feda8f..5af6e6e86f 100644
> --- a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
> +++ b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
> @@ -871,7 +871,7 @@ PeiCheckAndSwitchStack (
> Â Â //
> Â Â // Entry PEI Phase 2
> Â Â //
> - Â PeiCore (SecCoreData, NULL, Private);
> + Â SwitchPeiCore (SecCoreData, NULL, Private);
> } else {
> Â Â //
> Â Â // Migrate memory pages allocated in pre-memory phase.
> diff --git a/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
> b/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
> new file mode 100644
> index 00..23cfb5090b
> --- /dev/null
> +++ b/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
> @@ -0,0 +1,33 @@
> +;
> +--
> +
> +;
> +; Copyright (c) 2022, Intel Corporation. All rights reserved. ;
> +SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract:
> +;
> +; Â Â Switch PeiCore from temporary memory to permanent memory.
> +;
> +;
> +--
> +
> +
> + Â Â Â SECTION .text
> +
> +extern ASM_PFX(PeiCore)
> +
> +;
> +--
> +
> +; VOID
> +; EFIAPI
> +; SwitchPeiCore (
> +; Â Â EFI_SEC_PEI_HAND_OFF Â Â Â *SecCoreDataPtr, ; Â Â
> +EFI_PEI_PPI_DESCRIPTOR Â *PpiList, ; Â Â VOID Â Â Â *Data ; Â Â
> +);
> +;
> +--
> +
> +global ASM_PFX(SwitchPeiCore)
> +ASM_PFX(SwitchPeiCore):
> +  push   DWORD [esp + 12]
> +  push   DWORD [esp + 12]
> +  push   DWORD [esp + 12]
> +  call   ASM_PFX(PeiCore)
> +  jmp    $    ; Should never reach here
> + Â ret
> +
I think there were efforts in the past to avoid ASM whenever possible.
Can’t this just remain a C function (for IA32 only of course) and if not,
wouldn't a simple jmp instruction be sufficient?
> diff --git a/MdeModulePkg/Core/Pei/PeiMain.h
> b/MdeModulePkg/Core/Pei/PeiMain.h index 556beddad5..8e8ed3dadf 100644
> --- a/MdeModulePkg/Core/P
[edk2-devel][PATCH] UefiCpuPkg: Update BFV searching algorithm in VTF0
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3870
The new algorithm searches FFS3 GUID first and then FFS2 GUID at
every 4KB address in the top 16MB just below 4GB.
Cc: Ray Ni
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Min Xu
Signed-off-by: Ted Kuo
---
.../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 548 -> 532 bytes
.../ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw | Bin 516 -> 500 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw | Bin 932 -> 900 bytes
.../Bin/X64/PageTable1G/ResetVector.x64.port80.raw | Bin 12292 -> 12292 bytes
.../Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw| Bin 12292 -> 12292 bytes
.../Bin/X64/PageTable1G/ResetVector.x64.serial.raw | Bin 12292 -> 12292 bytes
.../Bin/X64/PageTable2M/ResetVector.x64.port80.raw | Bin 28676 -> 28676 bytes
.../Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw| Bin 28676 -> 28676 bytes
.../Bin/X64/PageTable2M/ResetVector.x64.serial.raw | Bin 28676 -> 28676 bytes
.../ResetVector/Vtf0/Ia32/SearchForBfvBase.asm | 19 +--
10 files changed, 5 insertions(+), 14 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
index
23254e83bf1a17dee9f38c235fcc9948624a7536..a3601274c25dde665872ff375f1deadf1c838476
100644
GIT binary patch
delta 190
zcmZ3&}9%{V6bIiVEA7Y*;pY^b)Yz;RJO4~e>a??t=
z8!KcwpPS4oWqPdwR8{e`r>FENP?c?$jDP7KpsJasor$HJfvQ>$>s~Hh)m)*%P`ae^
zFmr@L>D<@68#X*^*s*-2o*Lifq#%B#L8KWjnif8;k@l&;M&40Z#en#=M9m)(0
p4*W_7(q6?+ZeUbk^qjnqQF!tuMib78|1Z`5{r~@R;pF#>rU2NrRB!+Q
delta 211
zcmbQjvV^660uUG;*vZVmz@W<@z`$S)9RYyQbxs@7N`P<5a2DnL~gPkVYw4**r!cFFjcZU?HGY1)}sx(=wS^|0>c
z(xuH6Dh#FbI}bBQD3s24Eoykcv-u}uY2Sto!p|CZ><5C*qp$yU9^J6dOQg~Z-`xoM@`
zjTJJTYR}(^GmBsLHlW#=mqAP}NM+`WbuX8$YOYXWC|%Nd
zm^nhBbna`;9s7Zx^XTh;okw3fGBPk2-tN3Nabf`DyNQp=gu9|NoybVe$kLTf4OV)8Aly`5
delta 202
zcmeyu+`>{n0SF8a>||zOV9;d{U|_HXGX59EHUDHTRcoves5(#_Qu?g1LgcjVDc{n&
zjTI7m^W~3nW7tMv416`-n$r#(HT2Y{+C)y36^7FJorjqt6iR2j7BoEI+5D5Sv~S0L?*04scOHHHuk+|j`-v6djBh4hC>L(~
zub0NpD4w=MnSsH9U+F;FtK7*^j4~W{6XY2t{Qv)das#6oNB2vMfB*l#+%tI}qZt4b
C>RJ*2
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
index
e4aa4fc30a32bc3d4d8d0e1726c43fdafef4a374..48b46e3473e77a1179bf818a1f1deafb7e46cf3e
100644
GIT binary patch
delta 206
zcmZ3&-oidXwqBLl@PICZ00V<90|UeVqR7SyfvN+=A*Hg76(Xl?Px+RLG*(FL&6k^2
z%H3EY)A`(FRw>hK6`-n$r#(HTM}ewryJY-J_W)JRH0?|*-3(OKdRX^z>8j=m6^7C!
zorjqt6iVm5_DtLLm-)>Kg_7@SyM8clNO}k1Ph3~VXf;`t@fKssB|pc_!-61
zb|^D2IPfbSNPA^C`4CeKhus8uh6(@w|DSBatS4~b(Cv;e|i4T|Nk!!PA+0L
F0svn-S`YvL
delta 228
zcmZo+U&1~?w%(Q5@W4)H1_lOQ1_1^JTOi|qQC#y+=2ErB3W2Hv#UZ878Y@Ij+n(|*
zz1vtJu{U3CTIrR>3YpI5CbLRUzg7XNs(9MdQ+fcX%C<|!zjQlL)lAdQ#L{&@Rjr40
zFPAQDu25kpo!@zwIYOay#_K@C1D?%48B6=pcKv0ZcvWh02cy!?K-?lZ6>?F&0gJ
z$GBd&=D%JVKcjfs4rK-g2Y#gkX|I$gZ(xcM^O+#eFya6I{}WKaWD#aPfdzkFGrj)y
TlJ)<~^?&~Vf4O;b5VH{gPc~z_
diff --git
a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.port80.raw
index
51ad3ecde0e4e02e91ed299ec207e9f7460524b3..def0ec856d0d14b4ea11b0a33db1512077eae00f
100644
GIT binary patch
delta 296
zcmZokXi3<>rckfTAi%(2%fP_!zbLY?LZIqEaY(6bV};0R+f%-!B8?Rid-LU{m2x*$
z$aFq8nN`a4S_P=8;%QG$=~196+b$XZ(mg;`Gfg`aOE&{mwI0^JT)L{cLWQApN#|ka
z2!+zQuX#6Yc-F9EKM-^tef_WV=!T8Y8eUFfWMDA7J$br96r=g%PYP4a%Rc`9FTt=O
z1t>QM=$;)67ykd}SGw`~=mxQ84Zn6XeCWHq`@~1RG=4_$v>nO}3=aHC2hv`xnY>p~
zfzw5u;Q~rcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^t{?AX75Kkxp|qp$yU9^J6rckfTAi%(2%fP_!zbLY?LZIqEaY(6bV};0R+f%-!B8?Rid-LU{m2x*$
z$aFq8nN`a4S_P=8;%QG$=~196+b$XZ(mg;`Gfg`aOE&{mwI0^JT)L{cLWQApN#|ka
z2!+zQuQ_+@2ZGL{um5!(ec8pxz+ia0^IqqRwC-4g$rcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^tSd%lXob(@m2qS`Tp(
zR?6L2A=CNXWL7EDYZaiXil;q2rAL9PY`bLqOZNa(%{1*yEZq!L)p}U>a_Oq(3KfRZ
zC7p+vBNR=Mp^_Th03WbvIX}f+fZ%BFv;ZI(tP{w#@vZ~@O#y69crZBclo~q==
zC_4F$l8(lW(EcZT?PRL23sKGe^FfXPv%m!#tMO|1H~bw)R4PTQXH
zExp@VA+a}KZd#tNCv=O(jCPrp_Hs;YR}(^Gl?sLHlW#=mqsP}NM+`W
zbuX7LZLUyZD4pMVm^nhBbjIsI!vmhpKN(B=(suo2o_tk7YI297(?bK8yz@3oG7Y
zd^P!<;uOYdlbe;?7=ws9pHVz*hcW|$1HaONv{yEhHI-x7z10~OeE$D`
za-Xt|sK%eyOs~JaWc{LlaYFRlLqiMq}AmA`T;ynOX}0tf*8#t;_b#xP;R%gYcE
Huh!SMFv=?PJc=951qOffI}`2W8I
z!-f=~+#H~Lb}%|DRv!#_OXS#GW<$+RgBx@AmE!ANA7s8O76fC^IlP@GBiid$nfr
z-b4jX7j=dUKh!#EoIXgqO?^5wP$C0AK}^xBvhE
delta 272
zcmZp9z}WJDaRXaI{Z3{E1_oUQ0R{$JAme{gT=P%nQnkhkfvN+=A*Ih6D@0D)p7Jfd
z+gKs7H(zdA>6OL`na<}Xvr13DRspK2c-qrbdH|@(woAspbURShOw-Q9(se*pt%r3l
zmo9CtP+=+7ohLZNiVYf-}kp3OfQOZzr#c-F9E|Ni~F`#X=m{?~bQ!^UR~FZ(Aq
zB*ZhCOn#6sg{R}=|NjyU8(kTjsF%jiD4w=MnSsH9U+F;Ft9_GKCn~Tz
zsxv$Qs-1i#(UR|V!^;PM|NnoP^AAXvOqNNKV4Sc~Z~?EvORY~6Kmh1PhOiJfh6xj1
K3PVJ|!V>^C=zwYf
diff --git
a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw
index
Re: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in SearchForBfvBase.asm
Hi Ray,
No, I'll send patch to update the searching algorithm.
Thanks,
Ted
-Original Message-
From: Ni, Ray
Sent: Thursday, March 17, 2022 1:21 PM
To: devel@edk2.groups.io; Ni, Ray ; Kuo, Ted
Cc: De, Debkumar ; Han, Harry ;
West, Catharine ; Xu, Min M
Subject: RE: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in
SearchForBfvBase.asm
Ted,
Have you considered a case that BFV is a FFS2 FV and the logic may find a FFS3
FV just below the BFV?
Thanks,
Ray
-Original Message-
From: devel@edk2.groups.io On Behalf Of Ni, Ray
Sent: Friday, March 11, 2022 3:42 PM
To: Kuo, Ted ; devel@edk2.groups.io
Cc: De, Debkumar ; Han, Harry ;
West, Catharine
Subject: Re: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in
SearchForBfvBase.asm
Reviewed-by: Ray Ni
-Original Message-
From: Kuo, Ted
Sent: Friday, March 11, 2022 3:29 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; De, Debkumar ; Han,
Harry ; West, Catharine
Subject: [edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in
SearchForBfvBase.asm
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3862
The new algorithm searches BFV address with FFS3 GUID first.
If not found, it will search BFV address with FFS2 GUID.
Cc: Ray Ni
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Signed-off-by: Ted Kuo
---
.../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 484 -> 548 bytes
.../ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw | Bin 468 -> 516 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw | Bin 868 -> 932 bytes
.../Bin/X64/PageTable1G/ResetVector.x64.port80.raw | Bin 12292 -> 12292 bytes
.../Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw | Bin 12292 -> 12292 bytes
.../Bin/X64/PageTable1G/ResetVector.x64.serial.raw | Bin 12292 -> 12292 bytes
.../Bin/X64/PageTable2M/ResetVector.x64.port80.raw | Bin 28676 -> 28676 bytes
.../Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
.../Bin/X64/PageTable2M/ResetVector.x64.serial.raw | Bin 28676 -> 28676 bytes
.../ResetVector/Vtf0/Ia32/SearchForBfvBase.asm | 51 +
10 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
index
79b23c047bdc6e552d77d5c9e9aeae21ff04d91d..23254e83bf1a17dee9f38c235fcc9948624a7536
100644 GIT binary patch delta 227
zcmaFDyo9BG0uUG;*vZVmz@W<@z`$S)9RYyQbxs@7N`P<5a2DnL~gPkVYw4**r!cFFjcZU?HGY1)}sx(=wS^|0>c
z(xuH6Dh#FbI}bBQD3s24Eoykcv-u}uY2Sto!p|CZ><5C*qp$yU9^J6;8$wu(9TV=}(c8
zUjg)y@_Q48|1M?^0T*VtBLDzE4S>dJ0U!uIkRJe$|NsA!umLp*>x1c7{{R2!
Mtds8n6_W!3A^UepbpQYW
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
index
ce7faa502b858e99908bcdb397b776258205e1d5..18562d8f1f58601f66fcb0cbf2f994046ce48fde
100644 GIT binary patch delta 225
zcmcb@+`>{n0SF8a>||zOV9;d{U|_HXGX59EHUDHTRcoves5(#_Qu?g1LgcjVDc{n&
zjTI7m^W~3nW7tMv416`-n$r#(HT2Y{+C)y36^7FJorjqt6iR2j7BoEI+5D5Sv~S0L?*04scOHHHuk+|j`-wr}jBh5cDmQQY
zub0NpD4w=MnSsH9U+F;FtK9$p{|hkeaA0F#;8%K(wu6JA??`Yyb-n;_3H
Z0jOYd0;3s6_e+a^|Np<-GkG4P833r5W}5&2
delta 153
zcmZo+xxySY0SF8a=rRZ}FxWCMF#InvZmbZfc-qrb`ns_~#I{Suzw}XKg~UwL
zjTJJjhjlNPUTCgRVJJP-d6+puq4e-;>)Kp!4YKf1O8Px=-v1XZ$kpQMqv4f4ww*
zM)9;A$_xw+{7MJXUZqaXVU!VYn;_3H;s5{tAge)O@^>vc|Nj4fxn=S>Ml%58
CZbm==
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
index
6503a988abdac06f9aa88f0a65f2525e12233b0a..e4aa4fc30a32bc3d4d8d0e1726c43fdafef4a374
100644 GIT binary patch delta 214
zcmaFDwuF6xY`rV9;enmZ3=9mq3<3-cwm`=JqPXUt%%y6L6#`WUibG1DHCBk6wms!r
zdbhDcVsF0Ow9+e$6*8UAO=gvzeysvjRq?c^r}O|=df9ZChs+p#piKXj+s#*{0
zUM^kQT%p2HI=}NUbA&?ajMssN2Rxg9GM4tG?fT0+F{OjiW8`AFs>J_`LCD8
z@Lz#iWfnVuB+AHPBT}&|oJ`>~_Cj9^Ze*zRte#c}Yu;9;Yrq|zIvi^U${?Gsa
LFE>v%Vm1N**#ci0
delta 146
zcmV;D0B!%I2jm8j9YX~JF~BVV5C8x@00030ax;N=5P0Q`jCJdQcoaQ~98Y!Pfp{31
zHHl$$*@1W*g~Kh=brcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^t{?AX75Kkxp|qp$yU9^J6Bj4$8^oS9{Mya%q3`zYTOak(_!-61
zb|^D2IPfbSNPD$!a;u^OyQ4b81EBWFTNEw%UN^ja@b~}!mpT7{gvsPTiV}
delta 259
zcmZokXi3<>rVygbAi%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK
z$h02Tysxk81Z^i=0z<_Lw-!>@TaY`>8ANp?ZUi48fjh|6GZHF=g
zg9E?PfwWg`llLkr@O!Brcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^tq;e#OWC
z|0Nh+`|M`_}ygvDBH^Ya%+q?ID)Jx-M6i?fs%)sEluXG^o)w0RCiZc9u
z>I@fv+9p83MyJRzkL7q|Noc8|A2(?|NsAY0P%kh#bX|dM?DmecyvDa|7^m9
eje;9^6<$hx0&4}@$q*Le#xP;ROJ;}$oEHj+dD
delta 239
zcmZokXi3<>rr@K?Ai%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK
z$h02Tysxk81Z^i=0z<_Lw-!>>7a><5C*qp$yU9(`Fqxl19OQD^cag(*P}AOHWC
zV0bwdXz(3;+M~E8Tc~^4D}G_Hw|&%0<7X64+o8{
z27aXnX*)O=`fl_c=zGxjqVK|MS9OL7K>5iR6m9ulx4bm?_y7OP8W3SKSw=~Mal%Hy
e54;L5Z+)Bq0zms1!b02_CQNvF7$O1
Re: [edk2-devel][PATCH] MdeModulePkg: Make RSP 16-byte boundary aligned for PEI 64bit
Hi Liming and Mike,
Can you please review the change?
Thanks,
Ted
-Original Message-
From: devel@edk2.groups.io On Behalf Of Kuo, Ted
Sent: Thursday, March 10, 2022 2:21 PM
To: devel@edk2.groups.io
Cc: Bi, Dandan ; Gao, Liming ;
De, Debkumar ; Han, Harry ; West,
Catharine ; Wang, Jian J ; S,
Ashraf Ali
Subject: [edk2-devel][PATCH] MdeModulePkg: Make RSP 16-byte boundary aligned
for PEI 64bit
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3865
Use SwitchPeiCore instead of calling PeiCore directly when switching PeiCore
from temporary memory to permanent memory. For PEI 32bit, SwitchPeiCore always
calls PeiCore without any additional step. For PEI 64bit, SwitchPeiCore makes
RSP 16-byte boundary aligned and then allocate 32 bytes as a shadow store on
call stack before calling PeiCore.
Cc: Dandan Bi
Cc: Liming Gao
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Jian J Wang
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c | 2 +-
MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm | 33 +++
MdeModulePkg/Core/Pei/PeiMain.h | 25 ++
MdeModulePkg/Core/Pei/PeiMain.inf | 6 +
MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm | 38 +++
5 files changed, 103 insertions(+), 1 deletion(-) create mode 100644
MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
create mode 100644 MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm
diff --git a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
index 3552feda8f..5af6e6e86f 100644
--- a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
+++ b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
@@ -871,7 +871,7 @@ PeiCheckAndSwitchStack (
//
// Entry PEI Phase 2
//
- PeiCore (SecCoreData, NULL, Private);
+ SwitchPeiCore (SecCoreData, NULL, Private);
} else {
//
// Migrate memory pages allocated in pre-memory phase.
diff --git a/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
b/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
new file mode 100644
index 00..23cfb5090b
--- /dev/null
+++ b/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
@@ -0,0 +1,33 @@
+;--
+
+;
+; Copyright (c) 2022, Intel Corporation. All rights reserved. ;
+SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract:
+;
+; Switch PeiCore from temporary memory to permanent memory.
+;
+;--
+
+
+SECTION .text
+
+extern ASM_PFX(PeiCore)
+
+;--
+
+; VOID
+; EFIAPI
+; SwitchPeiCore (
+; EFI_SEC_PEI_HAND_OFF*SecCoreDataPtr,
+; EFI_PEI_PPI_DESCRIPTOR *PpiList,
+; VOID*Data
+; );
+;--
+
+global ASM_PFX(SwitchPeiCore)
+ASM_PFX(SwitchPeiCore):
+ push DWORD [esp + 12]
+ push DWORD [esp + 12]
+ push DWORD [esp + 12]
+ call ASM_PFX(PeiCore)
+ jmp$; Should never reach here
+ ret
+
diff --git a/MdeModulePkg/Core/Pei/PeiMain.h b/MdeModulePkg/Core/Pei/PeiMain.h
index 556beddad5..8e8ed3dadf 100644
--- a/MdeModulePkg/Core/Pei/PeiMain.h
+++ b/MdeModulePkg/Core/Pei/PeiMain.h
@@ -2038,4 +2038,29 @@ PeiReinitializeFv (
IN PEI_CORE_INSTANCE *PrivateData
);
+/**
+ This routine is invoked by main entry of PeiMain module during
+transition
+ from temporary memory to permanent memory.
+
+ @param SecCoreDataPtr Points to a data structure containing information
about the PEI core's operating
+ environment, such as the size and location of
temporary RAM, the stack location and
+ the BFV location.
+ @param PpiList Points to a list of one or more PPI descriptors to be
installed initially by the PEI core.
+ An empty PPI list consists of a single descriptor
with the end-tag
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST. As part of its
initialization
+ phase, the PEI Foundation will add these SEC-hosted
PPIs to its PPI database such
+ that both the PEI Foundation and any modules can
leverage the associated service
+ calls and/or code in these early PPIs
+ @param DataPointer to old core data that is used to initialize
the
+ core's data areas.
+ If NULL, it is first PeiCore entering.
+
+**/
+VOID
+EFIAPI
+SwitchPeiCore (
+ IN CONST EFI_SEC_PEI_HAND_OFF*SecCoreDataPtr,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList,
+ IN VOID *Data
+ );
#endif
diff --git a/MdeModulePkg/Core/Pei/PeiMain.inf
b/MdeModulePkg/Core/Pei/PeiMain.inf
index 0cf357371a..b597aed8f6 100644
[edk2-devel][PATCH] IntelFsp2Pkg: BaseFspCommonLib Support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3867
Add BaseFspCommonLib Support for X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +-
IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +-
IntelFsp2Pkg/Include/FspGlobalData.h | 2 +-
IntelFsp2Pkg/Include/Library/FspCommonLib.h| 6 +-
.../Library/BaseFspCommonLib/FspCommonLib.c| 65 +-
5 files changed, 45 insertions(+), 32 deletions(-)
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index f79d45900e..68e588dd41 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -217,7 +217,7 @@ FspGlobalDataInit (
**/
VOID
FspDataPointerFixUp (
- IN UINT32 OffsetGap
+ IN UINTN OffsetGap
)
{
FSP_GLOBAL_DATA *NewFspData;
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/SecFsp.h
index aacd32f7f7..7c9be85fe0 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.h
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h
@@ -61,7 +61,7 @@ FspGlobalDataInit (
**/
VOID
FspDataPointerFixUp (
- IN UINT32 OffsetGap
+ IN UINTN OffsetGap
);
/**
diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h
b/IntelFsp2Pkg/Include/FspGlobalData.h
index 71033121c4..2b534075ae 100644
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -42,7 +42,7 @@ typedef struct {
UINT32 Signature;
UINT8 Version;
UINT8 Reserved1[3];
- UINT32 CoreStack;
+ UINTN CoreStack;
UINT32 StatusCode;
UINT32 Reserved2[8];
FSP_PLAT_DATA PlatformData;
diff --git a/IntelFsp2Pkg/Include/Library/FspCommonLib.h
b/IntelFsp2Pkg/Include/Library/FspCommonLib.h
index c70039d9e8..b5e38568e2 100644
--- a/IntelFsp2Pkg/Include/Library/FspCommonLib.h
+++ b/IntelFsp2Pkg/Include/Library/FspCommonLib.h
@@ -38,7 +38,7 @@ GetFspGlobalDataPointer (
@retval ApiParameter FSP API first parameter passed by the bootloader.
**/
-UINT32
+UINTN
EFIAPI
GetFspApiParameter (
VOID
@@ -49,7 +49,7 @@ GetFspApiParameter (
@retval ApiParameter FSP API second parameter passed by the bootloader.
**/
-UINT32
+UINTN
EFIAPI
GetFspApiParameter2 (
VOID
@@ -87,7 +87,7 @@ SetFspApiParameter (
VOID
EFIAPI
SetFspApiReturnStatus (
- IN UINT32 ReturnStatus
+ IN UINTN ReturnStatus
);
/**
diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
index 8f8453915e..cd10b63c95 100644
--- a/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
+++ b/IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
@@ -30,21 +30,34 @@ typedef struct {
UINT16IdtrLimit;
UINT32IdtrBase;
UINT16Reserved;
- UINT32Edi;
- UINT32Esi;
- UINT32Ebp;
- UINT32Esp;
- UINT32Ebx;
- UINT32Edx;
- UINT32Ecx;
- UINT32Eax;
+ UINT32Registers[8]; // General Purpose Registers: Edi, Esi, Ebp, Esp,
Ebx, Edx, Ecx and Eax
UINT16Flags[2];
UINT32FspInfoHeader;
UINT32ApiRet;
UINT32ApiParam[2];
} CONTEXT_STACK;
-#define CONTEXT_STACK_OFFSET(x) (UINT32)&((CONTEXT_STACK *)(UINTN)0)->x
+//
+// API return address +0xB0
+// pushAPI Parameter2 +0xA8
+// pushAPI Parameter1 +0xA0
+// pushFspInfoHeader+0x98
+// pushfq +0x90
+// cli
+// PUSHA_64 +0x10
+// sub rsp, 16 +0x00
+// sidt[rsp]
+//
+typedef struct {
+ UINT64Idtr[2];// IDTR Limit - bit0:bi15, IDTR Base - bit16:bit79
+ UINT64Registers[16]; // General Purpose Registers: RDI, RSI, RBP, RSP,
RBX, RDX, RCX, RAX, and R15 to R8
+ UINT32Flags[2];
+ UINT64FspInfoHeader;
+ UINT64ApiParam[2];
+ UINT64ApiRet; // 64bit stack format is different from the 32bit
one due to x64 calling convention
+} CONTEXT_STACK_64;
+
+#define CONTEXT_STACK_OFFSET(x) (sizeof(UINTN) == sizeof (UINT32) ?
(UINTN)&((CONTEXT_STACK *)(UINTN)0)->x : (UINTN)&((CONTEXT_STACK_64
*)(UINTN)0)->x)
#pragma pack()
@@ -85,7 +98,7 @@ GetFspGlobalDataPointer (
@retval ApiParameter FSP API first parameter passed by the bootloader.
**/
-UINT32
+UINTN
EFIAPI
GetFspApiParameter (
VOID
@@ -94,7 +107,7 @@ GetFspApiParameter (
FSP_GLOBAL_DATA *FspData;
FspData = GetFspGlobalDataPointer ();
- return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET
(ApiParam[0]));
+ return *(UINTN *)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[0]));
}
/**
@@ -119,7 +132,7 @@ GetFspEntryStack (
@retval ApiParameter FSP API second parameter passed by the bootloader.
**/
-UINT32
+UINTN
EFIAPI
GetFspApiParameter2 (
VOID
@@ -128,7 +141,7 @@ GetFspApiParameter2 (
FSP_GLOBAL_DATA *FspData;
FspData =
[edk2-devel][PATCH v2] IntelFsp2Pkg: BaseFspSwitchStackLib Support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3832
Add BaseFspSwitchStackLib Support for X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
IntelFsp2Pkg/Include/PushPopRegsNasm.inc | 67
.../BaseFspSwitchStackLib.inf | 5 +-
.../BaseFspSwitchStackLib/FspSwitchStackLib.c | 8 +--
.../Library/BaseFspSwitchStackLib/X64/Stack.nasm | 72 ++
4 files changed, 147 insertions(+), 5 deletions(-)
create mode 100644 IntelFsp2Pkg/Include/PushPopRegsNasm.inc
create mode 100644 IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
diff --git a/IntelFsp2Pkg/Include/PushPopRegsNasm.inc
b/IntelFsp2Pkg/Include/PushPopRegsNasm.inc
new file mode 100644
index 00..ec103940d8
--- /dev/null
+++ b/IntelFsp2Pkg/Include/PushPopRegsNasm.inc
@@ -0,0 +1,67 @@
+;--
+;
+; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+; Provide macro to push/pop registers in X64
+;
+;--
+
+;-
+; Macro:PUSHA_64
+;
+; Description: Saves all registers on stack
+;
+; Input:None
+;
+; Output: None
+;-
+%macro PUSHA_64 0
+ pushr8
+ pushr9
+ pushr10
+ pushr11
+ pushr12
+ pushr13
+ pushr14
+ pushr15
+ pushrax
+ pushrcx
+ pushrdx
+ pushrbx
+ pushrsp
+ pushrbp
+ pushrsi
+ pushrdi
+%endmacro
+
+;-
+; Macro:POPA_64
+;
+; Description: Restores all registers from stack
+;
+; Input:None
+;
+; Output: None
+;-
+%macro POPA_64 0
+ poprdi
+ poprsi
+ poprbp
+ poprsp
+ poprbx
+ poprdx
+ poprcx
+ poprax
+ popr15
+ popr14
+ popr13
+ popr12
+ popr11
+ popr10
+ popr9
+ popr8
+%endmacro
+
diff --git
a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
index 3dcf3b9598..6909aec651 100644
--- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
+++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
@@ -15,12 +15,15 @@
VERSION_STRING = 1.0
LIBRARY_CLASS = FspSwitchStackLib
-[Sources.IA32]
+[Sources]
FspSwitchStackLib.c
[Sources.IA32]
Ia32/Stack.nasm
+[Sources.X64]
+ X64/Stack.nasm
+
[Packages]
MdePkg/MdePkg.dec
IntelFsp2Pkg/IntelFsp2Pkg.dec
diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c
b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c
index 618c25c3b0..dae4e27172 100644
--- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c
+++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/FspSwitchStackLib.c
@@ -20,16 +20,16 @@
**/
-UINT32
+UINTN
SwapStack (
- IN UINT32 NewStack
+ IN UINTN NewStack
)
{
FSP_GLOBAL_DATA *FspData;
- UINT32 OldStack;
+ UINTNOldStack;
FspData= GetFspGlobalDataPointer ();
OldStack = FspData->CoreStack;
- FspData->CoreStack = NewStack;
+ FspData->CoreStack = (UINTN) NewStack;
return OldStack;
}
diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
new file mode 100644
index 00..bd36fe4b8b
--- /dev/null
+++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
@@ -0,0 +1,72 @@
+;--
+;
+; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+; Switch the stack from temporary memory to permanent memory.
+;
+;--
+
+SECTION .text
+
+%include"PushPopRegsNasm.inc"
+
+extern ASM_PFX(SwapStack)
+
+;--
+; UINT32
+; EFIAPI
+; Pei2LoaderSwitchStack (
+; VOID
+; )
+;--
+global ASM_PFX(Pei2LoaderSwitchStack)
+ASM_PFX(Pei2LoaderSwitchStack):
+xor rax, rax
+jmp ASM_PFX(FspSwitchStack)
+
+;--
+; UINT32
+; EFIAPI
+; Loader2PeiSwitchStack (
+; VOID
+; )
[edk2-devel][PATCH v2] IntelFsp2Pkg: BaseFspDebugLibSerialPort Support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3833
Add BaseFspDebugLibSerialPort Support for X64.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Ashraf Ali S
Cc: Ted Kuo
Signed-off-by: Ted Kuo
---
.../BaseFspDebugLibSerialPort.inf | 5 ++-
.../Library/BaseFspDebugLibSerialPort/DebugLib.c | 39 +-
.../BaseFspDebugLibSerialPort/X64/FspDebug.nasm| 25 ++
3 files changed, 53 insertions(+), 16 deletions(-)
create mode 100644
IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/X64/FspDebug.nasm
diff --git
a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
index 14b1899e6c..395def57c3 100644
---
a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
+++
b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/BaseFspDebugLibSerialPort.inf
@@ -16,7 +16,7 @@
LIBRARY_CLASS = DebugLib
#
-# VALID_ARCHITECTURES = IA32
+# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
@@ -25,6 +25,9 @@
[Sources.Ia32]
Ia32/FspDebug.nasm
+[Sources.X64]
+ X64/FspDebug.nasm
+
[Packages]
MdePkg/MdePkg.dec
IntelFsp2Pkg/IntelFsp2Pkg.dec
diff --git a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
index c8824cde7f..cb2317bfb2 100644
--- a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
+++ b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
@@ -33,7 +33,7 @@ VA_LIST mVaListNull;
@return StackFramePointer stack frame pointer of function call.
**/
-UINT32 *
+UINTN *
EFIAPI
GetStackFramePointer (
VOID
@@ -193,13 +193,13 @@ DebugBPrint (
**/
VOID
FillHex (
- UINT32 Value,
+ UINTN Value,
CHAR8 *Buffer
)
{
INTN Idx;
- for (Idx = 7; Idx >= 0; Idx--) {
+ for (Idx = (sizeof (UINTN) * 2) - 1; Idx >= 0; Idx--) {
Buffer[Idx] = mHexTable[Value & 0x0F];
Value >>= 4;
}
@@ -228,26 +228,35 @@ DebugAssertInternal (
)
{
CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];
- UINT32 *Frame;
+ UINTN *Frame;
- Frame = (UINT32 *)GetStackFramePointer ();
+ Frame = (UINTN *)GetStackFramePointer ();
//
// Generate the ASSERT() message in Ascii format
//
- AsciiStrnCpyS (
-Buffer,
-sizeof (Buffer) / sizeof (CHAR8),
-"-> EBP:0x EIP:0x\n",
-sizeof (Buffer) / sizeof (CHAR8) - 1
-);
+ if (sizeof (UINTN) == sizeof (UINT32)) {
+AsciiStrnCpyS (
+ Buffer,
+ sizeof (Buffer) / sizeof (CHAR8),
+ "-> EBP:0x EIP:0x\n",
+ sizeof (Buffer) / sizeof (CHAR8) - 1
+ );
+ } else {
+AsciiStrnCpyS (
+ Buffer,
+ sizeof (Buffer) / sizeof (CHAR8),
+ "-> RBP:0x RIP:0x\n",
+ sizeof (Buffer) / sizeof (CHAR8) - 1
+ );
+ }
SerialPortWrite ((UINT8 *)"ASSERT DUMP:\n", 13);
while (Frame != NULL) {
-FillHex ((UINT32)Frame, Buffer + 9);
-FillHex (Frame[1], Buffer + 9 + 8 + 8);
+FillHex ((UINTN)Frame, Buffer + 9);
+FillHex (Frame[1], Buffer + 9 + (sizeof (UINTN) * 2) + 8);
SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));
-if ((Frame[0] > (UINT32)Frame) && (Frame[0] < (UINT32)Frame + 0x0010))
{
- Frame = (UINT32 *)Frame[0];
+if ((Frame[0] > (UINTN)Frame) && (Frame[0] < (UINTN)Frame + 0x0010)) {
+ Frame = (UINTN *)Frame[0];
} else {
Frame = NULL;
}
diff --git a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/X64/FspDebug.nasm
b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/X64/FspDebug.nasm
new file mode 100644
index 00..6cf0f0af8b
--- /dev/null
+++ b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/X64/FspDebug.nasm
@@ -0,0 +1,25 @@
+;--
+;
+; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+; FSP Debug functions
+;
+;--
+
+SECTION .text
+
+;--
+; UINT32 *
+; EFIAPI
+; GetStackFramePointer (
+; VOID
+; );
+;--
+global ASM_PFX(GetStackFramePointer)
+ASM_PFX(GetStackFramePointer):
+mov rax, rbp
+ret
+
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#87522): https://edk2.groups.io/g/devel/message/87522
Mute This Topic: https://groups.io/mt/89765496/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH v2] UefiCpuPkg: Support FFS3 GUID in SearchForBfvBase.asm
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3862
The new algorithm searches BFV address with FFS3 GUID first.
If not found, it will search BFV address with FFS2 GUID.
Cc: Ray Ni
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Signed-off-by: Ted Kuo
---
.../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 484 -> 548 bytes
.../ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw | Bin 468 -> 516 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw | Bin 868 -> 932 bytes
.../Bin/X64/PageTable1G/ResetVector.x64.port80.raw | Bin 12292 -> 12292 bytes
.../Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw | Bin 12292 -> 12292 bytes
.../Bin/X64/PageTable1G/ResetVector.x64.serial.raw | Bin 12292 -> 12292 bytes
.../Bin/X64/PageTable2M/ResetVector.x64.port80.raw | Bin 28676 -> 28676 bytes
.../Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
.../Bin/X64/PageTable2M/ResetVector.x64.serial.raw | Bin 28676 -> 28676 bytes
.../ResetVector/Vtf0/Ia32/SearchForBfvBase.asm | 51 +
10 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
index
79b23c047bdc6e552d77d5c9e9aeae21ff04d91d..23254e83bf1a17dee9f38c235fcc9948624a7536
100644
GIT binary patch
delta 227
zcmaFDyo9BG0uUG;*vZVmz@W<@z`$S)9RYyQbxs@7N`P<5a2DnL~gPkVYw4**r!cFFjcZU?HGY1)}sx(=wS^|0>c
z(xuH6Dh#FbI}bBQD3s24Eoykcv-u}uY2Sto!p|CZ><5C*qp$yU9^J6;8$wu(9TV=}(c8
zUjg)y@_Q48|1M?^0T*VtBLDzE4S>dJ0U!uIkRJe$|NsA!umLp*>x1c7{{R2!
Mtds8n6_W!3A^UepbpQYW
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
index
ce7faa502b858e99908bcdb397b776258205e1d5..18562d8f1f58601f66fcb0cbf2f994046ce48fde
100644
GIT binary patch
delta 225
zcmcb@+`>{n0SF8a>||zOV9;d{U|_HXGX59EHUDHTRcoves5(#_Qu?g1LgcjVDc{n&
zjTI7m^W~3nW7tMv416`-n$r#(HT2Y{+C)y36^7FJorjqt6iR2j7BoEI+5D5Sv~S0L?*04scOHHHuk+|j`-wr}jBh5cDmQQY
zub0NpD4w=MnSsH9U+F;FtK9$p{|hkeaA0F#;8%K(wu6JA??`Yyb-n;_3H
Z0jOYd0;3s6_e+a^|Np<-GkG4P833r5W}5&2
delta 153
zcmZo+xxySY0SF8a=rRZ}FxWCMF#InvZmbZfc-qrb`ns_~#I{Suzw}XKg~UwL
zjTJJjhjlNPUTCgRVJJP-d6+puq4e-;>)Kp!4YKf1O8Px=-v1XZ$kpQMqv4f4ww*
zM)9;A$_xw+{7MJXUZqaXVU!VYn;_3H;s5{tAge)O@^>vc|Nj4fxn=S>Ml%58
CZbm==
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
index
6503a988abdac06f9aa88f0a65f2525e12233b0a..e4aa4fc30a32bc3d4d8d0e1726c43fdafef4a374
100644
GIT binary patch
delta 214
zcmaFDwuF6xY`rV9;enmZ3=9mq3<3-cwm`=JqPXUt%%y6L6#`WUibG1DHCBk6wms!r
zdbhDcVsF0Ow9+e$6*8UAO=gvzeysvjRq?c^r}O|=df9ZChs+p#piKXj+s#*{0
zUM^kQT%p2HI=}NUbA&?ajMssN2Rxg9GM4tG?fT0+F{OjiW8`AFs>J_`LCD8
z@Lz#iWfnVuB+AHPBT}&|oJ`>~_Cj9^Ze*zRte#c}Yu;9;Yrq|zIvi^U${?Gsa
LFE>v%Vm1N**#ci0
delta 146
zcmV;D0B!%I2jm8j9YX~JF~BVV5C8x@00030ax;N=5P0Q`jCJdQcoaQ~98Y!Pfp{31
zHHl$$*@1W*g~Kh=brcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^t{?AX75Kkxp|qp$yU9^J6Bj4$8^oS9{Mya%q3`zYTOak(_!-61
zb|^D2IPfbSNPD$!a;u^OyQ4b81EBWFTNEw%UN^ja@b~}!mpT7{gvsPTiV}
delta 259
zcmZokXi3<>rVygbAi%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK
z$h02Tysxk81Z^i=0z<_Lw-!>@TaY`>8ANp?ZUi48fjh|6GZHF=g
zg9E?PfwWg`llLkr@O!Brcl3=nSp^pmqCDm!4}B)UliB;letu_u|lBgKygUvv)3
zNbJp*n^tq;e#OWC
z|0Nh+`|M`_}ygvDBH^Ya%+q?ID)Jx-M6i?fs%)sEluXG^o)w0RCiZc9u
z>I@fv+9p83MyJRzkL7q|Noc8|A2(?|NsAY0P%kh#bX|dM?DmecyvDa|7^m9
eje;9^6<$hx0&4}@$q*Le#xP;ROJ;}$oEHj+dD
delta 239
zcmZokXi3<>rr@K?Ai%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK
z$h02Tysxk81Z^i=0z<_Lw-!>>7a><5C*qp$yU9(`Fqxl19OQD^cag(*P}AOHWC
zV0bwdXz(3;+M~E8Tc~^4D}G_Hw|&%0<7X64+o8{
z27aXnX*)O=`fl_c=zGxjqVK|MS9OL7K>5iR6m9ulx4bm?_y7OP8W3SKSw=~Mal%Hy
e54;L5Z+)Bq0zms1!b02_CQNvF7$O1|o$orgJI)
diff --git
a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw
index
d9b051ff06d1d30b0dfd585e05e75c98ebd88b03..de97b858ddd03171114aa0efb1929796b1aa5435
100644
GIT binary patch
delta 259
zcmZokXi3;0t5Cm}+3>(lW(EcZT?PRL23sKGe^FfXPv%m!#tMO|1H~bw)R4PTQXH
zExp@VA+a}KZd#tNCv=O(jCPrp_Hs;YR}(^Gl?sLHlW#=mqsP}NM+`W
zbuX7LZLUyZD4pMVm^nhBbjIsI!vmhpKN(B=(suo2o}8l4!FXWuTZLPUuO^>RoWeM5
za;%aYqwwSrau&;S2V#)%f$8
z>GijlZ2w=H|M~y_rS)GRQMY-&@>gz!m#;og00E$%7{Wr_7$!`3c^M)C7M=hAKvr~s
delta 209
zcmZokXi3;0tKi(rY;
zmfmcvkZC=vd%5<{+>8Z}c%n=HuhhKY6o}tjgcw(}u;w{Ecla!_~#!a58nO}3=aHC2hv`#Otw~z;SW}4DER#U{{$$QJWtt1G~&-|rq|zI
x{`>bb{m=jZFOB~KiL%Y_mA`UNR4`C@x$84nG0>R|VIgh|6DGV|3=x5t0RVO0UcCSS
diff --git
a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.port80.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.port80.raw
index
0e53a574fab74db6973d7ea41a6a495266a4d0ae..23c58501b5a48448ffcd2757310442ef33f45fa0
100644
GIT binary patch
delta 291
zcmZp9z}WJDaRXaI{Z3{E1_oUQ0R{$JAme{gT=P%nQnkhkfvN+=A*Ih6D@0D)p7Jfd
z+gKs7H(zdA>6OL`na<}Xvr13DRspK2c-qrbdH|@(woAspbURShOw-Q9(se*pt%r3l
Re: [edk2-devel][PATCH] UefiCpuPkg: Support FFS3 GUID in SearchForBfvBase.asm
Hi Ray,
Please find my inline comments with [Ted].
Thanks,
Ted
-Original Message-
From: Ni, Ray
Sent: Thursday, March 10, 2022 12:15 PM
To: Kuo, Ted ; devel@edk2.groups.io
Cc: De, Debkumar ; Han, Harry ;
West, Catharine
Subject: RE: [edk2-devel][PATCH] UefiCpuPkg: Support FFS3 GUID in
SearchForBfvBase.asm
3 comments starting with "[Ray]".
;#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \ ; { 0x8c8ce578, 0x8a3d, 0x4f1c, {
0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } } -%define FFS_GUID_DWORD0
0x8c8ce578 -%define FFS_GUID_DWORD1 0x4f1c8a3d -%define FFS_GUID_DWORD2
0x61893599 -%define FFS_GUID_DWORD3 0xd32dc385
+%define FFS2_GUID_DWORD0 0x8c8ce578
+%define FFS2_GUID_DWORD1 0x4f1c8a3d
+%define FFS2_GUID_DWORD2 0x61893599
+%define FFS2_GUID_DWORD3 0xd32dc385
+
+;#define EFI_FIRMWARE_FILE_SYSTEM3_GUID \ ; { 0x8c8ce578, 0x3dcb,
+0x4dca, { 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a } } %define
+FFS3_GUID_DWORD0 0x5473c07a %define FFS3_GUID_DWORD1 0x4dca3dcb %define
+FFS3_GUID_DWORD2 0x961e6fbd %define FFS3_GUID_DWORD3 0x9a34e789
[Ray] 1. I am not sure if it's the best representation of GUID in NASM? I am
not the NASM expert. If there is no recommendation, I am ok with this.
[Ted] Somehow the diff doesn't reflect the actual representation in my editor.
I'll check and update the patch.
BITS32
@@ -25,6 +32,7 @@ BITS32
Flat32SearchForBfvBase:
xor eax, eax
+mov ecx, 2 ; 2: FFS3 GUID, 1: FFS2 GUID, 0: Not Found
[Ray] 2. Can you map ECX 2 to FFS2 GUID, ECX 3 to FFS3 GUID?
[Ted] Yes, will update in next patch.
searchingForBfvHeaderLoop:
;
; We check for a firmware volume at every 4KB address in the top 16MB @@
-32,20 +40,37 @@ searchingForBfvHeaderLoop:
;
sub eax, 0x1000
cmp eax, 0xff00
-jb searchedForBfvHeaderButNotFound
+jb searchingForBfvWithOtherFfsGuid
+cmp ecx, 2
+jne searchingForFfs2Guid
;
-; Check FFS GUID
+; Check FFS3 GUID
;
-cmp dword [eax + 0x10], FFS_GUID_DWORD0
+cmp dword [eax + 0x10], FFS3_GUID_DWORD0
jne searchingForBfvHeaderLoop
-cmp dword [eax + 0x14], FFS_GUID_DWORD1
+cmp dword [eax + 0x14], FFS3_GUID_DWORD1
jne searchingForBfvHeaderLoop
-cmp dword [eax + 0x18], FFS_GUID_DWORD2
+cmp dword [eax + 0x18], FFS3_GUID_DWORD2
jne searchingForBfvHeaderLoop
-cmp dword [eax + 0x1c], FFS_GUID_DWORD3
+cmp dword [eax + 0x1c], FFS3_GUID_DWORD3
jne searchingForBfvHeaderLoop
+jmp checkingFvLength
+searchingForFfs2Guid:
+;
+; Check FFS2 GUID
+;
+cmp dword [eax + 0x10], FFS2_GUID_DWORD0
+jne searchingForBfvHeaderLoop
+cmp dword [eax + 0x14], FFS2_GUID_DWORD1
+jne searchingForBfvHeaderLoop
+cmp dword [eax + 0x18], FFS2_GUID_DWORD2
+jne searchingForBfvHeaderLoop
+cmp dword [eax + 0x1c], FFS2_GUID_DWORD3
+jne searchingForBfvHeaderLoop
+
+checkingFvLength:
[Ray] 3. Why is this label added?
[Ted] You meant searchingForBfvWithOtherFfsGuid? This is used to restart a new
search with a new target guid before reaching the end of the supported ffs guid
list.
;
; Check FV Length
;
@@ -57,6 +82,12 @@ searchingForBfvHeaderLoop:
jmp searchedForBfvHeaderAndItWasFound
+searchingForBfvWithOtherFfsGuid:
+xor eax, eax
+dec ecx
+cmp ecx, 0
+jne searchingForBfvHeaderLoop
+
searchedForBfvHeaderButNotFound:
;
; Hang if the SEC entry point was not found
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#87405): https://edk2.groups.io/g/devel/message/87405
Mute This Topic: https://groups.io/mt/89613429/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel][PATCH] MdeModulePkg: Make RSP 16-byte boundary aligned for PEI 64bit
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3865
Use SwitchPeiCore instead of calling PeiCore directly when switching
PeiCore from temporary memory to permanent memory. For PEI 32bit,
SwitchPeiCore always calls PeiCore without any additional step. For
PEI 64bit, SwitchPeiCore makes RSP 16-byte boundary aligned and then
allocate 32 bytes as a shadow store on call stack before calling
PeiCore.
Cc: Dandan Bi
Cc: Liming Gao
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Jian J Wang
Cc: Ashraf Ali S
Signed-off-by: Ted Kuo
---
MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c | 2 +-
MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm | 33 +++
MdeModulePkg/Core/Pei/PeiMain.h | 25 ++
MdeModulePkg/Core/Pei/PeiMain.inf | 6 +
MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm | 38 +++
5 files changed, 103 insertions(+), 1 deletion(-)
create mode 100644 MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
create mode 100644 MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm
diff --git a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
index 3552feda8f..5af6e6e86f 100644
--- a/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
+++ b/MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c
@@ -871,7 +871,7 @@ PeiCheckAndSwitchStack (
//
// Entry PEI Phase 2
//
- PeiCore (SecCoreData, NULL, Private);
+ SwitchPeiCore (SecCoreData, NULL, Private);
} else {
//
// Migrate memory pages allocated in pre-memory phase.
diff --git a/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
b/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
new file mode 100644
index 00..23cfb5090b
--- /dev/null
+++ b/MdeModulePkg/Core/Pei/Ia32/SwitchPeiCore.nasm
@@ -0,0 +1,33 @@
+;--
+;
+; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+; Switch PeiCore from temporary memory to permanent memory.
+;
+;--
+
+SECTION .text
+
+extern ASM_PFX(PeiCore)
+
+;--
+; VOID
+; EFIAPI
+; SwitchPeiCore (
+; EFI_SEC_PEI_HAND_OFF*SecCoreDataPtr,
+; EFI_PEI_PPI_DESCRIPTOR *PpiList,
+; VOID*Data
+; );
+;--
+global ASM_PFX(SwitchPeiCore)
+ASM_PFX(SwitchPeiCore):
+ push DWORD [esp + 12]
+ push DWORD [esp + 12]
+ push DWORD [esp + 12]
+ call ASM_PFX(PeiCore)
+ jmp$; Should never reach here
+ ret
+
diff --git a/MdeModulePkg/Core/Pei/PeiMain.h b/MdeModulePkg/Core/Pei/PeiMain.h
index 556beddad5..8e8ed3dadf 100644
--- a/MdeModulePkg/Core/Pei/PeiMain.h
+++ b/MdeModulePkg/Core/Pei/PeiMain.h
@@ -2038,4 +2038,29 @@ PeiReinitializeFv (
IN PEI_CORE_INSTANCE *PrivateData
);
+/**
+ This routine is invoked by main entry of PeiMain module during transition
+ from temporary memory to permanent memory.
+
+ @param SecCoreDataPtr Points to a data structure containing information
about the PEI core's operating
+ environment, such as the size and location of
temporary RAM, the stack location and
+ the BFV location.
+ @param PpiList Points to a list of one or more PPI descriptors to be
installed initially by the PEI core.
+ An empty PPI list consists of a single descriptor
with the end-tag
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST. As part of its
initialization
+ phase, the PEI Foundation will add these SEC-hosted
PPIs to its PPI database such
+ that both the PEI Foundation and any modules can
leverage the associated service
+ calls and/or code in these early PPIs
+ @param DataPointer to old core data that is used to initialize
the
+ core's data areas.
+ If NULL, it is first PeiCore entering.
+
+**/
+VOID
+EFIAPI
+SwitchPeiCore (
+ IN CONST EFI_SEC_PEI_HAND_OFF*SecCoreDataPtr,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList,
+ IN VOID *Data
+ );
#endif
diff --git a/MdeModulePkg/Core/Pei/PeiMain.inf
b/MdeModulePkg/Core/Pei/PeiMain.inf
index 0cf357371a..b597aed8f6 100644
--- a/MdeModulePkg/Core/Pei/PeiMain.inf
+++ b/MdeModulePkg/Core/Pei/PeiMain.inf
@@ -47,6 +47,12 @@
PciCfg2/PciCfg2.c
PeiMain.h
+[Sources.IA32]
+ Ia32/SwitchPeiCore.nasm
+
+[Sources.X64]
+ X64/SwitchPeiCore.nasm
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
diff --git a/MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm
b/MdeModulePkg/Core/Pei/X64/SwitchPeiCore.nasm
new file mode 100644
index
[edk2-devel][PATCH] UefiCpuPkg: Support FFS3 GUID in SearchForBfvBase.asm
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3862
The new algorithm searches BFV address with FFS3 GUID first.
If not found, it will search BFV address with FFS2 GUID.
Cc: Ray Ni
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Signed-off-by: Ted Kuo
---
.../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 484 -> 548 bytes
.../ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw | Bin 468 -> 516 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw | Bin 868 -> 932 bytes
.../Bin/X64/PageTable1G/ResetVector.x64.port80.raw | Bin 12292 -> 12292 bytes
.../Vtf0/Bin/X64/PageTable1G/ResetVector.x64.raw | Bin 12292 -> 12292 bytes
.../Bin/X64/PageTable1G/ResetVector.x64.serial.raw | Bin 12292 -> 12292 bytes
.../Bin/X64/PageTable2M/ResetVector.x64.port80.raw | Bin 28676 -> 28676 bytes
.../Vtf0/Bin/X64/PageTable2M/ResetVector.x64.raw | Bin 28676 -> 28676 bytes
.../Bin/X64/PageTable2M/ResetVector.x64.serial.raw | Bin 28676 -> 28676 bytes
.../ResetVector/Vtf0/Ia32/SearchForBfvBase.asm | 51 +
10 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.port80.raw
index
79b23c047bdc6e552d77d5c9e9aeae21ff04d91d..ccb5fb9d28d295dabdf41113e959d4a04823e917
100644
GIT binary patch
delta 227
zcmaFDyo9BG0uUG;*vZ7ez@W<@z`$S)9RYyQbps@7N`P<5a2DnL~gPkVYw4**r!cFFjcZU?HGY1)}sx(=wS^|0>c
z(xuH6Dh#FbI}bBQD3s24Eoykcv-u}OY2Sto!p|CZ><5C*qp$yU9^J6F
delta 158
zcmV;P0Ac^61mpu+kdTm~BVV5C8x@00030ax;N=5P0Q`jCJdQcoaQ~98Y!Pfp{31
zHHl$$*@1W*g~Kh=b;8$wu(9TV=}(c8
zUjg)y@_Q48|1M?^0T*VtBLDzE4S>dJ0U!uIkRJe$|NsA!umLp*>x1c7{{R2!
Mtds8n6_W!3A^UepbpQYW
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.raw
index
ce7faa502b858e99908bcdb397b776258205e1d5..45ef6ccbcb61368711b3d1e90fd9f0633a8424dd
100644
GIT binary patch
delta 225
zcmcb@+`>{n0SF8a>||nKV9;d{U|_HXGX59EHUDHPRcoves5(#_Qu?g1LgcjVDc{n&
zjTI7m^W~3nW7tMv416`-n$r#(HT2Y{+C)y36^7FJorjqt6iR2j7BoEI+5D5Cv~S0L?*04scOHHHuk+|j`-wr}jBh5cDmQQY
zub0NpD4w=MnSsH9U+F;FtK9$p{|hkeaA0F#;8%K(wu6JA??`Yyb-n;_3H
Z0jOYd0;3s6_e+a^|Np<-GkG4P833l9W|#l~
delta 153
zcmZo+xxySY0SF8a=rRZ}FxWCMF#InvZmbZfc-qrb`ns_~#I{Suzw}XKg~UwL
zjTJJjhjlNPUTCgRVJJP-d6+puq4e-;>)Kp!4YKf1O8Px=-v1XZ$kpQMqv4f4ww*
zM)9;A$_xw+{7MJXUZqaXVU!VYn;_3H;s5{tAge)O@^>vc|Nj4fxn=S>Ml%58
CZbm==
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/IA32/ResetVector.ia32.serial.raw
index
6503a988abdac06f9aa88f0a65f2525e12233b0a..16143454c0b6df93468bcde510289e43b343d8fd
100644
GIT binary patch
delta 214
zcmaFDwuF6xY`rV9;enk@3=9mq3<3-cwm`=JqPXUtOr>g#6#`WUibG1DHCBk6wms!r
zdbhDcVsF0Ow9+e$6*8UAO=gvzeysvjRq?c^r}O|=df9ZChs+p#piKXj+s#*{0
zUM^kQT%p2HI=}NUbA&?ajMssN2Rxg9GL-hE?fT0+F{OjiW8`AFs>J_`LCD8
z@Lz#iWfnVuB+AHPBT}&|oJ`>~_Cj9^Ze*zRte#c}Yu;9;Yrq|zIvi^U${?Gsa
LFE>v%Vm1N**C}5Y
delta 146
zcmV;D0B!%I2jm8j9YX~JF~BVV5C8x@00030ax;N=5P0Q`jCJdQcoaQ~98Y!Pfp{31
zHHl$$*@1W*g~Kh=brcl3=iGhJZmqCDm!4}B)UliB;lc`j#u|lBgKygUvv)3
zNbJp*n^t{?AX75Kkxp|qp$yU9^J6Bj4$8^oS9{Mya%q3`zYTOak(_!-61
zb|^D2IPfbSNPD$!a;u^OyQ4b81EBWFTNEw%UN^ja@b~}!mpT7{gvsPTiV}rVygbAi%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK
z$h02Tysxk81Z^i=0z<_Lw-!>@TaY`>8ANp?ZUi48fjh|6GZHF=g
zg9E?PfwWg`llLkr@O!Brcl3=iGhJZmqCDm!4}B)UliB;lc`j#u|lBgKygUvv)3
zNbJp*n^tq;e#OWC
z|0Nh+`|M`_}ygvDBH^Ya%+q?ID)Jx-M6i?fs%)sEluXG^o)w0RCiZc9u
z>I@fv+9p83MyJRzkL7q|Noc8|A2(?|NsAY0P%kh#bX|dM?DmecyvDa|7^m9
eje;9^6<$hx0&4}@$q*Le#xP;ROJ;}$oBQj$Rc
delta 239
zcmZokXi3<>rr@K?Ai%(2%fP_!zsR_;LZISlPfzLV#tISJE*byQM~xK{Gfg`aOK
z$h02Tysxk81Z^i=0z<_Lw-!>>7a><5C*qp$yU9(`Fqxl19OQD^cag(*P}AOHWC
zV0bwdXz(3;+M~E8Tc~^4D}G_Hw|&%0<7X64+o8{
z27aXnX*)O=`fl_c=zGxjqVK|MS9OL7K>5iR6m9ulx4bm?_y7OP8W3SKSw=~Mal%Hy
e54;L5Z+)Bq0zms1!b02_CQNvF7$O1|o$orgJI)
diff --git
a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable1G/ResetVector.x64.serial.raw
index
d9b051ff06d1d30b0dfd585e05e75c98ebd88b03..45e8a5f25e082462e79ef894749fc02a8f5e112c
100644
GIT binary patch
delta 259
zcmZokXi3;0t5Cm}+3>(lCI$uuT?PRL23sKGe^FfXPo`3}#tMO|1H~bw)R4PTQXH
zExp@VA+a}KZd#tNCv=O(jCPrp_Hs;YR}(^Gl?sLHlW#=mqsP}NM+`W
zbuX7LZLUyZD4pMVm^nhBbjIsI!vmhpKN(8<(suo2o}8l4!FXWuTZLPUuO^>RoWeM5
za;%aYqwwSrau&;S2V#)%f$8
z>GijlZ2w=H|M~y_rS)GRQMY-&@>gz!m#;og00E$%7{Wr_7$!`3c^M)C7M=hAJ^6Hf
delta 209
zcmZokXi3;0tKi(rY;
zmfmcvkZC=vd%5<{+>8Z}c%n=HuhhKY6o}tjgcw(}u;w{Ecla!_~#!a58nO}3=aHC2hv`#Otw~z;SW}4DER#U{{$$QJWtt1G~&-|rq|zI
x{`>bb{m=jZFOB~KiL%Y_mA`UNR4`C@x$84nG0>R|VIgh|6DGV|3=x5t0RVO0UcCSS
diff --git
a/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.port80.raw
b/UefiCpuPkg/ResetVector/Vtf0/Bin/X64/PageTable2M/ResetVector.x64.port80.raw
index
0e53a574fab74db6973d7ea41a6a495266a4d0ae..4acf69533a7b60ad0902e9b3dc320e32baa79d23
100644
GIT binary patch
delta 291
[edk2-devel] [PATCH v2] IntelSiliconPkg/VTd: Fix to support IntelVTdDmarPei in 64bit
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3836
Changed VtdIndex defined in PROCESS_DRHD_CALLBACK_FUNC from UINT32 to UINTN
to avoid type incompatible error when enable PEI in 64bit.
Cc: Sheng Wei
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Jenny Huang
Cc: Robert Kowalewski
Signed-off-by: Ted Kuo
---
.../IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.c | 4 ++--
.../IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.c
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.c
index f97d627eca..2844f366bb 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.c
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.c
@@ -434,7 +434,7 @@ GetVTdInfoHob (
VOID
ProcessDhrdPreMemory (
IN OUT VOID *Context,
- IN UINT32 VTdIndex,
+ IN UINTN VTdIndex,
IN EFI_ACPI_DMAR_DRHD_HEADER *DmarDrhd
)
{
@@ -454,7 +454,7 @@ ProcessDhrdPreMemory (
VOID
ProcessDrhdPostMemory (
IN OUT VOID *Context,
- IN UINT32 VTdIndex,
+ IN UINTN VTdIndex,
IN EFI_ACPI_DMAR_DRHD_HEADER *DmarDrhd
)
{
diff --git
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.h
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.h
index 351a7810d8..7bed0a5363 100644
---
a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.h
+++
b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDmarPei.h
@@ -49,7 +49,7 @@ typedef
VOID
(*PROCESS_DRHD_CALLBACK_FUNC) (
IN OUT VOID *Context,
- IN UINT32 VTdIndex,
+ IN UINTN VTdIndex,
IN EFI_ACPI_DMAR_DRHD_HEADER *DmarDrhd
);
--
2.16.2.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#86672): https://edk2.groups.io/g/devel/message/86672
Mute This Topic: https://groups.io/mt/89156060/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] IntelFsp2WrapperPkg: Make GetFspm(s)UpdDataAddress reusable
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3821
Moved GetFspmUpdDataAddress and GetFspsUpdDataAddress to FspWrapperApiLib
so that they can be consumed by other drivers.
Signed-off-by: Ted Kuo
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 18 ---
.../FspmWrapperPeim/FspmWrapperPeim.inf| 2 --
.../FspsWrapperPeim/FspsWrapperPeim.c | 18 ---
.../FspsWrapperPeim/FspsWrapperPeim.inf| 2 --
.../Include/Library/FspWrapperApiLib.h | 22 +
.../BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf | 5 +++
.../BaseFspWrapperApiLib/FspWrapperApiLib.c| 36 ++
7 files changed, 63 insertions(+), 40 deletions(-)
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index b0c6b2f8a6..d119f0b710 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -38,24 +38,6 @@
extern EFI_GUID gFspHobGuid;
-/**
- Get the FSP M UPD Data address
-
- @return FSP-M UPD Data Address
-**/
-
-UINTN
-GetFspmUpdDataAddress (
- VOID
- )
-{
- if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) {
-return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64);
- } else {
-return (UINTN) PcdGet32 (PcdFspmUpdDataAddress);
- }
-}
-
/**
Call FspMemoryInit API.
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 5d0e021401..95317fb70d 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -56,11 +56,9 @@
[Pcd]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64 ## CONSUMES
[Sources]
FspmWrapperPeim.c
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index fadadd40e6..d34de97c1b 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -181,24 +181,6 @@ FspSiliconInitDoneGetFspHobList (
}
}
-/**
- Get the FSP S UPD Data address
-
- @return FSP-S UPD Data Address
-**/
-
-UINTN
-GetFspsUpdDataAddress (
- VOID
- )
-{
- if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {
-return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64);
- } else {
-return (UINTN) PcdGet32 (PcdFspsUpdDataAddress);
- }
-}
-
/**
This function is for FSP dispatch mode to perform post FSP-S process.
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
index da0049a654..50d33d0e0e 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
@@ -65,10 +65,8 @@
[Pcd]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## CONSUMES
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64 ## CONSUMES
[Guids]
gFspHobGuid ## CONSUMES ## HOB
diff --git a/IntelFsp2WrapperPkg/Include/Library/FspWrapperApiLib.h
b/IntelFsp2WrapperPkg/Include/Library/FspWrapperApiLib.h
index d38582d3e5..4ae42ff180 100644
--- a/IntelFsp2WrapperPkg/Include/Library/FspWrapperApiLib.h
+++ b/IntelFsp2WrapperPkg/Include/Library/FspWrapperApiLib.h
@@ -11,6 +11,28 @@
#include
+/**
+ Get the FSP M UPD Data address
+
+ @return FSP-M UPD Data Address
+**/
+UINTN
+EFIAPI
+GetFspmUpdDataAddress (
+ VOID
+ );
+
+/**
+ Get the FSP S UPD Data address
+
+ @return FSP-S UPD Data Address
+**/
+UINTN
+EFIAPI
+GetFspsUpdDataAddress (
+ VOID
+ );
+
/**
Find FSP header pointer.
diff --git
a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
index 1e348b539f..82496eb300 100644
--- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
+++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
@@ -63,3 +63,8 @@
[Pcd]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64 ## CONSUMES
+
Re: [edk2-devel] [PATCH v8] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type
Can we use the size of UINTN instead of the value of PcdFspmUpdDataAddress64 to
decide which PCD should be returned in GetFspmUpdDataAddress and
GetFspsUpdDataAddress?
Thanks,
Ted
-Original Message-
From: S, Ashraf Ali
Sent: Thursday, December 16, 2021 4:10 PM
To: devel@edk2.groups.io
Cc: S, Ashraf Ali ; Chiu, Chasel
; Desimone, Nathaniel L
; Zeng, Star ; Kuo, Ted
; Duggapu, Chinni B ; Chaganty,
Rangasai V ; Solanki, Digant H
; V, Sangeetha ; Ni, Ray
Subject: [PATCH v8] IntelFsp2WrapperPkg : FSPM/S UPD data address based on
Build Type
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to building error.
when a module built-in X64 function pointer will be the size of 64bit width
which cannot be fit in 32bit address which will lead to error. to overcome this
issue introducing the 2 new PCD's for the 64bit modules can consume it. based
on the which pcd platform set, use that.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Kuo Ted
Cc: Duggapu Chinni B
Cc: Rangasai V Chaganty
Cc: Digant H Solanki
Cc: Sangeetha V
Cc: Ray Ni
Signed-off-by: Ashraf Ali S
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 25 ---
.../FspmWrapperPeim/FspmWrapperPeim.inf | 3 ++-
.../FspsWrapperPeim/FspsWrapperPeim.c | 25 ---
.../FspsWrapperPeim/FspsWrapperPeim.inf | 3 ++-
IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 2 ++
5 files changed, 50 insertions(+), 8 deletions(-)
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
index 287e7f9159..49fbb27eca 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c
@@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register
MemoryDiscoveredPpi
notify to call FspSiliconInit API.
- Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights
+ reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -38,6 +38,25 @@
extern EFI_GUID gFspHobGuid;
+/**
+ Get the FSP M UPD Data address
+
+ @return FSP-M UPD Data Address
+**/
+
+UINTN
+EFIAPI
+GetFspmUpdDataAddress (
+ VOID
+ )
+{
+ if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) {
+return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64);
+ } else {
+return (UINTN) PcdGet32 (PcdFspmUpdDataAddress);
+ }
+}
+
/**
Call FspMemoryInit API.
@@ -67,7 +86,7 @@ PeiFspMemoryInit (
return EFI_DEVICE_ERROR;
}
- if ((PcdGet32 (PcdFspmUpdDataAddress) == 0) && (FspmHeaderPtr->CfgRegionSize
!= 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
+ if ((GetFspmUpdDataAddress () == 0) && (FspmHeaderPtr->CfgRegionSize
+ != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
//
// Copy default FSP-M UPD data from Flash
//
@@ -79,7 +98,7 @@ PeiFspMemoryInit (
//
// External UPD is ready, get the buffer from PCD pointer.
//
-FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
+FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress();
ASSERT (FspmUpdDataPtr != NULL);
}
diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
index 00166e56a0..5d0e021401 100644
--- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
@@ -6,7 +6,7 @@
# register TemporaryRamDonePpi to call TempRamExit API, and register
MemoryDiscoveredPpi # notify to call FspSiliconInit API.
#
-# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights
+reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -60,6 +60,7 @@
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64 ## CONSUMES
[Sources]
FspmWrapperPeim.c
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
index f7459a90b5..ddee9cd029 100644
--- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
+++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c
@@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register
MemoryDiscoveredPpi
notify to call FspSiliconInit API.
- Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights
+ reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -181,6 +181,25 @@ FspSiliconInitDoneGetFspHobList (
}
}
+/**
+ Get the F
