[edk2-devel] [edk2-platforms] Pull Request cleanup

[Marcin Juszkiewicz]

I looked at pull requests for edk2-platforms yesterday. Went through 
those from times when we used only mail for patches.


Closed several ones as their code was already merged, left "please 
rebase or close" like comments in those which require work.


Repo went from 44 to 26 open pull requests.


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Re: [edk2-devel] [PATCH edk2-platforms v5 1/1] Move to the GitHub Pull Request workflow

[Marcin Juszkiewicz]

On 3.09.2024 23:41, Michael D Kinney via groups.io wrote:

Pushed as 4f49a843ff..f709251f5b


I did pull request then for sbsaqemu fix. Github action [1] failed:

Failed to create token for "edk2-platforms" (attempt 1): Not Found - 
https://docs.github.com/rest/apps/apps#get-a-repository-installation-for-the-authenticated-app


1. 
https://github.com/tianocore/edk2-platforms/actions/runs/10704761167/job/29678524816?pr=188



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Re: [edk2-devel] SbsaQemu: SIP_SVC_GET_CPU_TOPOLOGY call failed (need updated binaries in edk2-non-osi?)

[Marcin Juszkiewicz]

On 30.08.2024 16:36, Rebecca Cran wrote:

Do the TF-A binaries in edk2-non-osi need updated for SbsaQemu?

With the binaries in Platform/Qemu/Sbsa I get the following error during 
boot:


GetCpuCount: We have 4 cpus.
GetMpidr: MPIDR for CPU0: = 0
GetMpidr: MPIDR for CPU1: = 1
GetMpidr: MPIDR for CPU2: = 2
GetMpidr: MPIDR for CPU3: = 3
GetCpuCount: We have 4 cpus.
ERROR:   sbsa_sip_smc_handler: unhandled SMC (0xc2ca) (function id: 
202)
GetCpuTopology: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no cpu 
topology information.


Ops, forgot to update binaries. Sent patch for review.



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[edk2-devel] [PATCH edk2-non-osi 1/1] Qemu/Sbsa: update TF-A binaries to get SMC topology calls

[Marcin Juszkiewicz]

EDK2 requires SIP_SVC_GET_CPU_TOPOLOGY call nowadays. Bump binaries to
provide it.

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/Sbsa/Readme.md |  15 ++-
 Platform/Qemu/Sbsa/bl1.bin   | Bin 2 -> 2 bytes
 Platform/Qemu/Sbsa/fip.bin   | Bin 82722 -> 82722 bytes
 3 files changed, 10 insertions(+), 5 deletions(-)
 mode change 100644 => 100755 Platform/Qemu/Sbsa/bl1.bin

diff --git a/Platform/Qemu/Sbsa/Readme.md b/Platform/Qemu/Sbsa/Readme.md
index ceef51b6a500..cfacd1443be5 100644
--- a/Platform/Qemu/Sbsa/Readme.md
+++ b/Platform/Qemu/Sbsa/Readme.md
@@ -4,12 +4,17 @@ Qemu SBSA TF-A binaries
 These binaries have been created from the mainline TF-A
 code checked out at the following commit ID:
 
-commit f2735ebccf5173f74c0458736ec526276106097e (tag: v2.11.0, tag: v2.11)
-Merge: 6370f2cbb 669e2b159
-Author: Manish Pandey 
-Date:   Thu May 23 13:51:22 2024 +0200
+commit adc63c99f14ff0584dd8899eb15d8751d7bf4e6e
+Author: Marcin Juszkiewicz 
+Date:   Thu Jun 27 10:11:31 2024 +0200
 
-Merge "docs(changelog): changelog for v2.11 release" into integration
+refactor(qemu-sbsa): use fdt_read_uint32_default more
+
+We have fdt_read_uint32_default() function which allows us to use less
+temporary variables. Let make use of it where applicable.
+
+Signed-off-by: Marcin Juszkiewicz 
+Change-Id: I6fc8a87d5aac427703fd3c8b689e153ed58fa8b7
 
 
 NOTE: No modifications to the source code have been done.
diff --git a/Platform/Qemu/Sbsa/bl1.bin b/Platform/Qemu/Sbsa/bl1.bin
old mode 100644
new mode 100755
index 
9e0136efdf85b743d28b59bb46a66f09fe3a3557..bae19d6382deca0739d87db60edfd07ddffc3a50
GIT binary patch
delta 7793
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Re: [edk2-devel] [PATCH edk2-platforms 0/3] SbsaQemu: Move from ArmSmcLib to ArmMonitorLib

[Marcin Juszkiewicz]

On 8.08.2024 18:51, Leif Lindholm via groups.io wrote:

During last weeks Ard updated ArmMonitorLib to current SMCCC
specification. This allows to use 18 registers as both arguments and
return values.

We already have one SMC call with 5 return values (GetCpuTopology) so
let move all calls to use of ArmMonitorLib to simplify code.

First patch also moves all SMC calls we use into HardwareInfoLib to have
all hardware related queries in one place.

Signed-off-by: Marcin Juszkiewicz 


For the series:
Leif Lindholm 

Thanks!


Thanks, pushed as 22ed007688b181a7682e4f82ae4537def48186c0.


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[edk2-devel] [PATCH edk2-platforms 3/3] SbsaQemu: drop not needed packages

[Marcin Juszkiewicz]

SbsaQemuPlatformDxe does not need ArmVirtPkg and EmbeddedPkg.
SbsaHardwareInfoLib does not need EmbeddedPkg.

Signed-off-by: Marcin Juszkiewicz 
---
 .../Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf   | 2 --
 .../Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf | 1 -
 2 files changed, 3 deletions(-)

diff --git 
a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
index 72492df11342..b94f01cc0e6d 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
@@ -21,8 +21,6 @@ [Sources]
 
 [Packages]
   ArmPkg/ArmPkg.dec
-  ArmVirtPkg/ArmVirtPkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/Qemu/SbsaQemu/SbsaQemu.dec
diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
index dd920546b11a..1f3525eb95f9 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
@@ -19,7 +19,6 @@ [Sources]
 
 [Packages]
   ArmPkg/ArmPkg.dec
-  EmbeddedPkg/EmbeddedPkg.dec
   MdePkg/MdePkg.dec
   MdeModulePkg/MdeModulePkg.dec
   Silicon/Qemu/SbsaQemu/SbsaQemu.dec

-- 
2.45.2



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[edk2-devel] [PATCH edk2-platforms 2/3] SbsaQemu: move from ArmSmcLib to ArmMonitorLib

[Marcin Juszkiewicz]

ArmMonitorLib allows to use 18 registers are both arguments and results.

Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemuHardwareInfoLib.inf  |  2 +-
 .../SbsaQemuHardwareInfoLib.c| 75 ++--
 2 files changed, 37 insertions(+), 40 deletions(-)

diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
index 58a9c03f18b8..dd920546b11a 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
@@ -25,7 +25,7 @@ [Packages]
   Silicon/Qemu/SbsaQemu/SbsaQemu.dec
 
 [LibraryClasses]
-  ArmSmcLib
+  ArmMonitorLib
   ResetSystemLib
 
 [Pcd]
diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 1d5291cf5b28..cd9db02ba9fe 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -7,7 +7,6 @@
 *
 **/
 
-#include 
 #include 
 #include 
 #include 
@@ -24,18 +23,19 @@ GetCpuCount (
   VOID
   )
 {
-  UINTN  Arg0;
-  UINTN  SmcResult;
+  ARM_MONITOR_ARGS  SmcArgs;
 
-  SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL);
-  if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+  SmcArgs.Arg0 = SIP_SVC_GET_CPU_COUNT;
+  ArmMonitorCall (&SmcArgs);
+
+  if (SmcArgs.Arg0 != SMC_SIP_CALL_SUCCESS) {
 DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_COUNT call failed. We have no 
cpu information.\n", __FUNCTION__));
 ResetShutdown ();
   }
 
-  DEBUG ((DEBUG_INFO, "%a: We have %d cpus.\n", __FUNCTION__, Arg0));
+  DEBUG ((DEBUG_INFO, "%a: We have %d cpus.\n", __FUNCTION__, SmcArgs.Arg1));
 
-  return Arg0;
+  return SmcArgs.Arg1;
 }
 
 /**
@@ -50,21 +50,20 @@ GetMpidr (
   IN UINTN  CpuId
   )
 {
-  UINTN  SmcResult;
-  UINTN  Arg0;
-  UINTN  Arg1;
+  ARM_MONITOR_ARGS  SmcArgs;
 
-  Arg0 = CpuId;
+  SmcArgs.Arg0 = SIP_SVC_GET_CPU_NODE;
+  SmcArgs.Arg1 = CpuId;
+  ArmMonitorCall (&SmcArgs);
 
-  SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL);
-  if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+  if (SmcArgs.Arg0 != SMC_SIP_CALL_SUCCESS) {
 DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_NODE call failed. We have no 
MPIDR for CPU%d.\n", __FUNCTION__, CpuId));
 ResetShutdown ();
   }
 
-  DEBUG ((DEBUG_INFO, "%a: MPIDR for CPU%d: = %d\n", __FUNCTION__, CpuId, 
Arg1));
+  DEBUG ((DEBUG_INFO, "%a: MPIDR for CPU%d: = %d\n", __FUNCTION__, CpuId, 
SmcArgs.Arg2));
 
-  return Arg1;
+  return SmcArgs.Arg2;
 }
 
 /**
@@ -79,21 +78,20 @@ GetCpuNumaNode (
   IN UINTN  CpuId
   )
 {
-  UINTN  SmcResult;
-  UINTN  Arg0;
-  UINTN  Arg1;
+  ARM_MONITOR_ARGS  SmcArgs;
 
-  Arg0 = CpuId;
+  SmcArgs.Arg0 = SIP_SVC_GET_CPU_NODE;
+  SmcArgs.Arg1 = CpuId;
+  ArmMonitorCall (&SmcArgs);
 
-  SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL);
-  if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+  if (SmcArgs.Arg0 != SMC_SIP_CALL_SUCCESS) {
 DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_NODE call failed. Could not find 
information for CPU%d.\n", __FUNCTION__, CpuId));
 return 0;
   }
 
-  DEBUG ((DEBUG_INFO, "%a: NUMA node for CPU%d: = %d\n", __FUNCTION__, CpuId, 
Arg0));
+  DEBUG ((DEBUG_INFO, "%a: NUMA node for CPU%d: = %d\n", __FUNCTION__, CpuId, 
SmcArgs.Arg1));
 
-  return Arg0;
+  return SmcArgs.Arg1;
 }
 
 UINT32
@@ -101,17 +99,18 @@ GetMemNodeCount (
   VOID
   )
 {
-  UINTN  SmcResult;
-  UINTN  Arg0;
+  ARM_MONITOR_ARGS  SmcArgs;
 
-  SmcResult = ArmCallSmc0 (SIP_SVC_GET_MEMORY_NODE_COUNT, &Arg0, NULL, NULL);
-  if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+  SmcArgs.Arg0 = SIP_SVC_GET_MEMORY_NODE_COUNT;
+  ArmMonitorCall (&SmcArgs);
+
+  if (SmcArgs.Arg0 != SMC_SIP_CALL_SUCCESS) {
 DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_MEMORY_NODE_COUNT call failed. We 
have no memory information.\n", __FUNCTION__));
 ResetShutdown ();
   }
 
-  DEBUG ((DEBUG_INFO, "%a: The number of the memory nodes is %ld\n", 
__FUNCTION__, Arg0));
-  return (UINT32)Arg0;
+  DEBUG ((DEBUG_INFO, "%a: The number of the memory nodes is %ld\n", 
__FUNCTION__, SmcArgs.Arg1));
+  return (UINT32)SmcArgs.Arg1;
 }
 
 VOID
@@ -120,21 +119,19 @@ GetMemInfo (
   OUT MemoryInfo  *MemInfo
   )
 {
-  UINTN  SmcResult;
-  UINTN  Arg0;
-  UINTN  Arg1;
-  UINTN  Arg2;
+  ARM_MONITOR_ARGS  SmcArgs;
 
-  Arg0 = MemoryId;
+  SmcArgs.Arg0 = SIP_SVC_GET_MEMORY_NODE;
+  SmcArgs.Arg1 = MemoryId;
+  ArmMonitorCall (&SmcArgs);
 
-  SmcResult = ArmCallSmc1 (SIP_SVC_GET_MEMORY_NODE, &Arg0, &Arg1, &Arg2);
-  if (SmcResult

[edk2-devel] [PATCH edk2-platforms 1/3] SbsaQemu: move SMC calls to HardwareInfoLib

[Marcin Juszkiewicz]

We now have HardwareInfo library so let move all hardware queries there.

Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf  |  2 +-
 .../SbsaQemuHardwareInfoLib.inf  |  5 ++
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h  | 31 +++
 .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c| 57 +---
 .../SbsaQemuHardwareInfoLib.c| 57 
 5 files changed, 108 insertions(+), 44 deletions(-)

diff --git 
a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
index 19534b7a274a..72492df11342 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
@@ -28,9 +28,9 @@ [Packages]
   Silicon/Qemu/SbsaQemu/SbsaQemu.dec
 
 [LibraryClasses]
-  ArmSmcLib
   PcdLib
   DebugLib
+  HardwareInfoLib
   NonDiscoverableDeviceRegistrationLib
   UefiDriverEntryPoint
 
diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
index 2acb2a1e7c76..58a9c03f18b8 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
@@ -27,3 +27,8 @@ [Packages]
 [LibraryClasses]
   ArmSmcLib
   ResetSystemLib
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h 
b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
index 7e0bd962f8a9..03335609bef6 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
@@ -28,6 +28,17 @@ typedef struct {
   UINT32Threads;
 } CpuTopology;
 
+typedef struct {
+  UINTNDistributorBase;
+  UINTNRedistributorBase;
+  UINTNItsBase;
+} GicInfo;
+
+typedef struct {
+  UINT32Major;
+  UINT32Minor;
+} PlatformVersion;
+
 /**
   Get CPU count from information passed by Qemu.
 
@@ -109,4 +120,24 @@ GetCpuTopology (
   OUT CpuTopology  *CpuTopo
   );
 
+/**
+  Get GIC information (base of GICD, GICR, GICI) from TF-A.
+
+  @param [out]  GicInfo A pointer to the GIC information.
+**/
+VOID
+GetGicInformation (
+  OUT GicInfo  *GicInfo
+  );
+
+/**
+  Get Platform version from TF-A.
+
+  @param [out]  PlatVer A pointer to the Platform version.
+**/
+VOID
+GetPlatformVersion (
+  OUT PlatformVersion  *PlatVer
+  );
+
 #endif /* HARDWARE_INFO_LIB */
diff --git 
a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
index 657f9700062b..a9c664e1db1f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
@@ -7,14 +7,13 @@
 *
 **/
 
-#include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 
 EFI_STATUS
@@ -24,13 +23,11 @@ InitializeSbsaQemuPlatformDxe (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS Status;
-  UINTN  Size;
-  VOID   *Base;
-  UINTN  Arg0;
-  UINTN  Arg1;
-  UINTN  SmcResult;
-  RETURN_STATUS  Result;
+  EFI_STATUS   Status;
+  UINTNSize;
+  VOID *Base;
+  GicInfo  GicInfo;
+  PlatformVersion  PlatVer;
 
   DEBUG ((DEBUG_INFO, "%a: InitializeSbsaQemuPlatformDxe called\n", 
__FUNCTION__));
 
@@ -68,44 +65,18 @@ InitializeSbsaQemuPlatformDxe (
 return Status;
   }
 
-  SmcResult = ArmCallSmc0 (SIP_SVC_VERSION, &Arg0, &Arg1, NULL);
-  if (SmcResult == SMC_ARCH_CALL_SUCCESS) {
-Result = PcdSet32S (PcdPlatformVersionMajor, Arg0);
-ASSERT_RETURN_ERROR (Result);
-Result = PcdSet32S (PcdPlatformVersionMinor, Arg1);
-ASSERT_RETURN_ERROR (Result);
-  }
+  GetPlatformVersion (&PlatVer);
 
-  Arg0 = PcdGet32 (PcdPlatformVersionMajor);
-  Arg1 = PcdGet32 (PcdPlatformVersionMinor);
+  PcdSet32S (PcdPlatformVersionMajor, PlatVer.Major);
+  PcdSet32S (PcdPlatformVersionMinor, PlatVer.Minor);
 
-  DEBUG ((DEBUG_INFO, "Platform version: %d.%d\n", Arg0, Arg1));
+  DEBUG ((DEBUG_INFO, "Platform version: %d.%d\n", PlatVer.Major, 
PlatVer.Minor));
 
-  SmcResult = ArmCallSmc0 (SIP_SVC_GET_GIC, &Arg0, &Arg1, NULL);
-  if (SmcResult == SMC_ARCH_CALL_SUCCESS) {
-Result = PcdSet64S (PcdGicDistributorBase, Arg0);
-ASSERT_RETURN_ERROR (Result);
-Result = PcdSet64S (PcdGicRedistributorsBase, Arg1);
-ASSERT_RETURN_ERROR (Result);
-  }
+  GetGicInformation (&

[edk2-devel] [PATCH edk2-platforms 0/3] SbsaQemu: Move from ArmSmcLib to ArmMonitorLib

[Marcin Juszkiewicz]

During last weeks Ard updated ArmMonitorLib to current SMCCC
specification. This allows to use 18 registers as both arguments and
return values.

We already have one SMC call with 5 return values (GetCpuTopology) so
let move all calls to use of ArmMonitorLib to simplify code.

First patch also moves all SMC calls we use into HardwareInfoLib to have
all hardware related queries in one place.

Signed-off-by: Marcin Juszkiewicz 

---
Marcin Juszkiewicz (3):
  SbsaQemu: move SMC calls to HardwareInfoLib
  SbsaQemu: move from ArmSmcLib to ArmMonitorLib
  SbsaQemu: drop not needed packages

 .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf |   4 +-
 .../SbsaQemuHardwareInfoLib.inf |   8 +-
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h |  31 +
 .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c   |  57 +++--
 .../SbsaQemuHardwareInfoLib.c   | 132 ++--
 5 files changed, 145 insertions(+), 87 deletions(-)
---
base-commit: a8344967ba17584c13620a639fb24990be020878
change-id: 20240808-move-from-armsmclib-to-armmonitorlib-7ce6c2456c95

Best regards,
-- 
Marcin Juszkiewicz 



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Re: [edk2-devel] [PATCH edk2-platforms v6 0/6] SbsaQemu: Align the PPTT tables with QEMU

[Marcin Juszkiewicz]

On 7.08.2024 18:29, Leif Lindholm via groups.io wrote:

We want to make sure that CPU topology information given to QEMU would
be provided to the operating system. So we use SMC call to ask TF-A for
amount of sockets, clusters, cores and threads set in QEMU config.

The TF-A part is already merged:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27189

Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz

For the series:
Reviewed-by: Leif Lindholm
Thanks!


Thanks.

Pushed as f30a670e507712794b04f9c360467ba329c1f381


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[edk2-devel] [PATCH edk2-platforms v6 5/6] SbsaQemu: introduce helper in PPTT generation

[Marcin Juszkiewicz]

Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 243 +++-
 1 file changed, 133 insertions(+), 110 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index e4bdd5edbd95..61f9de45d082 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -31,6 +31,9 @@ static UINTN  GicItsBase;
 
 #pragma pack ()
 
+static UINTN  mCpuId;
+static UINTN  mCacheId;
+
 /*
  * A Function to Compute the ACPI Table Checksum
  */
@@ -491,6 +494,127 @@ AddSsdtTable (
   return Status;
 }
 
+STATIC
+UINT32
+AddCoresToPpttTable (
+  UINT8*New,
+  UINT32   ClusterOffset,
+  CpuTopology  CpuTopo
+  )
+{
+  UINT32  L1DCacheOffset;
+  UINT32  L1ICacheOffset;
+  UINT32  L2CacheOffset;
+  UINT32  CoreOffset;
+  UINT32  Offset;
+  UINT32  CoreCpuId;
+  UINT32  CoreIndex;
+  UINT32  ThreadIndex;
+  UINT32  *PrivateResourcePtr;
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS  CoreFlags = {
+EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+  };
+
+  if (CpuTopo.Threads > 1) {
+// The Thread structure is the leaf structure, adjust the value of 
CoreFlags.
+CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
+CoreFlags.NodeIsALeaf  = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
+  }
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS  ThreadFlags = {
+EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
+EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+  };
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L1DCache = 
SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L1ICache = 
SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L2Cache  = 
SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+
+  CoreOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+  Offset = CoreOffset;
+
+  for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
+if (CpuTopo.Threads == 1) {
+  CoreCpuId = mCpuId;
+} else {
+  CoreCpuId = 0;
+}
+
+// space for Core + PrivateResourcePtr
+Offset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+Offset += sizeof (UINT32) * 2;
+
+L1DCacheOffset = Offset;
+L1ICacheOffset = L1DCacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+L2CacheOffset  = L1ICacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Core = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+CoreFlags,
+ClusterOffset,
+CoreCpuId,
+2
+);
+
+CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+
+PrivateResourcePtr= (UINT32 *)New;
+PrivateResourcePtr[0] = L1DCacheOffset;
+PrivateResourcePtr[1] = L1ICacheOffset;
+New  += (2 * sizeof (UINT32));
+
+// Add L1 D Cache structure
+L1DCache.CacheId = mCacheId++;
+CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L1 I Cache structure
+L1ICache.CacheId = mCacheId++;
+CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L2 Cache structure
+L2Cache.CacheId = mCacheId++;
+CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+Offset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
+
+if (CpuTopo.Threads == 1) {
+  mCpuId++;
+} else {
+  // Add the Thread PPTT structure
+  for (ThreadIndex = 0; ThreadIndex < CpuTopo.Threads; ThreadIndex++) {
+EFI_ACPI_6_5_P

[edk2-devel] [PATCH edk2-platforms v6 6/6] SbsaQemu: export proper cache values in PPTT

[Marcin Juszkiewicz]

We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.

This change gets rid of fake values in favour of existing ones.

Based on Ampere platform core. Added support for cpus with FEAT_CCIDX
(Neoverse-V1 and above).

Reported-by: Jonathan Cameron 
Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 32 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 45 
 2 files changed, 55 insertions(+), 22 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index fa2e2b30bb7d..9a7c96fc6970 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -74,18 +74,6 @@ typedef struct {
   UINT8uid[8];
 } SBSAQEMU_ACPI_CPU_DEVICE;
 
-#define SBSAQEMU_L1_D_CACHE_SIZE  SIZE_32KB
-#define SBSAQEMU_L1_D_CACHE_SETS  256
-#define SBSAQEMU_L1_D_CACHE_ASSC  2
-
-#define SBSAQEMU_L1_I_CACHE_SIZE  SIZE_32KB
-#define SBSAQEMU_L1_I_CACHE_SETS  256
-#define SBSAQEMU_L1_I_CACHE_ASSC  2
-
-#define SBSAQEMU_L2_CACHE_SIZE  SIZE_512KB
-#define SBSAQEMU_L2_CACHE_SETS  1024
-#define SBSAQEMU_L2_CACHE_ASSC  8
-
 #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
 #define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
 #define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
@@ -106,9 +94,9 @@ typedef struct {
   1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
-SBSAQEMU_L1_D_CACHE_SIZE,  /* Size */  
\
-SBSAQEMU_L1_D_CACHE_SETS,  /* NumberOfSets */  
\
-SBSAQEMU_L1_D_CACHE_ASSC,  /* Associativity */ 
\
+0, /* Size */  
\
+0, /* NumberOfSets */  
\
+0, /* Associativity */ 
\
 {  
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,   
\
@@ -133,9 +121,9 @@ typedef struct {
   1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
-SBSAQEMU_L1_I_CACHE_SIZE,  /* Size */  
\
-SBSAQEMU_L1_I_CACHE_SETS,  /* NumberOfSets */  
\
-SBSAQEMU_L1_I_CACHE_ASSC,  /* Associativity */ 
\
+0, /* Size */  
\
+0, /* NumberOfSets */  
\
+0, /* Associativity */ 
\
 {  
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ,   
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION,
\
@@ -159,10 +147,10 @@ typedef struct {
   1, /* LineSizeValid */   
\
   1, /* CacheIdValid */
\
 }, 
\
-0,   /* NextLevelOfCache */
\
-SBSAQEMU_L2_CACHE_SIZE,  /* Size */
\
-SBSAQEMU_L2_CACHE_SETS,  /* NumberOfSets */
\
-SBSAQEMU_L2_CACHE_ASSC,  /* Associativity */   
\
+0, /* NextLevelOfCache */  
\
+0, /* Size */  
\
+0, /* NumberOfSets */  
\
+0, /* Associativity */ 
\
 {  
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
\
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 61f9de45d082..9554956432c3 100644

[edk2-devel] [PATCH edk2-platforms v6 4/6] SbsaQemu: provide cache info per core in PPTT

[Marcin Juszkiewicz]

During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.

So topology moves from:

Socket -> Clusters -> Cores + Caches -> Threads (if exist)

to:

Socket -> Clusters -> Cores -> Caches + Threads (if exist)

Cache sizes are still 32+32+512KB (L1d, L1i, L2).

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 50 ++--
 1 file changed, 26 insertions(+), 24 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 8770b2293b92..e4bdd5edbd95 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -572,8 +572,8 @@ AddPpttTable (
   TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
   CpuTopo.Sockets * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
  CpuTopo.Clusters * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
- sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
  CpuTopo.Cores * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+  sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
   sizeof 
(UINT32) * 2)));
 
   if (CpuTopo.Threads > 1) {
@@ -617,11 +617,6 @@ AddPpttTable (
 
 ClusterOffset = SocketOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 for (ClusterIndex = 0; ClusterIndex < CpuTopo.Clusters; ClusterIndex++) {
-  L1DCacheOffset = ClusterOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
-  L1ICacheOffset = L1DCacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  L2CacheOffset  = L1ICacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  CoreOffset = L2CacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
   // Add the Cluster PPTT structure
   EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Cluster = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
  ClusterFlags,
@@ -632,27 +627,16 @@ AddPpttTable (
   CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
   New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 
-  // Add L1 D Cache structure
-  L1DCache.CacheId = CacheId++;
-  CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  // Add L1 I Cache structure
-  L1ICache.CacheId = CacheId++;
-  CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  // Add L2 Cache structure
-  L2Cache.CacheId = CacheId++;
-  CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
+  CoreOffset = ClusterOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
   for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
 UINT32  *PrivateResourcePtr;
 UINT32  CoreCpuId;
 
+// two UINT32s for PrivateResourcePtr data
+L1DCacheOffset = CoreOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+L1ICacheOffset = L1DCacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+L2CacheOffset  = L1ICacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
 if (CpuTopo.Threads == 1) {
   CoreCpuId = CpuId;
 } else {
@@ -673,6 +657,23 @@ AddPpttTable (
 PrivateResourcePtr[1] = L1ICacheOffset;
 New  += (2 * sizeof (UINT32));
 
+// Add L1 D Cache structure
+L1DCache.CacheId = CacheId++;
+CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L1 I Cache structure
+L1ICache.CacheId = CacheId++;
+CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New   

[edk2-devel] [PATCH edk2-platforms v6 2/6] SbsaQemu: align the PPTT tables with QEMU

[Marcin Juszkiewicz]

From: Xiong Yining 

To align the CPU topology information recognized by the operating system
with the CPU topology information configured by QEMU, we need to make
use of the CPU topology information to create complex PPTT tables
setups.

We can get the CPU topology information via SMC.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  11 ++
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  32 
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 195 
 3 files changed, 166 insertions(+), 72 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index e5f0748bb16e..085c681ba55f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -88,4 +88,15 @@ typedef struct {
 ClockDomain /* Clock Domain */ 
   \
   }
 
+#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, 
ACPIProcessorID, NumberOfPrivateResources) \
+  {
 \
+EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
+{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
+Flags, 
  /* Flags */\
+Parent,
  /* Parent */   \
+ACPIProcessorID,   
  /* ACPI Processor ID */\
+NumberOfPrivateResources   
  /* Number of private resources */  \
+  }
+
 #endif
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index ae151210c2c6..2f87591e737a 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -166,36 +166,4 @@ typedef struct {
 64/* LineSize */   
\
   }
 
-#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT  {   
\
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR),
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */   
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a Thread */
\
-  EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */   
\
-  EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */
\
-}, 
\
-0,/* Parent */ 
\
-0,/* AcpiProcessorId */
\
-0,/* NumberOfPrivateResources */   
\
-  }
-
-#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT  {  
\
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-(sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))),  
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,   /* AcpiProcessorValid */ 
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a Thread */
\
-  EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */   
\
-  EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */
\
-}, 
\
-0,/* Parent */ 
\
-0,/* AcpiProcessorId

[edk2-devel] [PATCH edk2-platforms v6 3/6] SbsaQemu: update PPTT to ACPI 6.5

[Marcin Juszkiewicz]

ACPI 6.5 is the newest version of specification so far. The only
functional change to make is handling of CacheId (has to be unique and
higher than zero).

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |   4 +-
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  46 ---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 129 ++--
 3 files changed, 95 insertions(+), 84 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index 085c681ba55f..5aaf02e3ca30 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -90,8 +90,8 @@ typedef struct {
 
 #define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, 
ACPIProcessorID, NumberOfPrivateResources) \
   {
 \
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
+EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
 { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
 Flags, 
  /* Flags */\
 Parent,
  /* Parent */   \
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 2f87591e737a..fa2e2b30bb7d 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -87,13 +87,13 @@ typedef struct {
 #define SBSAQEMU_L2_CACHE_ASSC  8
 
 #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
-#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
-#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
-#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
+#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
+#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
 
 #define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT  {
\
-EFI_ACPI_6_3_PPTT_TYPE_CACHE,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE),
\
+EFI_ACPI_6_5_PPTT_TYPE_CACHE,  
\
+sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE),
\
 { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
 {  
\
   1,   /* SizePropertyValid */ 
\
@@ -103,22 +103,24 @@ typedef struct {
   1,   /* CacheTypeValid */
\
   1,   /* WritePolicyValid */  
\
   1,   /* LineSizeValid */ 
\
+  1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
 SBSAQEMU_L1_D_CACHE_SIZE,  /* Size */  
\
 SBSAQEMU_L1_D_CACHE_SETS,  /* NumberOfSets */  
\
 SBSAQEMU_L1_D_CACHE_ASSC,  /* Associativity */ 
\
 {  
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,   
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK,   
\
+  EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
+  EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA

[edk2-devel] [PATCH edk2-platforms v6 1/6] SbsaQemu: get the information of CPU topology via SMC calls

[Marcin Juszkiewicz]

Provide functions to check for CPU topology information:
 - the number of sockets on sbsa-ref platform.
 - the number of clusters in one socket.
 - the number of cores in one cluster.
 - the number of threads in one core.

As SMC calls can return up to 4 return values, the number of sockets,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h  |  1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h  | 26 +++
 .../SbsaQemuHardwareInfoLib.c| 35 
 3 files changed, 62 insertions(+)

diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
index af6b120561ad..b57573735ace 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
@@ -16,6 +16,7 @@
 #define SIP_SVC_GET_GIC_ITSSMC_SIP_FUNCTION_ID(101)
 #define SIP_SVC_GET_CPU_COUNT  SMC_SIP_FUNCTION_ID(200)
 #define SIP_SVC_GET_CPU_NODE   SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY   SMC_SIP_FUNCTION_ID(202)
 #define SIP_SVC_GET_MEMORY_NODE_COUNT  SMC_SIP_FUNCTION_ID(300)
 #define SIP_SVC_GET_MEMORY_NODESMC_SIP_FUNCTION_ID(301)
 
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h 
b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
index e5076274fa0a..7e0bd962f8a9 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
@@ -15,6 +15,19 @@ typedef struct {
   UINT64AddressSize;
 } MemoryInfo;
 
+/**
+  Sockets: the number of sockets on sbsa-ref platform.
+  Clusters: the number of clusters in one socket.
+  Cores: the number of cores in one cluster.
+  Threads: the number of threads in one core.
+**/
+typedef struct {
+  UINT32Sockets;
+  UINT32Clusters;
+  UINT32Cores;
+  UINT32Threads;
+} CpuTopology;
+
 /**
   Get CPU count from information passed by Qemu.
 
@@ -83,4 +96,17 @@ GetNumaNodeCount (
   VOID
   );
 
+/**
+  Get cpu topology (sockets, clusters, cores, threads) from TF-A.
+
+  @param [out]  CpuTopo A pointer to the cpu topology.
+
+
+  @retval   the information of cpu topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  );
+
 #endif /* HARDWARE_INFO_LIB */
diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 05b6fca9e538..b8d1abe2d0bc 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -8,6 +8,7 @@
 **/
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -181,3 +182,37 @@ GetNumaNodeCount (
 
   return NumberNumaNodes;
 }
+
+/**
+  Get CPU topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  )
+{
+  ARM_MONITOR_ARGS  SmcArgs;
+
+  SmcArgs.Arg0 = SIP_SVC_GET_CPU_TOPOLOGY;
+  ArmMonitorCall (&SmcArgs);
+
+  if (SmcArgs.Arg0 != SMC_SIP_CALL_SUCCESS) {
+DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no 
cpu topology information.\n", __FUNCTION__));
+ResetShutdown ();
+  } else {
+CpuTopo->Sockets  = SmcArgs.Arg1;
+CpuTopo->Clusters = SmcArgs.Arg2;
+CpuTopo->Cores= SmcArgs.Arg3;
+CpuTopo->Threads  = SmcArgs.Arg4;
+  }
+
+  DEBUG ((
+DEBUG_INFO,
+"%a: CPU Topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n",
+__FUNCTION__,
+CpuTopo->Sockets,
+CpuTopo->Clusters,
+CpuTopo->Cores,
+CpuTopo->Threads
+));
+}

-- 
2.45.2



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[edk2-devel] [PATCH edk2-platforms v6 0/6] SbsaQemu: Align the PPTT tables with QEMU

[Marcin Juszkiewicz]

We want to make sure that CPU topology information given to QEMU would
be provided to the operating system. So we use SMC call to ask TF-A for
amount of sockets, clusters, cores and threads set in QEMU config.

The TF-A part is already merged:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27189

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 

To: devel@edk2.groups.io
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Graeme Gregory 
Cc: Chen Baozi 
Cc: Xiong Yining 
Cc: Jonathan Cameron 

Changes in v6:
- use ArmMonitorLib for GetCpuTopology() as we need 5 return values
- Link to v5: 
https://openfw.io/edk2-devel/20240711-acpi65-v5-0-a30180b74...@linaro.org

Changes in v5:
- added support for cache sizes on cores with FEAT_CCIDX (Neoverse V1+)
- Link to v4: 
https://openfw.io/edk2-devel/20240710-acpi65-v4-0-bc32224e4...@linaro.org

Changes in v4:
- renamed all *Index variables to *Offset ones for clarity
- renamed static CpuId/CacheId variable to mCpuId/mCacheId
- moved above variables outside of pragma pack
- moved all variables definitions to start of functions
- added reading cpu cache size from CCIDR registers
- changed wording in SbsaHardwareInfoLib header
- changed wording in 3rd patch commit message
- Link to v3: 
https://openfw.io/edk2-devel/20240709-acpi65-v3-0-ee93ba536...@linaro.org

Changes in v3:
- split ACPI 6.5 changes into separate patch
- moved adding cores/threads to separate function
- fixed cache offsets
- Link to v2: 
https://openfw.io/edk2-devel/20240702-acpi65-v2-0-3cb18a892...@linaro.org/T/#t

Changes in v2 (Marcin Juszkiewicz):
- use ACPI 6.5 structures (instead of 6.3)
- add patch to move cache data to cores (instead of clusters)
  - this is for future MPAM support
- reformatted sources using uncrustify
- changed debug output to allow singular values (s/are/:/)

---
Marcin Juszkiewicz (5):
  SbsaQemu: get the information of CPU topology via SMC calls
  SbsaQemu: update PPTT to ACPI 6.5
  SbsaQemu: provide cache info per core in PPTT
  SbsaQemu: introduce helper in PPTT generation
  SbsaQemu: export proper cache values in PPTT

Xiong Yining (1):
  SbsaQemu: align the PPTT tables with QEMU

 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  11 +
 .../Include/IndustryStandard/SbsaQemuAcpi.h | 110 +++-
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h |   1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h |  26 ++
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 274 +---
 .../SbsaQemuHardwareInfoLib.c   |  35 +++
 6 files changed, 341 insertions(+), 116 deletions(-)
---
base-commit: a3c898956a4d48dc5980336fa6ce6eeb23c4f72b
change-id: 20240702-acpi65-1bfdb20bde1a

Best regards,
-- 
Marcin Juszkiewicz 



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Re: [edk2-devel] [PATCH edk2-platforms 1/2] Platform AARCH64: Move PrePeiCore users to Sec.inf

[Marcin Juszkiewicz]

On 31.07.2024 18:33, Ard Biesheuvel wrote:

PrePeiCore has been superseded by Sec.inf, which is a more common naming
for the SEC module, aligned with other architectures. No functional
changes intended.

Switch all users to Sec.inf so the old implementation can be retired
from EDK2.

Signed-off-by: Ard Biesheuvel


For Qemu/SbsaQemu:

Reviewed-by: Marcin Juszkiewicz 

SbsaQemu does not boot without this patch applied:

UEFI firmware (version 1.0 built at 21:12:07 on Aug  5 2024)
add-symbol-file 
/home/marcin/devel/linaro/sbsa-qemu/code/Build/SbsaQemu/DEBUG_CLANGDWARF/AARCH64/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore/DEBUG/ArmPlatformPrePeiCore.dll 
0x1800
add-symbol-file 
/home/marcin/devel/linaro/sbsa-qemu/code/Build/SbsaQemu/DEBUG_CLANGDWARF/AARCH64/MdeModulePkg/Core/Pei/PeiMain/DEBUG/PeiCore.dll 
0x10007240

Synchronous Exception at 0x0


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Re: [edk2-devel] [PATCH edk2-platforms 0/2] SbsaQemu: some simple cleanups

[Marcin Juszkiewicz]

On 15.07.2024 10:55, Ard Biesheuvel wrote:

During recent work I found some places in a need of cleanups. Piled them
in separate branch waiting for better commit messages.

One patch drops Pcds for Core/Cluster count as we do not use them.

Other updates some comments in code.

To:devel@edk2.groups.io
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory

Signed-off-by: Marcin Juszkiewicz
---
Marcin Juszkiewicz (2):
   SbsaQemu: fix comments in SbsaQemuHardwareInfoLib
   SbsaQemu: drop not used Pcds for Cluster/Core count


Reviewed-by: Ard Biesheuvel


Thanks, pushed as b40ce006a6dbc87daedbe1d71b4dc32593101d1d


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Re: [edk2-devel] [PATCH edk2-platforms 2/2] SbsaQemu: set CPU model in SMBIOS

[Marcin Juszkiewicz]

On 12.07.2024 12:01, Ard Biesheuvel wrote:

SbsaQemu platform have several cpu models available. Since start it
reported "arm-virt" one in SMBIOS instead of real one.

This change replaces it with the real cpu model like Cortex-A57,
Neoverse-N2 etc.

Requires change in EDK2 to make PcdProcessorVersion dynamic.

Signed-off-by: Marcin Juszkiewicz

I am going to make the same remark as I did before in a different
context: how is it guaranteed that the code that sets the PCD executes
before the code that consumes it?

Making PCDs dynamic is usually not the solution here, unless they are
set in the PEI phase and consumed in the DXE phase or after.

The EFI SMBIOS protocol has an 'update string' method that you can
call from a platform driver. That might be a better fit here, and the
PCD can remain fixed, and carry a fallback default value.


Thanks. Will take a look.


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[edk2-devel] [PATCH edk2-platforms 2/2] SbsaQemu: set CPU model in SMBIOS

[Marcin Juszkiewicz]

SbsaQemu platform have several cpu models available. Since start it
reported "arm-virt" one in SMBIOS instead of real one.

This change replaces it with the real cpu model like Cortex-A57,
Neoverse-N2 etc.

Requires change in EDK2 to make PcdProcessorVersion dynamic.

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc   |  2 +-
 .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf   |  2 +
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 50 +++
 3 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc 
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index e78f1d71998a..a823a2967525 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -485,7 +485,6 @@ [PcdsFixedAtBuild.common]
   # These values are fixed for now, but should be configurable via
   # something like an emulated SCP.
   gArmTokenSpaceGuid.PcdProcessorManufacturer|L"QEMU"
-  gArmTokenSpaceGuid.PcdProcessorVersion|L"arm-virt"
   gArmTokenSpaceGuid.PcdProcessorSerialNumber|L"SN"
   gArmTokenSpaceGuid.PcdProcessorAssetTag|L"AT"
   gArmTokenSpaceGuid.PcdProcessorPartNumber|L"PN"
@@ -495,6 +494,7 @@ [PcdsFixedAtBuild.common]
 
 [PcdsDynamicDefault.common]
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
+  gArmTokenSpaceGuid.PcdProcessorVersion|L""
 
   # Core and Cluster Count
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|1
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index 727c8e82d16e..616296f5a485 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -53,6 +53,8 @@ [Pcd]
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformVersionMinor
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSmmuBase
 
+  gArmTokenSpaceGuid.PcdProcessorVersion
+
 [Depex]
   gEfiAcpiTableProtocolGuid   ## CONSUMES
 
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index e0eef54ff907..b19edf5a4ff8 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -845,6 +845,51 @@ DisableXhciOnOlderPlatVer (
   return Status;
 }
 
+EFI_STATUS
+UpdateCpuNameInSmbios (
+  )
+{
+  EFI_STATUS  Status;
+  UINT64  ProcessorId;
+  UINT16  PartNum;
+  UINTN   CpuLen;
+  CHAR16  CpuName[16];
+
+  ProcessorId = ArmReadMidr ();
+  PartNum = (UINT16)((ProcessorId >> 4) & 0xFFF);
+
+  switch (PartNum) {
+case 0x51:
+  StrCpyS (CpuName, 16, L"QEMU Max");
+  break;
+case 0xd07:
+  StrCpyS (CpuName, 16, L"Arm Cortex-A57");
+  break;
+case 0xd08:
+  StrCpyS (CpuName, 16, L"Arm Cortex-A72");
+  break;
+case 0xd0c:
+  StrCpyS (CpuName, 16, L"Arm Neoverse-N1");
+  break;
+case 0xd40:
+  StrCpyS (CpuName, 16, L"Arm Neoverse-V1");
+  break;
+case 0xd49:
+  StrCpyS (CpuName, 16, L"Arm Neoverse-N2");
+  break;
+default:
+  StrCpyS (CpuName, 16, L"virtual cpu");
+  break;
+  }
+
+  CpuLen = sizeof (CHAR16) * StrLen (CpuName);
+
+  Status = PcdSetPtrS (PcdProcessorVersion, &CpuLen, CpuName);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
 EFI_STATUS
 EFIAPI
 InitializeSbsaQemuAcpiDxe (
@@ -907,5 +952,10 @@ InitializeSbsaQemuAcpiDxe (
 DEBUG ((DEBUG_ERROR, "Failed to handle XHCI enablement\n"));
   }
 
+  Status = UpdateCpuNameInSmbios ();
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to set CPU name in SMBIOS\n"));
+  }
+
   return EFI_SUCCESS;
 }
--
2.45.2



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[edk2-devel] [PATCH 1/2] ArmPkg: make PcdProcessorVersion dynamic

[Marcin Juszkiewicz]

On SbsaQemu platform we would like to be able to set this variable
during bootup as cpu model can be different on each system run.

Signed-off-by: Marcin Juszkiewicz 
---
 ArmPkg/ArmPkg.dec | 2 +-
 .../Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index c0861140e858..cd922a04ddfa 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -198,7 +198,6 @@ [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x3056
   gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x3057
   gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x3071
-  gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x3072
   gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x3073
   gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x3074
   gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x3075
@@ -301,6 +300,7 @@ [PcdsFixedAtBuild.AARCH64]
 #
 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 
+  gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x3072
   # System Memory (DRAM): These PCDs define the region of in-built system 
memory
   # Some platforms can get DRAM extensions, these additional regions may be
   # declared to UEFI using separate resource descriptor HOBs
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c 
b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 4f2d42133756..4a787b603698 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -527,8 +527,8 @@ AllocateType4AndSetProcessorInformationStrings (
 OemUpdateSmbiosInfo (mHiiHandle, PartNumber, ProcessorPartNumType04);
   }
 
-  if (StrLen ((CHAR16 *)FixedPcdGetPtr (PcdProcessorVersion)) > 0) {
-HiiSetString (mHiiHandle, ProcessorVersion, (CHAR16 *)FixedPcdGetPtr 
(PcdProcessorVersion), NULL);
+  if (StrLen ((CHAR16 *)PcdGetPtr (PcdProcessorVersion)) > 0) {
+HiiSetString (mHiiHandle, ProcessorVersion, (CHAR16 *)PcdGetPtr 
(PcdProcessorVersion), NULL);
   } else {
 OemUpdateSmbiosInfo (mHiiHandle, ProcessorVersion, ProcessorVersionType04);
   }
--
2.45.2



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[edk2-devel] [PATCH 0/2] Set CPU model in SMBIOS

[Marcin Juszkiewicz]

During last changes to SbsaQemu platform I noticed that it says
"arm-virt" as Processor Version in SMBIOS and decided to change it.

The problem is that this value is set in stone as PcdProcessorVersion is
FixedAtBuild one.

So first patch make it dynamic in ArmPkg and second reads MIDR and sets
cpu model name.

Marcin Juszkiewicz (2):
  ArmPkg: make PcdProcessorVersion dynamic
  SbsaQemu: set CPU model in SMBIOS

 ArmPkg/ArmPkg.dec | 2 +-
 .../Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

 Platform/Qemu/SbsaQemu/SbsaQemu.dsc   |  2 +-
 .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf   |  2 +
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 50 +++
 3 files changed, 53 insertions(+), 1 deletion(-)
--
2.45.2



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[edk2-devel] [PATCH edk2-platforms v5 2/6] SbsaQemu: align the PPTT tables with QEMU

[Marcin Juszkiewicz]

From: Xiong Yining 

To align the CPU topology information recognized by the operating system
with the CPU topology information configured by QEMU, we need to make
use of the CPU topology information to create complex PPTT tables
setups.

We can get the CPU topology information via SMC.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  11 ++
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  32 
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 195 
 3 files changed, 166 insertions(+), 72 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index e5f0748bb16e..085c681ba55f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -88,4 +88,15 @@ typedef struct {
 ClockDomain /* Clock Domain */ 
   \
   }
 
+#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, 
ACPIProcessorID, NumberOfPrivateResources) \
+  {
 \
+EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
+{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
+Flags, 
  /* Flags */\
+Parent,
  /* Parent */   \
+ACPIProcessorID,   
  /* ACPI Processor ID */\
+NumberOfPrivateResources   
  /* Number of private resources */  \
+  }
+
 #endif
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index ae151210c2c6..2f87591e737a 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -166,36 +166,4 @@ typedef struct {
 64/* LineSize */   
\
   }
 
-#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT  {   
\
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR),
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */   
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a Thread */
\
-  EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */   
\
-  EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */
\
-}, 
\
-0,/* Parent */ 
\
-0,/* AcpiProcessorId */
\
-0,/* NumberOfPrivateResources */   
\
-  }
-
-#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT  {  
\
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-(sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))),  
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,   /* AcpiProcessorValid */ 
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a Thread */
\
-  EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */   
\
-  EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */
\
-}, 
\
-0,/* Parent */ 
\
-0,/* AcpiProcessorId

[edk2-devel] [PATCH edk2-platforms v5 6/6] SbsaQemu: export proper cache values in PPTT

[Marcin Juszkiewicz]

We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.

This change gets rid of fake values in favour of existing ones.

Based on Ampere platform core. Added support for cpus with FEAT_CCIDX
(Neoverse-V1 and above).

Reported-by: Jonathan Cameron 
Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 32 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 45 
 2 files changed, 55 insertions(+), 22 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index fa2e2b30bb7d..9a7c96fc6970 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -74,18 +74,6 @@ typedef struct {
   UINT8uid[8];
 } SBSAQEMU_ACPI_CPU_DEVICE;
 
-#define SBSAQEMU_L1_D_CACHE_SIZE  SIZE_32KB
-#define SBSAQEMU_L1_D_CACHE_SETS  256
-#define SBSAQEMU_L1_D_CACHE_ASSC  2
-
-#define SBSAQEMU_L1_I_CACHE_SIZE  SIZE_32KB
-#define SBSAQEMU_L1_I_CACHE_SETS  256
-#define SBSAQEMU_L1_I_CACHE_ASSC  2
-
-#define SBSAQEMU_L2_CACHE_SIZE  SIZE_512KB
-#define SBSAQEMU_L2_CACHE_SETS  1024
-#define SBSAQEMU_L2_CACHE_ASSC  8
-
 #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
 #define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
 #define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
@@ -106,9 +94,9 @@ typedef struct {
   1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
-SBSAQEMU_L1_D_CACHE_SIZE,  /* Size */  
\
-SBSAQEMU_L1_D_CACHE_SETS,  /* NumberOfSets */  
\
-SBSAQEMU_L1_D_CACHE_ASSC,  /* Associativity */ 
\
+0, /* Size */  
\
+0, /* NumberOfSets */  
\
+0, /* Associativity */ 
\
 {  
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,   
\
@@ -133,9 +121,9 @@ typedef struct {
   1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
-SBSAQEMU_L1_I_CACHE_SIZE,  /* Size */  
\
-SBSAQEMU_L1_I_CACHE_SETS,  /* NumberOfSets */  
\
-SBSAQEMU_L1_I_CACHE_ASSC,  /* Associativity */ 
\
+0, /* Size */  
\
+0, /* NumberOfSets */  
\
+0, /* Associativity */ 
\
 {  
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ,   
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION,
\
@@ -159,10 +147,10 @@ typedef struct {
   1, /* LineSizeValid */   
\
   1, /* CacheIdValid */
\
 }, 
\
-0,   /* NextLevelOfCache */
\
-SBSAQEMU_L2_CACHE_SIZE,  /* Size */
\
-SBSAQEMU_L2_CACHE_SETS,  /* NumberOfSets */
\
-SBSAQEMU_L2_CACHE_ASSC,  /* Associativity */   
\
+0, /* NextLevelOfCache */  
\
+0, /* Size */  
\
+0, /* NumberOfSets */  
\
+0, /* Associativity */ 
\
 {  
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
\
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 61f9de45d082..9554956432c3 100644

[edk2-devel] [PATCH edk2-platforms v5 5/6] SbsaQemu: introduce helper in PPTT generation

[Marcin Juszkiewicz]

Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 243 +++-
 1 file changed, 133 insertions(+), 110 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index e4bdd5edbd95..61f9de45d082 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -31,6 +31,9 @@ static UINTN  GicItsBase;
 
 #pragma pack ()
 
+static UINTN  mCpuId;
+static UINTN  mCacheId;
+
 /*
  * A Function to Compute the ACPI Table Checksum
  */
@@ -491,6 +494,127 @@ AddSsdtTable (
   return Status;
 }
 
+STATIC
+UINT32
+AddCoresToPpttTable (
+  UINT8*New,
+  UINT32   ClusterOffset,
+  CpuTopology  CpuTopo
+  )
+{
+  UINT32  L1DCacheOffset;
+  UINT32  L1ICacheOffset;
+  UINT32  L2CacheOffset;
+  UINT32  CoreOffset;
+  UINT32  Offset;
+  UINT32  CoreCpuId;
+  UINT32  CoreIndex;
+  UINT32  ThreadIndex;
+  UINT32  *PrivateResourcePtr;
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS  CoreFlags = {
+EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+  };
+
+  if (CpuTopo.Threads > 1) {
+// The Thread structure is the leaf structure, adjust the value of 
CoreFlags.
+CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
+CoreFlags.NodeIsALeaf  = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
+  }
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS  ThreadFlags = {
+EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
+EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+  };
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L1DCache = 
SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L1ICache = 
SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L2Cache  = 
SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+
+  CoreOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+  Offset = CoreOffset;
+
+  for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
+if (CpuTopo.Threads == 1) {
+  CoreCpuId = mCpuId;
+} else {
+  CoreCpuId = 0;
+}
+
+// space for Core + PrivateResourcePtr
+Offset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+Offset += sizeof (UINT32) * 2;
+
+L1DCacheOffset = Offset;
+L1ICacheOffset = L1DCacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+L2CacheOffset  = L1ICacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Core = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+CoreFlags,
+ClusterOffset,
+CoreCpuId,
+2
+);
+
+CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+
+PrivateResourcePtr= (UINT32 *)New;
+PrivateResourcePtr[0] = L1DCacheOffset;
+PrivateResourcePtr[1] = L1ICacheOffset;
+New  += (2 * sizeof (UINT32));
+
+// Add L1 D Cache structure
+L1DCache.CacheId = mCacheId++;
+CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L1 I Cache structure
+L1ICache.CacheId = mCacheId++;
+CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L2 Cache structure
+L2Cache.CacheId = mCacheId++;
+CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+Offset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
+
+if (CpuTopo.Threads == 1) {
+  mCpuId++;
+} else {
+  // Add the Thread PPTT structure
+  for (ThreadIndex = 0; ThreadIndex < CpuTopo.Threads; ThreadIndex++) {
+EFI_ACPI_6_5_P

[edk2-devel] [PATCH edk2-platforms v5 4/6] SbsaQemu: provide cache info per core in PPTT

[Marcin Juszkiewicz]

During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.

So topology moves from:

Socket -> Clusters -> Cores + Caches -> Threads (if exist)

to:

Socket -> Clusters -> Cores -> Caches + Threads (if exist)

Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 50 ++--
 1 file changed, 26 insertions(+), 24 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 8770b2293b92..e4bdd5edbd95 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -572,8 +572,8 @@ AddPpttTable (
   TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
   CpuTopo.Sockets * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
  CpuTopo.Clusters * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
- sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
  CpuTopo.Cores * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+  sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
   sizeof 
(UINT32) * 2)));
 
   if (CpuTopo.Threads > 1) {
@@ -617,11 +617,6 @@ AddPpttTable (
 
 ClusterOffset = SocketOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 for (ClusterIndex = 0; ClusterIndex < CpuTopo.Clusters; ClusterIndex++) {
-  L1DCacheOffset = ClusterOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
-  L1ICacheOffset = L1DCacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  L2CacheOffset  = L1ICacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  CoreOffset = L2CacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
   // Add the Cluster PPTT structure
   EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Cluster = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
  ClusterFlags,
@@ -632,27 +627,16 @@ AddPpttTable (
   CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
   New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 
-  // Add L1 D Cache structure
-  L1DCache.CacheId = CacheId++;
-  CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  // Add L1 I Cache structure
-  L1ICache.CacheId = CacheId++;
-  CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  // Add L2 Cache structure
-  L2Cache.CacheId = CacheId++;
-  CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
+  CoreOffset = ClusterOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
   for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
 UINT32  *PrivateResourcePtr;
 UINT32  CoreCpuId;
 
+// two UINT32s for PrivateResourcePtr data
+L1DCacheOffset = CoreOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+L1ICacheOffset = L1DCacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+L2CacheOffset  = L1ICacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
 if (CpuTopo.Threads == 1) {
   CoreCpuId = CpuId;
 } else {
@@ -673,6 +657,23 @@ AddPpttTable (
 PrivateResourcePtr[1] = L1ICacheOffset;
 New  += (2 * sizeof (UINT32));
 
+// Add L1 D Cache structure
+L1DCache.CacheId = CacheId++;
+CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L1 I Cache structure
+L1ICache.CacheId = CacheId++;
+CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_

[edk2-devel] [PATCH edk2-platforms v5 3/6] SbsaQemu: update PPTT to ACPI 6.5

[Marcin Juszkiewicz]

ACPI 6.5 is the newest version of specification so far. The only
functional change to make is handling of CacheId (has to be unique and
higher than zero).

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |   4 +-
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  46 ---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 129 ++--
 3 files changed, 95 insertions(+), 84 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index 085c681ba55f..5aaf02e3ca30 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -90,8 +90,8 @@ typedef struct {
 
 #define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, 
ACPIProcessorID, NumberOfPrivateResources) \
   {
 \
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
+EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
 { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
 Flags, 
  /* Flags */\
 Parent,
  /* Parent */   \
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 2f87591e737a..fa2e2b30bb7d 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -87,13 +87,13 @@ typedef struct {
 #define SBSAQEMU_L2_CACHE_ASSC  8
 
 #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
-#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
-#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
-#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
+#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
+#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
 
 #define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT  {
\
-EFI_ACPI_6_3_PPTT_TYPE_CACHE,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE),
\
+EFI_ACPI_6_5_PPTT_TYPE_CACHE,  
\
+sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE),
\
 { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
 {  
\
   1,   /* SizePropertyValid */ 
\
@@ -103,22 +103,24 @@ typedef struct {
   1,   /* CacheTypeValid */
\
   1,   /* WritePolicyValid */  
\
   1,   /* LineSizeValid */ 
\
+  1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
 SBSAQEMU_L1_D_CACHE_SIZE,  /* Size */  
\
 SBSAQEMU_L1_D_CACHE_SETS,  /* NumberOfSets */  
\
 SBSAQEMU_L1_D_CACHE_ASSC,  /* Associativity */ 
\
 {  
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,   
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK,   
\
+  EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
+  EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA

[edk2-devel] [PATCH edk2-platforms v5 0/6] SbsaQemu: Align the PPTT tables with QEMU

[Marcin Juszkiewicz]

We want to make sure that CPU topology information given to QEMU would
be provided to the operating system. So we use SMC call to ask TF-A for
amount of sockets, clusters, cores and threads set in QEMU config.

The TF-A part is already merged:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27189

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 

To: devel@edk2.groups.io
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Graeme Gregory 
Cc: Chen Baozi 
Cc: Xiong Yining 
Cc: Jonathan Cameron 

Changes in v5:
- added support for cache sizes on cores with FEAT_CCIDX (Neoverse V1+)
- Link to v4: 
https://openfw.io/edk2-devel/20240710-acpi65-v4-0-bc32224e4...@linaro.org

Changes in v4:
- renamed all *Index variables to *Offset ones for clarity
- renamed static CpuId/CacheId variable to mCpuId/mCacheId
- moved above variables outside of pragma pack
- moved all variables definitions to start of functions
- added reading cpu cache size from CCIDR registers
- changed wording in SbsaHardwareInfoLib header
- changed wording in 3rd patch commit message
- Link to v3: 
https://openfw.io/edk2-devel/20240709-acpi65-v3-0-ee93ba536...@linaro.org

Changes in v3:
- split ACPI 6.5 changes into separate patch
- moved adding cores/threads to separate function
- fixed cache offsets
- Link to v2: 
https://openfw.io/edk2-devel/20240702-acpi65-v2-0-3cb18a892...@linaro.org/T/#t

Changes in v2 (Marcin Juszkiewicz):
- use ACPI 6.5 structures (instead of 6.3)
- add patch to move cache data to cores (instead of clusters)
  - this is for future MPAM support
- reformatted sources using uncrustify
- changed debug output to allow singular values (s/are/:/)

---
Marcin Juszkiewicz (5):
  SbsaQemu: get the information of CPU topology via SMC calls
  SbsaQemu: update PPTT to ACPI 6.5
  SbsaQemu: provide cache info per core in PPTT
  SbsaQemu: introduce helper in PPTT generation
  SbsaQemu: export proper cache values in PPTT

Xiong Yining (1):
  SbsaQemu: align the PPTT tables with QEMU

 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  11 +
 .../Include/IndustryStandard/SbsaQemuAcpi.h | 110 +++-
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h |   1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h |  26 ++
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 274 +---
 .../SbsaQemuHardwareInfoLib.c   |  36 +++
 6 files changed, 342 insertions(+), 116 deletions(-)
---
base-commit: ad553efc01125cad4ebdbe694b82cf6a59ce6a03
change-id: 20240702-acpi65-1bfdb20bde1a

Best regards,
-- 
Marcin Juszkiewicz 



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[edk2-devel] [PATCH edk2-platforms v5 1/6] SbsaQemu: get the information of CPU topology via SMC calls

[Marcin Juszkiewicz]

Provide functions to check for CPU topology information:
 - the number of sockets on sbsa-ref platform.
 - the number of clusters in one socket.
 - the number of cores in one cluster.
 - the number of threads in one core.

As SMC calls can return up to 4 return values, the number of sockets,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h  |  1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h  | 26 ++
 .../SbsaQemuHardwareInfoLib.c| 36 
 3 files changed, 63 insertions(+)

diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
index af6b120561ad..b57573735ace 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
@@ -16,6 +16,7 @@
 #define SIP_SVC_GET_GIC_ITSSMC_SIP_FUNCTION_ID(101)
 #define SIP_SVC_GET_CPU_COUNT  SMC_SIP_FUNCTION_ID(200)
 #define SIP_SVC_GET_CPU_NODE   SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY   SMC_SIP_FUNCTION_ID(202)
 #define SIP_SVC_GET_MEMORY_NODE_COUNT  SMC_SIP_FUNCTION_ID(300)
 #define SIP_SVC_GET_MEMORY_NODESMC_SIP_FUNCTION_ID(301)
 
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h 
b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
index e5076274fa0a..7e0bd962f8a9 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
@@ -15,6 +15,19 @@ typedef struct {
   UINT64AddressSize;
 } MemoryInfo;
 
+/**
+  Sockets: the number of sockets on sbsa-ref platform.
+  Clusters: the number of clusters in one socket.
+  Cores: the number of cores in one cluster.
+  Threads: the number of threads in one core.
+**/
+typedef struct {
+  UINT32Sockets;
+  UINT32Clusters;
+  UINT32Cores;
+  UINT32Threads;
+} CpuTopology;
+
 /**
   Get CPU count from information passed by Qemu.
 
@@ -83,4 +96,17 @@ GetNumaNodeCount (
   VOID
   );
 
+/**
+  Get cpu topology (sockets, clusters, cores, threads) from TF-A.
+
+  @param [out]  CpuTopo A pointer to the cpu topology.
+
+
+  @retval   the information of cpu topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  );
+
 #endif /* HARDWARE_INFO_LIB */
diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 596a3453c70f..a2ea8a523625 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -181,3 +181,39 @@ GetNumaNodeCount (
 
   return NumberNumaNodes;
 }
+
+/**
+  Get CPU topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  )
+{
+  UINTN   SmcResult;
+  UINTN   Arg0;
+  UINTN   Arg1;
+  UINTN   Arg2;
+  UINT32  NumCores = GetCpuCount ();
+
+  SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_TOPOLOGY, &Arg0, &Arg1, &Arg2);
+  if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no 
cpu topology information.\n", __FUNCTION__));
+ResetShutdown ();
+  } else {
+CpuTopo->Sockets  = Arg0;
+CpuTopo->Clusters = Arg1;
+CpuTopo->Cores= Arg2;
+CpuTopo->Threads  = NumCores / (CpuTopo->Sockets * CpuTopo->Clusters * 
CpuTopo->Cores);
+  }
+
+  DEBUG ((
+DEBUG_INFO,
+"%a: CPU Topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n",
+__FUNCTION__,
+CpuTopo->Sockets,
+CpuTopo->Clusters,
+CpuTopo->Cores,
+CpuTopo->Threads
+));
+}

-- 
2.45.2



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Re: [edk2-devel] [PATCH edk2-platforms v4 6/6] SbsaQemu: export proper cache values in PPTT

[Marcin Juszkiewicz]

On 10.07.2024 19:52, Marcin Juszkiewicz via groups.io wrote:

We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.

This change gets rid of fake values in favour of existing ones.

Code taken from Ampere platform core.

Reported-by: Jonathan Cameron
Signed-off-by: Marcin Juszkiewicz


This patch needs work. As this way only works for older cores (before 
Neoverse-V1).


Need to check FEAT_CCIDX and if it present then calculate caches properly.


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[edk2-devel] [PATCH edk2-platforms 2/2] SbsaQemu: drop not used Pcds for Cluster/Core count

[Marcin Juszkiewicz]

We read CPU topology from TF-A so there is no need to keep fake values
anymore.

Signed-off-by: Marcin Juszkiewicz 
---
 Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 3 ---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc   | 4 
 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 1 -
 3 files changed, 8 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec 
b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index 8f3533800767..60daeff915c5 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -49,9 +49,6 @@ [PcdsFixedAtBuild.common]
   
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0x|UINT64|0x0010
 
 [PcdsDynamic.common]
-  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x0100
-  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x0101
-
   
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemManufacturer|L""|VOID*|0x0110
   
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSerialNumber|L""|VOID*|0x0111
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSKU|L""|VOID*|0x0112
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc 
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index e78f1d71998a..02d62b377c45 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -496,10 +496,6 @@ [PcdsFixedAtBuild.common]
 [PcdsDynamicDefault.common]
   gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
 
-  # Core and Cluster Count
-  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|1
-  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|1
-
   # System Memory Size -- 128 MB initially, actual size will be fetched from DT
   # TODO as no DT will be used we should pass this by some other method
   gArmTokenSpaceGuid.PcdSystemMemorySize|0x0800
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index 727c8e82d16e..035901ecab40 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -44,7 +44,6 @@ [LibraryClasses]
 
 [Pcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile
-  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount
 
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gArmTokenSpaceGuid.PcdGicRedistributorsBase

-- 
2.45.2



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[edk2-devel] [PATCH edk2-platforms 1/2] SbsaQemu: fix comments in SbsaQemuHardwareInfoLib

[Marcin Juszkiewicz]

EDK2 takes information from TF-A. How it got that info does not interest
us.

Signed-off-by: Marcin Juszkiewicz 
---
 .../Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c   | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 596a3453c70f..05b6fca9e538 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -15,7 +15,7 @@
 #include 
 
 /**
-  Get CPU count from information passed by Qemu.
+  Get CPU count from information passed by TF-A.
 
 **/
 UINT32
@@ -38,7 +38,7 @@ GetCpuCount (
 }
 
 /**
-  Get MPIDR for a given cpu from device tree passed by Qemu.
+  Get MPIDR for a given cpu from TF-A.
 
   @param [in]   CpuIdIndex of cpu to retrieve MPIDR value for.
 
@@ -67,7 +67,7 @@ GetMpidr (
 }
 
 /**
-  Get NUMA node id for a given cpu from device tree passed by Qemu.
+  Get NUMA node id for a given cpu from TF-A.
 
   @param [in]   CpuIdIndex of cpu to retrieve NUMA node id for.
 

-- 
2.45.2



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[edk2-devel] [PATCH edk2-platforms 0/2] SbsaQemu: some simple cleanups

[Marcin Juszkiewicz]

During recent work I found some places in a need of cleanups. Piled them
in separate branch waiting for better commit messages.

One patch drops Pcds for Core/Cluster count as we do not use them.

Other updates some comments in code.

To: devel@edk2.groups.io
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Graeme Gregory 

Signed-off-by: Marcin Juszkiewicz 
---
Marcin Juszkiewicz (2):
  SbsaQemu: fix comments in SbsaQemuHardwareInfoLib
  SbsaQemu: drop not used Pcds for Cluster/Core count

 Silicon/Qemu/SbsaQemu/SbsaQemu.dec  | 3 ---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 4 
 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf   | 1 -
 .../Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c   | 6 +++---
 4 files changed, 3 insertions(+), 11 deletions(-)
---
base-commit: ad553efc01125cad4ebdbe694b82cf6a59ce6a03
change-id: 20240711-b4-cleanups-9f28a3e38597

Best regards,
-- 
Marcin Juszkiewicz 



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[edk2-devel] [PATCH edk2-platforms v4 4/6] SbsaQemu: provide cache info per core in PPTT

[Marcin Juszkiewicz]

During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.

So topology moves from:

Socket -> Clusters -> Cores + Caches -> Threads (if exist)

to:

Socket -> Clusters -> Cores -> Caches + Threads (if exist)

Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 50 ++--
 1 file changed, 26 insertions(+), 24 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 8770b2293b92..e4bdd5edbd95 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -572,8 +572,8 @@ AddPpttTable (
   TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
   CpuTopo.Sockets * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
  CpuTopo.Clusters * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
- sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
  CpuTopo.Cores * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+  sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
   sizeof 
(UINT32) * 2)));
 
   if (CpuTopo.Threads > 1) {
@@ -617,11 +617,6 @@ AddPpttTable (
 
 ClusterOffset = SocketOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 for (ClusterIndex = 0; ClusterIndex < CpuTopo.Clusters; ClusterIndex++) {
-  L1DCacheOffset = ClusterOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
-  L1ICacheOffset = L1DCacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  L2CacheOffset  = L1ICacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  CoreOffset = L2CacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
   // Add the Cluster PPTT structure
   EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Cluster = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
  ClusterFlags,
@@ -632,27 +627,16 @@ AddPpttTable (
   CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
   New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 
-  // Add L1 D Cache structure
-  L1DCache.CacheId = CacheId++;
-  CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  // Add L1 I Cache structure
-  L1ICache.CacheId = CacheId++;
-  CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  // Add L2 Cache structure
-  L2Cache.CacheId = CacheId++;
-  CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
+  CoreOffset = ClusterOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
   for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
 UINT32  *PrivateResourcePtr;
 UINT32  CoreCpuId;
 
+// two UINT32s for PrivateResourcePtr data
+L1DCacheOffset = CoreOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+L1ICacheOffset = L1DCacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+L2CacheOffset  = L1ICacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
 if (CpuTopo.Threads == 1) {
   CoreCpuId = CpuId;
 } else {
@@ -673,6 +657,23 @@ AddPpttTable (
 PrivateResourcePtr[1] = L1ICacheOffset;
 New  += (2 * sizeof (UINT32));
 
+// Add L1 D Cache structure
+L1DCache.CacheId = CacheId++;
+CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L1 I Cache structure
+L1ICache.CacheId = CacheId++;
+CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_

[edk2-devel] [PATCH edk2-platforms v4 6/6] SbsaQemu: export proper cache values in PPTT

[Marcin Juszkiewicz]

We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.

This change gets rid of fake values in favour of existing ones.

Code taken from Ampere platform core.

Reported-by: Jonathan Cameron 
Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 32 ++---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 36 
 2 files changed, 46 insertions(+), 22 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index fa2e2b30bb7d..9a7c96fc6970 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -74,18 +74,6 @@ typedef struct {
   UINT8uid[8];
 } SBSAQEMU_ACPI_CPU_DEVICE;
 
-#define SBSAQEMU_L1_D_CACHE_SIZE  SIZE_32KB
-#define SBSAQEMU_L1_D_CACHE_SETS  256
-#define SBSAQEMU_L1_D_CACHE_ASSC  2
-
-#define SBSAQEMU_L1_I_CACHE_SIZE  SIZE_32KB
-#define SBSAQEMU_L1_I_CACHE_SETS  256
-#define SBSAQEMU_L1_I_CACHE_ASSC  2
-
-#define SBSAQEMU_L2_CACHE_SIZE  SIZE_512KB
-#define SBSAQEMU_L2_CACHE_SETS  1024
-#define SBSAQEMU_L2_CACHE_ASSC  8
-
 #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
 #define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
 #define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
@@ -106,9 +94,9 @@ typedef struct {
   1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
-SBSAQEMU_L1_D_CACHE_SIZE,  /* Size */  
\
-SBSAQEMU_L1_D_CACHE_SETS,  /* NumberOfSets */  
\
-SBSAQEMU_L1_D_CACHE_ASSC,  /* Associativity */ 
\
+0, /* Size */  
\
+0, /* NumberOfSets */  
\
+0, /* Associativity */ 
\
 {  
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,   
\
@@ -133,9 +121,9 @@ typedef struct {
   1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
-SBSAQEMU_L1_I_CACHE_SIZE,  /* Size */  
\
-SBSAQEMU_L1_I_CACHE_SETS,  /* NumberOfSets */  
\
-SBSAQEMU_L1_I_CACHE_ASSC,  /* Associativity */ 
\
+0, /* Size */  
\
+0, /* NumberOfSets */  
\
+0, /* Associativity */ 
\
 {  
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ,   
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION,
\
@@ -159,10 +147,10 @@ typedef struct {
   1, /* LineSizeValid */   
\
   1, /* CacheIdValid */
\
 }, 
\
-0,   /* NextLevelOfCache */
\
-SBSAQEMU_L2_CACHE_SIZE,  /* Size */
\
-SBSAQEMU_L2_CACHE_SETS,  /* NumberOfSets */
\
-SBSAQEMU_L2_CACHE_ASSC,  /* Associativity */   
\
+0, /* NextLevelOfCache */  
\
+0, /* Size */  
\
+0, /* NumberOfSets */  
\
+0, /* Associativity */ 
\
 {  
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
   EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
\
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 61f9de45d082..49f561e9bc2e 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe

[edk2-devel] [PATCH edk2-platforms v4 2/6] SbsaQemu: align the PPTT tables with QEMU

[Marcin Juszkiewicz]

From: Xiong Yining 

To align the CPU topology information recognized by the operating system
with the CPU topology information configured by QEMU, we need to make
use of the CPU topology information to create complex PPTT tables
setups.

We can get the CPU topology information via SMC.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  11 ++
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  32 
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 195 
 3 files changed, 166 insertions(+), 72 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index e5f0748bb16e..085c681ba55f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -88,4 +88,15 @@ typedef struct {
 ClockDomain /* Clock Domain */ 
   \
   }
 
+#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, 
ACPIProcessorID, NumberOfPrivateResources) \
+  {
 \
+EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
+{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
+Flags, 
  /* Flags */\
+Parent,
  /* Parent */   \
+ACPIProcessorID,   
  /* ACPI Processor ID */\
+NumberOfPrivateResources   
  /* Number of private resources */  \
+  }
+
 #endif
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index ae151210c2c6..2f87591e737a 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -166,36 +166,4 @@ typedef struct {
 64/* LineSize */   
\
   }
 
-#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT  {   
\
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR),
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */   
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a Thread */
\
-  EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */   
\
-  EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */
\
-}, 
\
-0,/* Parent */ 
\
-0,/* AcpiProcessorId */
\
-0,/* NumberOfPrivateResources */   
\
-  }
-
-#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT  {  
\
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-(sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))),  
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,   /* AcpiProcessorValid */ 
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a Thread */
\
-  EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */   
\
-  EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */
\
-}, 
\
-0,/* Parent */ 
\
-0,/* AcpiProcessorId

[edk2-devel] [PATCH edk2-platforms v4 5/6] SbsaQemu: introduce helper in PPTT generation

[Marcin Juszkiewicz]

Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 243 +++-
 1 file changed, 133 insertions(+), 110 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index e4bdd5edbd95..61f9de45d082 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -31,6 +31,9 @@ static UINTN  GicItsBase;
 
 #pragma pack ()
 
+static UINTN  mCpuId;
+static UINTN  mCacheId;
+
 /*
  * A Function to Compute the ACPI Table Checksum
  */
@@ -491,6 +494,127 @@ AddSsdtTable (
   return Status;
 }
 
+STATIC
+UINT32
+AddCoresToPpttTable (
+  UINT8*New,
+  UINT32   ClusterOffset,
+  CpuTopology  CpuTopo
+  )
+{
+  UINT32  L1DCacheOffset;
+  UINT32  L1ICacheOffset;
+  UINT32  L2CacheOffset;
+  UINT32  CoreOffset;
+  UINT32  Offset;
+  UINT32  CoreCpuId;
+  UINT32  CoreIndex;
+  UINT32  ThreadIndex;
+  UINT32  *PrivateResourcePtr;
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS  CoreFlags = {
+EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+  };
+
+  if (CpuTopo.Threads > 1) {
+// The Thread structure is the leaf structure, adjust the value of 
CoreFlags.
+CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
+CoreFlags.NodeIsALeaf  = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
+  }
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS  ThreadFlags = {
+EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
+EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+  };
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L1DCache = 
SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L1ICache = 
SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L2Cache  = 
SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+
+  CoreOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+  Offset = CoreOffset;
+
+  for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
+if (CpuTopo.Threads == 1) {
+  CoreCpuId = mCpuId;
+} else {
+  CoreCpuId = 0;
+}
+
+// space for Core + PrivateResourcePtr
+Offset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+Offset += sizeof (UINT32) * 2;
+
+L1DCacheOffset = Offset;
+L1ICacheOffset = L1DCacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+L2CacheOffset  = L1ICacheOffset + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Core = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+CoreFlags,
+ClusterOffset,
+CoreCpuId,
+2
+);
+
+CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+
+PrivateResourcePtr= (UINT32 *)New;
+PrivateResourcePtr[0] = L1DCacheOffset;
+PrivateResourcePtr[1] = L1ICacheOffset;
+New  += (2 * sizeof (UINT32));
+
+// Add L1 D Cache structure
+L1DCache.CacheId = mCacheId++;
+CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L1 I Cache structure
+L1ICache.CacheId = mCacheId++;
+CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheOffset;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L2 Cache structure
+L2Cache.CacheId = mCacheId++;
+CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+Offset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
+
+if (CpuTopo.Threads == 1) {
+  mCpuId++;
+} else {
+  // Add the Thread PPTT structure
+  for (ThreadIndex = 0; ThreadIndex < CpuTopo.Threads; ThreadIndex++) {
+EFI_ACPI_6_5_P

[edk2-devel] [PATCH edk2-platforms v4 3/6] SbsaQemu: update PPTT to ACPI 6.5

[Marcin Juszkiewicz]

ACPI 6.5 is the newest version of specification so far. The only
functional change to make is handling of CacheId (has to be unique and
higher than zero).

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |   4 +-
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  46 ---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 129 ++--
 3 files changed, 95 insertions(+), 84 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index 085c681ba55f..5aaf02e3ca30 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -90,8 +90,8 @@ typedef struct {
 
 #define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, 
ACPIProcessorID, NumberOfPrivateResources) \
   {
 \
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
+EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
 { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
 Flags, 
  /* Flags */\
 Parent,
  /* Parent */   \
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 2f87591e737a..fa2e2b30bb7d 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -87,13 +87,13 @@ typedef struct {
 #define SBSAQEMU_L2_CACHE_ASSC  8
 
 #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
-#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
-#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
-#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
+#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
+#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
 
 #define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT  {
\
-EFI_ACPI_6_3_PPTT_TYPE_CACHE,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE),
\
+EFI_ACPI_6_5_PPTT_TYPE_CACHE,  
\
+sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE),
\
 { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
 {  
\
   1,   /* SizePropertyValid */ 
\
@@ -103,22 +103,24 @@ typedef struct {
   1,   /* CacheTypeValid */
\
   1,   /* WritePolicyValid */  
\
   1,   /* LineSizeValid */ 
\
+  1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
 SBSAQEMU_L1_D_CACHE_SIZE,  /* Size */  
\
 SBSAQEMU_L1_D_CACHE_SETS,  /* NumberOfSets */  
\
 SBSAQEMU_L1_D_CACHE_ASSC,  /* Associativity */ 
\
 {  
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,   
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK,   
\
+  EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
+  EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA

[edk2-devel] [PATCH edk2-platforms v4 1/6] SbsaQemu: get the information of CPU topology via SMC calls

[Marcin Juszkiewicz]

Provide functions to check for CPU topology information:
 - the number of sockets on sbsa-ref platform.
 - the number of clusters in one socket.
 - the number of cores in one cluster.
 - the number of threads in one core.

As SMC calls can return up to 4 return values, the number of sockets,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h  |  1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h  | 26 ++
 .../SbsaQemuHardwareInfoLib.c| 36 
 3 files changed, 63 insertions(+)

diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
index af6b120561ad..b57573735ace 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
@@ -16,6 +16,7 @@
 #define SIP_SVC_GET_GIC_ITSSMC_SIP_FUNCTION_ID(101)
 #define SIP_SVC_GET_CPU_COUNT  SMC_SIP_FUNCTION_ID(200)
 #define SIP_SVC_GET_CPU_NODE   SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY   SMC_SIP_FUNCTION_ID(202)
 #define SIP_SVC_GET_MEMORY_NODE_COUNT  SMC_SIP_FUNCTION_ID(300)
 #define SIP_SVC_GET_MEMORY_NODESMC_SIP_FUNCTION_ID(301)
 
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h 
b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
index e5076274fa0a..7e0bd962f8a9 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
@@ -15,6 +15,19 @@ typedef struct {
   UINT64AddressSize;
 } MemoryInfo;
 
+/**
+  Sockets: the number of sockets on sbsa-ref platform.
+  Clusters: the number of clusters in one socket.
+  Cores: the number of cores in one cluster.
+  Threads: the number of threads in one core.
+**/
+typedef struct {
+  UINT32Sockets;
+  UINT32Clusters;
+  UINT32Cores;
+  UINT32Threads;
+} CpuTopology;
+
 /**
   Get CPU count from information passed by Qemu.
 
@@ -83,4 +96,17 @@ GetNumaNodeCount (
   VOID
   );
 
+/**
+  Get cpu topology (sockets, clusters, cores, threads) from TF-A.
+
+  @param [out]  CpuTopo A pointer to the cpu topology.
+
+
+  @retval   the information of cpu topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  );
+
 #endif /* HARDWARE_INFO_LIB */
diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 596a3453c70f..a2ea8a523625 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -181,3 +181,39 @@ GetNumaNodeCount (
 
   return NumberNumaNodes;
 }
+
+/**
+  Get CPU topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  )
+{
+  UINTN   SmcResult;
+  UINTN   Arg0;
+  UINTN   Arg1;
+  UINTN   Arg2;
+  UINT32  NumCores = GetCpuCount ();
+
+  SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_TOPOLOGY, &Arg0, &Arg1, &Arg2);
+  if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no 
cpu topology information.\n", __FUNCTION__));
+ResetShutdown ();
+  } else {
+CpuTopo->Sockets  = Arg0;
+CpuTopo->Clusters = Arg1;
+CpuTopo->Cores= Arg2;
+CpuTopo->Threads  = NumCores / (CpuTopo->Sockets * CpuTopo->Clusters * 
CpuTopo->Cores);
+  }
+
+  DEBUG ((
+DEBUG_INFO,
+"%a: CPU Topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n",
+__FUNCTION__,
+CpuTopo->Sockets,
+CpuTopo->Clusters,
+CpuTopo->Cores,
+CpuTopo->Threads
+));
+}

-- 
2.45.2



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[edk2-devel] [PATCH edk2-platforms v4 0/6] SbsaQemu: Align the PPTT tables with QEMU

[Marcin Juszkiewicz]

We want to make sure that CPU topology information given to QEMU would
be provided to the operating system. So we use SMC call to ask TF-A for
amount of sockets, clusters, cores and threads set in QEMU config.

The TF-A part is already merged:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27189

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 

To: devel@edk2.groups.io
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Graeme Gregory 
Cc: Chen Baozi 
Cc: Xiong Yining 
Cc: Jonathan Cameron 

Changes in v4:
- renamed all *Index variables to *Offset ones for clarity
- renamed static CpuId/CacheId variable to mCpuId/mCacheId
- moved above variables outside of pragma pack
- moved all variables definitions to start of functions
- added reading cpu cache size from CCIDR registers
- changed wording in SbsaHardwareInfoLib header
- changed wording in 3rd patch commit message
- Link to v3: 
https://openfw.io/edk2-devel/20240709-acpi65-v3-0-ee93ba536...@linaro.org

Changes in v3:
- split ACPI 6.5 changes into separate patch
- moved adding cores/threads to separate function
- fixed cache offsets
- Link to v2: 
https://openfw.io/edk2-devel/20240702-acpi65-v2-0-3cb18a892...@linaro.org/T/#t

Changes in v2 (Marcin Juszkiewicz):
- use ACPI 6.5 structures (instead of 6.3)
- add patch to move cache data to cores (instead of clusters)
  - this is for future MPAM support
- reformatted sources using uncrustify
- changed debug output to allow singular values (s/are/:/)

---
Marcin Juszkiewicz (5):
  SbsaQemu: get the information of CPU topology via SMC calls
  SbsaQemu: update PPTT to ACPI 6.5
  SbsaQemu: provide cache info per core in PPTT
  SbsaQemu: introduce helper in PPTT generation
  SbsaQemu: export proper cache values in PPTT

Xiong Yining (1):
  SbsaQemu: align the PPTT tables with QEMU

 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  11 +
 .../Include/IndustryStandard/SbsaQemuAcpi.h | 110 +++-
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h |   1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h |  26 ++
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 265 
 .../SbsaQemuHardwareInfoLib.c   |  36 +++
 6 files changed, 333 insertions(+), 116 deletions(-)
---
base-commit: ad553efc01125cad4ebdbe694b82cf6a59ce6a03
change-id: 20240702-acpi65-1bfdb20bde1a

Best regards,
-- 
Marcin Juszkiewicz 



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Re: [edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation

[Marcin Juszkiewicz]

Dnia wtorek, 9 lipca 2024 15:00:12 CEST Leif Lindholm via groups.io pisze:
> On Tue, Jul 09, 2024 at 12:47:10 +0200, Marcin Juszkiewicz wrote:
> > Function AddPpttTable() adding PPTT got too long. This change moves part
> > of it into helper function AddCoresToPpttTable() which takes care of
> > generating entries for Core and below (Cache, Thread).
> > 
> > Signed-off-by: Marcin Juszkiewicz 
> > ---
> > 
> >  .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 237
> >  +++- 1 file changed, 133 insertions(+), 104 deletions(-)
> > 
> > diff --git
> > a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index
> > a7a9664abdcb..a4b2ee2fdcb0 100644
> > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
> > @@ -29,6 +29,9 @@
> > 
> >  static UINTN  GicItsBase;
> > 
> > +static UINTN  CpuId;
> > +static UINTN  CacheId;
> > +
> 
> static variables are supposed to have g (global) or m (module) prefix.
> This is local, so m.
> (Yes, that means I missed that when reviewing the GitIts bits.)
> 
> Also, why are these in a #pragma pack(1) block?

Added right after GicItsBase. Moved out of block.

> >  #pragma pack ()
 
> STATIC
> 
> > +UINT32
> > +AddCoresToPpttTable (
> > +  UINT8*New,
> > +  UINT32   ClusterIndex,
> > +  CpuTopology  CpuTopo
> > +  )

done

> > -  ClusterIndex = CoreIndex;
> > +  CoresPartSize = AddCoresToPpttTable (New, ClusterIndex, CpuTopo);
> > +  ClusterIndex += CoresPartSize;
> 
> This sounds like ClisterIndex is no longer an Index after this patch.
> Should it be renamed?

It is still an Index. CoresPartSize is a size taken by Core/Cache/Thread part 
of this Cluster.




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[edk2-devel] [PATCH edk2-platforms v3 1/5] SbsaQemu: get the information of CPU topology via SMC calls

[Marcin Juszkiewicz]

Provide functions to check for CPU topology information:
 - the number of sockets on sbsa-ref platform.
 - the number of clusters in one socket.
 - the number of cores in one cluster.
 - the number of threads in one core.

As SMC calls can return up to 4 return values, the number of sockets,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h  |  1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h  | 26 ++
 .../SbsaQemuHardwareInfoLib.c| 36 
 3 files changed, 63 insertions(+)

diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
index af6b120561ad..b57573735ace 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
@@ -16,6 +16,7 @@
 #define SIP_SVC_GET_GIC_ITSSMC_SIP_FUNCTION_ID(101)
 #define SIP_SVC_GET_CPU_COUNT  SMC_SIP_FUNCTION_ID(200)
 #define SIP_SVC_GET_CPU_NODE   SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY   SMC_SIP_FUNCTION_ID(202)
 #define SIP_SVC_GET_MEMORY_NODE_COUNT  SMC_SIP_FUNCTION_ID(300)
 #define SIP_SVC_GET_MEMORY_NODESMC_SIP_FUNCTION_ID(301)
 
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h 
b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
index e5076274fa0a..cef6f6f58194 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
@@ -15,6 +15,19 @@ typedef struct {
   UINT64AddressSize;
 } MemoryInfo;
 
+/**
+  Sockets: the number of sockets on sbsa-ref platform.
+  Clusters: the number of clusters in one socket.
+  Cores: the number of cores in one cluster.
+  Threads: the number of threads in one core.
+**/
+typedef struct {
+  UINT32Sockets;
+  UINT32Clusters;
+  UINT32Cores;
+  UINT32Threads;
+} CpuTopology;
+
 /**
   Get CPU count from information passed by Qemu.
 
@@ -83,4 +96,17 @@ GetNumaNodeCount (
   VOID
   );
 
+/**
+  Get cpu topology(sockets, clusters, cores, threads) from device tree passed 
by Qemu.
+
+  @param [out]  CpuTopo A pointer to the cpu topology.
+
+
+  @retval   the information of cpu topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  );
+
 #endif /* HARDWARE_INFO_LIB */
diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 596a3453c70f..b17a2ae99b4e 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -181,3 +181,39 @@ GetNumaNodeCount (
 
   return NumberNumaNodes;
 }
+
+/**
+  Get CPU topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  )
+{
+  UINTN   SmcResult;
+  UINTN   Arg0;
+  UINTN   Arg1;
+  UINTN   Arg2;
+  UINT32  NumCores = GetCpuCount ();
+
+  SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_TOPOLOGY, &Arg0, &Arg1, &Arg2);
+  if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no 
cpu topology information.\n", __FUNCTION__));
+ResetShutdown ();
+  } else {
+CpuTopo->Sockets  = Arg0;
+CpuTopo->Clusters = Arg1;
+CpuTopo->Cores= Arg2;
+CpuTopo->Threads  = NumCores / (CpuTopo->Sockets * CpuTopo->Clusters * 
CpuTopo->Cores);
+  }
+
+  DEBUG ((
+DEBUG_INFO,
+"%a: CPU Topology: sockets are %d, clusters are %d, cores are %d, threads 
are %d\n",
+__FUNCTION__,
+CpuTopo->Sockets,
+CpuTopo->Clusters,
+CpuTopo->Cores,
+CpuTopo->Threads
+));
+}

-- 
2.45.2



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[edk2-devel] [PATCH edk2-platforms v3 2/5] SbsaQemu: align the PPTT tables with QEMU

[Marcin Juszkiewicz]

From: Xiong Yining 

To align the CPU topology information recognized by the operating system
with the CPU topology information configured by QEMU, we need to make
use of the CPU topology information to create complex PPTT tables
setups.

We can get the CPU topology information via SMC.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  11 ++
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  32 
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 187 +++-
 3 files changed, 158 insertions(+), 72 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index e5f0748bb16e..085c681ba55f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -88,4 +88,15 @@ typedef struct {
 ClockDomain /* Clock Domain */ 
   \
   }
 
+#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, 
ACPIProcessorID, NumberOfPrivateResources) \
+  {
 \
+EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
+{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
+Flags, 
  /* Flags */\
+Parent,
  /* Parent */   \
+ACPIProcessorID,   
  /* ACPI Processor ID */\
+NumberOfPrivateResources   
  /* Number of private resources */  \
+  }
+
 #endif
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index ae151210c2c6..2f87591e737a 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -166,36 +166,4 @@ typedef struct {
 64/* LineSize */   
\
   }
 
-#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT  {   
\
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR),
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */   
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a Thread */
\
-  EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */   
\
-  EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */
\
-}, 
\
-0,/* Parent */ 
\
-0,/* AcpiProcessorId */
\
-0,/* NumberOfPrivateResources */   
\
-  }
-
-#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT  {  
\
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-(sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))),  
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,   /* AcpiProcessorValid */ 
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a Thread */
\
-  EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */   
\
-  EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */
\
-}, 
\
-0,/* Parent */ 
\
-0,/* AcpiProcessorId

[edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT

[Marcin Juszkiewicz]

During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.

So topology moves from:

Socket -> Clusters -> Cores + Caches -> Threads (if exist)

to:

Socket -> Clusters -> Cores -> Caches + Threads (if exist)

Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 47 +++-
 1 file changed, 25 insertions(+), 22 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index cf0102d11f1f..a7a9664abdcb 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -562,8 +562,8 @@ AddPpttTable (
   TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
   CpuTopo.Sockets * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
  CpuTopo.Clusters * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
- sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
  CpuTopo.Cores * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+  sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
   sizeof 
(UINT32) * 2)));
 
   if (CpuTopo.Threads > 1) {
@@ -609,10 +609,7 @@ AddPpttTable (
 
 ClusterIndex = SocketIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
-  L1DCacheIndex = ClusterIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
-  L1ICacheIndex = L1DCacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  L2CacheIndex  = L1ICacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  CoreIndex = L2CacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+  CoreIndex = ClusterIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 
   // Add the Cluster PPTT structure
   EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Cluster = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
@@ -624,27 +621,15 @@ AddPpttTable (
   CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
   New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 
-  // Add L1 D Cache structure
-  L1DCache.CacheId = CacheId++;
-  CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  // Add L1 I Cache structure
-  L1ICache.CacheId = CacheId++;
-  CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  // Add L2 Cache structure
-  L2Cache.CacheId = CacheId++;
-  CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
   for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
 UINT32  *PrivateResourcePtr;
 UINT32  CoreCpuId;
 
+// two UINT32s for PrivateResourcePtr data
+L1DCacheIndex = CoreIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+L1ICacheIndex = L1DCacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+L2CacheIndex  = L1ICacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
 if (CpuTopo.Threads == 1) {
   CoreCpuId = CpuId;
 } else {
@@ -665,6 +650,23 @@ AddPpttTable (
 PrivateResourcePtr[1] = L1ICacheIndex;
 New  += (2 * sizeof (UINT32));
 
+// Add L1 D Cache structure
+L1DCache.CacheId = CacheId++;
+CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L1 I Cache structure
+L1ICache.CacheId = CacheId++;
+CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
+New += sizeof 
(EFI_ACPI_6_5_P

[edk2-devel] [PATCH edk2-platforms v3 5/5] SbsaQemu: introduce helper in PPTT generation

[Marcin Juszkiewicz]

Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 237 +++-
 1 file changed, 133 insertions(+), 104 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index a7a9664abdcb..a4b2ee2fdcb0 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -29,6 +29,9 @@
 
 static UINTN  GicItsBase;
 
+static UINTN  CpuId;
+static UINTN  CacheId;
+
 #pragma pack ()
 
 /*
@@ -491,6 +494,126 @@ AddSsdtTable (
   return Status;
 }
 
+UINT32
+AddCoresToPpttTable (
+  UINT8*New,
+  UINT32   ClusterIndex,
+  CpuTopology  CpuTopo
+  )
+{
+  UINT32  L1DCacheIndex;
+  UINT32  L1ICacheIndex;
+  UINT32  L2CacheIndex;
+  UINT32  CoreIndex;
+  UINT32  Index;
+  UINT32  CoreCpuId;
+  UINT32  CoreNum;
+  UINT32  ThreadNum;
+  UINT32  *PrivateResourcePtr;
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS  CoreFlags = {
+EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+  };
+
+  if (CpuTopo.Threads > 1) {
+// The Thread structure is the leaf structure, adjust the value of 
CoreFlags.
+CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
+CoreFlags.NodeIsALeaf  = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
+  }
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS  ThreadFlags = {
+EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
+EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+  };
+
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L1DCache = 
SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L1ICache = 
SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+  EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE  L2Cache  = 
SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+
+  CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+  Index = CoreIndex;
+
+  for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
+if (CpuTopo.Threads == 1) {
+  CoreCpuId = CpuId;
+} else {
+  CoreCpuId = 0;
+}
+
+// space for Core + PrivateResourcePtr
+Index += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+Index += sizeof (UINT32) * 2;
+
+L1DCacheIndex = Index;
+L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+L2CacheIndex  = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Core = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+CoreFlags,
+ClusterIndex,
+CoreCpuId,
+2
+);
+
+CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+
+PrivateResourcePtr= (UINT32 *)New;
+PrivateResourcePtr[0] = L1DCacheIndex;
+PrivateResourcePtr[1] = L1ICacheIndex;
+New  += (2 * sizeof (UINT32));
+
+// Add L1 D Cache structure
+L1DCache.CacheId = CacheId++;
+CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L1 I Cache structure
+L1ICache.CacheId = CacheId++;
+CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+// Add L2 Cache structure
+L2Cache.CacheId = CacheId++;
+CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+Index += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
+
+if (CpuTopo.Threads == 1) {
+  CpuId++;
+} else {
+  // Add the Thread PPTT structure
+  for (ThreadNum = 0; ThreadNum < CpuTopo.Threads; ThreadNum++) {
+EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Thread = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+  

[edk2-devel] [PATCH edk2-platforms v3 3/5] SbsaQemu: update PPTT to ACPI 6.5

[Marcin Juszkiewicz]

ACPI 6.5 is the newest version of specification so far. The only change
to make is handling of CacheId (has to be unique and higher than zero).

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |   4 +-
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  46 ---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 127 ++--
 3 files changed, 94 insertions(+), 83 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index 085c681ba55f..5aaf02e3ca30 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -90,8 +90,8 @@ typedef struct {
 
 #define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, 
ACPIProcessorID, NumberOfPrivateResources) \
   {
 \
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
+EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
 { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
 Flags, 
  /* Flags */\
 Parent,
  /* Parent */   \
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 2f87591e737a..fa2e2b30bb7d 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -87,13 +87,13 @@ typedef struct {
 #define SBSAQEMU_L2_CACHE_ASSC  8
 
 #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
-#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
-#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
-#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
+#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
+#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
 
 #define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT  {
\
-EFI_ACPI_6_3_PPTT_TYPE_CACHE,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE),
\
+EFI_ACPI_6_5_PPTT_TYPE_CACHE,  
\
+sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE),
\
 { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
 {  
\
   1,   /* SizePropertyValid */ 
\
@@ -103,22 +103,24 @@ typedef struct {
   1,   /* CacheTypeValid */
\
   1,   /* WritePolicyValid */  
\
   1,   /* LineSizeValid */ 
\
+  1,   /* CacheIdValid */  
\
 }, 
\
 0, /* NextLevelOfCache */  
\
 SBSAQEMU_L1_D_CACHE_SIZE,  /* Size */  
\
 SBSAQEMU_L1_D_CACHE_SETS,  /* NumberOfSets */  
\
 SBSAQEMU_L1_D_CACHE_ASSC,  /* Associativity */ 
\
 {  
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,   
\
-  EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK,   
\
+  EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, 
\
+  EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA

[edk2-devel] [PATCH edk2-platforms v3 0/5] SbsaQemu: Align the PPTT tables with QEMU

[Marcin Juszkiewicz]

We want to make sure that CPU topology information given to QEMU would
be provided to the operating system. So we use SMC call to ask TF-A for
amount of sockets, clusters, cores and threads set in QEMU config.

The TF-A part is already merged:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27189

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 

To: devel@edk2.groups.io
Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Graeme Gregory 
Cc: Chen Baozi 
Cc: Xiong Yining 

Changes in v3:
- split ACPI 6.5 changes into separate patch
- moved adding cores/threads to separate function
- fixed cache offsets
- Link to v2: 
https://openfw.io/edk2-devel/20240702-acpi65-v2-0-3cb18a892...@linaro.org/T/#t

Changes in v2 (Marcin Juszkiewicz):
- use ACPI 6.5 structures (instead of 6.3)
- add patch to move cache data to cores (instead of clusters)
  - this is for future MPAM support
- reformatted sources using uncrustify
- changed debug output to allow singular values (s/are/:/)

---
Marcin Juszkiewicz (4):
  SbsaQemu: get the information of CPU topology via SMC calls
  SbsaQemu: update PPTT to ACPI 6.5
  SbsaQemu: provide cache info per core in PPTT
  SbsaQemu: introduce helper in PPTT generation

Xiong Yining (1):
  SbsaQemu: align the PPTT tables with QEMU

 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  11 +
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  78 +++
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h |   1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h |  26 +++
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 228 
 .../SbsaQemuHardwareInfoLib.c   |  36 
 6 files changed, 286 insertions(+), 94 deletions(-)
---
base-commit: ad553efc01125cad4ebdbe694b82cf6a59ce6a03
change-id: 20240702-acpi65-1bfdb20bde1a

Best regards,
-- 
Marcin Juszkiewicz 



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Re: [edk2-devel] [PATCH edk2-platforms v2] SbsaQemu: use FEAT_RNG for EFI_RNG_PROTOCOL

[Marcin Juszkiewicz]

Dnia czwartek, 4 lipca 2024 13:27:38 CEST Leif Lindholm pisze:
> > By default we have Neoverse-N2 cpu which supports FEAT_RNG feature. This
> > allows us to add RngDxe to have EFI_RNG_PROTOCOL available on
> > Neoverse-N2 and 'max' cpu cores.
> > 
> > Commit 5de5e230a80bed083360da95ba16a2c4a001620d (in EDK2) enabled that for
> > ArmVirt platform.
> > 
> > RNDR is implemented by both Neoverse-N2 and 'max' cpu implemented by QEMU.
> > Other cpu models lack it which prevents the RngDxe driver from running,
> > resulting in the same situation as before.
> > 
> > TRNG is not implemented in TCG mode but is required by RngDxe to run.
> > 
> > On older cpu cores nothing changes.
> > 
> > Signed-off-by: Marcin Juszkiewicz 
> 
> Thanks!
> 
> Reviewed-by: Leif Lindholm 
> With one niggle below:

Thanks. Fixed and pushed as 25d66c5b9e5cd672b6e2723d4308cd815639f880





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[edk2-devel] [PATCH edk2-platforms v2] SbsaQemu: use FEAT_RNG for EFI_RNG_PROTOCOL

[Marcin Juszkiewicz]

By default we have Neoverse-N2 cpu which supports FEAT_RNG feature. This
allows us to add RngDxe to have EFI_RNG_PROTOCOL available on
Neoverse-N2 and 'max' cpu cores.

Commit 5de5e230a80bed083360da95ba16a2c4a001620d (in EDK2) enabled that for
ArmVirt platform.

RNDR is implemented by both Neoverse-N2 and 'max' cpu implemented by QEMU.
Other cpu models lack it which prevents the RngDxe driver from running,
resulting in the same situation as before.

TRNG is not implemented in TCG mode but is required by RngDxe to run.

On older cpu cores nothing changes.

Signed-off-by: Marcin Juszkiewicz 
---
By default we have Neoverse-N2 cpu which supports FEAT_RNG feature. This
allows us to add RngDxe to have EFI_RNG_PROTOCOL available on
Neoverse-N2 and 'max' cpu cores.

When I boot with Neoverse-N2 or 'max' cpu then EFI_RNG_PROTOCOL gets
reported by 'EFI stub' on Linux boot and KASLR gets enabled.

Commit 5de5e230a80bed083360da95ba16a2c4a001620d (in EDK2) enabled that for
ArmVirt platform.

RNDR is implemented by both Neoverse-N2 and 'max' cpu implemented by QEMU.
Other cpu models lack it which prevents the RngDxe driver from running,
resulting in the same situation as before.

TRNG is not implemented in TCG mode but is required by RngDxe to run.

On older cpu cores nothing changes.
---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 7 +++
 Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
 2 files changed, 8 insertions(+)

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc 
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 9306986bf7c0..72b6a6d9a8b8 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -660,6 +660,13 @@ [Components.common]
   OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
   MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.inf
+  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf {
+
+  RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf
+  ArmTrngLib|ArmPkg/Library/ArmTrngLib/ArmTrngLib.inf
+  ArmMonitorLib|ArmPkg/Library/ArmMonitorLib/ArmMonitorLib.inf
+  }
+
 
   #
   # FAT filesystem + GPT/MBR partitioning
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf 
b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
index b35f42e11aa4..51a1ef8519f9 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
@@ -192,6 +192,7 @@ [FV.FvMain]
   INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
   INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
   INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  INF SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
 
   #
   # FAT filesystem + GPT/MBR partitioning + UDF filesystem

---
base-commit: c7ed8deaa8c1d7ee83af994b2c90d4490ef27bdc
change-id: 20240703-efi-rng-protocol-be991536709a

Best regards,
-- 
Marcin Juszkiewicz 



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[edk2-devel] [PATCH edk2-platforms v2 2/3] Silicon/SbsaQemu: align the PPTT tables with QEMU

[Marcin Juszkiewicz]

From: Xiong Yining 

To align the CPU topology information recognized by the operating system
with the CPU topology information configured by QEMU, we need to make
use of the CPU topology information to create complex PPTT tables
setups.

We get the CPU topology information via SMC.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  17 +-
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  78 +++-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 190 +++-
 3 files changed, 180 insertions(+), 105 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index e5f0748bb16e..5e50749051c9 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -61,8 +61,7 @@ typedef struct {
 
 #define GTDT_WDTIMER_FLAGS  (GTDT_WDTIMER_ACTIVE_HIGH | 
GTDT_WDTIMER_LEVEL_TRIGGERED)
 
-#define SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT(  
   \
-   
   ProximityDomain, Base, Length, Flags)   \
+#define SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT(ProximityDomain, Base, 
Length, Flags) \
   {
   \
 1,  /* Type */ 
   \
 sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE),/* Length */   
   \
@@ -77,8 +76,7 @@ typedef struct {
 0   /* Reserved */ 
   \
   }
 
-#define SBSAQEMU_ACPI_GICC_AFFINITY_STRUCTURE_INIT(
   \
-   
   ProximityDomain, ACPIProcessorUID, Flags, ClockDomain)  \
+#define SBSAQEMU_ACPI_GICC_AFFINITY_STRUCTURE_INIT(ProximityDomain, 
ACPIProcessorUID, Flags, ClockDomain) \
   {
   \
 3,  /* Type */ 
   \
 sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE),  /* Length */   
   \
@@ -88,4 +86,15 @@ typedef struct {
 ClockDomain /* Clock Domain */ 
   \
   }
 
+#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, 
ACPIProcessorID, NumberOfPrivateResources) \
+  {
 \
+EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \
+{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
+Flags, 
  /* Flags */\
+Parent,
  /* Parent */   \
+ACPIProcessorID,   
  /* ACPI Processor ID */\
+NumberOfPrivateResources   
  /* Number of private resources */  \
+  }
+
 #endif
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index ae151210c2c6..fa2e2b30bb7d 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -87,13 +87,13 @@ typedef struct {
 #define SBSAQEMU_L2_CACHE_ASSC  8
 
 #define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
-#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
-#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
-#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+#define L1_D_CACHE_INDEX  (CLUSTER_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
+#define L1_I_CACHE_INDEX  (L1_D_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
+#define L2_CACHE_INDEX(L1_I_CACHE_INDEX + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
 
 #define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT  {
\
-EFI_ACPI_6_3_PPTT_TYPE_CACHE,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE

[edk2-devel] [PATCH edk2-platforms v2 3/3] SbsaQemu: provide cache info per core in PPTT

[Marcin Juszkiewicz]

During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.

So topology moves from:

Socket -> Clusters -> Cores + Caches -> Threads (if exist)

to:

Socket -> Clusters -> Cores -> Caches + Threads (if exist)

Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 46 ++--
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 4c275faf7de6..02c84a16a4bc 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -561,8 +561,8 @@ AddPpttTable (
   TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
   CpuTopo.Sockets * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
  CpuTopo.Clusters * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
- sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
  CpuTopo.Cores * (sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+  sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
   sizeof 
(UINT32) * 2)));
 
   if (CpuTopo.Threads > 1) {
@@ -604,37 +604,21 @@ AddPpttTable (
 
 ClusterIndex = SocketIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) {
-  L1DCacheIndex = ClusterIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
-  L1ICacheIndex = L1DCacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  L2CacheIndex  = L1ICacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-  CoreIndex = L2CacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+  CoreIndex = ClusterIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 
   // Add the Cluster PPTT structure
   EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR  Cluster = 
SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (ClusterFlags, 
SocketIndex, 0, 0);
   CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
   New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
 
-  L1DCache.CacheId = CacheId++;
-  // Add L1 D Cache structure
-  CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  L1ICache.CacheId = CacheId++;
-  // Add L1 I Cache structure
-  CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
-  New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
-  L2Cache.CacheId = CacheId++;
-  // Add L2 Cache structure
-  CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
-  New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
   for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) {
 UINT32  *PrivateResourcePtr;
 UINT32  CoreCpuId;
 
+L1DCacheIndex = CoreIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+L1ICacheIndex = L1DCacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+L2CacheIndex  = L1ICacheIndex + sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
 if (CpuTopo.Threads == 1) {
   CoreCpuId = CpuId;
 } else {
@@ -650,6 +634,23 @@ AddPpttTable (
 PrivateResourcePtr[1] = L1ICacheIndex;
 New  += (2 * sizeof (UINT32));
 
+L1DCache.CacheId = CacheId++;
+// Add L1 D Cache structure
+CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+L1ICache.CacheId = CacheId++;
+// Add L1 I Cache structure
+CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 
L2CacheIndex;
+New += sizeof 
(EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+L2Cache.CacheId = Ca

[edk2-devel] [PATCH edk2-platforms v2 1/3] Platform/SbsaQemu: get the information of CPU topology via SMC calls

[Marcin Juszkiewicz]

Provide functions to check for CPU topology information:
- the number of sockets on sbsa-ref platform.
- the number of clusters in one socket.
- the number of cores in one cluster.
- the number of threads in one core.

As SMC calls can return up to 4 return values. the number of
sockets, clusters and cores are read from TF-A using platform
specific SMC calls. And the number of threads is caluculated
using the total number of cpus and the number of sockets,
clusters and cores.

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h  |  1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h  | 26 ++
 .../SbsaQemuHardwareInfoLib.c| 36 
 3 files changed, 63 insertions(+)

diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
index af6b120561ad..b57573735ace 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
@@ -16,6 +16,7 @@
 #define SIP_SVC_GET_GIC_ITSSMC_SIP_FUNCTION_ID(101)
 #define SIP_SVC_GET_CPU_COUNT  SMC_SIP_FUNCTION_ID(200)
 #define SIP_SVC_GET_CPU_NODE   SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY   SMC_SIP_FUNCTION_ID(202)
 #define SIP_SVC_GET_MEMORY_NODE_COUNT  SMC_SIP_FUNCTION_ID(300)
 #define SIP_SVC_GET_MEMORY_NODESMC_SIP_FUNCTION_ID(301)
 
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h 
b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
index e5076274fa0a..cef6f6f58194 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
@@ -15,6 +15,19 @@ typedef struct {
   UINT64AddressSize;
 } MemoryInfo;
 
+/**
+  Sockets: the number of sockets on sbsa-ref platform.
+  Clusters: the number of clusters in one socket.
+  Cores: the number of cores in one cluster.
+  Threads: the number of threads in one core.
+**/
+typedef struct {
+  UINT32Sockets;
+  UINT32Clusters;
+  UINT32Cores;
+  UINT32Threads;
+} CpuTopology;
+
 /**
   Get CPU count from information passed by Qemu.
 
@@ -83,4 +96,17 @@ GetNumaNodeCount (
   VOID
   );
 
+/**
+  Get cpu topology(sockets, clusters, cores, threads) from device tree passed 
by Qemu.
+
+  @param [out]  CpuTopo A pointer to the cpu topology.
+
+
+  @retval   the information of cpu topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  );
+
 #endif /* HARDWARE_INFO_LIB */
diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 596a3453c70f..a2ea8a523625 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -181,3 +181,39 @@ GetNumaNodeCount (
 
   return NumberNumaNodes;
 }
+
+/**
+  Get CPU topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology  *CpuTopo
+  )
+{
+  UINTN   SmcResult;
+  UINTN   Arg0;
+  UINTN   Arg1;
+  UINTN   Arg2;
+  UINT32  NumCores = GetCpuCount ();
+
+  SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_TOPOLOGY, &Arg0, &Arg1, &Arg2);
+  if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no 
cpu topology information.\n", __FUNCTION__));
+ResetShutdown ();
+  } else {
+CpuTopo->Sockets  = Arg0;
+CpuTopo->Clusters = Arg1;
+CpuTopo->Cores= Arg2;
+CpuTopo->Threads  = NumCores / (CpuTopo->Sockets * CpuTopo->Clusters * 
CpuTopo->Cores);
+  }
+
+  DEBUG ((
+DEBUG_INFO,
+"%a: CPU Topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n",
+__FUNCTION__,
+CpuTopo->Sockets,
+CpuTopo->Clusters,
+CpuTopo->Cores,
+CpuTopo->Threads
+));
+}

-- 
2.45.2



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[edk2-devel] [PATCH edk2-platforms v2 0/3] SbsaQemu: Align the PPTT tables with QEMU

[Marcin Juszkiewicz]

We want to make sure that CPU topology information given to QEMU would
be provided to the operating system. So we use SMC call to ask TF-A for
amount of sockets, clusters, cores and threads set in QEMU config.

The TF-A part is already merged:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27189

Signed-off-by: Xiong Yining 
Signed-off-by: Marcin Juszkiewicz 

Changes since v1 (Marcin Juszkiewicz):
- use ACPI 6.5 structures (instead of 6.3)
- add patch to move cache data to cores (instead of clusters)
  - this is for future MPAM support
- reformatted sources using uncrustify
- changed debug output to allow singular values (s/are/:/)

---
Marcin Juszkiewicz (2):
  Platform/SbsaQemu: get the information of CPU topology via SMC calls
  SbsaQemu: provide cache info per core in PPTT

Xiong Yining (1):
  Silicon/SbsaQemu: align the PPTT tables with QEMU

 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h   |  17 +-
 .../Include/IndustryStandard/SbsaQemuAcpi.h |  78 +++-
 .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h |   1 +
 .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h |  26 +++
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 192 +++-
 .../SbsaQemuHardwareInfoLib.c   |  36 
 6 files changed, 245 insertions(+), 105 deletions(-)
---
base-commit: ba73190ddccc0d0e8c9ff4d3cac1f10bde8b0f71
change-id: 20240702-acpi65-1bfdb20bde1a

Best regards,
-- 
Marcin Juszkiewicz 



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Re: [edk2-devel] [PATCH edk2-platforms 1/1] SbsaQemu: use FEAT_RNG for EFI_RNG_PROTOCOL

[Marcin Juszkiewicz]

W dniu 1.07.2024 o 13:08, Leif Lindholm pisze:

On 2024-06-27 15:22, Marcin Juszkiewicz wrote:

By default we have Neoverse-N2 cpu which supports FEAT_RNG feature.

Commit 5de5e230a80bed083360da95ba16a2c4a001620d (in EDK2) enabled that 
for

ArmVirt platform.

RNDR is implemented by both Neoverse-N2 and 'max' cpu implemented by 
QEMU.

Other cpu models lack it which prevents the RngDxe driver from running,
resulting in the same situation as before.

TRNG is not implemented in TCG mode but is required by RngDxe to run.


This commit also adds RngDxe for this platform, which neither the short 
nor the long description mentions.



Signed-off-by: Marcin Juszkiewicz 
---
  Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +-
  Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
  2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc 
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc

index 9306986bf7c0..3463e5c7a635 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -148,7 +148,9 @@ [LibraryClasses.common]
    #


Since sbsa-ref still supports processors without FEAT_RNG, this may 
cause unexpected breakages for some users.


That's why I sent it as more of RFC than changes for merging.


Could we first of all conditionalise this change:

[Defines]
...
   DEFINE_DEBUG_PRINT_ERROR_LEVEL = ...
   DEFINE FEATRNG_ENABLE = TRUE

so that someone who still wishes to run tests against older cpus can 
still do so through a rebuild with -D FEATRNG_ENABLE=FALSE


Is there a way to load both BaseRngLib and BaseRngLibTimerLib and switch
between them depending on availability of FEAT_RNG?
 

    IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
    OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf


!if $(FEATRNG_ENABLE) == TRUE
   RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf
!else
   RngLib|MdeModulePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf
!endif
   ArmTrngLib|ArmPkg/Library/ArmTrngLib/ArmTrngLib.inf
   ArmMonitorLib|ArmPkg/Library/ArmMonitorLib/ArmMonitorLib.inf


    BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
    #
@@ -660,6 +662,8 @@ [Components.common]
    OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
    MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf

Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.inf

+  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
+


Spurious added newline.


    #
    # FAT filesystem + GPT/MBR partitioning
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf 
b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf

index b35f42e11aa4..51a1ef8519f9 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
@@ -192,6 +192,7 @@ [FV.FvMain]
    INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
    INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
    INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  INF SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf


Second:
What is the failure mode of running the BaseRngLib flavour on cpus that 
don't support FEAT_RNG? RngDxe itself seems to do the right thing, but 
do we get any warning messages or will certain operations now fail 
silently?


On FEAT_RNG cores we get:

InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 101FAD68798
ProtectUefiImageCommon - 0xFAD683C0
  - 0x0101FBBDB000 - 0x7000
ArmTrngLib could not be correctly initialized.
InstallProtocolInterface: 3152BCA5-EADE-433D-862E-C01CDC291F44 101FBBE0020
Loading driver B601F8C4-43B7-4784-95B1-F4226CB40CEE


On core without FEAT_RNG:

InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 101FAD68798
ProtectUefiImageCommon - 0xFAD683C0
  - 0x0101FBBDB000 - 0x7000
ArmTrngLib could not be correctly initialized.
Error: Image at 101FBBDB000 start failed: 0001
remove-symbol-file 
/home/marcin/devel/linaro/sbsa-qemu/code/Build/SbsaQemu/DEBUG_GCC/AARCH64/SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe/DEBUG/RngDxe.dll
 0xFBBDC000
Loading driver B601F8C4-43B7-4784-95B1-F4226CB40CEE


So there is some kind of information but you need to know what
to look for ;(



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[edk2-devel] [PATCH edk2-platforms 1/1] SbsaQemu: use FEAT_RNG for EFI_RNG_PROTOCOL

[Marcin Juszkiewicz]

By default we have Neoverse-N2 cpu which supports FEAT_RNG feature.

Commit 5de5e230a80bed083360da95ba16a2c4a001620d (in EDK2) enabled that for
ArmVirt platform.

RNDR is implemented by both Neoverse-N2 and 'max' cpu implemented by QEMU.
Other cpu models lack it which prevents the RngDxe driver from running,
resulting in the same situation as before.

TRNG is not implemented in TCG mode but is required by RngDxe to run.

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +-
 Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc 
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 9306986bf7c0..3463e5c7a635 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -148,7 +148,9 @@ [LibraryClasses.common]
   #
   IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
   OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
-  RngLib|MdeModulePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf
+  RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf
+  ArmTrngLib|ArmPkg/Library/ArmTrngLib/ArmTrngLib.inf
+  ArmMonitorLib|ArmPkg/Library/ArmMonitorLib/ArmMonitorLib.inf
   BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
 
   #
@@ -660,6 +662,8 @@ [Components.common]
   OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
   MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
   Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.inf
+  SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
+
 
   #
   # FAT filesystem + GPT/MBR partitioning
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf 
b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
index b35f42e11aa4..51a1ef8519f9 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.fdf
@@ -192,6 +192,7 @@ [FV.FvMain]
   INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
   INF OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.inf
   INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  INF SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf
 
   #
   # FAT filesystem + GPT/MBR partitioning + UDF filesystem
-- 
2.45.2



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[edk2-devel] [PATCH edk2-platforms 0/1] RFC: SbsaQemu use FEAT_RNG for EFI_RNG_PROTOCOL

[Marcin Juszkiewicz]

SBSA Reference Platform in QEMU uses Neoverse-N2 cpu by default now.
This core supports FEAT_RNG feature so I thought that it should be
possible to use it for EFI_RNG_PROTOCOL.

Checked history and found that commit
5de5e230a80bed083360da95ba16a2c4a001620d (in EDK2) enabled that for
ArmVirt platform.

When I boot with Neoverse-N2 or 'max' cpu then EFI_RNG_PROTOCOL gets
reported by 'efi-stub' on Linux boot.

Other cpu models do not have FEAT_RNG so RngDxe driver is not running
and we have situation similar to previous one - no EFI_RNG_PROTOCOL
reported.

I left ArmTrngLib enabled because RngDxe does not start without it.
Probably there is a better way to handle it.

Now the question is: do we want to go this way?

And what to do with older cores? BaseRngLibTimerLib is not(?) used now
so are they left with nothing? I would prefer to not add
'virtio-rng-pci' device in QEMU to have some TRNG emulated.

Signed-off-by: Marcin Juszkiewicz 


Marcin Juszkiewicz (1):
  SbsaQemu: use FEAT_RNG for EFI_RNG_PROTOCOL

 Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +-
 Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

-- 
2.45.2



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Re: [edk2-devel] [PATCH edk2-platforms 1/1] SbsaQemu: bump OemRevision to today

[Marcin Juszkiewicz]

W dniu 25.06.2024 o 20:04, Leif Lindholm pisze:

Makes sense.

If you change the new version to 2024 instead of 2023 :)


Oops. Fixed.


Reviewed-by: Leif Lindholm 


Thanks, pushed as feff6a709d5d4d392f4f34529b909e2c4176fa33


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[edk2-devel] [PATCH edk2-platforms 1/1] SbsaQemu: bump OemRevision to today

[Marcin Juszkiewicz]

Lot of time passed since 10th of August 2020 when this platform was
added to EDK2-platforms repository.

So let bump PcdAcpiDefaultOemRevision value to today. So everyone will
see during OS boot that things are changing.

Signed-off-by: Marcin Juszkiewicz 
---
 Silicon/Qemu/SbsaQemu/Acpi.dsc.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc 
b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
index 54e5646e9249..db782afa2cea 100644
--- a/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
+++ b/Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
@@ -16,7 +16,7 @@ [PcdsFeatureFlag]
 [PcdsFixedAtBuild.common]
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"LINARO"
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x554D455141534253 
#SBSAQEMU
-  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20200810
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20230625
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c #LNRO
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1
 
-- 
2.45.2



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Re: [edk2-devel] hardware for development

[Marcin Juszkiewicz]

W dniu 25.06.2024 o 12:41, Marcin Juszkiewicz via groups.io pisze:

W dniu 25.06.2024 o 12:40, Marcin Juszkiewicz via groups.io pisze:
My work on EDK2 is only around SBSA Reference Platform (QemuSbsa) 
which is software emulated machine. And from time to time there are 
moments when I am wondering on getting some physical system which runs 
EDK2 to have system for experiments.


Can someone recommend some hardware?

It does not matter which architecture (from Arm, Risc-v, x86-64). I am 
looking for something what runs quite up-to-date EDK2 (can be fork as 
long as it is maintained and not far behind EDK2).


Needs to be able to run some Linux distribution (Debian, Fedora 
preferred).


And one thing: firmware stored in on-board flash. Not read from microsd 
or other storage media.


I was pointed to https://github.com/edk2-porting/edk2-rk3588 fork. Went 
through a list of supported boards and will go with NanoPC-T6 LTS one.



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Re: [edk2-devel] hardware for development

[Marcin Juszkiewicz]

W dniu 25.06.2024 o 12:40, Marcin Juszkiewicz via groups.io pisze:
My work on EDK2 is only around SBSA Reference Platform (QemuSbsa) which 
is software emulated machine. And from time to time there are moments 
when I am wondering on getting some physical system which runs EDK2 to 
have system for experiments.


Can someone recommend some hardware?

It does not matter which architecture (from Arm, Risc-v, x86-64). I am 
looking for something what runs quite up-to-date EDK2 (can be fork as 
long as it is maintained and not far behind EDK2).


Needs to be able to run some Linux distribution (Debian, Fedora preferred).


And one thing: firmware stored in on-board flash. Not read from microsd 
or other storage media.




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[edk2-devel] hardware for development

[Marcin Juszkiewicz]

My work on EDK2 is only around SBSA Reference Platform (QemuSbsa) which 
is software emulated machine. And from time to time there are moments 
when I am wondering on getting some physical system which runs EDK2 to 
have system for experiments.


Can someone recommend some hardware?

It does not matter which architecture (from Arm, Risc-v, x86-64). I am 
looking for something what runs quite up-to-date EDK2 (can be fork as 
long as it is maintained and not far behind EDK2).


Needs to be able to run some Linux distribution (Debian, Fedora preferred).


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Re: [edk2-devel] Alignment fault in __memcpy when SbsaQemu is built uncompressed

[Marcin Juszkiewicz]

W dniu 22.06.2024 o 20:04, Rebecca Cran pisze:

I decided to do some testing around the cost of copying vs
decompressing and moved all the drivers in SbsaQemu into the
uncompressed section (as described in 
https://github.com/tianocore/tianocore.github.io/wiki/ArmPkg-Compression),

but firmware built with CLANGDWARF causes an alignment fault when
writing the last 64 bytes in __memcpy via FvReadFile ->
AllocateCopyPool -> InternalAllocateCopyPool -> InternalMemCopyMem ->
__memcpy (AArch64/CopyMem.S in BaseMemoryLibOptDxe).


I can confirm that managed to reproduce failure. Sorry, but that's all I 
can say at the moment. No idea what is going on here.



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Re: [edk2-devel] [PATCH edk2-platforms v2 1/1] SbsaQemu: reformat all sources using uncrustify

[Marcin Juszkiewicz]

W dniu 22.06.2024 o 15:18, Leif Lindholm via groups.io pisze:

On Fri, Jun 21, 2024 at 16:04:07 +0200, Marcin Juszkiewicz wrote:

uncrustify is required in EDK2 repository. SbsaQemu (and other platforms
in edk2-platforms) code was free from using it IIRC.

Reformat all files to make new contributions easier. We can recommend
formatting sources without generating extra work for developers.

Signed-off-by: Marcin Juszkiewicz

Reviewed-by: Leif Lindholm


Thanks, pushed as 3425cf8eb5f1bdf5c94599549e3abcb9868df7b8


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[edk2-devel] [PATCH edk2-platforms v2 1/1] SbsaQemu: reformat all sources using uncrustify

[Marcin Juszkiewicz]

uncrustify is required in EDK2 repository. SbsaQemu (and other platforms
in edk2-platforms) code was free from using it IIRC.

Reformat all files to make new contributions easier. We can recommend
formatting sources without generating extra work for developers.

Signed-off-by: Marcin Juszkiewicz 
---
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h |  50 +-
 .../Include/IndustryStandard/SbsaQemuAcpi.h   |  86 +--
 .../SbsaQemuPlatformVersion.h |   2 +-
 .../Include/IndustryStandard/SbsaQemuSmc.h|  14 +-
 .../Include/Library/HardwareInfoLib.h |   8 +-
 .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c |  78 +--
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 490 +-
 .../SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.c   |   8 +-
 .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c |  88 ++--
 .../SbsaQemuSmbiosDxe/SbsaQemuSmbiosDxe.c |  94 ++--
 .../SbsaQemuHardwareInfoLib.c |  66 +--
 .../Library/SbsaQemuLib/SbsaQemuLib.c |  23 +-
 .../Library/SbsaQemuLib/SbsaQemuMem.c |  49 +-
 .../SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c |  14 +-
 .../SbsaQemuPciHostBridgeLib.c|  90 ++--
 15 files changed, 603 insertions(+), 557 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index 83a085cd86f4..e5f0748bb16e 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -11,60 +11,58 @@
 #define SBSAQEMU_ACPI_DXE_H
 
 typedef struct {
-  EFI_ACPI_6_0_IO_REMAPPING_ITS_NODENode;
-  UINT32Identifiers;
+  EFI_ACPI_6_0_IO_REMAPPING_ITS_NODENode;
+  UINT32Identifiers;
 } SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
 
-typedef struct
-{
-  EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode;
-  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE   SmmuIdMap;
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODESmmuNode;
+  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE  SmmuIdMap;
 } SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
 
-typedef struct
-{
-  EFI_ACPI_6_0_IO_REMAPPING_RC_NODERcNode;
-  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE   RcIdMap;
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode;
+  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLERcIdMap;
 } SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
 
 typedef struct {
-  EFI_ACPI_6_0_IO_REMAPPING_TABLE   Iort;
-  SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE   ItsNode;
-  SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode;
-  SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODERcNode;
+  EFI_ACPI_6_0_IO_REMAPPING_TABLE  Iort;
+  SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE  ItsNode;
+  SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODESmmuNode;
+  SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE   RcNode;
 } SBSA_IO_REMAPPING_STRUCTURE;
 
 typedef struct {
-  EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE  mGtdt;
-  EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE mGwdt;
+  EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE mGtdt;
+  EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTUREmGwdt;
 } GENERIC_TIMER_DESCRIPTION_TABLES;
 
 #ifndef SYSTEM_TIMER_BASE_ADDRESS
-  #define SYSTEM_TIMER_BASE_ADDRESS MAX_ADDRESS
+#define SYSTEM_TIMER_BASE_ADDRESS  MAX_ADDRESS
 #endif
 
 #define GTDT_TIMER_LEVEL_TRIGGERED  0
 #define GTDT_TIMER_ACTIVE_LOW   
EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
 #define GTDT_TIMER_ALWAYS_ON
EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
 
-#define GTDT_GTIMER_FLAGS   (GTDT_TIMER_ACTIVE_LOW | \
+#define GTDT_GTIMER_FLAGS  (GTDT_TIMER_ACTIVE_LOW |  \
  GTDT_TIMER_LEVEL_TRIGGERED | \
  GTDT_TIMER_ALWAYS_ON)
 
-#define SBSA_PLATFORM_WATCHDOG_COUNT1
-#define SBSA_PLATFORM_TIMER_COUNT   (SBSA_PLATFORM_WATCHDOG_COUNT)
+#define SBSA_PLATFORM_WATCHDOG_COUNT  1
+#define SBSA_PLATFORM_TIMER_COUNT (SBSA_PLATFORM_WATCHDOG_COUNT)
 
-#define SBSAQEMU_WDT_REFRESH_FRAME_BASE  0x5001
-#define SBSAQEMU_WDT_CONTROL_FRAME_BASE  0x50011000
-#define SBSAQEMU_WDT_IRQ 48
+#define SBSAQEMU_WDT_REFRESH_FRAME_BASE  0x5001
+#define SBSAQEMU_WDT_CONTROL_FRAME_BASE  0x50011000
+#define SBSAQEMU_WDT_IRQ 48
 
 #define GTDT_WDTIMER_LEVEL_TRIGGERED  0
 #define GTDT_WDTIMER_ACTIVE_HIGH  0
 
-#define GTDT_WDTIMER_FLAGS  (GTDT_WDTIMER_ACTIVE_HIGH | 
GTDT_WDTIMER_LEVEL_TRIGGERED)
+#define GTDT_WDTIMER_FLAGS  (GTDT_WDTIMER_ACTIVE_HIGH | 
GTDT_WDTIMER_LEVEL_TRIGGERED)
 
 #define SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT(  
   \
-  ProximityDomain, Base, Length, Flags)
   \
+   
   ProximityDomain, Base, Length, Flags

[edk2-devel] [PATCH edk2-platforms 1/1] SbsaQemu: reformat all sources using uncrustify

[Marcin Juszkiewicz]

uncrustify is required in EDK2 repository. SbsaQemu (and other platforms
in edk2-platforms) code was free from using it IIRC.

Reformat all files to make new contributions easier. We can recommend
formatting sources without generating extra work for developers.

Signed-off-by: Marcin Juszkiewicz 
---
 .../Include/Library/QemuOpenFwCfgLib.h|   7 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h |  50 +-
 .../Include/IndustryStandard/SbsaQemuAcpi.h   |  86 +--
 .../SbsaQemuPlatformVersion.h |   2 +-
 .../Include/IndustryStandard/SbsaQemuSmc.h|  14 +-
 .../Include/Library/HardwareInfoLib.h |   8 +-
 .../BoardBootManagerLib/BoardBootManager.c|  14 +-
 .../Library/PeiReportFvLib/PeiReportFvLib.c   | 237 -
 .../QemuOpenBoardPkg/PlatformInitPei/Memory.c |   4 +-
 .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c |  78 +--
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 490 +-
 .../SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.c   |   8 +-
 .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c |  88 ++--
 .../SbsaQemuSmbiosDxe/SbsaQemuSmbiosDxe.c |  94 ++--
 .../SbsaQemuHardwareInfoLib.c |  66 +--
 .../Library/SbsaQemuLib/SbsaQemuLib.c |  23 +-
 .../Library/SbsaQemuLib/SbsaQemuMem.c |  49 +-
 .../SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c |  14 +-
 .../SbsaQemuPciHostBridgeLib.c|  90 ++--
 19 files changed, 735 insertions(+), 687 deletions(-)

diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Library/QemuOpenFwCfgLib.h 
b/Platform/Qemu/QemuOpenBoardPkg/Include/Library/QemuOpenFwCfgLib.h
index 8e5f8ccf70e2..828b272ca5ed 100644
--- a/Platform/Qemu/QemuOpenBoardPkg/Include/Library/QemuOpenFwCfgLib.h
+++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Library/QemuOpenFwCfgLib.h
@@ -10,7 +10,6 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
-
 #ifndef QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_
 #define QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_
 
@@ -27,7 +26,7 @@
 #define FW_CFG_ID 0x0001
 #define FW_CFG_FILE_DIR   0x0019
 
-#define FW_CFG_QEMU_SIGNATURE SIGNATURE_32('Q', 'E', 'M', 'U')
+#define FW_CFG_QEMU_SIGNATURE  SIGNATURE_32('Q', 'E', 'M', 'U')
 
 typedef struct {
   UINT32Size;
@@ -98,8 +97,8 @@ QemuFwCfgReadBytes (
 EFI_STATUS
 EFIAPI
 QemuFwCfgFindFile (
-  IN  CHAR8  *String,
-  OUT QEMU_FW_CFG_FILE   *FWConfigFile
+  IN  CHAR8 *String,
+  OUT QEMU_FW_CFG_FILE  *FWConfigFile
   );
 
 #endif // QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index 83a085cd86f4..e5f0748bb16e 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -11,60 +11,58 @@
 #define SBSAQEMU_ACPI_DXE_H
 
 typedef struct {
-  EFI_ACPI_6_0_IO_REMAPPING_ITS_NODENode;
-  UINT32Identifiers;
+  EFI_ACPI_6_0_IO_REMAPPING_ITS_NODENode;
+  UINT32Identifiers;
 } SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
 
-typedef struct
-{
-  EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode;
-  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE   SmmuIdMap;
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODESmmuNode;
+  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE  SmmuIdMap;
 } SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
 
-typedef struct
-{
-  EFI_ACPI_6_0_IO_REMAPPING_RC_NODERcNode;
-  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE   RcIdMap;
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode;
+  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLERcIdMap;
 } SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
 
 typedef struct {
-  EFI_ACPI_6_0_IO_REMAPPING_TABLE   Iort;
-  SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE   ItsNode;
-  SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode;
-  SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODERcNode;
+  EFI_ACPI_6_0_IO_REMAPPING_TABLE  Iort;
+  SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE  ItsNode;
+  SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODESmmuNode;
+  SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE   RcNode;
 } SBSA_IO_REMAPPING_STRUCTURE;
 
 typedef struct {
-  EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE  mGtdt;
-  EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE mGwdt;
+  EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE mGtdt;
+  EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTUREmGwdt;
 } GENERIC_TIMER_DESCRIPTION_TABLES;
 
 #ifndef SYSTEM_TIMER_BASE_ADDRESS
-  #define SYSTEM_TIMER_BASE_ADDRESS MAX_ADDRESS
+#define SYSTEM_TIMER_BASE_ADDRESS  MAX_ADDRESS
 #endif
 
 #define GTDT_TIMER_LEVEL_TRIGGERED  0
 #define GTDT_TIMER_ACTIVE_LOW   
EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
 #define GTDT_TIMER_ALWAYS_ON
EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
 
-#define G

Re: [edk2-devel] [PATCH 1/2] Platform/SbsaQemu: get the information of CPU topology via SMC calls

[Marcin Juszkiewicz]

W dniu 17.04.2024 o 13:26, Xiong Yining pisze:

Provide functions to check for CPU topology information:
- the number of sockets on sbsa-ref platform.
- the number of clusters in one socket.
- the number of cores in one cluster.
- the number of threads in one cores.

As SMC calls can return up to 4 return values. the number of
sockets, clusters and cores are read from TF-A using platform
specific SMC calls. And the number of threads is caluculated
using the total number of cpus and the number of sockets,
clusters and cores.

Signed-off-by: Xiong Yining 
---
  .../Include/IndustryStandard/SbsaQemuSmc.h|  1 +
  .../Include/Library/HardwareInfoLib.h | 26 +++
  .../SbsaQemuHardwareInfoLib.c | 33 +++
  3 files changed, 60 insertions(+)

diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
index e3092007d27d..9d9780ca70fe 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
@@ -16,6 +16,7 @@
  #define SIP_SVC_GET_GIC_ITSSMC_SIP_FUNCTION_ID(101)
  #define SIP_SVC_GET_CPU_COUNT  SMC_SIP_FUNCTION_ID(200)
  #define SIP_SVC_GET_CPU_NODE   SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY SMC_SIP_FUNCTION_ID(202)
  #define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300)
  #define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301)
  
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h

index 46fdad45353c..3e451ee344c7 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
@@ -15,6 +15,19 @@ typedef struct{
UINT64  AddressSize;
  } MemoryInfo;
  
+/**

+  Sockets: the number of sockets on sbsa-ref platform.
+  Clusters: the number of clusters in one socket.
+  Cores: the number of cores in one cluster.
+  Threads: the number of threads in one core.
+**/
+typedef struct{
+  UINT32 Sockets;
+  UINT32 Clusters;
+  UINT32 Cores;
+  UINT32 Threads;
+} CpuTopology;
+
  /**
Get CPU count from information passed by Qemu.
  
@@ -83,4 +96,17 @@ GetNumaNodeCount (

VOID
);
  
+/**

+  Get cpu topology(sockets, clusters, cores, threads) from device tree passed 
by Qemu.
+
+  @param [out]  CpuTopo A pointer to the cpu topology.
+
+
+  @retval   the information of cpu topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology *CpuTopo
+  );
+
  #endif /* HARDWARE_INFO_LIB */
diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 4c22e7d6ee47..a12dc0244da5 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -179,3 +179,36 @@ GetNumaNodeCount (
  
return NumberNumaNodes;

  }
+
+/**
+  Get CPU topology.
+**/
+VOID
+GetCpuTopology (
+  OUT CpuTopology *CpuTopo
+  )
+{
+  UINTN  SmcResult;
+  UINTN  Arg0;
+  UINTN  Arg1;
+  UINTN  Arg2;
+  UINT32 NumCores = GetCpuCount();
+
+  SmcResult = ArmCallSmc0(SIP_SVC_GET_CPU_TOPOLOGY, &Arg0, &Arg1, &Arg2);


Can you use ArmCallSmc() directly? TF-A returns 5 arguments for this SMC 
call, we use 4 and calculate 5th one. Once we improve SMCCC code in EDK2 
the 5th one would be used directly.



+  if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no cpu 
topology information.\n", __FUNCTION__));
+ResetShutdown ();
+  } else {
+CpuTopo->Sockets = Arg0;
+CpuTopo->Clusters = Arg1;
+CpuTopo->Cores = Arg2;



+CpuTopo->Threads = NumCores / (CpuTopo->Sockets * CpuTopo->Clusters * 
CpuTopo->Cores);


Once SMCCC gets improved this would be read directly from TF-A.


+  }
+
+  DEBUG(( DEBUG_INFO, "%a: CPU Topology: sockets are %d, clusters are %d, cores are 
%d, threads are %d\n",


Can you replace " are" with ":" ("sockets: %d, clusters: %d")? Those 
numbers can be singular.



+  __FUNCTION__,
+  CpuTopo->Sockets,
+  CpuTopo->Clusters,
+  CpuTopo->Cores,
+  CpuTopo->Threads ));
+}
\ No newline at end of file




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Re: [edk2-devel] [PATCH 2/2] Silicon/SbsaQemu: align the PPTT tables with qemu configuration

[Marcin Juszkiewicz]

W dniu 17.04.2024 o 13:26, Xiong Yining pisze:

To align the CPU topology information recognized by the operating system with 
the CPU topology
information configured by QEMU, we need to make use of the CPU topology 
information to create
complex PPTT tables setups.

We can get the CPU topology information via SMC.

Signed-off-by: Xiong Yining 


Thanks for submittion. Some issues to handle. Also: please call
uncrucify on your code.


---
  .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h |  12 ++
  .../Include/IndustryStandard/SbsaQemuAcpi.h   |  32 
  .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 140 +-
  3 files changed, 114 insertions(+), 70 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index 83a085cd86f4..e29635b28938 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -90,4 +90,16 @@ typedef struct {
  ClockDomain /* Clock Domain */
\
}
  
+#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(  \

+  Flags, Parent, ACPIProcessorID, NumberOfPrivateResources)
 \
+  {
 \
+EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
  /* Type */ \
+sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources 
* sizeof (UINT32), /* Length */   \


First suggestion: please use latest ACPI version (6.5 at the moment).
There are 2-3 entries more inside of struct. One of them is CacheId
which can be anything as long as it is unique and > 0 (just do
incremental).


+{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
  /* Reserved */ \
+Flags, 
  /* Flags */\
+Parent,
  /* Parent */   \
+ACPIProcessorID,   
  /* ACPI Processor ID */\
+NumberOfPrivateResources   
  /* Number of private resources */  \
+  }
+
  #endif
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h 
b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 61d8bce8c959..7ef85b7e2f79 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -166,36 +166,4 @@ typedef struct {
  64/* LineSize */  
 \
}
  
-#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT  {   \

-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR),
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */   
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a Thread */
\
-  EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */   
\
-  EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */
\
-}, 
\
-0,/* Parent */ 
\
-0,/* AcpiProcessorId */
\
-0,/* NumberOfPrivateResources */   
\
-  }
-
-#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT  {  
\
-EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR,  
\
-(sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))),  
\
-{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE },
\
-{  
\
-  EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,   /* AcpiProcessorValid */ 
\
-  EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,  /* Is not a 

Re: [edk2-devel] [PATCH edk2-platforms 1/5] Platform/SbsaQemu: fix .dsc line endings

[Marcin Juszkiewicz]

W dniu 20.06.2024 o 16:32, Leif Lindholm pisze:

A patch adding a mapping for ImagePropertiesRecordLib introduced a bunch of
LF line endings in otherwise CRLF files, so clean that up.

Cc: Ard Biesheuvel
Cc: Chuong Tran
Cc: Graeme Gregory
Cc: Marcin Juszkiewicz
Cc: Marcin Wojtas
Cc: Meenakshi Aggarwal
Cc: Narinder Dhillon
Cc: Nhi Pham
Cc: Rebecca Cran
Cc: Sami Mujawar
Cc: Thomas Abraham
Signed-off-by: Leif Lindholm


I hate line endings in EDK2. Having them sorted out is good.

Reviewed-by: Marcin Juszkiewicz 



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Re: [edk2-devel] [PATCH edk2-platforms 1/1] QemuSbsa: enable WriteCombine for the FrameBuffer

[Marcin Juszkiewicz]

W dniu 19.06.2024 o 09:09, Ard Biesheuvel pisze:

On Wed, 19 Jun 2024 at 07:52, Marcin Juszkiewicz
  wrote:

QEMU no longer permits misaligned access to device memory, which breaks
QemuVideoDxe on SbsaQemu.

c1d1910be6e04a8b1a73090cf2881fb698947a6e commit in EDK2 fixed it by
enabling WriteCombine for Framebuffer memory. This change enables that
fix.

Signed-off-by: Marcin Juszkiewicz

Reviewed-by: Ard Biesheuvel


Thanks. Pushed as 3f08401365d67e10924c774e6c3f64be56bc15b6.


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[edk2-devel] [PATCH edk2-platforms 1/1] QemuSbsa: enable WriteCombine for the FrameBuffer

[Marcin Juszkiewicz]

QEMU no longer permits misaligned access to device memory, which breaks
QemuVideoDxe on SbsaQemu.

c1d1910be6e04a8b1a73090cf2881fb698947a6e commit in EDK2 fixed it by
enabling WriteCombine for Framebuffer memory. This change enables that
fix.

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc 
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index b012eaa34147..11126bcaa1fe 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -311,6 +311,9 @@ [PcdsFeatureFlag.common]
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
 
+  # Enable WriteCombine for FrameBuffer
+  gUefiOvmfPkgTokenSpaceGuid.PcdRemapFrameBufferWriteCombine|TRUE
+
 [PcdsFixedAtBuild.common]
   gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100
-- 
2.45.1



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Re: [edk2-devel] ArmCallSmc() and SMCCC specification

[Marcin Juszkiewicz]

W dniu 3.06.2024 o 18:47, Leif Lindholm via groups.io pisze:

In 2020 we got version C of spec (and then D, E, F) which allows to 
use more registers:


 > Allow R4—R7 (SMC32/HVC32) to be used as result registers.
 > Allow X8—X17 to be used as parameter registers in SMC64/HVC64.
 > Allow X4—X17 to be used as result registers in SMC64/HVC64.

And I started to wonder how to update EDK2 to newer version of SMCCC 
spec as one of in-progress QemuSbsa SMC calls may return more than 4 
values.


Yes, definitely. This has been a wishlist item for some time, but in 
reality we've only ever updated these when we needed new functionality.




ARM_SMC_ARGS in ArmSmcLib.h can be expanded to handle up to Arg17 in 
an easy way and guarded by "#if defined(__aarch64__)" to not change it 
on Arm32.


My example code for it (including comment update):

diff --git a/ArmPkg/Include/Library/ArmSmcLib.h 
b/ArmPkg/Include/Library/ArmSmcLib.h
index beef0175c35c..af27781b72f6 100644
--- a/ArmPkg/Include/Library/ArmSmcLib.h
+++ b/ArmPkg/Include/Library/ArmSmcLib.h
@@ -23,14 +23,31 @@ typedef struct {
   UINTNArg5;
   UINTNArg6;
   UINTNArg7;
+#if defined(__aarch64__)
+  UINTNArg8;
+  UINTNArg9;
+  UINTNArg10;
+  UINTNArg11;
+  UINTNArg12;
+  UINTNArg13;
+  UINTNArg14;
+  UINTNArg15;
+  UINTNArg16;
+  UINTNArg17;
+#endif
 } ARM_SMC_ARGS;

 /**
   Trigger an SMC call

-  SMC calls can take up to 7 arguments and return up to 4 return values.
-  Therefore, the 4 first fields in the ARM_SMC_ARGS structure are used
-  for both input and output values.
+  on SMC32/HVC32
+  - R0 is a function identifier, R1-R7 are arguments
+  - R0-R7 are results, R4-R7 must be preserved unless they contain results
+
+
+  on SMC64/HVC64
+  - W0 is a function identifier, X1-X17 are arguments
+  - X0-X17 are results, X4-X17 must be preserved unless they contain results

 **/
 VOID


Then ArmCallSmc() in {AArch64,Arm}/ArmSmc.S needs changes. But here it 
gets tricky.


On Arm we preserve r4-r8 and restore them after call like spec says. 
Which we do not do on AArch64 as version B of spec did not required 
that (and this changed in version C).


If we start handling more than 4 results then we need to know how many 
results are expected and restore rest of r4-r7/x4-x17 registers:


Yeah, it feels like we may want to add a version field or/and number of 
registers to save/restore to a new struct. And we should definitely 
align Arm/AArch64 behaviour.





 From what I saw in both edk2/ and edk2-platforms/ most of code uses 
ArmCallSmc() function with ARM_SMC_ARGS structure populared with 
arguments. ArmCallSmc[0-3]() are used by Smbios, Psci and QemuSbsa 
code only.


The ArmCallSmc[0-3] helpers were only added as shorthand for most common 
cases. I don't think we should worry about how those work for making any 
design decisions. Everything they do can be described by the main 
ArmCallSmc functions and a few lines of struct stuffing.



Now the question is: how to handle change?


It could be that it would be easiest to add a new call function, and 
maybe even ra new egister struct, than trying to adapt the existing ones 
in ways that doesn't break existing users?


That is if we care about existing users. We could always modify it to 
guarantee breakage and expect users to update their code. Since this is 
a library, and not a protocol, we *mostly* don't need to worry about 
users mixing prebuilt binaries using old structs with new functions.


We could add ArmCallSmc[4-17] but that name only tells how many 
arguments we pass to SMC call, not how many results we expect. Or 
should we add NumberOfResults argument to ArmCallSmc() to know which 
registers we should preserve and which are results? And how 
complicated this assembly function will become?


I don't think the assembly function needs to be that complicated. It'd 
be a bit tedious with a bunch of tests, but...


Note: I do not know aarch64 assembly. Did some changes to ArmCallSmc().
I moved to use x18 register (preserved on stack) instead of x9 one. And
changed code to handle 8 results (without preserving x4-x7).

diff --git a/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S 
b/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S
index 4a8c2a8f59ea..0525a0a7887f 100644
--- a/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S
+++ b/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S
@@ -8,8 +8,10 @@
 #include 

 ASM_FUNC(ArmCallSmc)
+  // preserve x18
+  str   x18, [sp, #-16]!
   // Push x0 on the stack - The stack must always be quad-word aligned
-  str   x0, [sp, #-16]!
+  str   x0, [sp, #-32]!

   // Load the SMC arguments values into the appropriate registers
   ldp   x6, x7, [x0, #48]
@@ -19,14 +21,18 @@ ASM_FUNC(ArmCallSmc)

   smc   #0

-  // Pop the ARM_SMC_ARGS structure address from the stack into x9
-  ldr   x9, [sp], #16
+  // Pop the ARM_SMC_ARGS structure address from the stack into x18
+  ldr   x18, [sp], #32

   // Store the SMC returned values into the ARM_SMC_ARGS struc

Re: [edk2-devel] [PATCH edk2-platforms v2 0/3] SbsaQemu: support multiple PCI Express buses

[Marcin Juszkiewicz]

W dniu 28.05.2024 o 16:31, Ard Biesheuvel pisze:

I would expect each host bridge to have its own separate resource
windows for config space, buses and MMIO regions.

So each host bridge gets a different segment number, and each segment
is associated with a different ECAM region. That also means the bus
range can start at 0x0 for each segment, as they are completely
disjoint.

This is a more accurate representation of the physical topology, given
that each host bridge has its own link to the CPU side interconnect,
and so things like peer-to-peer DMA between endpoints does not
generally work unless the endpoints share a segment, especially in the
presence of SMMUs.


OK. I have to admit that I never checked how physical NUMA system 
handles PCI Express. The code in patches was done by comparing with 
other QEMU targets.


To make PCIe in a way you describe we probably need to go to QEMU devel 
ML and discuss how it can be done there. Or I did not got deep enough 
into PCIe world to notice how to make it happen with current implementation.



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[edk2-devel] ArmCallSmc() and SMCCC specification

[Marcin Juszkiewicz]

EDK2/ArmPkg/Library/ArmSmcLib has code to do SMC calls.

There are ArmCallSmc[0-3]() functions for up to 3 arguments/results and 
ArmCallSmc() function which can use 7 arguments and get 4 results back.


This implementation looks like version B (Nov 2016) of SMCCC 
specification [1] with one more register used.


1. https://developer.arm.com/documentation/den0028/b/


In 2020 we got version C of spec (and then D, E, F) which allows to use 
more registers:


> Allow R4—R7 (SMC32/HVC32) to be used as result registers.
> Allow X8—X17 to be used as parameter registers in SMC64/HVC64.
> Allow X4—X17 to be used as result registers in SMC64/HVC64.

And I started to wonder how to update EDK2 to newer version of SMCCC 
spec as one of in-progress QemuSbsa SMC calls may return more than 4 values.



ARM_SMC_ARGS in ArmSmcLib.h can be expanded to handle up to Arg17 in an 
easy way and guarded by "#if defined(__aarch64__)" to not change it on 
Arm32.



Then ArmCallSmc() in {AArch64,Arm}/ArmSmc.S needs changes. But here it 
gets tricky.


On Arm we preserve r4-r8 and restore them after call like spec says. 
Which we do not do on AArch64 as version B of spec did not required that 
(and this changed in version C).


If we start handling more than 4 results then we need to know how many 
results are expected and restore rest of r4-r7/x4-x17 registers:


> When an SMC32/HVC32 call is made from AArch32:
> • A Function Identifier is passed in register R0.
> • Arguments are passed in registers R1-R7.
> • Results are returned in R0-R7.
> • The registers R4-R7 must be preserved unless they contain results,
>   as specified in the function definition.
> • Registers R8-R14 are saved by the function that is called, and must
>   be preserved over the SMC or HVC call.
>
> When an SMC64/HVC64 call is made from AArch64:
> • A Function Identifier is passed in register W0.
> • Arguments are passed in registers X1-X17.
> • Results are returned in X0-X17.
> • Registers X4-X17 must be preserved unless they contain results, as
>   specified in the function definition.
> • Registers X18-X30 and stack pointers SP_EL0 and SP_ELx are saved by 
>   the function that is called, and must be preserved over the SMC or

>   HVC call.


From what I saw in both edk2/ and edk2-platforms/ most of code uses 
ArmCallSmc() function with ARM_SMC_ARGS structure populared with 
arguments. ArmCallSmc[0-3]() are used by Smbios, Psci and QemuSbsa code 
only.



Now the question is: how to handle change?

We could add ArmCallSmc[4-17] but that name only tells how many 
arguments we pass to SMC call, not how many results we expect. Or should 
we add NumberOfResults argument to ArmCallSmc() to know which registers 
we should preserve and which are results? And how complicated this 
assembly function will become?



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Re: [edk2-devel] [PATCH edk2-non-osi v2 1/1] Qemu/Sbsa: update to TF-A 2.11.0

[Marcin Juszkiewicz]

W dniu 29.05.2024 o 15:30, Leif Lindholm via groups.io pisze:

On 2024-05-29 14:29, Marcin Juszkiewicz wrote:

Update TF-A binaries to the same version as QEMU CI uses.

Signed-off-by: Marcin Juszkiewicz 


Reviewed-by: Leif Lindholm 


Thanks, pushed as 5fdbccd742d4206a2370a08c5420a1aa8c6ad85b


---
  Platform/Qemu/Sbsa/Readme.md |  49 ---
  Platform/Qemu/Sbsa/bl1.bin   | Bin 23349 -> 2 bytes
  Platform/Qemu/Sbsa/fip.bin   | Bin 82722 -> 82722 bytes
  3 files changed, 5 insertions(+), 44 deletions(-)
  mode change 100755 => 100644 Platform/Qemu/Sbsa/bl1.bin




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[edk2-devel] [PATCH edk2-non-osi v2 1/1] Qemu/Sbsa: update to TF-A 2.11.0

[Marcin Juszkiewicz]

Update TF-A binaries to the same version as QEMU CI uses.

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/Sbsa/Readme.md |  49 ---
 Platform/Qemu/Sbsa/bl1.bin   | Bin 23349 -> 2 bytes
 Platform/Qemu/Sbsa/fip.bin   | Bin 82722 -> 82722 bytes
 3 files changed, 5 insertions(+), 44 deletions(-)
 mode change 100755 => 100644 Platform/Qemu/Sbsa/bl1.bin

diff --git a/Platform/Qemu/Sbsa/Readme.md b/Platform/Qemu/Sbsa/Readme.md
index b1351043d2b4..ceef51b6a500 100644
--- a/Platform/Qemu/Sbsa/Readme.md
+++ b/Platform/Qemu/Sbsa/Readme.md
@@ -4,51 +4,12 @@ Qemu SBSA TF-A binaries
 These binaries have been created from the mainline TF-A
 code checked out at the following commit ID:
 
-commit 56b263cb2a25892038761acea8c2b57a638d19bf (HEAD -> integration, 
origin/integration, gerrit/integration)
-Merge: 09d3fd141 e769f830d
-Author: Yann Gautier 
-Date:   Tue Apr 23 10:42:01 2024 +0200
+commit f2735ebccf5173f74c0458736ec526276106097e (tag: v2.11.0, tag: v2.11)
+Merge: 6370f2cbb 669e2b159
+Author: Manish Pandey 
+Date:   Thu May 23 13:51:22 2024 +0200
 
-Merge "feat(qemu): allow ARM_ARCH_MAJOR/MINOR override" into integration
-
-
-This ensures that the following features for qemu_sbsa platform are
-merged upstream and included in the build:
-
-commit 5436047a0e1f32543042d6de9f1f6a3edcd47591
-Author: Marcin Juszkiewicz 
-Date:   Mon Apr 22 17:27:56 2024 +0200
-
-refactor(qemu): do not hardcode counter frequency
-
-From QEMU change:
-
-> In previous versions of the Arm architecture, the frequency of the
-> generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
-> and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
-> In Armv8.6, the architecture standardized this frequency to 1GHz.
-
-This change stops TF-A from hardcoding 62.5MHz frequency. Instead value
-stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older
-cores and 1GHz on newer ones.
-
-Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4
-    Signed-off-by: Marcin Juszkiewicz 
-
-commit 1b694c77c497cb8272c97417ef1fa4f5f9c869c1
-Author: Jean-Philippe Brucker 
-Date:   Mon Apr 15 14:28:11 2024 +0100
-
-feat(qemu): enable FEAT_ECV when present
-
-QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
-FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
-auto-detecting the feature on the QEMU platforms, in order to set
-SCR.ECVEN. Without this, EL2 gets undefined instruction exceptions when
-trying to access the new CNTPOFF register.
-
-Change-Id: I555a5f9a9a84fd23e64ca85219ed1599204c6bb2
-Signed-off-by: Jean-Philippe Brucker 
+Merge "docs(changelog): changelog for v2.11 release" into integration
 
 
 NOTE: No modifications to the source code have been done.
diff --git a/Platform/Qemu/Sbsa/bl1.bin b/Platform/Qemu/Sbsa/bl1.bin
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[edk2-devel] [PATCH edk2-non-osi 1/1] Qemu/Sbsa: update to TF-A 2.11.0

[Marcin Juszkiewicz]

Update TF-A binaries to the same version as QEMU CI uses.

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/Sbsa/bl1.bin | Bin 23349 -> 2 bytes
 Platform/Qemu/Sbsa/fip.bin | Bin 82722 -> 82722 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)
 mode change 100755 => 100644 Platform/Qemu/Sbsa/bl1.bin

diff --git a/Platform/Qemu/Sbsa/bl1.bin b/Platform/Qemu/Sbsa/bl1.bin
old mode 100755
new mode 100644
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zQ)#e

[edk2-devel] [PATCH edk2-platforms v2 0/3] SbsaQemu: support multiple PCI Express buses

[Marcin Juszkiewicz]

QEMU allows to have NUMA setup where each node has own cpus, memory and
i/o. We already handle cpus and memory. This patchset adds support for
having multiple PCI Express buses.

SbsaQemu assumed that there is only bus 0. First patch does PCIe bus
scan to find all host bridges (bus 0 one and additional 'pxb-pcie'
ones).

Second patch moves description of PCIe from DSDT to SSDT (one per each
PCIe bus). So Operating System will know about all of them.

Third patch moves generation of MCFG table to C. It is preparation to
move PCIe Pcds from being fixed to dynamic ones.

There are some booting issues with assigning resources for cards:

pci :00:03.0: BAR 15: no space for [mem size 0x0020 64bit pref]
pci :00:03.0: BAR 15: failed to assign [mem size 0x0020 64bit pref]
pci :00:01.0: BAR 6: no space for [mem size 0x0004 pref]
pci :00:01.0: BAR 6: failed to assign [mem size 0x0004 pref]
pci :00:03.0: BAR 13: no space for [io  size 0x1000]
pci :00:03.0: BAR 13: failed to assign [io  size 0x1000]

Boot log (Linux + lspci + ACPI tables dump):
https://people.linaro.org/~marcin.juszkiewicz/sbsa-ref/boot-linux-with-numa-multiple-pcie-buses.txt

I am wondering where I made mistakes in handling PCIe buses.

Thanks go to Leif for pointing me to use of Aml to generate SSDT tables.

Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Graeme Gregory 
Cc: Ray Ni 
To: devel@edk2.groups.io

Signed-off-by: Marcin Juszkiewicz 
---
Changes in v2:
- Dropped [WIP] status
- Link to v1: 
https://openfw.io/edk2-devel/20240425-review-multiple-pcie-0425-v1-0-68fdfd781...@linaro.org/

---
Marcin Juszkiewicz (3):
  SbsaQemu: scan for PCIe buses
  SbsaQemu: describe PCIe buses in SSDT tables
  SbsaQemu: generate MCFG table

 Platform/Qemu/SbsaQemu/SbsaQemu.dsc |   2 +
 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf |   1 -
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf |  37 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h  |  23 +
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 170 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.c  | 576 
 .../SbsaQemuPciHostBridgeLib.c  | 185 ---
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl   | 302 --
 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc  |  43 --
 .../Drivers/SbsaQemuAcpiDxe/SsdtTemplate.asl|  82 +++
 10 files changed, 982 insertions(+), 439 deletions(-)
---
base-commit: 4bbd0ed440322e49edffdebe15e12aa76916d1b0
change-id: 20240425-review-multiple-pcie-0425-54ce3817fd3f

Best regards,
-- 
Marcin Juszkiewicz 



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[edk2-devel] [PATCH edk2-platforms v2 3/3] SbsaQemu: generate MCFG table

[Marcin Juszkiewicz]

We want to have dynaminc PCI Express variables. Which forces us to
generate MCFG from C code.

Signed-off-by: Marcin Juszkiewicz 
---
 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf  |  1 -
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 83 
 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc   | 43 --
 3 files changed, 83 insertions(+), 44 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf 
b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 8d4905362edc..37abf2f4c512 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -19,7 +19,6 @@ [Sources]
   Dbg2.aslc
   Dsdt.asl
   Fadt.aslc
-  Mcfg.aslc
   Spcr.aslc
 
 [Packages]
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index f3d5dc9e9ba7..6c7913eead81 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -7,6 +7,7 @@
 *
 **/
 #include 
+#include 
 #include 
 #include 
 
@@ -883,6 +884,83 @@ AddSsdtPcieTable (
   return EFI_SUCCESS;
 }
 
+/** Adds the MCFG ACPI table.
+
+  @param AcpiTableThe ACPI Table.
+  @param PcieCfgData  PCIe configuration data.
+  @param NumPcieSegments  Number of PCIe segments.
+
+  @return EFI_SUCCESS on success, or an error code.
+
+**/
+STATIC
+EFI_STATUS
+AddMcfgTable (
+  IN EFI_ACPI_TABLE_PROTOCOL  *AcpiTable
+  )
+{
+  EFI_STATUSStatus;
+  UINTN TableHandle;
+  UINT32TableSize;
+  EFI_PHYSICAL_ADDRESS  PageAddress;
+  UINT8 *New;
+
+  EFI_ACPI_DESCRIPTION_HEADER  Header =
+SBSAQEMU_ACPI_HEADER (
+  
EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+  EFI_ACPI_DESCRIPTION_HEADER,
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION
+  );
+
+  TableSize = sizeof 
(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) +
+  sizeof 
(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
+
+  Status = gBS->AllocatePages (
+  AllocateAnyPages,
+  EfiACPIReclaimMemory,
+  EFI_SIZE_TO_PAGES (TableSize),
+  &PageAddress
+  );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MCFG table\n"));
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  New = (UINT8 *)(UINTN)PageAddress;
+  ZeroMem (New, TableSize);
+
+  // Add the  ACPI Description table header
+  CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
+  ((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
+  New += sizeof 
(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER);
+
+  
EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE
  *CfgPtr;
+
+  CfgPtr = (VOID *)New;
+
+  CfgPtr->BaseAddress   = PcdGet64 (PcdPciExpressBaseAddress);
+  CfgPtr->PciSegmentGroupNumber = 0;
+  CfgPtr->StartBusNumber= PcdGet32 (PcdPciBusMin);
+  CfgPtr->EndBusNumber  = PcdGet32 (PcdPciBusMax);
+
+  New += sizeof 
(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
+
+  // Perform Checksum
+  AcpiTableChecksum ((UINT8 *)PageAddress, TableSize);
+
+  Status = AcpiTable->InstallAcpiTable (
+AcpiTable,
+(EFI_ACPI_COMMON_HEADER *)PageAddress,
+TableSize,
+&TableHandle
+);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to install MCFG table\n"));
+  }
+
+  return Status;
+}
+
 
 EFI_STATUS
 EFIAPI
@@ -951,6 +1029,11 @@ InitializeSbsaQemuAcpiDxe (
 DEBUG ((DEBUG_ERROR, "Failed to add SSDT table\n"));
   }
 
+  Status = AddMcfgTable (AcpiTable);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to add MCFG table\n"));
+  }
+
 
   return EFI_SUCCESS;
 }
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc 
b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
deleted file mode 100644
index 289f4ad4ea3a..
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
+++ /dev/null
@@ -1,43 +0,0 @@
-/** @file
-*  ACPI Memory mapped configuration space base address Description Table 
(MCFG).
-*
-*  Copyright (c) 2020, Linaro Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include 
-#include 
-#include 
-
-#pragma pack(push, 1)
-
-typedef struct {
-  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
-  
EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE
 Structure[1

[edk2-devel] [PATCH edk2-platforms v2 2/3] SbsaQemu: describe PCIe buses in SSDT tables

[Marcin Juszkiewicz]

We can have more than one PCI Express bus. So instead of having static
description in DSDT we create SSDT table for each existing PCIe bus.

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc |   2 +
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf |  37 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h  |  23 +
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   |  87 ++-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.c  | 576 
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl   | 302 --
 .../Drivers/SbsaQemuAcpiDxe/SsdtTemplate.asl|  82 +++
 7 files changed, 790 insertions(+), 319 deletions(-)

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc 
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index e246db8b0a23..b012eaa34147 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -173,6 +173,8 @@ [LibraryClasses.common]
   
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
 
   AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  AcpiHelperLib|DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf
+  AmlLib|DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf
 
   ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
   ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index 727c8e82d16e..6de1073e6ac2 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -18,18 +18,25 @@ [Defines]
 
 [Sources]
   SbsaQemuAcpiDxe.c
+  SbsaQemuAcpiDxe.h
+  SbsaQemuAcpiPcie.c
+  SbsaQemuAcpiPcie.h
+  SsdtTemplate.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
   ArmVirtPkg/ArmVirtPkg.dec
+  DynamicTablesPkg/DynamicTablesPkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/Qemu/SbsaQemu/SbsaQemu.dec
 
 [LibraryClasses]
+  AcpiHelperLib
   AcpiLib
+  AmlLib
   ArmLib
   BaseMemoryLib
   BaseLib
@@ -37,6 +44,7 @@ [LibraryClasses]
   DxeServicesLib
   HardwareInfoLib
   PcdLib
+  PciLib
   PrintLib
   UefiDriverEntryPoint
   UefiLib
@@ -54,14 +62,39 @@ [Pcd]
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSmmuBase
 
 [Depex]
-  gEfiAcpiTableProtocolGuid   ## CONSUMES
+  # We want all PCIe buses to be scanned first
+  gEfiPciIoProtocolGuid ## CONSUMES
 
 [Guids]
   gEdkiiPlatformHasAcpiGuid
 
 [Protocols]
   gEfiAcpiSdtProtocolGuid
-  gEfiAcpiTableProtocolGuid   ## CONSUMES
+  gEfiAcpiTableProtocolGuid
+  gEfiPciRootBridgeIoProtocolGuid
+
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdPciBusMin
+  gArmTokenSpaceGuid.PcdPciBusMax
+  gArmTokenSpaceGuid.PcdPciIoBase
+  gArmTokenSpaceGuid.PcdPciIoSize
+  gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit
+
+  gArmTokenSpaceGuid.PcdPciMmio32Base
+  gArmTokenSpaceGuid.PcdPciMmio32Size
+  gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit
+
+  gArmTokenSpaceGuid.PcdPciMmio64Base
+  gArmTokenSpaceGuid.PcdPciMmio64Size
+  gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit
+
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit
 
 [FixedPcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h
new file mode 100644
index ..56cc6f1381da
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h
@@ -0,0 +1,23 @@
+/** @file
+*  This file is an ACPI driver for the Qemu SBSA platform.
+*
+*  Copyright (c) 2024, Linaro Ltd. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef SBSAQEMU_ACPI_PCIE_H
+#define SBSAQEMU_ACPI_PCIE_H
+
+#pragma pack(1)
+
+/* AML bytecode generated from SsdtTemplate.asl */
+extern CHAR8  ssdttemplate_aml_code[];
+
+EFI_STATUS
+AddPcieHostBridges (
+  AML_OBJECT_NODE_HANDLE  ScopeNode
+  );
+
+#endif
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 30239e7dca0d..f3d5dc9e9ba7 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -6,28 +6,27 @@
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
 **/
-#include 
-#include 
 #include 
 #include 
 #include 
+
 #include 
+#include 
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
 #include

[edk2-devel] [PATCH edk2-platforms v2 1/3] SbsaQemu: scan for PCIe buses

[Marcin Juszkiewicz]

SbsaQemu assumes that there is only one PCI Express bus. But there can
be multiple PCIe buses as NUMA systems can get 'pxb-pcie' HostBridge
devices added.

Let scan for all PCIe buses and report them back so EDK2 will be able to
find all expansions.

Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemuPciHostBridgeLib.c  | 185 
 1 file changed, 109 insertions(+), 76 deletions(-)

diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
index 9739c7500def..1c4ed1c74e52 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
@@ -6,10 +6,14 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -52,76 +56,49 @@ CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
   L"Mem", L"I/O", L"Bus"
 };
 
-STATIC PCI_ROOT_BRIDGE mRootBridge = {
-  /* UINT32 Segment; Segment number */
-  0,
-
-  /* UINT64 Supports; Supported attributes */
-  EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
-  EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16,
-
-  /* UINT64 Attributes; Initial attributes */
-  EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
-  EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16,
-
-  /* BOOLEAN DmaAbove4G; DMA above 4GB memory */
-  TRUE,
-
-  /* BOOLEAN NoExtendedConfigSpace; When FALSE, the root bridge supports
- Extended (4096-byte) Configuration Space.  When TRUE, the root bridge
- supports 256-byte Configuration Space only. */
-  FALSE,
-
-  /* BOOLEAN ResourceAssigned; Resource assignment status of the root bridge.
- Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned */
-  FALSE,
-
-  /* UINT64 AllocationAttributes; Allocation attributes. */
-  EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
-  EFI_PCI_HOST_BRIDGE_MEM64_DECODE, /* as Mmio64Size > 0 */
-
-  {
- /* PCI_ROOT_BRIDGE_APERTURE Bus; Bus aperture which can be used by the
-  * root bridge. */
- FixedPcdGet32 (PcdPciBusMin),
- FixedPcdGet32 (PcdPciBusMax)
-  },
-
-  /* PCI_ROOT_BRIDGE_APERTURE Io; IO aperture which can be used by the root
- bridge */
-  {
- FixedPcdGet64 (PcdPciIoBase),
- FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
-  },
-
-  /* PCI_ROOT_BRIDGE_APERTURE Mem; MMIO aperture below 4GB which can be used by
- the root bridge
- (gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation as 0x0) */
-  {
-FixedPcdGet32 (PcdPciMmio32Base),
-FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1,
-  },
-
-  /* PCI_ROOT_BRIDGE_APERTURE MemAbove4G; MMIO aperture above 4GB which can be
- used by the root bridge.
- (gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation as 0x0) */
-  {
-FixedPcdGet64 (PcdPciMmio64Base),
-FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
-  },
-
-  /* PCI_ROOT_BRIDGE_APERTURE PMem; Prefetchable MMIO aperture below 4GB which
- can be used by the root bridge.
- In our case, there are no separate ranges for prefetchable and
- non-prefetchable BARs */
-  { MAX_UINT64, 0 },
-
-  /* PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; Prefetchable MMIO aperture above 4GB
- which can be used by the root bridge. */
-  { MAX_UINT64, 0 },
-  /* EFI_DEVICE_PATH_PROTOCOL *DevicePath; Device path. */
-  (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath,
-};
+EFI_STATUS
+EFIAPI
+PciHostBridgeUtilityInitRootBridge (
+  IN UINTN RootBusNumber,
+  OUT PCI_ROOT_BRIDGE  *RootBus
+  )
+{
+  EFI_PCI_ROOT_BRIDGE_DEVICE_PATH  *DevicePath;
+  UINTNMaxSubBusNumber = 255;
+
+  DevicePath = AllocateCopyPool (
+ sizeof mEfiPciRootBridgeDevicePath,
+ &mEfiPciRootBridgeDevicePath
+ );
+  if (DevicePath == NULL) {
+DEBUG ((DEBUG_ERROR, "%a: %r\n", __func__, EFI_OUT_OF_RESOURCES));
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  DevicePath->AcpiDevicePath.UID = RootBusNumber;
+
+  RootBus->Segment   = 0;
+  RootBus->Supports  = 0;
+  RootBus->Attributes= 0;
+  RootBus->DmaAbove4G= TRUE;
+  RootBus->AllocationAttributes  = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | 
EFI_PCI_HOST_BRIDGE_MEM64_DECODE, /* as Mmio64Size > 0 */
+  RootBus->Bus.Base  = RootBusNumber;
+  RootBus->Bus.Limit = MaxSubBusNumber;
+  RootBus->Io.Base   = PcdGet64 (PcdPciIoBase);
+  RootBus->Io.Limit  = PcdGet64 (PcdPciIoBase) + PcdGet64 
(PcdPciIoSize) - 1;
+  RootBus->Mem.Base  

Re: [edk2-devel] [PATCH v1 1/2] OvmfPkg: Add no hardcode version of FtdNorFlashQemuLib

[Marcin Juszkiewicz]

W dniu 17.05.2024 o 09:17, Chao Li via groups.io pisze:

This library is copied from ArmVirtPkg, in the Arm version, the value of
PcdFlashNvStorageVariableBase, PcdFlashNvStorageFtwWorkingBase and
PcdFlashNvStorageFtwSpareBase are hardcoded in INC file.

This version will calculate them from FDT resource and using the set PCD
to store when the NorFlashInitialise is called. By default, the first
available flash(not used for storage UEFI code) as NV variable storage
medium.

In this way, UEFI can better handle the change of flash base address,
which is suitable for different cpu architecture board implementation.

BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=4770

Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Sami Mujawar
Cc: Gerd Hoffmann
Cc: Jiewen Yao
Signed-off-by: Chao Li
Signed-off-by: Xianglai Li


Can you split it into driver itself and part which uses DT data to setup 
parameters?


This way driver can be used on other platforms as well, despite do they 
hardcode flash data, read it via Firmware Handoff protocol, SMC calls to 
embedded controller or have other way to keep flash data.



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Re: [edk2-devel] Proposal to switch TianoCore Code Review from email to GitHub Pull Requests on 5-24-2024

[Marcin Juszkiewicz]

W dniu 1.05.2024 o 19:43, Michael D Kinney via groups.io pisze:

I would like to propose that TianoCore move all code review from email
based code reviews to GitHub Pull Requests based code reviews.

The proposed date to switch would be immediately after the next stable
tag which is currently scheduled for May 24, 2024.


O yes! Fully for it!

Does it mean edk2 only or edk2/edk2-platforms/edk2-non-osi and other 
tianocore/ repositories?




* The Pull Request submitter is required to invite the required
   maintainers and reviewers to the pull request. This is the same
   set of maintainers and reviewers that are required to be listed in
   Cc: tags in today's process.


That can be done by github action started automatically after opening 
PR. May require changes to GetMaintainer.py script. Would be good to 
have in case someone forget to add one of maintainers.


Also would be nice to have a bot running PatchCheck and uncrustify on PR.


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[edk2-devel] [PATCH edk2-platforms WIP 2/3] SbsaQemu: describe PCIe buses in SSDT tables

[Marcin Juszkiewicz]

We can have more than one PCI Express bus. So instead of having static
description in DSDT we create SSDT table for each existing PCIe bus.

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc |   2 +
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf |  37 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h  |  23 +
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   |  87 ++-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.c  | 576 
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl   | 302 --
 .../Drivers/SbsaQemuAcpiDxe/SsdtTemplate.asl|  82 +++
 7 files changed, 790 insertions(+), 319 deletions(-)

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc 
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index e246db8b0a23..b012eaa34147 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -173,6 +173,8 @@ [LibraryClasses.common]
   
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
 
   AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+  AcpiHelperLib|DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf
+  AmlLib|DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf
 
   ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
   ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
index 727c8e82d16e..6de1073e6ac2 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
@@ -18,18 +18,25 @@ [Defines]
 
 [Sources]
   SbsaQemuAcpiDxe.c
+  SbsaQemuAcpiDxe.h
+  SbsaQemuAcpiPcie.c
+  SbsaQemuAcpiPcie.h
+  SsdtTemplate.asl
 
 [Packages]
   ArmPkg/ArmPkg.dec
   ArmPlatformPkg/ArmPlatformPkg.dec
   ArmVirtPkg/ArmVirtPkg.dec
+  DynamicTablesPkg/DynamicTablesPkg.dec
   EmbeddedPkg/EmbeddedPkg.dec
   MdeModulePkg/MdeModulePkg.dec
   MdePkg/MdePkg.dec
   Silicon/Qemu/SbsaQemu/SbsaQemu.dec
 
 [LibraryClasses]
+  AcpiHelperLib
   AcpiLib
+  AmlLib
   ArmLib
   BaseMemoryLib
   BaseLib
@@ -37,6 +44,7 @@ [LibraryClasses]
   DxeServicesLib
   HardwareInfoLib
   PcdLib
+  PciLib
   PrintLib
   UefiDriverEntryPoint
   UefiLib
@@ -54,14 +62,39 @@ [Pcd]
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSmmuBase
 
 [Depex]
-  gEfiAcpiTableProtocolGuid   ## CONSUMES
+  # We want all PCIe buses to be scanned first
+  gEfiPciIoProtocolGuid ## CONSUMES
 
 [Guids]
   gEdkiiPlatformHasAcpiGuid
 
 [Protocols]
   gEfiAcpiSdtProtocolGuid
-  gEfiAcpiTableProtocolGuid   ## CONSUMES
+  gEfiAcpiTableProtocolGuid
+  gEfiPciRootBridgeIoProtocolGuid
+
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdPciBusMin
+  gArmTokenSpaceGuid.PcdPciBusMax
+  gArmTokenSpaceGuid.PcdPciIoBase
+  gArmTokenSpaceGuid.PcdPciIoSize
+  gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit
+
+  gArmTokenSpaceGuid.PcdPciMmio32Base
+  gArmTokenSpaceGuid.PcdPciMmio32Size
+  gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit
+
+  gArmTokenSpaceGuid.PcdPciMmio64Base
+  gArmTokenSpaceGuid.PcdPciMmio64Size
+  gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit
+
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit
 
 [FixedPcd]
   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h
new file mode 100644
index ..56cc6f1381da
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h
@@ -0,0 +1,23 @@
+/** @file
+*  This file is an ACPI driver for the Qemu SBSA platform.
+*
+*  Copyright (c) 2024, Linaro Ltd. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef SBSAQEMU_ACPI_PCIE_H
+#define SBSAQEMU_ACPI_PCIE_H
+
+#pragma pack(1)
+
+/* AML bytecode generated from SsdtTemplate.asl */
+extern CHAR8  ssdttemplate_aml_code[];
+
+EFI_STATUS
+AddPcieHostBridges (
+  AML_OBJECT_NODE_HANDLE  ScopeNode
+  );
+
+#endif
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 30239e7dca0d..f3d5dc9e9ba7 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -6,28 +6,27 @@
 *  SPDX-License-Identifier: BSD-2-Clause-Patent
 *
 **/
-#include 
-#include 
 #include 
 #include 
 #include 
+
 #include 
+#include 
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
 #include

[edk2-devel] [PATCH edk2-platforms WIP 3/3] SbsaQemu: generate MCFG table

[Marcin Juszkiewicz]

We want to have dynaminc PCI Express variables. Which forces us to
generate MCFG from C code.

Signed-off-by: Marcin Juszkiewicz 
---
 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf  |  1 -
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 83 
 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc   | 43 --
 3 files changed, 83 insertions(+), 44 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf 
b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 8d4905362edc..37abf2f4c512 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -19,7 +19,6 @@ [Sources]
   Dbg2.aslc
   Dsdt.asl
   Fadt.aslc
-  Mcfg.aslc
   Spcr.aslc
 
 [Packages]
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c 
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index f3d5dc9e9ba7..6c7913eead81 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -7,6 +7,7 @@
 *
 **/
 #include 
+#include 
 #include 
 #include 
 
@@ -883,6 +884,83 @@ AddSsdtPcieTable (
   return EFI_SUCCESS;
 }
 
+/** Adds the MCFG ACPI table.
+
+  @param AcpiTableThe ACPI Table.
+  @param PcieCfgData  PCIe configuration data.
+  @param NumPcieSegments  Number of PCIe segments.
+
+  @return EFI_SUCCESS on success, or an error code.
+
+**/
+STATIC
+EFI_STATUS
+AddMcfgTable (
+  IN EFI_ACPI_TABLE_PROTOCOL  *AcpiTable
+  )
+{
+  EFI_STATUSStatus;
+  UINTN TableHandle;
+  UINT32TableSize;
+  EFI_PHYSICAL_ADDRESS  PageAddress;
+  UINT8 *New;
+
+  EFI_ACPI_DESCRIPTION_HEADER  Header =
+SBSAQEMU_ACPI_HEADER (
+  
EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+  EFI_ACPI_DESCRIPTION_HEADER,
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION
+  );
+
+  TableSize = sizeof 
(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) +
+  sizeof 
(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
+
+  Status = gBS->AllocatePages (
+  AllocateAnyPages,
+  EfiACPIReclaimMemory,
+  EFI_SIZE_TO_PAGES (TableSize),
+  &PageAddress
+  );
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MCFG table\n"));
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  New = (UINT8 *)(UINTN)PageAddress;
+  ZeroMem (New, TableSize);
+
+  // Add the  ACPI Description table header
+  CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER));
+  ((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
+  New += sizeof 
(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER);
+
+  
EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE
  *CfgPtr;
+
+  CfgPtr = (VOID *)New;
+
+  CfgPtr->BaseAddress   = PcdGet64 (PcdPciExpressBaseAddress);
+  CfgPtr->PciSegmentGroupNumber = 0;
+  CfgPtr->StartBusNumber= PcdGet32 (PcdPciBusMin);
+  CfgPtr->EndBusNumber  = PcdGet32 (PcdPciBusMax);
+
+  New += sizeof 
(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
+
+  // Perform Checksum
+  AcpiTableChecksum ((UINT8 *)PageAddress, TableSize);
+
+  Status = AcpiTable->InstallAcpiTable (
+AcpiTable,
+(EFI_ACPI_COMMON_HEADER *)PageAddress,
+TableSize,
+&TableHandle
+);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to install MCFG table\n"));
+  }
+
+  return Status;
+}
+
 
 EFI_STATUS
 EFIAPI
@@ -951,6 +1029,11 @@ InitializeSbsaQemuAcpiDxe (
 DEBUG ((DEBUG_ERROR, "Failed to add SSDT table\n"));
   }
 
+  Status = AddMcfgTable (AcpiTable);
+  if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Failed to add MCFG table\n"));
+  }
+
 
   return EFI_SUCCESS;
 }
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc 
b/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
deleted file mode 100644
index 289f4ad4ea3a..
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc
+++ /dev/null
@@ -1,43 +0,0 @@
-/** @file
-*  ACPI Memory mapped configuration space base address Description Table 
(MCFG).
-*
-*  Copyright (c) 2020, Linaro Limited. All rights reserved.
-*
-*  SPDX-License-Identifier: BSD-2-Clause-Patent
-**/
-
-#include 
-#include 
-#include 
-
-#pragma pack(push, 1)
-
-typedef struct {
-  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;
-  
EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE
 Structure[1

[edk2-devel] [PATCH WIP edk2-platforms 0/3] SbsaQemu: add support for multiple PCI Express buses

[Marcin Juszkiewicz]

QEMU allows to have NUMA setup where each node has own cpus, memory and
i/o. We already handle cpus and memory. This patchset adds support for
having multiple PCI Express buses.

SbsaQemu assumed that there is only bus 0. First patch does PCIe bus
scan to find all host bridges (bus 0 one and additional 'pxb-pcie'
ones).

Second patch moves description of PCIe from DSDT to SSDT (one per each
PCIe bus). So Operating System will know about all of them.

Third patch moves generation of MCFG table to C. It is preparation to
move PCIe Pcds from being fixed to dynamic ones.

There are some booting issues with assigning resources for cards:

pci :00:03.0: BAR 15: no space for [mem size 0x0020 64bit pref]
pci :00:03.0: BAR 15: failed to assign [mem size 0x0020 64bit pref]
pci :00:01.0: BAR 6: no space for [mem size 0x0004 pref]
pci :00:01.0: BAR 6: failed to assign [mem size 0x0004 pref]
pci :00:03.0: BAR 13: no space for [io  size 0x1000]
pci :00:03.0: BAR 13: failed to assign [io  size 0x1000]

Boot log (Linux + lspci + ACPI tables dump):
https://people.linaro.org/~marcin.juszkiewicz/sbsa-ref/boot-linux-with-numa-multiple-pcie-buses.txt

I am wondering where I made mistakes in handling PCIe buses.

Thanks go to Leif for pointing me to use of Aml to generate SSDT tables.

Cc: Leif Lindholm 
Cc: Ard Biesheuvel 
Cc: Graeme Gregory 
Cc: Ray Ni 
To: devel@edk2.groups.io

Signed-off-by: Marcin Juszkiewicz 
---
Marcin Juszkiewicz (3):
  SbsaQemu: scan for PCIe buses
  SbsaQemu: describe PCIe buses in SSDT tables
  SbsaQemu: generate MCFG table

 Platform/Qemu/SbsaQemu/SbsaQemu.dsc |   2 +
 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf |   1 -
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf |  37 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.h  |  23 +
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c   | 170 +-
 .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiPcie.c  | 576 
 .../SbsaQemuPciHostBridgeLib.c  | 185 ---
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl   | 302 --
 Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc  |  43 --
 .../Drivers/SbsaQemuAcpiDxe/SsdtTemplate.asl|  82 +++
 10 files changed, 982 insertions(+), 439 deletions(-)
---
base-commit: 73cfdc4afff3e641be217b31b985761ef8338412
change-id: 20240425-review-multiple-pcie-0425-54ce3817fd3f

Best regards,
-- 
Marcin Juszkiewicz 



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[edk2-devel] [PATCH edk2-platforms WIP 1/3] SbsaQemu: scan for PCIe buses

[Marcin Juszkiewicz]

SbsaQemu assumes that there is only one PCI Express bus. But there can
be multiple PCIe buses as NUMA systems can get 'pxb-pcie' HostBridge
devices added.

Let scan for all PCIe buses and report them back so EDK2 will be able to
find all expansions.

Signed-off-by: Marcin Juszkiewicz 
---
 .../SbsaQemuPciHostBridgeLib.c  | 185 
 1 file changed, 109 insertions(+), 76 deletions(-)

diff --git 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
index 9739c7500def..1c4ed1c74e52 100644
--- 
a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
+++ 
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
@@ -6,10 +6,14 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -52,76 +56,49 @@ CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
   L"Mem", L"I/O", L"Bus"
 };
 
-STATIC PCI_ROOT_BRIDGE mRootBridge = {
-  /* UINT32 Segment; Segment number */
-  0,
-
-  /* UINT64 Supports; Supported attributes */
-  EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
-  EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16,
-
-  /* UINT64 Attributes; Initial attributes */
-  EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
-  EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16,
-
-  /* BOOLEAN DmaAbove4G; DMA above 4GB memory */
-  TRUE,
-
-  /* BOOLEAN NoExtendedConfigSpace; When FALSE, the root bridge supports
- Extended (4096-byte) Configuration Space.  When TRUE, the root bridge
- supports 256-byte Configuration Space only. */
-  FALSE,
-
-  /* BOOLEAN ResourceAssigned; Resource assignment status of the root bridge.
- Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned */
-  FALSE,
-
-  /* UINT64 AllocationAttributes; Allocation attributes. */
-  EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |
-  EFI_PCI_HOST_BRIDGE_MEM64_DECODE, /* as Mmio64Size > 0 */
-
-  {
- /* PCI_ROOT_BRIDGE_APERTURE Bus; Bus aperture which can be used by the
-  * root bridge. */
- FixedPcdGet32 (PcdPciBusMin),
- FixedPcdGet32 (PcdPciBusMax)
-  },
-
-  /* PCI_ROOT_BRIDGE_APERTURE Io; IO aperture which can be used by the root
- bridge */
-  {
- FixedPcdGet64 (PcdPciIoBase),
- FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
-  },
-
-  /* PCI_ROOT_BRIDGE_APERTURE Mem; MMIO aperture below 4GB which can be used by
- the root bridge
- (gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation as 0x0) */
-  {
-FixedPcdGet32 (PcdPciMmio32Base),
-FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1,
-  },
-
-  /* PCI_ROOT_BRIDGE_APERTURE MemAbove4G; MMIO aperture above 4GB which can be
- used by the root bridge.
- (gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation as 0x0) */
-  {
-FixedPcdGet64 (PcdPciMmio64Base),
-FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
-  },
-
-  /* PCI_ROOT_BRIDGE_APERTURE PMem; Prefetchable MMIO aperture below 4GB which
- can be used by the root bridge.
- In our case, there are no separate ranges for prefetchable and
- non-prefetchable BARs */
-  { MAX_UINT64, 0 },
-
-  /* PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; Prefetchable MMIO aperture above 4GB
- which can be used by the root bridge. */
-  { MAX_UINT64, 0 },
-  /* EFI_DEVICE_PATH_PROTOCOL *DevicePath; Device path. */
-  (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath,
-};
+EFI_STATUS
+EFIAPI
+PciHostBridgeUtilityInitRootBridge (
+  IN UINTN RootBusNumber,
+  OUT PCI_ROOT_BRIDGE  *RootBus
+  )
+{
+  EFI_PCI_ROOT_BRIDGE_DEVICE_PATH  *DevicePath;
+  UINTNMaxSubBusNumber = 255;
+
+  DevicePath = AllocateCopyPool (
+ sizeof mEfiPciRootBridgeDevicePath,
+ &mEfiPciRootBridgeDevicePath
+ );
+  if (DevicePath == NULL) {
+DEBUG ((DEBUG_ERROR, "%a: %r\n", __func__, EFI_OUT_OF_RESOURCES));
+return EFI_OUT_OF_RESOURCES;
+  }
+
+  DevicePath->AcpiDevicePath.UID = RootBusNumber;
+
+  RootBus->Segment   = 0;
+  RootBus->Supports  = 0;
+  RootBus->Attributes= 0;
+  RootBus->DmaAbove4G= TRUE;
+  RootBus->AllocationAttributes  = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | 
EFI_PCI_HOST_BRIDGE_MEM64_DECODE, /* as Mmio64Size > 0 */
+  RootBus->Bus.Base  = RootBusNumber;
+  RootBus->Bus.Limit = MaxSubBusNumber;
+  RootBus->Io.Base   = PcdGet64 (PcdPciIoBase);
+  RootBus->Io.Limit  = PcdGet64 (PcdPciIoBase) + PcdGet64 
(PcdPciIoSize) - 1;
+  RootBus->Mem.Base  

Re: [edk2-devel] [PATCH edk2-non-osi 1/1] Qemu/Sbsa: update TF-A binaries for QEMU v9.0+

[Marcin Juszkiewicz]

W dniu 23.04.2024 o 12:36, Leif Lindholm via groups.io pisze:

QEMU v9 uses 1GHz frequency for generic timers as required for Arm v8.6+
cpu cores. TF-A was hardcoding 62.5MHz value which is used for older
designs. Now it will use value present in CNTFRQ_EL0 register (set by
QEMU).

Enable FEAT_ECV for QEMU v9.0+ to get access to CNTPOFF register.

Signed-off-by: Marcin Juszkiewicz

Reviewed-by: Leif Lindholm
Thanks!

Can you push the change yourself?


Thanks, pushed.


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[edk2-devel] Are there any plans for something like EdkStandardLib?

[Marcin Juszkiewicz]

The more I dig in EDK2 during SbsaQemu work, the more I see duplicated 
code.


Want to scan PCI bus to check for host bridges? Two or three 
implementations exist. Want to calculate checksum of just created ACPI 
table? AcpiPlatformChecksum() has several, incompatible with each other, 
implementations waiting for you.


Are there any plans for making some kind of standard library?

Moving AmlLib outside of DynamicTables framework? Second uses first one 
but first one can be used without second.


Some kind of ACPI table generators from DynamicTables but without using 
ConfigurationManager?



Anyone?


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[edk2-devel] [PATCH edk2-platforms v2 1/2] SbsaQemu: do not set Timer interrupts

[Marcin Juszkiewicz]

Timer interrupts are set by ArmPkg.dec to recommended values.
We do not need to repeat it (and we missed HypVirtIntrNum one).

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 10 --
 1 file changed, 10 deletions(-)

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc 
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index fefb7a7ae92d..e246db8b0a23 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -437,16 +437,6 @@ [PcdsFixedAtBuild.common]
   # PL011 - Serial Terminal
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x6000
 
-  # Timer IRQs
-  # PPI #13
-  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29
-  # PPI #14
-  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30
-  # PPI #11
-  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27
-  # PPI #10
-  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26
-
   ## PL031 RealTimeClock
   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x6001
 
-- 
2.44.0



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[edk2-devel] [PATCH edk2-platforms v2 2/2] SbsaQemu: remove some methods from DSDT

[Marcin Juszkiewicz]

IASL complained that DSDT is not optimal:

Dsdt.
83: Name (RBUF, ResourceTemplate() {
Remark   2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead ^
(\_SB.USB0._CRS)

Dsdt.
377:   Name (RBUF, ResourceTemplate () {
Remark   2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead ^
(\_SB.PCI0._CRS)

Simplified some _CRS nodes.

Signed-off-by: Marcin Juszkiewicz 
---
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 23 ---
 1 file changed, 8 insertions(+), 15 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl 
b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
index b55ad6c5cc07..c134fb66e860 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -77,15 +77,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
 Method (_STA) {
   Return (XHCI)
 }
-Method (_CRS, 0x0, Serialized) {
-Name (RBUF, ResourceTemplate() {
-Memory32Fixed (ReadWrite,
-   FixedPcdGet32 (PcdPlatformXhciBase),
-   FixedPcdGet32 (PcdPlatformXhciSize))
-Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 
43 }
-})
-Return (RBUF)
-}
+Name (_CRS, ResourceTemplate() {
+Memory32Fixed (ReadWrite,
+   FixedPcdGet32 (PcdPlatformXhciBase),
+   FixedPcdGet32 (PcdPlatformXhciSize))
+Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
+})
 
 // Root Hub
 Device (RHUB) {
@@ -371,8 +368,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
   })
 
   // Root complex resources
-  Method (_CRS, 0, Serialized) {
-  Name (RBUF, ResourceTemplate () {
+  Name (_CRS, ResourceTemplate () {
 WordBusNumber ( // Bus numbers assigned to this root
 ResourceProducer,
 MinFixed, MaxFixed, PosDecode,
@@ -418,10 +414,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
   FixedPcdGet32 (PcdPciIoSize),// Length
   ,,,TypeTranslation
   )
-}) // Name(RBUF)
-
-Return (RBUF)
-  } // Method(_CRS)
+  }) // Name(_CRS)
 
   Device (RES0)
   {
-- 
2.44.0



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[edk2-devel] [PATCH edk2-platforms v2 0/2] SbsaQemu: some cleanups

[Marcin Juszkiewicz]

I am working on some changes to SbsaQemu and got some cleanups in
meantime.

First patch gets rid of setting Pcds for Timer interrupts. ArmPkg does
it for us so we do not have to.

Second changes DSDT nodes so iasl does not complain.

Marcin Juszkiewicz (2):
  SbsaQemu: do not set Timer interrupts
  SbsaQemu: remove some methods from DSDT

 Platform/Qemu/SbsaQemu/SbsaQemu.dsc   | 10 --
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 23 ---
 2 files changed, 8 insertions(+), 25 deletions(-)

-- 
2.44.0



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[edk2-devel] [PATCH edk2-non-osi 1/1] Qemu/Sbsa: update TF-A binaries for QEMU v9.0+

[Marcin Juszkiewicz]

QEMU v9 uses 1GHz frequency for generic timers as required for Arm v8.6+
cpu cores. TF-A was hardcoding 62.5MHz value which is used for older
designs. Now it will use value present in CNTFRQ_EL0 register (set by
QEMU).

Enable FEAT_ECV for QEMU v9.0+ to get access to CNTPOFF register.

Signed-off-by: Marcin Juszkiewicz 
---
 Platform/Qemu/Sbsa/Readme.md |  55 ++-
 Platform/Qemu/Sbsa/bl1.bin   | Bin 23365 -> 23349 bytes
 Platform/Qemu/Sbsa/fip.bin   | Bin 82722 -> 82722 bytes
 3 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/Platform/Qemu/Sbsa/Readme.md b/Platform/Qemu/Sbsa/Readme.md
index 5ed05f0f3021..b1351043d2b4 100644
--- a/Platform/Qemu/Sbsa/Readme.md
+++ b/Platform/Qemu/Sbsa/Readme.md
@@ -4,50 +4,51 @@ Qemu SBSA TF-A binaries
 These binaries have been created from the mainline TF-A
 code checked out at the following commit ID:
 
-commit f36faa71578a14a8c9910aaa57e761f0256ccd52 (HEAD -> master, 
origin/master, origin/integration, origin/HEAD)
-Merge: 8dad296d6 57ab6d897
-Author: Lauren Wehrmeister 
-Date:   Tue Mar 12 19:17:49 2024 +0100
+commit 56b263cb2a25892038761acea8c2b57a638d19bf (HEAD -> integration, 
origin/integration, gerrit/integration)
+Merge: 09d3fd141 e769f830d
+Author: Yann Gautier 
+Date:   Tue Apr 23 10:42:01 2024 +0200
 
-Merge "fix(cpus): fix a defect in Cortex-A715 erratum 2561034" into 
integration
+Merge "feat(qemu): allow ARM_ARCH_MAJOR/MINOR override" into integration
 
 
 This ensures that the following features for qemu_sbsa platform are
 merged upstream and included in the build:
 
-commit 42925c15bee09162c6dfc8c2204843ffac6201c1
+commit 5436047a0e1f32543042d6de9f1f6a3edcd47591
 Author: Marcin Juszkiewicz 
-Date:   Tue Nov 21 14:53:26 2023 +0100
+Date:   Mon Apr 22 17:27:56 2024 +0200
 
-feat(qemu-sbsa): handle CPU information
+refactor(qemu): do not hardcode counter frequency
 
-We want to remove use of DeviceTree from EDK2. So we move
-functions to TF-A:
+From QEMU change:
 
-- counting cpu cores
-- checking NUMA node id
-- checking MPIDR
+> In previous versions of the Arm architecture, the frequency of the
+> generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
+> and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
+> In Armv8.6, the architecture standardized this frequency to 1GHz.
 
-And then it gets passed to EDK2 via SMC calls.
+This change stops TF-A from hardcoding 62.5MHz frequency. Instead value
+stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older
+cores and 1GHz on newer ones.
 
-Change-Id: I1c7fc234ba90ba32433b6e4aa2cf127f26da00fd
+Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4
 Signed-off-by: Marcin Juszkiewicz 
 
-commit 8b7dd8397dd017b61ecda8447e8956a1d9d6d5d3
-Author: Xiong Yining 
-Date:   Fri Jan 12 10:47:03 2024 +
+commit 1b694c77c497cb8272c97417ef1fa4f5f9c869c1
+Author: Jean-Philippe Brucker 
+Date:   Mon Apr 15 14:28:11 2024 +0100
 
-feat(qemu-sbsa): handle memory information
+feat(qemu): enable FEAT_ECV when present
 
-As a part of removing DeviceTree from EDK2, we move functions to TF-A:
+QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
+FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
+auto-detecting the feature on the QEMU platforms, in order to set
+SCR.ECVEN. Without this, EL2 gets undefined instruction exceptions when
+trying to access the new CNTPOFF register.
 
-- counting the number of memory nodes
-- checking NUMA node id
-- checking the memory address
-
-Signed-off-by: Xiong Yining 
-Signed-off-by: Chen Baozi 
-Change-Id: Ib7bce3a65c817a5b3bef6c9e0a459c7ce76c7e35
+Change-Id: I555a5f9a9a84fd23e64ca85219ed1599204c6bb2
+Signed-off-by: Jean-Philippe Brucker 
 
 
 NOTE: No modifications to the source code have been done.
diff --git a/Platform/Qemu/Sbsa/bl1.bin b/Platform/Qemu/Sbsa/bl1.bin
index 
8eac6204b64be03036c6aabe84618a7c979e78e0..6ad39377a464050dcc714d1316ff8981ad637ded
 100755
GIT binary patch
delta 4429
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zQ=M4#_He@8+5)pe^K?|Kw{T}_Pi9sp46qn3_Y@;b8fqXjvi_#Wb??9ksq?ehQ{3g}Ze
z8KS|os2||b<6xTB-=SUmnLlQ%EUk2oku6`1VMj2W#Z84+dA$b0Mzz|*(zf+u9RP1p
z{Na4c100yo(oK6qp&U6rc?eSBGu4zGjgFLQ1-q~^@RMFl&
zBvGO;%Oopow3Hp1NA}j|@jA24J!+Jnr4%2aSZ{c}jh|4dH+*?KGxa@h#(7Vcz=@k2pk-T0$$r@lMiLzC*!
zbYoV?V$z-rIYZxfg+64IM41`vo(g~yEY#K8i=Cl4rt|q8WetC&xg7isWEjA(NqaTA
zLVRITyv-RaJNxoIi2x&Z)y=DKD;=|
z8a)^*S7=1}*C_DB2zJkaR-5_`PSr{JZ}L5Z?}O|d#JhA`HC7S-p-a;91gPVSy5x|2
zQN9|Bk@{427VprD>;t?{@0f8mq^&;`JR>wk%BBE{nmeHJDD~X){xYc#-_ys72AW+(
zR+d)M6}Eu@C6Z2$zvyRboUtf|-EA5WW!G3i8!*V6LCNnP!-vB*3Z$OJufww0I*ggT
zj1}XC$vfB>em{8u>qCoSF?$_185Xb}eAO_IJ%L})_k$Q7Ua4`$;nwifnMU51QQ!7E
zPg61!wk7JIx&@$&@-RsTJ-#3QsK!``3nJo`hASdcBL?GS1zyp_JlkZ{x9*KdWrD-i
z

[edk2-devel] [PATCH edk2-platforms] SbsaQemu: move code outside of methods in DSDT

[Marcin Juszkiewicz]

IASL complained that DSDT is not optimal:

Dsdt.
83: Name (RBUF, ResourceTemplate() {
Remark   2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead ^
(\_SB.USB0._CRS)

Dsdt.
377:   Name (RBUF, ResourceTemplate () {
Remark   2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead ^
(\_SB.PCI0._CRS)
---
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl 
b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
index b55ad6c5cc07..60c72fecc74f 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -77,13 +77,13 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
 Method (_STA) {
   Return (XHCI)
 }
+Name (RBUF, ResourceTemplate() {
+Memory32Fixed (ReadWrite,
+   FixedPcdGet32 (PcdPlatformXhciBase),
+   FixedPcdGet32 (PcdPlatformXhciSize))
+Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
+})
 Method (_CRS, 0x0, Serialized) {
-Name (RBUF, ResourceTemplate() {
-Memory32Fixed (ReadWrite,
-   FixedPcdGet32 (PcdPlatformXhciBase),
-   FixedPcdGet32 (PcdPlatformXhciSize))
-Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 
43 }
-})
 Return (RBUF)
 }
 
@@ -371,7 +371,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
   })
 
   // Root complex resources
-  Method (_CRS, 0, Serialized) {
   Name (RBUF, ResourceTemplate () {
 WordBusNumber ( // Bus numbers assigned to this root
 ResourceProducer,
@@ -418,10 +417,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
   FixedPcdGet32 (PcdPciIoSize),// Length
   ,,,TypeTranslation
   )
-}) // Name(RBUF)
-
+  }) // Name(RBUF)
+  Method (_CRS, 0, Serialized) {
 Return (RBUF)
-  } // Method(_CRS)
+  }
 
   Device (RES0)
   {
-- 
2.44.0



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Re: [edk2-devel] ACPI table generators and ConfigurationManagerProtocol

[Marcin Juszkiewicz]

W dniu 16.04.2024 o 09:38, Marcin Juszkiewicz via groups.io pisze:
And if someone considers using ConfigurationManager for their platform: 
please reconsider it as it may not be worth your time.


Wrote blog post about my adventure with CM:

https://marcin.juszkiewicz.com.pl/2024/04/16/configurationmanager-in-edk2-just-say-no/


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Re: [edk2-devel] ACPI table generators and ConfigurationManagerProtocol

[Marcin Juszkiewicz]

W dniu 12.04.2024 o 14:43, Marcin Juszkiewicz via groups.io pisze:

W dniu 8.10.2023 o 19:25, Marcin Juszkiewicz via groups.io pisze:

I hate replying to myself after half a year of not seeing any answer. So 
added some people from repo to Cc:


Can someone point me to documentation on how to use ACPI table 
generators and ConfigurationManagerProtocol?


https://github.com/tianocore/edk2/blob/master/DynamicTablesPkg/Readme.md 
tells the story and points to presentation from 2018 with some pictures 
in it.


Looks like the only documentation is the code itself. Is checkout of 
some old tree and looking change by change how it was done on some 
platform the easiest way to find out how to use it?


The more I look at */ConfigurationManager.[ch] the more I do not like 
the amount of static structures there. All those 
EDKII_PLATFORM_REPOSITORY_INFO covering 1000 lines looks like "how the 
hell I will find what to change in other piece of code".


Any doc pointers? Recommendations (other than "change your job")?


I have spent two days on trying ConfigurationManager and finally gave 
up. The idea behind may look interesting but implementation of it is 
terrible. And there is no documentation for it.


Edk2_Platform_Repo_Info struct full of other structs can be one thousand 
lines long. Then are functions to query those structs - which can take 
almost another thousand lines.


For hardware where amount of system components is known and does not 
change it may be tempting. For those like sbsa-ref/QemuSbsa it means 
extra code to fill struct of structs with hardware details (cpu nodes, 
gic nodes, cpu topology/hierarchy/cache info etc).


So I am going back to how "my" platform is done. Probably will learn 
AmlLib to create DSDT from C code.



And if someone considers using ConfigurationManager for their platform: 
please reconsider it as it may not be worth your time.



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Re: [edk2-devel] ACPI table generators and ConfigurationManagerProtocol

[Marcin Juszkiewicz]

W dniu 8.10.2023 o 19:25, Marcin Juszkiewicz via groups.io pisze:

I hate replying to myself after half a year of not seeing any answer. So 
added some people from repo to Cc:


Can someone point me to documentation on how to use ACPI table 
generators and ConfigurationManagerProtocol?


https://github.com/tianocore/edk2/blob/master/DynamicTablesPkg/Readme.md 
tells the story and points to presentation from 2018 with some pictures 
in it.


Looks like the only documentation is the code itself. Is checkout of 
some old tree and looking change by change how it was done on some 
platform the easiest way to find out how to use it?



And tell which of platforms is a good example of using those?


Juno, FVP, Morello, N1SDP, one NXP platform and ArmVirt use them. 
Probably the last one would be best to look at but who knows...


From first look it seems like using ACPI table generators may allow 
to simplify code by not creating tables by hand (or in ASL). I would
like to do some changes around SBSA Reference Platform without 
rewriting ASL into C again.


In meantime I rewrote some ASL into C. Again. Now need a way to generate 
DSDT for PCIe buses. Can write something in C again. But do I really 
need to?


I am aware that moving platform to use configuration manager may 
require even more work.


The more I look at */ConfigurationManager.[ch] the more I do not like 
the amount of static structures there. All those 
EDKII_PLATFORM_REPOSITORY_INFO covering 1000 lines looks like "how the 
hell I will find what to change in other piece of code".


Any doc pointers? Recommendations (other than "change your job")?


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Re: [edk2-devel] [PATCH v4 1/1] SbsaQemu: AcpiDxe: Create SRAT table at runtime

[Marcin Juszkiewicz]

W dniu 28.03.2024 o 07:19, Xiong Yining pisze:

Add support to create SRAT(System resource affinity table) for
sbsa platform at runtime.

Signed-off-by: Xiong Yining



Reviewed-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm


When you send a new version of patch, with changes done compared to 
previous one you drop "Reviewed-by" tags because it is not code anyone 
saw before.


You add/copy "Reviewed-by" only if patch is in the same version as the 
one reviewed. And only if someone really added that tag in review, not 
when they looked and commented (I never gave "Reviewed-by" tag to any 
version of this patch).



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Re: [edk2-devel] [PATCH v2 1/1] SbsaQemu: AcpiDxe: Create SRAT table at runtime

[Marcin Juszkiewicz]

W dniu 20.02.2024 o 08:47, Xiong Yining pisze:

Add support to create SRAT(System resource affinity table) for
sbsa platform at runtime.

Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi


Needs rebase on top of "get rid of DeviceTree from SbsaQemu" series.

Rename SbsaQemuHardwareInfoLib to HardwareInfoLib and use newer function 
names.



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Re: [edk2-devel] [PATCH v3 1/1] SbsaQemu: add memory space for the high memory nodes

[Marcin Juszkiewicz]

W dniu 20.02.2024 o 08:33, Xiong Yining pisze:

To support more memory nodes, we refer to the implement of
"OvmfPkg/Fdt/HighMemDxe" to add memory space for the high memory nodes
except the first one.

Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi


Needs rebase on top of "get rid of DeviceTree from SbsaQemu" series.

Rename SbsaQemuHardwareInfoLib to HardwareInfoLib and use newer function 
names.



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