[edk2-devel] [RFC PATCH edk2-platforms 2/2] SbsaQemu: AcpiTables: Add CEDT Table
Provide CXL Early Discovery Table that describes the static CXL
Platform Components of sbsa-ref.
This adds a static CXL Host Bridge structure and a CXL Fixed Memory
Window structure which are implemented as two independent space on
sbsa-ref: [SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW].
Signed-off-by: Yuquan Wang
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 6 +-
Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc| 70 +++
Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 7 ++
3 files changed, 82 insertions(+), 1 deletion(-)
create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index b4d5aa807bd9..f39b06d708d5 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -21,7 +21,7 @@
Fadt.aslc
Mcfg.aslc
Spcr.aslc
-
+ Cedt.aslc
[Packages]
ArmPlatformPkg/ArmPlatformPkg.dec
ArmPkg/ArmPkg.dec
@@ -78,6 +78,10 @@
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarSize
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarLimit
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChbcrBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCfmwsBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCfmwsSize
+
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc
b/Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc
new file mode 100644
index ..66c9dc8858bc
--- /dev/null
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc
@@ -0,0 +1,70 @@
+/** @file
+* CXL Early Discovery Table (CEDT)
+*
+* Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved.
+*
+**/
+
+#include
+#include
+#include
+
+#pragma pack(1)
+
+typedef struct
+{
+ EFI_ACPI_6_4_CXL_Early_Discovery_TABLE Header;
+ EFI_ACPI_6_4_CXL_Host_Bridge_Structure Chbs;
+ EFI_ACPI_6_4_CXL_Fixed_Memory_Window_Structure Cfmws;
+} SBSA_REF_CEDT;
+
+
+SBSA_REF_CEDT Cedt =
+{
+ // EFI_ACPI_6_4_CXL_Early_Discovery_TABLE(Header)
+ {
+ SBSAQEMU_ACPI_HEADER // EFI_ACPI_DESCRIPTION_HEADER
+ (
+ EFI_ACPI_6_4_CXL_EARLY_DISCOVERY_TABLE_SIGNATURE,
+ SBSA_REF_CEDT,
+ EFI_ACPI_CXL_Early_Discovery_TABLE_REVISION_01
+ ),
+ },
+ // EFI_ACPI_6_4_CXL_Host_Bridge_Structure
+ {
+// EFI_ACPI_6_4_CEDT_Structure
+{
+EFI_ACPI_CEDT_TYPE_CHBS, // Type
+0, // Reserved
+sizeof (EFI_ACPI_6_4_CXL_Host_Bridge_Structure), // Length
+},
+FixedPcdGet32 (PcdCxlBusMin), // UID
+0x1, // CXLVersion
+0, // Reserved
+FixedPcdGet32 (PcdChbcrBase), // CHBCR Base
+0X1, // Length
+ },
+ // EFI_ACPI_6_4_CXL_Fixed_Memory_Window_Structure
+ {
+// EFI_ACPI_6_4_CEDT_Structure
+{
+EFI_ACPI_CEDT_TYPE_CFMWS,// Type
+0, // Reserved
+sizeof (EFI_ACPI_6_4_CXL_Fixed_Memory_Window_Structure), // Length
+},
+0, // Reserved
+FixedPcdGet32 (PcdCfmwsBase), // BaseHPA
+FixedPcdGet32 (PcdCfmwsSize), // WindowSize
+0, // InterleaveMembers
+0, // InterleaveArithmetic
+0, // Reserved1
+0, // Granularity
+0xF, // Restrictions
+0, // QtgId
+FixedPcdGet32 (PcdCxlBusMin), // FirstTarget
+ }
+};
+
+#pragma pack ()
+
+VOID* CONST ReferenceAcpiTable = &Cedt;
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index 7d8c7997160b..dff838315d06 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -65,6 +65,13 @@ HardwareInfoLib|Include/Library/HardwareInfoLib.h
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMin|254|UINT32|0x0019
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMax|255|UINT32|0x0020
+ # PCDs complementing base address for CXL CHBCR (CXL Host Bridge Component
Registers)
+
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChbcrBase|0x6012|UINT64|0x0021
+
+ # CXL Fixed Memory Window
+
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCfmwsBase|0xA00|UINT64|0x0022
+
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCfmwsSize|0x100|UINT64|0x0023
+
[PcdsDynamic.common]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemManufacturer|L""|VOID*|0x0110
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSer
[edk2-devel] [RFC PATCH edk2-platforms 1/2] SbsaQemu: Add acpi0016 & acpi0017 objects into DSDT
This adds relevant definitions and descriptions of acpi0016 and acpi0017 to support CXL. With the implementation of pxb-cxl on the original pcie host bridge, the previous space layout of mmio32 & mmio64 have to be divided to provide the mmio space for cxl host bridge. I'm not sure if the new space layout would bring a series of bad influence, but it seems that the base address and size of cxl host bridge is ok. Signed-off-by: Yuquan Wang --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 30 +- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 14 + Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 410 +- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc| 2 +- .../SbsaQemuPciHostBridgeLib.c| 4 +- .../SbsaQemuPciHostBridgeLib.inf | 3 + Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 27 +- 7 files changed, 473 insertions(+), 17 deletions(-) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc index 9f54a8915707..5694c0bc8b01 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -452,23 +452,39 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE # # ECAM size == 0x1000 gArmTokenSpaceGuid.PcdPciBusMin|0 - gArmTokenSpaceGuid.PcdPciBusMax|255 + gArmTokenSpaceGuid.PcdPciBusMax|253 gArmTokenSpaceGuid.PcdPciIoBase|0x0 gArmTokenSpaceGuid.PcdPciIoSize|0x0001 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x gArmTokenSpaceGuid.PcdPciMmio32Base|0x8000 - gArmTokenSpaceGuid.PcdPciMmio32Size|0x7000 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFFF + gArmTokenSpaceGuid.PcdPciMmio32Size|0x6FE0 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFDF gArmTokenSpaceGuid.PcdPciMmio64Base|0x1 - gArmTokenSpaceGuid.PcdPciMmio64Size|0xFF - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFF + gArmTokenSpaceGuid.PcdPciMmio64Size|0xFE + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFE + + # + # CXL Host Bridge (pxb-cxl on PCI Root Complex) + # + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMin|254 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMax|255 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Base|0xEFE0 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Size|0x0020 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Base|0xFF + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Size|0x1 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Limit|0xEFFF + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Limit|0xFF # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this # PCD and PcdPciDisableBusEnumeration have not been assigned yet # TODO: PcdPciExpressBaseAddress set to max_uint64 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xf000 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x1000 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0x + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x0FE0 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFDF + # PCDs complementing CXL ECAM Base & Size + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBaseAddress|0xFFE0 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarSize|0x0020 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBarLimit|0x gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x7fff gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation|0x0 diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf index 8d4905362edc..b4d5aa807bd9 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -44,6 +44,8 @@ gArmTokenSpaceGuid.PcdPciBusMin gArmTokenSpaceGuid.PcdPciBusMax + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMin + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBusMax gArmTokenSpaceGuid.PcdPciIoBase gArmTokenSpaceGuid.PcdPciIoSize @@ -60,10 +62,22 @@ gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Base + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Size + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio32Limit + + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Base + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Size + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlMmio64Limit + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCxlBaseAddress + gArmVirtSbsaQemuPlatformTokenSpaceGuid.
[edk2-devel] [RFC PATCH edk2-platforms 0/2] add basic support for CXL on sbsa-ref
RFC because - Many contents are ported from Jonathan' patch on qemu virt design - Bring plenty of PCDs values and modifying the original PCIE values - Less experience and not particularly confident in ACPI area so this might be stupidly broken in a way I've not considered. This series leverages Jonathan's patches[1] to add acpi0016 & acpi0017 objects into the previous DSDT table of sbsa-ref. Since the acpi0016 implementation model on qemu side is the pxb-cxl, this cxl Bus would share the MMIO space and ECAM sapce of PCIE Bus. Thus I divide some space from PciMmio32、PciMmio64、PciExpressBar to support cxl-related values. Based on the new CEDT definitions patch on edk2[2], this series adds a static Cedt.aslc to support the [SBSA_CXL_HOST] & [SBSA_CXL_FIXED_WINDOW] space on sbsa-ref. Since I was first developing this platform design for cxl, at the initial stage I only reserved one cxl host bridge (Bus: :fe) and a cxl root port underneath (fe:00.0), therefore, only one cxl device(ff:00.0)could be added by user on this cxl Bus. Link: [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-2-jonathan.came...@huawei.com/ [2]: https://edk2.groups.io/g/devel/topic/rfc_patch_0_1/108173029 Yuquan Wang (2): SbsaQemu: Add acpi0016 & acpi0017 objects into DSDT SbsaQemu: AcpiTables: Add CEDT Table Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 30 +- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 20 +- Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc| 70 +++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 410 +- Silicon/Qemu/SbsaQemu/AcpiTables/Mcfg.aslc| 2 +- .../SbsaQemuPciHostBridgeLib.c| 4 +- .../SbsaQemuPciHostBridgeLib.inf | 3 + Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 34 +- 8 files changed, 555 insertions(+), 18 deletions(-) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Cedt.aslc -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#120438): https://edk2.groups.io/g/devel/message/120438 Mute This Topic: https://groups.io/mt/108173682/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [RFC PATCH 1/1] MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT
This adds #defines and struct typedefs for the various structure
types in the ACPI 6.4 CXL Early Discovery Table (CEDT).
Signed-off-by: Yuquan Wang
---
MdePkg/Include/IndustryStandard/Acpi64.h | 5 ++
.../IndustryStandard/CXLEarlyDiscoveryTable.h | 69 +++
2 files changed, 74 insertions(+)
create mode 100644 MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h
diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h
b/MdePkg/Include/IndustryStandard/Acpi64.h
index bbe6a3c9eb..c988de8ebf 100644
--- a/MdePkg/Include/IndustryStandard/Acpi64.h
+++ b/MdePkg/Include/IndustryStandard/Acpi64.h
@@ -3169,6 +3169,11 @@ typedef struct {
///
#define EFI_ACPI_6_4_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N',
'V')
+///
+/// "CEDT" CXL Early Discovery Table
+///
+#define EFI_ACPI_6_4_CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32 ('C',
'E', 'D', 'T')
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h
b/MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h
new file mode 100644
index 00..84f88dc737
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h
@@ -0,0 +1,69 @@
+/** @file
+ ACPI CXL Early Discovery Table (CEDT) definitions.
+
+ Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved.
+
+**/
+
+#ifndef __CXL_Early_Discovery_TABLE_H__
+#define __CXL_Early_Discovery_TABLE_H__
+
+#include
+#include
+
+#define EFI_ACPI_CXL_Early_Discovery_TABLE_REVISION_01 0x1 //CXL2.0
+#define EFI_ACPI_CXL_Early_Discovery_TABLE_REVISION_02 0x2 //CXL3.1
+
+#define EFI_ACPI_CEDT_TYPE_CHBS 0x0
+#define EFI_ACPI_CEDT_TYPE_CFMWS0x1
+
+#pragma pack(1)
+
+///
+/// Table header
+///
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADERHeader;
+} EFI_ACPI_6_4_CXL_Early_Discovery_TABLE;
+
+///
+/// Node header definition shared by all structure types
+///
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16Length;
+} EFI_ACPI_6_4_CEDT_Structure;
+
+///
+/// Definition for CXL Host Bridge Structure
+///
+typedef struct {
+ EFI_ACPI_6_4_CEDT_Structureheader;
+ UINT32 UID;
+ UINT32 CXLVersion;
+ UINT32 Reserved;
+ UINT64 Base;
+ UINT64 Length;
+} EFI_ACPI_6_4_CXL_Host_Bridge_Structure;
+
+///
+/// Definition for CXL Fixed Memory Window Structure
+///
+typedef struct {
+ EFI_ACPI_6_4_CEDT_Structureheader;
+ UINT32 Reserved;
+ UINT64 BaseHPA;
+ UINT64 WindowSize;
+ UINT8 InterleaveMembers;
+ UINT8 InterleaveArithmetic;
+ UINT16 Reserved1;
+ UINT32 Granularity;
+ UINT16 Restrictions;
+ UINT16 QtgId;
+ UINT32 FirstTarget;
+} EFI_ACPI_6_4_CXL_Fixed_Memory_Window_Structure;
+
+#pragma pack()
+
+#endif
--
2.34.1
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[edk2-devel] [RFC PATCH 0/1] MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT
RFC because - Less experience and not particularly confident in edk2 area so this might be stupidly broken in a way I've not considered. I am trying to support cxl on Qemu sbsa-ref platform, but it relies on CXL ACPI elements within compiled UEFI flash instead of virt/i386 using qemu-build-Acpi tables. Thus I create the header file CXLEarlyDiscoveryTable.h as the fundamental format for CEDT building in edk2-platforms. Yuquan Wang (1): MdePkg/IndustryStandard: add definitions for ACPI 6.4 CEDT MdePkg/Include/IndustryStandard/Acpi64.h | 5 ++ .../IndustryStandard/CXLEarlyDiscoveryTable.h | 69 +++ 2 files changed, 74 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/CXLEarlyDiscoveryTable.h -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#120436): https://edk2.groups.io/g/devel/message/120436 Mute This Topic: https://groups.io/mt/108173029/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] Question about the boundary and difference between System Firmware and UEFI CXL drivers
On 2023-12-08 15:42, Yoshinoya wrote: There is a description about UEFI Drivers in 1.4 Abbreviations in this doc. UEFI Drivers : UEFI CXL Bus and memory device drivers. I think UEFI CXL Drivers is a part of System Firmware(UEFI BIOS). These UEFI Drivers may do some basic configuation for some direct attached clx type-3 devices. _._,_._ I found that description too, but in "Figure 34-High-level sequence: System Firmware boot" it shows that system firmware could enumerate CXL components and be followed with an optional UEFI Boot Sequence which also could enumerate CXL components (Figure 35). In my understanding, only UEFI CXL Bus and memory device drivers could enumerate CXL components, therefore, how system firmware could finish this responsibilty? Many thanks Yuquan -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112269): https://edk2.groups.io/g/devel/message/112269 Mute This Topic: https://groups.io/mt/103008846/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] Question about the boundary and difference between System Firmware and UEFI CXL drivers
Addition: [the link of CXL Memory Device SW Guide] https://cdrdv2-public.intel.com/643805/643805_CXL%20Memory%20Device%20SW%20Guide_Rev1p0.pdf -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112093): https://edk2.groups.io/g/devel/message/112093 Mute This Topic: https://groups.io/mt/103008846/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] Question about the boundary and difference between System Firmware and UEFI CXL drivers
Hi, folks CXL Memory Device SW Guide [1] rev1.0 2.4 provides little description about the difference between System Firmware and UEFI CXL drivers. IIRC, the UEFI drivers are part of system firmware, so I am confused about the boundary on them. I greatly appreciate insight/help in this regard! Many thanks Yuquan -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112092): https://edk2.groups.io/g/devel/message/112092 Mute This Topic: https://groups.io/mt/103008846/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH edk2-platforms v3 1/1] Platform/SbsaQemu: add XHCI support and replace EHCI
As sbsa-ref does not have DRAM below 4G, it cannot utilize EHCI
that only has 32-bit DMA capablity and sbsa-ref board uses xhci
to replace ehci.
This updates DSDT to match the platform xhci controller with two
usb ports changed from type A to type C.
This also registers the non-discoverable XHCI for sbsa-ref.
Signed-off-by: Yuquan Wang
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 4 +-
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +--
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 4 +-
.../SbsaQemuPlatformDxe.inf | 2 +
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 41 +++
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 15 +++
6 files changed, 49 insertions(+), 23 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index aab2894e6455..913d1d75ef29 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -32,8 +32,8 @@ [PcdsFixedAtBuild.common]
# Non discoverable devices Pcds
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase|0|UINT64|0x0001
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize|0x1|UINT32|0x0002
-
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0|UINT64|0x0003
-
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x1|UINT32|0x0004
+
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciBase|0|UINT64|0x0003
+
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciSize|0x1|UINT32|0x0004
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x100|UINT64|0x0005
# PCDs complementing PCIe layout pulled into ACPI tables
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index be406144c242..948e42326c33 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -429,11 +429,11 @@ [PcdsFixedAtBuild.common]
# Initial Device Tree Location
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x100
- # Non discoverable devices (AHCI,EHCI)
+ # Non discoverable devices (AHCI,XHCI)
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase|0x6010
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize|0x0001
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0x6011
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x0001
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciBase|0x6011
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciSize|0x0001
# PL011 - Serial Terminal
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x6000
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 97021f7971c7..abd10b6c3098 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -69,8 +69,8 @@ [FixedPcd]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciSize
[Pcd]
gArmTokenSpaceGuid.PcdGicDistributorBase
diff --git
a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
index 0e3b11d60426..19534b7a274a 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
@@ -37,6 +37,8 @@ [LibraryClasses]
[Pcd]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciSize
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformVersionMajor
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformVersionMinor
diff --git
a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
index ddcca2b7243c..4a04dbeb07ae 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
@@ -26,8 +26,9 @@ InitializeSbsaQemuPlatformDxe (
)
{
EFI_STATUS Status;
- UINTN Size;
- VOID* Base;
+ UINTN AhciSize, XhciSize;
+ VOID* AhciBase;
+ VOID* XhciBase;
UINTN Arg0;
UINTN Arg1;
UINTN
[edk2-devel] [PATCH edk2-platforms v3 0/1] Platform/SbsaQemu: use XHCI to replace EHCI
This patchset implements XHCI on sbsa-ref board to replace EHCI. As sbsa-ref does not have DRAM below 4G, it cannot utilize EHCI that only has 32-bit DMA capablity. Now this board has XHCI as an available usb controller with 64-bit DMA capablity. History: v2 -> v3: - remained the original USB hierarchy in DSDT - changed two usb ports from type A to type C - refactored patchset v1 -> v2: - rebased on master as v1 did not applied - moved pcd setting in dec file into the first commit Yuquan Wang (1): Platform/SbsaQemu: add XHCI support and replace EHCI Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 4 +- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +-- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 4 +- .../SbsaQemuPlatformDxe.inf | 2 + .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 41 +++ Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 15 +++ 6 files changed, 49 insertions(+), 23 deletions(-) -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108988): https://edk2.groups.io/g/devel/message/108988 Mute This Topic: https://groups.io/mt/101521162/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 0/3] use XHCI to replace EHCI
On 2023-09-05 14:30, marcin.juszkiewicz wrote: Project is meant to be buildable at every commit. Your patchset breaks that rule. Oh! I get it ! I did not consider this principle when designing these patches. Thanks for your explanation : ) I am going to recheck and combine some content together. Many thanks Yuquan -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108277): https://edk2.groups.io/g/devel/message/108277 Mute This Topic: https://groups.io/mt/101073211/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 0/3] use XHCI to replace EHCI
Hi, Leif On 2023-09-04 21:51, quic_llindhol wrote: > > However, this version still breaks bisect: attempting to build at 1/3 > or 2/3 leads to: > --- > /work/git/edk2-platforms/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf(72): > error 3000: PCD > [gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase] in > [/work/git/edk2-platforms/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf] > is not found in dependent packages: > --- Maybe it is a stupid question: What is the meaning of bisect in here? > > Also, I think Ard's comments on the ACPI changes still apply. > Do you have a comment on that? > Sorry, I' m honestly not knowledgable enough about the DSDT content so I just managed to use the "Device (XHCI)" node to support the xhci controller to work and remove the previous "Device (USB0)" node. If you have time to discuss it, I'm glad to continue to fix and improve my patches. And I will go on to improve myself and learn from experienced experts like yours. Many thanks Yuquan -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108274): https://edk2.groups.io/g/devel/message/108274 Mute This Topic: https://groups.io/mt/101073211/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH 0/3] use XHCI to replace EHCI
Hi, Leif On 2023-08-31 21:06, Leif wrote: I had to move one hunk (.dec change) from 2/3 to 1/3 in order to not break bisect. If you're happy with the slightly modified version, I think this is good to go in. Please let me know. It' ok. In the second version of this series patches, in fact, I have moved the .dec change into 1/3. It is my fault that I forgot to add "Cc" to Ard, Leif and Graeme in my latest version of "xhci" patches. The link is: https://edk2.groups.io/g/devel/message/106729 Many thanks Yuquan -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108252): https://edk2.groups.io/g/devel/message/108252 Mute This Topic: https://groups.io/mt/101073211/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH edk2-platforms v2 1/3] Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define XHCI Pcd settings
Define the pcd settings for identifying the base address of XHCI and XHCI's mmio size, and remove relevant EHCI settings. Signed-off-by: Yuquan Wang --- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 4 ++-- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec index 5182978cf56d..90776f1007dc 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -32,8 +32,8 @@ [PcdsFixedAtBuild.common] # Non discoverable devices Pcds gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase|0|UINT64|0x0001 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize|0x1|UINT32|0x0002 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0|UINT64|0x0003 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x1|UINT32|0x0004 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciBase|0|UINT64|0x0003 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciSize|0x1|UINT32|0x0004 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x100|UINT64|0x0005 # PCDs complementing PCIe layout pulled into ACPI tables diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc index b88729ad8ad6..dbb08756d10f 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -429,11 +429,11 @@ [PcdsFixedAtBuild.common] # Initial Device Tree Location gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x100 - # Non discoverable devices (AHCI,EHCI) + # Non discoverable devices (AHCI,XHCI) gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase|0x6010 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize|0x0001 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase|0x6011 - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x0001 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciBase|0x6011 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciSize|0x0001 # PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x6000 -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106729): https://edk2.groups.io/g/devel/message/106729 Mute This Topic: https://groups.io/mt/13412/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH edk2-platforms v2 3/3] SbsaQemu: AcpiTables: Add XHCI info into DSDT
As sbsa-ref board uses xhci to replace ehci, the DSDT is updated to match
the platform xhci controller. This also removes previous ehci structure.
Signed-off-by: Yuquan Wang
---
.../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 4 +-
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 125 ++
2 files changed, 15 insertions(+), 114 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 0501c670d565..89afbd9315ae 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -69,8 +69,8 @@ [FixedPcd]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciBase
- gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciSize
[Pcd]
gArmTokenSpaceGuid.PcdGicDistributorBase
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
index e50772fcf76d..cc8b99a8fb31 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -68,120 +68,21 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
}
}
-// USB EHCI Host Controller
-Device (USB0) {
-Name (_HID, "LNRO0D20")
-Name (_CID, "PNP0D20")
+// USB XHCI Host Controller
+Device (XHCI) {
+Name (_HID, "PNP0D10") // _HID: Hardware ID
+Name (_UID, 0x00)// _UID: Unique ID
+Name (_CCA, 0x01)// _CCA: Cache Coherency Attribute
+Name (_CRS, ResourceTemplate() {
+Memory32Fixed (ReadWrite,
+ FixedPcdGet32 (PcdPlatformXhciBase),
+ FixedPcdGet32 (PcdPlatformXhciSize))
+Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 }
+})
Method (_STA) {
- Return (0xF)
+Return (0xF)
}
-Method (_CRS, 0x0, Serialized) {
-Name (RBUF, ResourceTemplate() {
-Memory32Fixed (ReadWrite,
- FixedPcdGet32 (PcdPlatformEhciBase),
- FixedPcdGet32 (PcdPlatformEhciSize))
-Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {
43 }
-})
-Return (RBUF)
-}
-
-// Root Hub
-Device (RHUB) {
-Name (_ADR, 0x) // Address of Root Hub should be 0 as per
ACPI 5.0 spec
-Method (_STA) {
- Return (0xF)
-}
-
-// Ports connected to Root Hub
-Device (HUB1) {
-Name (_ADR, 0x0001)
-Name (_UPC, Package() {
-0x00, // Port is NOT connectable
-0xFF, // Don't care
-0x, // Reserved 0 must be zero
-0x // Reserved 1 must be zero
-})
-Method (_STA) {
- Return (0xF)
-}
-
-Device (PRT1) {
-Name (_ADR, 0x0001)
-Name (_UPC, Package() {
-0xFF,// Port is connectable
-0x00,// Port connector is A
-0x,
-0x
-})
-Name (_PLD, Package() {
-Buffer(0x10) {
-0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-}
-})
-Method (_STA) {
- Return (0xF)
-}
-} // USB0_RHUB_HUB1_PRT1
-Device (PRT2) {
-Name (_ADR, 0x0002)
-Name (_UPC, Package() {
-0xFF,// Port is connectable
-0x00,// Port connector is A
-0x,
-0x
-})
-Name (_PLD, Package() {
-Buffer(0x10) {
-0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-}
-})
-Method (_STA) {
- Return (0xF)
-}
-} // USB0_RHUB_HUB1_PRT2
-
-Device (PRT3) {
-Name (_ADR, 0x0003)
-Name (_UPC, Package() {
-
[edk2-devel] [PATCH edk2-platforms v2 2/3] SbsaQemu: Drivers: Add initial support for XHCI
This registers the non-discoverable XHCI for sbsa-ref.
Signed-off-by: Yuquan Wang
---
.../SbsaQemuPlatformDxe.inf | 2 +
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 41 +++
2 files changed, 34 insertions(+), 9 deletions(-)
diff --git
a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
index 545794a8c7ff..06700331efea 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
@@ -37,6 +37,8 @@ [LibraryClasses]
[Pcd]
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciBase
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformAhciSize
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciBase
+ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformXhciSize
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformVersionMajor
gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformVersionMinor
diff --git
a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
index f6a3e84483fe..969c25ae0e17 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c
@@ -26,22 +26,23 @@ InitializeSbsaQemuPlatformDxe (
)
{
EFI_STATUS Status;
- UINTN Size;
- VOID* Base;
UINTN Arg0;
UINTN Arg1;
UINTN SmcResult;
RETURN_STATUS Result;
+ UINTN AhciSize, XhciSize;
+ VOID* AhciBase;
+ VOID* XhciBase;
DEBUG ((DEBUG_INFO, "%a: InitializeSbsaQemuPlatformDxe called\n",
__FUNCTION__));
- Base = (VOID*)(UINTN)PcdGet64 (PcdPlatformAhciBase);
- ASSERT (Base != NULL);
- Size = (UINTN)PcdGet32 (PcdPlatformAhciSize);
- ASSERT (Size != 0);
+ AhciBase = (VOID*)(UINTN)PcdGet64 (PcdPlatformAhciBase);
+ ASSERT (AhciBase != NULL);
+ AhciSize = (UINTN)PcdGet32 (PcdPlatformAhciSize);
+ ASSERT (AhciSize != 0);
DEBUG ((DEBUG_INFO, "%a: Got platform AHCI %llx %u\n",
- __FUNCTION__, Base, Size));
+ __FUNCTION__, AhciBase, AhciSize));
Status = RegisterNonDiscoverableMmioDevice (
NonDiscoverableDeviceTypeAhci,
@@ -49,11 +50,33 @@ InitializeSbsaQemuPlatformDxe (
NULL,
NULL,
1,
- Base, Size);
+ AhciBase, AhciSize);
if (EFI_ERROR(Status)) {
DEBUG ((DEBUG_ERROR, "%a: NonDiscoverable: Cannot install AHCI device @%p
(Staus == %r)\n",
-__FUNCTION__, Base, Status));
+__FUNCTION__, AhciBase, Status));
+return Status;
+ }
+
+ XhciBase = (VOID*)(UINTN)PcdGet64 (PcdPlatformXhciBase);
+ ASSERT (XhciBase != NULL);
+ XhciSize = (UINTN)PcdGet32 (PcdPlatformXhciSize);
+ ASSERT (XhciSize != 0);
+
+ DEBUG ((DEBUG_INFO, "%a: Got platform XHCI %llx %u\n",
+ __FUNCTION__, XhciBase, XhciSize));
+
+ Status = RegisterNonDiscoverableMmioDevice (
+ NonDiscoverableDeviceTypeXhci,
+ NonDiscoverableDeviceDmaTypeCoherent,
+ NULL,
+ NULL,
+ 1,
+ XhciBase, XhciSize);
+
+ if (EFI_ERROR(Status)) {
+DEBUG ((DEBUG_ERROR, "%a: NonDiscoverable: Cannot install XHCI device @%p
(Staus == %r)\n",
+__FUNCTION__, XhciBase, Status));
return Status;
}
--
2.34.1
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[edk2-devel] [PATCH edk2-platforms v2 0/3] Platform/SbsaQemu: use XHCI to replace EHCI
This patchset implements XHCI on sbsa-ref board to replace EHCI. As sbsa-ref does not have DRAM below 4G, it cannot utilize EHCI that only has 32-bit DMA capablity. Now this board has XHCI as an available usb controller with 64-bit DMA capablity. History: v1 -> v2: - rebased on master as v1 did not applied - moved pcd setting in dec file into the first commit Yuquan Wang (3): Platform/Qemu/SbsaQemu/SbsaQemu.dsc: define XHCI Pcd settings SbsaQemu: Drivers: Add initial support for XHCI SbsaQemu: AcpiTables: Add XHCI info into DSDT Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 4 +- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +- .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 4 +- .../SbsaQemuPlatformDxe.inf | 2 + .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 41 -- Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 125 ++ 6 files changed, 54 insertions(+), 128 deletions(-) -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106727): https://edk2.groups.io/g/devel/message/106727 Mute This Topic: https://groups.io/mt/13410/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH edk2-platforms v2 3/3] Platform/SbsaQemu: handle systems without GIC ITS
Hi, Marcin On 2023-07-04 15:36, marcin.juszkiewicz wrote: The problem is with QEMU 8.0.0 (no GIC ITS) where I get some kernel complaints about interrupts. And this is what I am working on right now. https://github.com/hrw/fork-edk2-platforms/commits/submit/0628-its has my work-in-progress tree. Thanks for your patient explanation and sharing. Many thanks Yuquan -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106630): https://edk2.groups.io/g/devel/message/106630 Mute This Topic: https://groups.io/mt/99854681/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [PATCH edk2-platforms v2 3/3] Platform/SbsaQemu: handle systems without GIC ITS
Hi Marcin, Sorry to disturb you but I would like to consult you a little question about this patch because of my lack of engineering experience: Q: It seems like that the third patch will delete Iort.aslc file and moving the creation of IORT into SbsaQemuAcpiDxe driver, so the firmware can dynamically create a suitable MADT & IORT ? By the way, dose this means part of Shashi's code in the first patch (add GIC ITS support) will be covered/removed? Many thanks Yuquan -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#106626): https://edk2.groups.io/g/devel/message/106626 Mute This Topic: https://groups.io/mt/99854681/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
