[edk2-devel] [PATCH v3] UefiPayloadPkg: Fix issues when MULTIPLE_DEBUG_PORT_SUPPORT is true
From: PaytonX Hsieh
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4427
1. Since UART speed is slower than CPU, BIOS need to check the write
buffer is empty, to avoid overwrite the buffer content.
2. LPSS UART might disable MMIO space for Windows debug usage during
ExitBootServices event. BIOS need to avoid access the MMIO space
after ExitBootServices.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: PaytonX Hsieh
---
UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c | 15
+-
UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c | 56
UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.inf | 41
++
UefiPayloadPkg/UefiPayloadPkg.dsc | 11
+++-
4 files changed, 120 insertions(+), 3 deletions(-)
diff --git a/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
b/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
index 8216195c62..82d0dd5855 100644
--- a/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
+++ b/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
@@ -52,7 +52,8 @@ typedef struct {
} UART_INFO;
UART_INFO mUartInfo[MAX_SIZE];
-UINT8 mUartCount = 0;
+UINT8 mUartCount = 0;
+BOOLEANmBaseSerialPortLibHobAtRuntime = FALSE;
/**
Reads an 8-bit register. If UseMmio is TRUE, then the value is read from
@@ -285,6 +286,11 @@ SerialPortWrite (
UseMmio = mUartInfo[Count].UseMmio;
Stride = mUartInfo[Count].RegisterStride;
+if (UseMmio && mBaseSerialPortLibHobAtRuntime) {
+ Count++;
+ continue;
+}
+
if (BaseAddress == 0) {
Count++;
continue;
@@ -294,6 +300,13 @@ SerialPortWrite (
BytesLeft = NumberOfBytes;
while (BytesLeft != 0) {
+ //
+ // Wait for the serial port to be ready, to make sure both the transmit
FIFO
+ // and shift register empty.
+ //
+ while ((SerialPortReadRegister (BaseAddress, R_UART_LSR, UseMmio,
Stride) & B_UART_LSR_TXRDY) == 0) {
+ }
+
//
// Fill the entire Tx FIFO
//
diff --git
a/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
new file mode 100644
index 00..6106e9a933
--- /dev/null
+++ b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
@@ -0,0 +1,56 @@
+/** @file
+ UART Serial Port library functions.
+
+ Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include
+
+extern BOOLEAN mBaseSerialPortLibHobAtRuntime;
+
+/**
+ Set mSerialIoUartLibAtRuntime flag as TRUE after ExitBootServices.
+
+ @param[in] Event The Event that is being processed.
+ @param[in] Context The Event Context.
+
+**/
+STATIC
+VOID
+EFIAPI
+BaseSerialPortLibHobExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ mBaseSerialPortLibHobAtRuntime = TRUE;
+}
+
+/**
+ The constructor function registers a callback for the ExitBootServices event.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval other Either the serial port failed to initialize or the
+ExitBootServices event callback registration failed.
+**/
+EFI_STATUS
+EFIAPI
+DxeBaseSerialPortLibHobConstructor (
+ IN EFI_HANDLEImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_EVENT SerialPortLibHobExitBootServicesEvent;
+
+ return SystemTable->BootServices->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,
+ TPL_NOTIFY,
+
BaseSerialPortLibHobExitBootServicesEvent,
+ NULL,
+
+ );
+}
diff --git
a/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.inf
b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.inf
new file mode 100644
index 00..7bb3a6ae96
--- /dev/null
+++ b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.inf
@@ -0,0 +1,41 @@
+## @file
+# SerialPortLib instance for UART information retrieved from bootloader.
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 0x00010005
+ BASE_NAME = DxeBaseSerialPortLibHob
+ FILE_GUID = c8def0c5-48e7-45b8-8299-485ea2e63b2c
+ MODULE_TYPE= DXE_DRIVER
+ VERSION_STRING
[edk2-devel] [PATCH v2] UefiPayloadPkg: Fix issues when MULTIPLE_DEBUG_PORT_SUPPORT is true
From: PaytonX Hsieh
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4427
1. Since UART speed is slower than CPU, BIOS need to check the write
buffer is empty, to avoid overwrite the buffer content.
2. LPSS UART might disable MMIO space for Windows debug usage during
ExitBootServices event. BIOS need to avoid access the MMIO space
after ExitBootServices.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: PaytonX Hsieh
---
UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c | 13
+
UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c | 55
UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.inf | 41
+++
UefiPayloadPkg/UefiPayloadPkg.dsc | 11
+++-
4 files changed, 118 insertions(+), 2 deletions(-)
diff --git a/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
b/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
index 8216195c62..88981a0863 100644
--- a/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
+++ b/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
@@ -53,6 +53,7 @@ typedef struct {
UART_INFO mUartInfo[MAX_SIZE];
UINT8 mUartCount = 0;
+BOOLEANmBaseSerialPortLibHobAtRuntime = FALSE;
/**
Reads an 8-bit register. If UseMmio is TRUE, then the value is read from
@@ -285,6 +286,11 @@ SerialPortWrite (
UseMmio = mUartInfo[Count].UseMmio;
Stride = mUartInfo[Count].RegisterStride;
+if (UseMmio && mBaseSerialPortLibHobAtRuntime) {
+ Count++;
+ continue;
+}
+
if (BaseAddress == 0) {
Count++;
continue;
@@ -294,6 +300,13 @@ SerialPortWrite (
BytesLeft = NumberOfBytes;
while (BytesLeft != 0) {
+ //
+ // Wait for the serial port to be ready, to make sure both the transmit
FIFO
+ // and shift register empty.
+ //
+ while ((SerialPortReadRegister (BaseAddress, R_UART_LSR, UseMmio,
Stride) & B_UART_LSR_TXRDY) == 0) {
+ }
+
//
// Fill the entire Tx FIFO
//
diff --git
a/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
new file mode 100644
index 00..dbbc02dcee
--- /dev/null
+++ b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
@@ -0,0 +1,55 @@
+/** @file
+ UART Serial Port library functions.
+
+ Copyright (c) 2023, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include
+
+extern BOOLEANmBaseSerialPortLibHobAtRuntime;
+
+/**
+ Set mSerialIoUartLibAtRuntime flag as TRUE after ExitBootServices.
+
+ @param[in] Event The Event that is being processed.
+ @param[in] Context The Event Context.
+
+**/
+STATIC
+VOID
+EFIAPI
+BaseSerialPortLibHobExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ mBaseSerialPortLibHobAtRuntime = TRUE;
+}
+
+/**
+ The constructor function registers a callback for the ExitBootServices event.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval other Either the serial port failed to initialize or the
+ExitBootServices event callback registration failed.
+**/
+EFI_STATUS
+EFIAPI
+DxeBaseSerialPortLibHobConstructor (
+ IN EFI_HANDLEImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_EVENT SerialPortLibHobExitBootServicesEvent;
+ return SystemTable->BootServices->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,
+ TPL_NOTIFY,
+
BaseSerialPortLibHobExitBootServicesEvent,
+ NULL,
+
+ );
+}
diff --git
a/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.inf
b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.inf
new file mode 100644
index 00..7bb3a6ae96
--- /dev/null
+++ b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.inf
@@ -0,0 +1,41 @@
+## @file
+# SerialPortLib instance for UART information retrieved from bootloader.
+#
+# Copyright (c) 2023, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 0x00010005
+ BASE_NAME = DxeBaseSerialPortLibHob
+ FILE_GUID = c8def0c5-48e7-45b8-8299-485ea2e63b2c
+ MODULE_TYPE= DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib|D
[edk2-devel] [PATCH] UefiPayloadPkg: Fix issues when MULTIPLE_DEBUG_PORT_SUPPORT is true
From: PaytonX Hsieh
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4427
1. Since UART speed is slower than CPU, BIOS need to check the write
buffer is empty, to avoid overwrite the buffer content.
2. LPSS UART might disable MMIO space for Windows debug usage during
ExitBootServices event. BIOS need to avoid access the MMIO space
after ExitBootServices.
Cc: Guo Dong
Cc: Ray Ni
Cc: Sean Rhodes
Cc: James Lu
Cc: Gua Guo
Signed-off-by: PaytonX Hsieh
---
.../BaseSerialPortLibHob.c| 7 +
.../DxeBaseSerialPortLibHob.c | 903 ++
.../DxeBaseSerialPortLibHob.inf | 40 +
UefiPayloadPkg/UefiPayloadPkg.dsc | 11 +-
4 files changed, 959 insertions(+), 2 deletions(-)
create mode 100644
UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
create mode 100644
UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.inf
diff --git a/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
b/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
index 8216195c62..3f844a42e1 100644
--- a/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
+++ b/UefiPayloadPkg/Library/BaseSerialPortLibHob/BaseSerialPortLibHob.c
@@ -294,6 +294,13 @@ SerialPortWrite (
BytesLeft = NumberOfBytes;
while (BytesLeft != 0) {
+ //
+ // Wait for the serial port to be ready, to make sure both the transmit
FIFO
+ // and shift register empty.
+ //
+ while ((SerialPortReadRegister (BaseAddress, R_UART_LSR, UseMmio,
Stride) & B_UART_LSR_TXRDY) == 0) {
+ }
+
//
// Fill the entire Tx FIFO
//
diff --git
a/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
new file mode 100644
index 00..5fcae9a699
--- /dev/null
+++ b/UefiPayloadPkg/Library/BaseSerialPortLibHob/DxeBaseSerialPortLibHob.c
@@ -0,0 +1,903 @@
+/** @file
+ UART Serial Port library functions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF 0// LCR_DLAB = 0
+#define R_UART_TXBUF 0// LCR_DLAB = 0
+#define R_UART_BAUD_LOW 0// LCR_DLAB = 1
+#define R_UART_BAUD_HIGH 1// LCR_DLAB = 1
+#define R_UART_IER 1// LCR_DLAB = 0
+#define R_UART_FCR 2
+#define B_UART_FCR_FIFOE BIT0
+#define B_UART_FCR_FIFO64 BIT5
+#define R_UART_LCR 3
+#define B_UART_LCR_DLABBIT7
+#define R_UART_MCR 4
+#define B_UART_MCR_DTRCBIT0
+#define B_UART_MCR_RTS BIT1
+#define R_UART_LSR 5
+#define B_UART_LSR_RXRDY BIT0
+#define B_UART_LSR_TXRDY BIT5
+#define B_UART_LSR_TEMTBIT6
+#define R_UART_MSR 6
+#define B_UART_MSR_CTS BIT4
+#define B_UART_MSR_DSR BIT5
+#define B_UART_MSR_RI BIT6
+#define B_UART_MSR_DCD BIT7
+
+#define MAX_SIZE 16
+
+typedef struct {
+ UINTN BaseAddress;
+ BOOLEANUseMmio;
+ UINT32 BaudRate;
+ UINT8 RegisterStride;
+} UART_INFO;
+
+UART_INFO mUartInfo[MAX_SIZE];
+UINT8 mUartCount = 0;
+EFI_EVENT mBaseSerialPortLibHobExitBootServicesEvent;
+BOOLEANmBaseSerialPortLibHobAtRuntime = FALSE;
+
+/**
+ Reads an 8-bit register. If UseMmio is TRUE, then the value is read from
+ MMIO space. If UseMmio is FALSE, then the value is read from I/O space. The
+ parameter Offset is added to the base address of the register.
+
+ @param Base The base address register of UART device.
+ @param Offset The offset of the register to read.
+ @param UseMmio Check if value has to be read from MMIO space or IO
space.
+ @param RegisterStride Number of bytes between registers in serial device.
+
+ @return The value read from the register.
+
+**/
+UINT8
+SerialPortReadRegister (
+ UINTNBase,
+ UINTNOffset,
+ BOOLEAN UseMmio,
+ UINT8RegisterStride
+ )
+{
+ if (UseMmio) {
+return MmioRead8 (Base + Offset * RegisterStride);
+ } else {
+return IoRead8 (Base + Offset * RegisterStride);
+ }
+}
+
+/**
+ Writes an 8-bit register.. If UseMmio is TRUE, then the value is written to
+ MMIO space. If UseMmio is FALSE, then the value is written to I/O space. The
+ parameter Offset is added to the base address of the registers.
+
+ @param Base The base address register of UART device.
+ @param Offset The offset of the register to write.
+ @param ValueValue to be written.
+ @param UseMmio Check if value has to be written to MMIO space or
IO space.
+ @param RegisterStride Number of bytes between registers in serial device.
+
+ @re
[edk2-devel] [PATCH] UefiPayloadPkg: Add macro to support selection of CryptoDxe driver
From: PaytonX Hsieh
REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4006
Add CRYPTO_PROTOCOL_SUPPORT to decide CryptoDxe built into UPL.efi
If CRYPTO_PROTOCOL_SUPPORT is true, BIOS will use crypto protocol
instead of building OpensslLib into drivers.
Cc: Guo Dong
Cc: Ray Ni
Cc: James Lu
Cc: Gua Guo
Signed-off-by: PaytonX Hsieh
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 10 ++
UefiPayloadPkg/UefiPayloadPkg.fdf | 2 ++
2 files changed, 12 insertions(+)
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 5e947526b7..862d440b16 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -39,6 +39,7 @@
DEFINE ATA_ENABLE = TRUE
DEFINE SD_ENABLE= TRUE
DEFINE PS2_MOUSE_ENABLE = TRUE
+ DEFINE CRYPTO_PROTOCOL_SUPPORT = FALSE
DEFINE SD_MMC_TIMEOUT = 100
#
@@ -189,8 +190,13 @@
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
DxeHobListLib|UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf
+!if $(CRYPTO_PROTOCOL_SUPPORT) == TRUE
BaseCryptLib|CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
TlsLib|CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
+!else
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+ TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf
+!endif
IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf
@@ -421,6 +427,7 @@
gUefiPayloadPkgTokenSpaceGuid.PcdBootManagerEscape|$(BOOT_MANAGER_ESCAPE)
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|180
+!if $(CRYPTO_PROTOCOL_SUPPORT) == TRUE
gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.HmacSha256.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Md5.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Pkcs.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
@@ -443,6 +450,7 @@
gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Tls.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.TlsSet.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.TlsGet.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+!endif
[PcdsPatchableInModule.X64]
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|$(RTC_INDEX_REGISTER)
@@ -764,11 +772,13 @@
#
# Misc
#
+!if $(CRYPTO_PROTOCOL_SUPPORT) == TRUE
CryptoPkg/Driver/CryptoDxe.inf {
BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf
}
+!endif
#--
# Build the shell
diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf
b/UefiPayloadPkg/UefiPayloadPkg.fdf
index 5c055e61b3..afdd6447a7 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
@@ -99,7 +99,9 @@ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
INF
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+!if $(CRYPTO_PROTOCOL_SUPPORT) == TRUE
INF CryptoPkg/Driver/CryptoDxe.inf
+!endif
!if $(SECURITY_STUB_ENABLE) == TRUE
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
!endif
--
2.28.0.windows.1
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[edk2-devel] [PATCH v2] UefiPayloadPkg: Add CryptoDxe driver to UefiPayload
From: PaytonX Hsieh
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3979
Add CryptoDxe into UPL.
Drviers can locate protocol instead of building openssl lib into drivers.
This can reduce the binary size that UPL required.
Cc: Guo Dong
Cc: Ray Ni
Cc: James Lu
Cc: Gua Guo
Signed-off-by: PaytonX Hsieh
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 36 ++--
UefiPayloadPkg/UefiPayloadPkg.fdf | 1 +
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc
b/UefiPayloadPkg/UefiPayloadPkg.dsc
index cfcf38578d..2428bb2ce9 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -180,8 +180,8 @@
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
DxeHobListLib|UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf
- BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
- TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
+ TlsLib|CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf
@@ -412,6 +412,29 @@
gUefiPayloadPkgTokenSpaceGuid.PcdBootManagerEscape|$(BOOT_MANAGER_ESCAPE)
gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|180
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.HmacSha256.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Md5.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Pkcs.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Dh.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Random.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Rsa.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sha1.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sha256.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sha384.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sha512.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.X509.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Tdes.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+
gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Aes.Services.GetContextSize
| TRUE
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Aes.Services.Init
| TRUE
+
gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Aes.Services.CbcEncrypt
| TRUE
+
gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Aes.Services.CbcDecrypt
| TRUE
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Arc4.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sm3.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Hkdf.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Tls.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.TlsSet.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+ gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.TlsGet.Family
| PCD_CRYPTO_SERVICE_ENABLE_FAMILY
+
[PcdsPatchableInModule.X64]
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|$(RTC_INDEX_REGISTER)
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|$(RTC_TARGET_REGISTER)
@@ -719,6 +742,15 @@
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
!endif
+ #
+ # Misc
+ #
+ CryptoPkg/Driver/CryptoDxe.inf {
+
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+ TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf
+ }
+
#--
# Build the shell
#--
diff --git
[edk2-devel] [PATCH] UefiPayloadPkg: Add CryptoDxe driver to UefiPayload
From: PaytonX Hsieh REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3979 Add macro CRYPTO_ENABLE to decide to build CryptoDxe into UPL. Drviers can locate protocol instead of building openssl lib into drivers. This can reduce the binary size that UPL required. Cc: Guo Dong Cc: Ray Ni Cc: James Lu Cc: Gua Guo Signed-off-by: PaytonX Hsieh --- UefiPayloadPkg/UefiPayloadPkg.dsc | 42 +++ UefiPayloadPkg/UefiPayloadPkg.fdf | 3 +++ 2 files changed, 45 insertions(+) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc index cfcf38578d..782635431b 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -36,6 +36,7 @@ DEFINE PLATFORM_BOOT_TIMEOUT= 3 DEFINE ABOVE_4G_MEMORY = TRUE DEFINE BOOT_MANAGER_ESCAPE = FALSE + DEFINE CRYPTO_ENABLE= FALSE DEFINE SD_MMC_TIMEOUT = 100 # # SBL: UEFI payload for Slim Bootloader @@ -180,8 +181,13 @@ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf DxeHobListLib|UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.inf +!if $(CRYPTO_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf + TlsLib|CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf +!else BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf +!endif IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf @@ -412,6 +418,31 @@ gUefiPayloadPkgTokenSpaceGuid.PcdBootManagerEscape|$(BOOT_MANAGER_ESCAPE) gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|180 +!if $(CRYPTO_ENABLE) == TRUE + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.HmacSha256.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Md5.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Pkcs.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Dh.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Random.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Rsa.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sha1.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sha256.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sha384.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sha512.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.X509.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Tdes.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Aes.Services.GetContextSize | TRUE + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Aes.Services.Init | TRUE + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Aes.Services.CbcEncrypt | TRUE + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Aes.Services.CbcDecrypt | TRUE + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Arc4.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Sm3.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Hkdf.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.Tls.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.TlsSet.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY + gEfiCryptoPkgTokenSpaceGuid.PcdCryptoServiceFamilyEnable.TlsGet.Family | PCD_CRYPTO_SERVICE_ENABLE_FAMILY +!endif + [PcdsPatchableInModule.X64] gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|$(RTC_INDEX_REGISTER
