Re: [edk2-devel] [PATCH] Revert "FmpDevicePkg: Fix various typos"
Revert patch submitted: efa12a3f029bd6ff4d2ada406c285f001b252907 Reapply patch submitted: 91cc60bafc7d6e49b7bc85990f895d6228f51364 Thanks! Chasel > -Original Message- > From: Antoine Cœur [mailto:co...@gmx.fr] > Sent: Thursday, July 11, 2019 5:37 PM > To: devel@edk2.groups.io > Cc: Antoine Cœur ; Zeng, Star ; Chiu, > Chasel > Subject: [PATCH] Revert "FmpDevicePkg: Fix various typos" > > This reverts commit f527942e6bdd9f198db90f2de99a0482e9be5b1b. > Commit message was incorrect. > > Signed-off-by: Coeur > --- > .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +-- > .../FspSecCore/Ia32/InitializeFpu.nasm| 4 +-- > .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 4 +-- > IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 4 +-- > IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 +-- > IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +- > .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 4 +-- > IntelFsp2Pkg/Include/FspEas/FspApi.h | 8 ++--- > .../Include/Library/FspSecPlatformLib.h | 4 +-- > IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 12 +++ > .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +-- > .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 4 +-- > .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 4 +-- > .../PlatformSecLibNull.c | 4 +-- > IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +- > IntelFsp2Pkg/Tools/PatchFv.py | 2 +- > .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +- > .../Tools/UserManuals/PatchFvUserManual.md| 2 +- > 18 files changed, 52 insertions(+), 52 deletions(-) > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > index e7261b41cd..f14c18c7b9 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > @@ -194,9 +194,9 @@ StackSetupDone: > >; >; Pass BFV into the PEI Core > - ; It uses relative address to calculate the actual boot FV base > + ; It uses relative address to calucate the actual boot FV base >; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase > and > - ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, > + ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, >; they are different. The code below can handle both cases. >; >callASM_PFX(AsmGetFspBaseAddress) > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > index ebc91c41e4..e1886ea11b 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > @@ -1,6 +1,6 @@ > > ;-- > ; > -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. > +; Copyright (c) 2015, Intel Corporation. All rights reserved. > ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: > @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): > fldcw[ASM_PFX(mFpuControlWord)] > > ; > -; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test > +; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > index 4c321cbece..b257deb76c 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > @@ -1,6 +1,6 @@ > > ;-- > ; > -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. > +; Copyright (c) 2015, Intel Corporation. All rights reserved. > ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: > @@ -150,7 +150,7 @@ NextAddress: > fldcw [FpuControlWord] > > ; > -; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test > +; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to > + test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > index 5a7e27c240..d72212ed45 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > @@ -1,6 +1,6 @@ > > ;-- > ; > -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. > +; Copyright (c) 2015, Intel Corporation. All rights reserved. > ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: > @@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): > mov esp, eax ; From now,
[edk2-devel] [PATCH] Revert "FmpDevicePkg: Fix various typos"
This reverts commit f527942e6bdd9f198db90f2de99a0482e9be5b1b. Commit message was incorrect. Signed-off-by: Coeur --- .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +-- .../FspSecCore/Ia32/InitializeFpu.nasm| 4 +-- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc| 4 +-- IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 4 +-- IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 +-- IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +- .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 4 +-- IntelFsp2Pkg/Include/FspEas/FspApi.h | 8 ++--- .../Include/Library/FspSecPlatformLib.h | 4 +-- IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 12 +++ .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +-- .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 4 +-- .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 4 +-- .../PlatformSecLibNull.c | 4 +-- IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +- IntelFsp2Pkg/Tools/PatchFv.py | 2 +- .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +- .../Tools/UserManuals/PatchFvUserManual.md| 2 +- 18 files changed, 52 insertions(+), 52 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm index e7261b41cd..f14c18c7b9 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -194,9 +194,9 @@ StackSetupDone: ; ; Pass BFV into the PEI Core - ; It uses relative address to calculate the actual boot FV base + ; It uses relative address to calucate the actual boot FV base ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and - ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, + ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, ; they are different. The code below can handle both cases. ; callASM_PFX(AsmGetFspBaseAddress) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm index ebc91c41e4..e1886ea11b 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm @@ -1,6 +1,6 @@ ;-- ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. +; Copyright (c) 2015, Intel Corporation. All rights reserved. ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): fldcw[ASM_PFX(mFpuControlWord)] ; -; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test +; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test ; whether the processor supports SSE instruction. ; mov eax, 1 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 4c321cbece..b257deb76c 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -1,6 +1,6 @@ ;-- ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. +; Copyright (c) 2015, Intel Corporation. All rights reserved. ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -150,7 +150,7 @@ NextAddress: fldcw [FpuControlWord] ; -; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test +; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test ; whether the processor supports SSE instruction. ; mov eax, 1 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm index 5a7e27c240..d72212ed45 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -1,6 +1,6 @@ ;-- ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. +; Copyright (c) 2015, Intel Corporation. All rights reserved. ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): mov esp, eax ; From now, esp is pointed to permanent memory ; -; Fixup the ebp point to permanent memory +; Fixup the ebp point to permenent memory ; mov eax, ebp sub eax, ebx diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c index 446d1730e9..6497c88ebe 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved. + Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@
Re: [edk2-devel] [PATCH] Revert "FmpDevicePkg: Fix various typos" + Reapply as "IntelFsp2Pkg: Fix various typos"
Coeur: Please use git send-email to send those patches. And, Signed-off-by: Cœur <mailto:co...@gmx.fr>. Can you change it Signed-off-by: Coeur <mailto:co...@gmx.fr> with Ascii char only? Thanks Liming From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of C?ur Sent: Thursday, July 11, 2019 5:01 PM To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH] Revert "FmpDevicePkg: Fix various typos" + Reapply as "IntelFsp2Pkg: Fix various typos" Two patches attached: 1. revert f527942e6bdd9f198db90f2de99a0482e9be5b1b, because the commit message was incorrect. 2. reapply it with a correct commit message. If you apply both patches, the balance of changes should be zero (except for the commit messages). Sorry for the confusion. Coeur -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#43590): https://edk2.groups.io/g/devel/message/43590 Mute This Topic: https://groups.io/mt/32428310/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] Revert "FmpDevicePkg: Fix various typos" + Reapply as "IntelFsp2Pkg: Fix various typos"
Two patches attached: 1. revert f527942e6bdd9f198db90f2de99a0482e9be5b1b, because the commit message was incorrect. 2. reapply it with a correct commit message. If you apply both patches, the balance of changes should be zero (except for the commit messages). Sorry for the confusion. Coeur -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#43588): https://edk2.groups.io/g/devel/message/43588 Mute This Topic: https://groups.io/mt/32428310/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=- patch1.diff Description: Binary data patch2.diff Description: Binary data
