Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Looks good to me.
Reviewed-by: Andrei Warkentin
From: Tuan Phan
Sent: Wednesday, October 4, 2023 1:44 PM
To: devel@edk2.groups.io; Warkentin, Andrei
Cc: Kinney, Michael D ; Gao, Liming
; Liu, Zhiguang ;
suni...@ventanamicro.com; g...@danielschaefer.me; ardb+tianoc...@kernel.org
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for
SATP mode
https://github.com/pttuan/edk2.git
branch: tphan/riscv_mmu_new_pcd
From: devel@edk2.groups.io<mailto:devel@edk2.groups.io>
mailto:devel@edk2.groups.io>> on behalf of Andrei
Warkentin mailto:andrei.warken...@intel.com>>
Date: Wednesday, October 4, 2023 at 11:42 AM
To: Tuan Phan mailto:tp...@ventanamicro.com>>,
devel@edk2.groups.io<mailto:devel@edk2.groups.io>
mailto:devel@edk2.groups.io>>
Cc: Kinney, Michael D
mailto:michael.d.kin...@intel.com>>, Gao, Liming
mailto:gaolim...@byosoft.com.cn>>, Liu, Zhiguang
mailto:zhiguang@intel.com>>,
suni...@ventanamicro.com<mailto:suni...@ventanamicro.com>
mailto:suni...@ventanamicro.com>>,
g...@danielschaefer.me<mailto:g...@danielschaefer.me>
mailto:g...@danielschaefer.me>>,
ardb+tianoc...@kernel.org<mailto:ardb+tianoc...@kernel.org>
mailto:ardb+tianoc...@kernel.org>>
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for
SATP mode
Do you happen to have a link to a Github tree?
A
> -Original Message-
> From: Tuan Phan mailto:tp...@ventanamicro.com>>
> Sent: Tuesday, October 3, 2023 4:00 PM
> To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>
> Cc: Kinney, Michael D
> mailto:michael.d.kin...@intel.com>>; Gao, Liming
> mailto:gaolim...@byosoft.com.cn>>; Liu, Zhiguang
> mailto:zhiguang@intel.com>>;
> suni...@ventanamicro.com<mailto:suni...@ventanamicro.com>;
> g...@danielschaefer.me<mailto:g...@danielschaefer.me>; Warkentin, Andrei
> mailto:andrei.warken...@intel.com>>;
> ardb+tianoc...@kernel.org<mailto:ardb+tianoc...@kernel.org>; Tuan Phan
> mailto:tp...@ventanamicro.com>>
> Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
>
> Introduce a PCD to control the maximum SATP mode that MMU allowed to
> use. This PCD helps RISC-V platform set bare or minimum SATA mode during
> bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan
> mailto:tp...@ventanamicro.com>>
> ---
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
> UefiCpuPkg/UefiCpuPkg.dec | 8
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
> #define PTE_PPN_SHIFT 10 #define RISCV_MMU_PAGE_SHIFT 12 -
> STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57,
> SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN
> mMaxRootTableLevel; STATIC UINTN mBitPerLevel; STATIC UINTN
> mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
>UINTNIndex; EFI_STATUS
> Status; + if
> (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+return
> EFI_DEVICE_ERROR;+ }+ switch (SatpMode) { case SATP_MODE_OFF:
> return EFI_SUCCESS;diff --git
> a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
> [LibraryClasses] BaseLib++[Pcd]+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ##
> CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec
> b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..79191af18a05 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
># @Prompt Access to non-SMRAM memory is restricted to reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B
> OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+ ## Indicate the
> maximum SATP mode allowed.+ # 0 - Bare mode.+ # 8 - 39bit mode.+ # 9 -
> 48bit mode.+ # 10 - 57bit mode.+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6
> 021+ [PcdsDynamic, PcdsDynamicEx] ## Contai
Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
https://github.com/pttuan/edk2.git
branch: tphan/riscv_mmu_new_pcd
From: devel@edk2.groups.io on behalf of Andrei Warkentin
Date: Wednesday, October 4, 2023 at 11:42 AM
To: Tuan Phan , devel@edk2.groups.io
Cc: Kinney, Michael D , Gao, Liming
, Liu, Zhiguang ,
suni...@ventanamicro.com , g...@danielschaefer.me
, ardb+tianoc...@kernel.org
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for
SATP mode
Do you happen to have a link to a Github tree?
A
> -Original Message-
> From: Tuan Phan
> Sent: Tuesday, October 3, 2023 4:00 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ;
> suni...@ventanamicro.com; g...@danielschaefer.me; Warkentin, Andrei
> ; ardb+tianoc...@kernel.org; Tuan Phan
>
> Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
>
> Introduce a PCD to control the maximum SATP mode that MMU allowed to
> use. This PCD helps RISC-V platform set bare or minimum SATA mode during
> bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan
> ---
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
> UefiCpuPkg/UefiCpuPkg.dec | 8
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
> #define PTE_PPN_SHIFT 10 #define RISCV_MMU_PAGE_SHIFT 12 -
> STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57,
> SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN
> mMaxRootTableLevel; STATIC UINTN mBitPerLevel; STATIC UINTN
> mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
>UINTNIndex; EFI_STATUS
> Status; + if
> (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+return
> EFI_DEVICE_ERROR;+ }+ switch (SatpMode) { case SATP_MODE_OFF:
> return EFI_SUCCESS;diff --git
> a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
> [LibraryClasses] BaseLib++[Pcd]+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ##
> CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec
> b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..79191af18a05 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
># @Prompt Access to non-SMRAM memory is restricted to reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B
> OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+ ## Indicate the
> maximum SATP mode allowed.+ # 0 - Bare mode.+ # 8 - 39bit mode.+ # 9 -
> 48bit mode.+ # 10 - 57bit mode.+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6
> 021+ [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU
> S3 data buffer of structure ACPI_CPU_DATA. # @Prompt The pointer to a CPU
> S3 data buffer.--
> 2.25.1
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Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Do you happen to have a link to a Github tree?
A
> -Original Message-
> From: Tuan Phan
> Sent: Tuesday, October 3, 2023 4:00 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
> ; Liu, Zhiguang ;
> suni...@ventanamicro.com; g...@danielschaefer.me; Warkentin, Andrei
> ; ardb+tianoc...@kernel.org; Tuan Phan
>
> Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
>
> Introduce a PCD to control the maximum SATP mode that MMU allowed to
> use. This PCD helps RISC-V platform set bare or minimum SATA mode during
> bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan
> ---
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
> UefiCpuPkg/UefiCpuPkg.dec | 8
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
> #define PTE_PPN_SHIFT 10 #define RISCV_MMU_PAGE_SHIFT 12 -
> STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57,
> SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN
> mMaxRootTableLevel; STATIC UINTN mBitPerLevel; STATIC UINTN
> mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
>UINTNIndex; EFI_STATUS
> Status; + if
> (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+return
> EFI_DEVICE_ERROR;+ }+ switch (SatpMode) { case SATP_MODE_OFF:
> return EFI_SUCCESS;diff --git
> a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
> [LibraryClasses] BaseLib++[Pcd]+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ##
> CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec
> b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..79191af18a05 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
># @Prompt Access to non-SMRAM memory is restricted to reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B
> OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+ ## Indicate the
> maximum SATP mode allowed.+ # 0 - Bare mode.+ # 8 - 39bit mode.+ # 9 -
> 48bit mode.+ # 10 - 57bit mode.+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6
> 021+ [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU
> S3 data buffer of structure ACPI_CPU_DATA. # @Prompt The pointer to a CPU
> S3 data buffer.--
> 2.25.1
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Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
If we agree that default should be 10 then i will change it in the next
version.
On Wed, Oct 4, 2023 at 4:36 AM Sunil V L wrote:
> Hi Tuan,
>
> Thanks for the patch!. Adding UefiCpuPkg maintainers.
>
> On Tue, Oct 03, 2023 at 02:00:21PM -0700, Tuan Phan wrote:
> > Introduce a PCD to control the maximum SATP mode that MMU allowed
> > to use. This PCD helps RISC-V platform set bare or minimum SATA mode
>
> SATA -> SATP
>
> > during bring up to debug memory map issue.
> >
> > Signed-off-by: Tuan Phan
> > ---
> > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
> > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
> > UefiCpuPkg/UefiCpuPkg.dec | 8
> > 3 files changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > index 9cca5fc128af..826a1d32a1d4 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> > @@ -36,7 +36,7 @@
> > #define PTE_PPN_SHIFT 10
> > #define RISCV_MMU_PAGE_SHIFT 12
> >
> > -STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };
> > +STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39, SATP_MODE_OFF };
> > STATIC UINTN mMaxRootTableLevel;
> > STATIC UINTN mBitPerLevel;
> > STATIC UINTN mTableEntryCount;
> > @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
> >UINTNIndex;
> >EFI_STATUS Status;
> >
> > + if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
> > +return EFI_DEVICE_ERROR;
> > + }
> > +
> >switch (SatpMode) {
> > case SATP_MODE_OFF:
> >return EFI_SUCCESS;
> > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > index 9b28a98cb346..51ebe1750e97 100644
> > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > @@ -25,3 +25,6 @@
> >
> > [LibraryClasses]
> >BaseLib
> > +
> > +[Pcd]
> > + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES
> > diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> > index 68473fc640e6..79191af18a05 100644
> > --- a/UefiCpuPkg/UefiCpuPkg.dec
> > +++ b/UefiCpuPkg/UefiCpuPkg.dec
> > @@ -396,6 +396,14 @@
> ># @Prompt Access to non-SMRAM memory is restricted to reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> >
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
> >
> > +[PcdsFixedAtBuild.RISCV64]
> > + ## Indicate the maximum SATP mode allowed.
> > + # 0 - Bare mode.
> > + # 8 - 39bit mode.
> > + # 9 - 48bit mode.
> > + # 10 - 57bit mode.
> > +
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6021
> > +
> Shouldn't the default value be 10?
>
> Thanks,
> Sunil
>
> > [PcdsDynamic, PcdsDynamicEx]
> >## Contains the pointer to a CPU S3 data buffer of structure
> ACPI_CPU_DATA.
> ># @Prompt The pointer to a CPU S3 data buffer.
> > --
> > 2.25.1
> >
>
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Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Hi Tuan,
Thanks for the patch!. Adding UefiCpuPkg maintainers.
On Tue, Oct 03, 2023 at 02:00:21PM -0700, Tuan Phan wrote:
> Introduce a PCD to control the maximum SATP mode that MMU allowed
> to use. This PCD helps RISC-V platform set bare or minimum SATA mode
SATA -> SATP
> during bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan
> ---
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
> UefiCpuPkg/UefiCpuPkg.dec | 8
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
> #define PTE_PPN_SHIFT 10
> #define RISCV_MMU_PAGE_SHIFT 12
>
> -STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };
> +STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39, SATP_MODE_OFF };
> STATIC UINTN mMaxRootTableLevel;
> STATIC UINTN mBitPerLevel;
> STATIC UINTN mTableEntryCount;
> @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
>UINTNIndex;
>EFI_STATUS Status;
>
> + if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
> +return EFI_DEVICE_ERROR;
> + }
> +
>switch (SatpMode) {
> case SATP_MODE_OFF:
>return EFI_SUCCESS;
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
>
> [LibraryClasses]
>BaseLib
> +
> +[Pcd]
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES
> diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..79191af18a05 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
># @Prompt Access to non-SMRAM memory is restricted to reserved, runtime
> and ACPI NVS type after SmmReadyToLock.
>
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
>
> +[PcdsFixedAtBuild.RISCV64]
> + ## Indicate the maximum SATP mode allowed.
> + # 0 - Bare mode.
> + # 8 - 39bit mode.
> + # 9 - 48bit mode.
> + # 10 - 57bit mode.
> + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6021
> +
Shouldn't the default value be 10?
Thanks,
Sunil
> [PcdsDynamic, PcdsDynamicEx]
>## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
># @Prompt The pointer to a CPU S3 data buffer.
> --
> 2.25.1
>
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Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Reviewed-by: Dhaval Sharma -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109306): https://edk2.groups.io/g/devel/message/109306 Mute This Topic: https://groups.io/mt/101742937/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATA mode
during bring up to debug memory map issue.
Signed-off-by: Tuan Phan
---
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +-
UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
UefiCpuPkg/UefiCpuPkg.dec | 8
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 9cca5fc128af..826a1d32a1d4 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -36,7 +36,7 @@
#define PTE_PPN_SHIFT 10
#define RISCV_MMU_PAGE_SHIFT 12
-STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
SATP_MODE_SV39 };
+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
SATP_MODE_SV39, SATP_MODE_OFF };
STATIC UINTN mMaxRootTableLevel;
STATIC UINTN mBitPerLevel;
STATIC UINTN mTableEntryCount;
@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
UINTNIndex;
EFI_STATUS Status;
+ if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
+return EFI_DEVICE_ERROR;
+ }
+
switch (SatpMode) {
case SATP_MODE_OFF:
return EFI_SUCCESS;
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
index 9b28a98cb346..51ebe1750e97 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
@@ -25,3 +25,6 @@
[LibraryClasses]
BaseLib
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 68473fc640e6..79191af18a05 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -396,6 +396,14 @@
# @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and
ACPI NVS type after SmmReadyToLock.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
+[PcdsFixedAtBuild.RISCV64]
+ ## Indicate the maximum SATP mode allowed.
+ # 0 - Bare mode.
+ # 8 - 39bit mode.
+ # 9 - 48bit mode.
+ # 10 - 57bit mode.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6021
+
[PcdsDynamic, PcdsDynamicEx]
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
# @Prompt The pointer to a CPU S3 data buffer.
--
2.25.1
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