Re: [edk2-devel] [PATCH 6/6] UefiCpuPkg/MtrrTest: Add test cases for TME-MK enable case

2023-03-29 Thread Michael D Kinney 
Reviewed-by: Michael D Kinney 

> -Original Message-
> From: Ni, Ray 
> Sent: Tuesday, March 21, 2023 4:57 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Kumar, Rahul R 
> ; Gerd Hoffmann ; Kinney,
> Michael D ; Anadani, Ahmad 
> 
> Subject: [PATCH 6/6] UefiCpuPkg/MtrrTest: Add test cases for TME-MK enable 
> case
> 
> When TME-MK is enabled, the MtrrLib should substract the TME-MK
> reserved bits from the max PA returned from CPUID instruction.
> 
> The new test case guarantees such behavior in MtrrLib.
> 
> Signed-off-by: Ray Ni 
> Cc: Eric Dong 
> Cc: Rahul Kumar 
> Cc: Gerd Hoffmann 
> Cc: Michael D Kinney 
> Cc: Ahmad Anadani 
> ---
>  .../MtrrLib/UnitTest/MtrrLibUnitTest.c|  18 +--
>  .../MtrrLib/UnitTest/MtrrLibUnitTest.h|   3 +-
>  UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c | 119 ++
>  3 files changed, 107 insertions(+), 33 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c 
> b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
> index b9a97dee09..1409ae27bb 100644
> --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
> +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
> @@ -1,7 +1,7 @@
>  /** @file
> 
>Unit tests of the MtrrLib instance of the MtrrLib class
> 
> 
> 
> -  Copyright (c) 2020, Intel Corporation. All rights reserved.
> 
> +  Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
> 
>SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> 
> 
>  **/
> 
> @@ -30,6 +30,8 @@ STATIC MTRR_LIB_SYSTEM_PARAMETER  mSystemParameters[] = {
>{ 48, TRUE, TRUE, CacheWriteThrough,   12 },
> 
>{ 48, TRUE, TRUE, CacheWriteProtected, 12 },
> 
>{ 48, TRUE, TRUE, CacheWriteCombining, 12 },
> 
> +
> 
> +  { 48, TRUE, TRUE, CacheWriteBack,  12, 7}, // 7 bits for MKTME
> 
>  };
> 
> 
> 
>  UINT32  mFixedMtrrsIndex[] = {
> 
> @@ -219,7 +221,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
>  &WcCount
> 
>  );
> 
>GenerateValidAndConfigurableMtrrPairs (
> 
> -SystemParameter->PhysicalAddressBits,
> 
> +SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
> 
>  RawMtrrRange,
> 
>  UcCount,
> 
>  WtCount,
> 
> @@ -232,7 +234,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
>ExpectedMemoryRangesCount = ARRAY_SIZE (ExpectedMemoryRanges);
> 
>GetEffectiveMemoryRanges (
> 
>  SystemParameter->DefaultCacheType,
> 
> -SystemParameter->PhysicalAddressBits,
> 
> +SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
> 
>  RawMtrrRange,
> 
>  ExpectedVariableMtrrUsage,
> 
>  ExpectedMemoryRanges,
> 
> @@ -278,7 +280,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
>  ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
> 
>  CollectTestResult (
> 
>SystemParameter->DefaultCacheType,
> 
> -  SystemParameter->PhysicalAddressBits,
> 
> +  SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
> 
>SystemParameter->VariableMtrrCount,
> 
>&LocalMtrrs,
> 
>ActualMemoryRanges,
> 
> @@ -325,7 +327,7 @@ UnitTestInvalidMemoryLayouts (
>SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
> 
> 
> 
>RangeCount = Random32 (1, ARRAY_SIZE (Ranges));
> 
> -  MaxAddress = 1ull << SystemParameter->PhysicalAddressBits;
> 
> +  MaxAddress = 1ull << (SystemParameter->PhysicalAddressBits - 
> SystemParameter->MkTmeKeyidBits);
> 
> 
> 
>for (Index = 0; Index < RangeCount; Index++) {
> 
>  do {
> 
> @@ -967,7 +969,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
>  &WcCount
> 
>  );
> 
>GenerateValidAndConfigurableMtrrPairs (
> 
> -SystemParameter->PhysicalAddressBits,
> 
> +SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
> 
>  RawMtrrRange,
> 
>  UcCount,
> 
>  WtCount,
> 
> @@ -980,7 +982,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
>ExpectedMemoryRangesCount = ARRAY_SIZE (ExpectedMemoryRanges);
> 
>GetEffectiveMemoryRanges (
> 
>  SystemParameter->DefaultCacheType,
> 
> -SystemParameter->PhysicalAddressBits,
> 
> +SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
> 
>  RawMtrrRange,
> 
>  ExpectedVariableMtrrUsage,
> 
>  ExpectedMemoryRanges,
> 
> @@ -1019,7 +1021,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
>  ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
> 
>  CollectTestResult (
> 
>SystemParameter->DefaultCacheType,
> 
> -  SystemParameter->PhysicalAddressBits,
> 
> +  SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
> 
>SystemParameter->VariableMtrrCount,
> 
>&LocalMtrrs,
> 
>ActualMemoryRanges,
> 
> diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h 
> b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
> index 57e656c555..4471c1dcf7 100644
> --- a/UefiCpuPkg/Library/MtrrLib/UnitTes

[edk2-devel] [PATCH 6/6] UefiCpuPkg/MtrrTest: Add test cases for TME-MK enable case

2023-03-21 Thread Ni, Ray 
When TME-MK is enabled, the MtrrLib should substract the TME-MK
reserved bits from the max PA returned from CPUID instruction.

The new test case guarantees such behavior in MtrrLib.

Signed-off-by: Ray Ni 
Cc: Eric Dong 
Cc: Rahul Kumar 
Cc: Gerd Hoffmann 
Cc: Michael D Kinney 
Cc: Ahmad Anadani 
---
 .../MtrrLib/UnitTest/MtrrLibUnitTest.c|  18 +--
 .../MtrrLib/UnitTest/MtrrLibUnitTest.h|   3 +-
 UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c | 119 ++
 3 files changed, 107 insertions(+), 33 deletions(-)

diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c 
b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
index b9a97dee09..1409ae27bb 100644
--- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
+++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
@@ -1,7 +1,7 @@
 /** @file
   Unit tests of the MtrrLib instance of the MtrrLib class
 
-  Copyright (c) 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -30,6 +30,8 @@ STATIC MTRR_LIB_SYSTEM_PARAMETER  mSystemParameters[] = {
   { 48, TRUE, TRUE, CacheWriteThrough,   12 },
   { 48, TRUE, TRUE, CacheWriteProtected, 12 },
   { 48, TRUE, TRUE, CacheWriteCombining, 12 },
+
+  { 48, TRUE, TRUE, CacheWriteBack,  12, 7}, // 7 bits for MKTME
 };
 
 UINT32  mFixedMtrrsIndex[] = {
@@ -219,7 +221,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
 &WcCount
 );
   GenerateValidAndConfigurableMtrrPairs (
-SystemParameter->PhysicalAddressBits,
+SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
 RawMtrrRange,
 UcCount,
 WtCount,
@@ -232,7 +234,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
   ExpectedMemoryRangesCount = ARRAY_SIZE (ExpectedMemoryRanges);
   GetEffectiveMemoryRanges (
 SystemParameter->DefaultCacheType,
-SystemParameter->PhysicalAddressBits,
+SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
 RawMtrrRange,
 ExpectedVariableMtrrUsage,
 ExpectedMemoryRanges,
@@ -278,7 +280,7 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
 ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
 CollectTestResult (
   SystemParameter->DefaultCacheType,
-  SystemParameter->PhysicalAddressBits,
+  SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
   SystemParameter->VariableMtrrCount,
   &LocalMtrrs,
   ActualMemoryRanges,
@@ -325,7 +327,7 @@ UnitTestInvalidMemoryLayouts (
   SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
 
   RangeCount = Random32 (1, ARRAY_SIZE (Ranges));
-  MaxAddress = 1ull << SystemParameter->PhysicalAddressBits;
+  MaxAddress = 1ull << (SystemParameter->PhysicalAddressBits - 
SystemParameter->MkTmeKeyidBits);
 
   for (Index = 0; Index < RangeCount; Index++) {
 do {
@@ -967,7 +969,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
 &WcCount
 );
   GenerateValidAndConfigurableMtrrPairs (
-SystemParameter->PhysicalAddressBits,
+SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
 RawMtrrRange,
 UcCount,
 WtCount,
@@ -980,7 +982,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
   ExpectedMemoryRangesCount = ARRAY_SIZE (ExpectedMemoryRanges);
   GetEffectiveMemoryRanges (
 SystemParameter->DefaultCacheType,
-SystemParameter->PhysicalAddressBits,
+SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
 RawMtrrRange,
 ExpectedVariableMtrrUsage,
 ExpectedMemoryRanges,
@@ -1019,7 +1021,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
 ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
 CollectTestResult (
   SystemParameter->DefaultCacheType,
-  SystemParameter->PhysicalAddressBits,
+  SystemParameter->PhysicalAddressBits - SystemParameter->MkTmeKeyidBits,
   SystemParameter->VariableMtrrCount,
   &LocalMtrrs,
   ActualMemoryRanges,
diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h 
b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
index 57e656c555..4471c1dcf7 100644
--- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
+++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2020, Intel Corporation. All rights reserved.
+  Copyright (c) 2020 - 2023, Intel Corporation. All rights reserved.
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -40,6 +40,7 @@ typedef struct {
   BOOLEAN   FixedMtrrSupported;
   MTRR_MEMORY_CACHE_TYPEDefaultCacheType;
   UINT32VariableMtrrCount;
+  UINT8 MkTmeKeyidBits;
 } MTRR_LIB_SYSTEM_PARAMETER;
 
 extern UINT32   mFixedMtrrsIndex[];
diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c 
b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
index 260966e7b6..ba1de10034 100644
--- a/UefiCpuPkg/Libra