回复: [ ** SPAMMAIL ** ][edk2-devel] [PATCH v2 1/1] MdePkg: Add Cxl20.h into IndustryStandard
Acked-by: Liming Gao > -邮件原件- > 发件人: devel@edk2.groups.io 代表 Chris Li OS > via groups.io > 发送时间: 2023年7月3日 17:39 > 收件人: Ni, Ray ; devel@edk2.groups.io; Yao, Jiewen > ; Nong, Foster > 抄送: gaolim...@byosoft.com.cn; michael.d.kin...@intel.com; Open Source > Submission > 主题: [ ** SPAMMAIL ** ][edk2-devel] [PATCH v2 1/1] MdePkg: Add Cxl20.h > into IndustryStandard > > +To/Cc > > Updated places from v1: > +#define CXL_2_0_DVSEC_REVISON_ID 0x1 > > -#define CXL20_DVSEC_REVISON_REGISTOR_LOCATOR 0x0 > +#define CXL_2_0_DVSEC_REVISON_REGISTOR_LOCATOR0x0 > > -} HDM_DECODER_N_INFO; > +} CXL_HDM_DECODER_N_INFO; > > - > > 1) Add CXL 2.0 header file to comply with CXL 2.0 specification > 2) CXL 2.0 header will embed Cxl11.h > 3) Updated Cxl.h to point to 2.0 header file > > Signed-off-by: Chris Li > --- > MdePkg/Include/IndustryStandard/Cxl.h | 2 +- > MdePkg/Include/IndustryStandard/Cxl20.h | 479 > > 2 files changed, 480 insertions(+), 1 deletion(-) > create mode 100644 MdePkg/Include/IndustryStandard/Cxl20.h > > diff --git a/MdePkg/Include/IndustryStandard/Cxl.h > b/MdePkg/Include/IndustryStandard/Cxl.h > index 06c1230e3e..9ad3242e25 100644 > --- a/MdePkg/Include/IndustryStandard/Cxl.h > +++ b/MdePkg/Include/IndustryStandard/Cxl.h > @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #ifndef _CXL_MAIN_H_ > #define _CXL_MAIN_H_ > > -#include > +#include > // > // CXL assigned new Vendor ID > // > diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h > b/MdePkg/Include/IndustryStandard/Cxl20.h > new file mode 100644 > index 00..16ac6d5aff > --- /dev/null > +++ b/MdePkg/Include/IndustryStandard/Cxl20.h > @@ -0,0 +1,479 @@ > +/** @file > + CXL 2.0 Register definitions > + > + This file contains the register definitions based on the Compute Express > Link > + (CXL) Specification Revision 2.0. > + > + Copyright (c) 2023, Ampere Computing LLC. All rights reserved. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef CXL20_H_ > +#define CXL20_H_ > + > +#include > + > +// > +// Ensure proper structure formats > +// > +#pragma pack(1) > + > + > +// > +// CXL DVSEC IDs and Revisions > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.1 > +// > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICE0x0 > +#define CXL_DVSEC_ID_NON_CXL_FUNCTION_MAP > 0x2 > +#define CXL_DVSEC_ID_CXL20_EXTENSIONS_DVSEC_FOR_PORTS 0x3 > +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS 0x4 > +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES0x5 > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT 0x7 > +#define CXL_DVSEC_ID_REGISTER_LOCATOR 0x8 > +#define CXL_DVSEC_ID_MLD 0x9 > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_TEST_CAPABILITY 0xA > + > +#define CXL_2_0_DVSEC_REVISON_ID 0x1 > + > +#define CXL_2_0_DVSEC_REVISON_REGISTOR_LOCATOR0x0 > + > +// > +// Register Block ID > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9.1 > +// > +#define CXL_REGISTER_BLOCK_ID_EMPTY 0x0 > +#define CXL_REGISTER_BLOCK_ID_COMPONENT > 0x01 > +#define CXL_REGISTER_BLOCK_ID_BAR_VIRTUALIZATION_ACL 0x02 > +#define CXL_REGISTER_BLOCK_ID_DEVICE 0x03 > + > +// > +// Component Register Block Register Ranges Offset > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.4 > +// > +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_IO > 0x0 > +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_CACHE_MEM > 0x1000 > +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_ARB_MUX > 0xE000 > + > +// > +// CXL Cache Memory Capability IDs > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5 > +// > +#define CXL_CACHE_MEM_CAPABILITY_ID_CXL 0x1 > +#define CXL_CACHE_MEM_CAPABILITY_ID_RAS 0x2 > +#define CXL_CACHE_MEM_CAPABILITY_ID_SECURITY 0x3 > +#define CXL_CACHE_MEM_CAPABILITY_ID_LINK 0x4 > +#define CXL_CACHE_MEM_CAPABILITY_ID_HDM_DECODER > 0x5 > +#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_SECURITY 0x6 > +#define CXL_CACHE_MEM_CAPABILITY_ID_IDE 0x7 > +#define CXL_CACHE_MEM_CAPABILITY_ID_SNOOP_FILTER 0x8 > +#define CXL_CACHE_MEM_CAPABILITY_ID_MASK > 0x > + > +// > +// Generic CXL Device Capability IDs 0x ~ 0x3FFF > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1 > +// >
[edk2-devel] [PATCH v2 1/1] MdePkg: Add Cxl20.h into IndustryStandard
+To/Cc Updated places from v1: +#define CXL_2_0_DVSEC_REVISON_ID 0x1 -#define CXL20_DVSEC_REVISON_REGISTOR_LOCATOR 0x0 +#define CXL_2_0_DVSEC_REVISON_REGISTOR_LOCATOR0x0 -} HDM_DECODER_N_INFO; +} CXL_HDM_DECODER_N_INFO; - 1) Add CXL 2.0 header file to comply with CXL 2.0 specification 2) CXL 2.0 header will embed Cxl11.h 3) Updated Cxl.h to point to 2.0 header file Signed-off-by: Chris Li --- MdePkg/Include/IndustryStandard/Cxl.h | 2 +- MdePkg/Include/IndustryStandard/Cxl20.h | 479 2 files changed, 480 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Include/IndustryStandard/Cxl20.h diff --git a/MdePkg/Include/IndustryStandard/Cxl.h b/MdePkg/Include/IndustryStandard/Cxl.h index 06c1230e3e..9ad3242e25 100644 --- a/MdePkg/Include/IndustryStandard/Cxl.h +++ b/MdePkg/Include/IndustryStandard/Cxl.h @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _CXL_MAIN_H_ #define _CXL_MAIN_H_ -#include +#include // // CXL assigned new Vendor ID // diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h b/MdePkg/Include/IndustryStandard/Cxl20.h new file mode 100644 index 00..16ac6d5aff --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl20.h @@ -0,0 +1,479 @@ +/** @file + CXL 2.0 Register definitions + + This file contains the register definitions based on the Compute Express Link + (CXL) Specification Revision 2.0. + + Copyright (c) 2023, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef CXL20_H_ +#define CXL20_H_ + +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + + +// +// CXL DVSEC IDs and Revisions +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.1 +// +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICE0x0 +#define CXL_DVSEC_ID_NON_CXL_FUNCTION_MAP 0x2 +#define CXL_DVSEC_ID_CXL20_EXTENSIONS_DVSEC_FOR_PORTS 0x3 +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS 0x4 +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES0x5 +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT 0x7 +#define CXL_DVSEC_ID_REGISTER_LOCATOR 0x8 +#define CXL_DVSEC_ID_MLD 0x9 +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_TEST_CAPABILITY 0xA + +#define CXL_2_0_DVSEC_REVISON_ID 0x1 + +#define CXL_2_0_DVSEC_REVISON_REGISTOR_LOCATOR0x0 + +// +// Register Block ID +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9.1 +// +#define CXL_REGISTER_BLOCK_ID_EMPTY 0x0 +#define CXL_REGISTER_BLOCK_ID_COMPONENT 0x01 +#define CXL_REGISTER_BLOCK_ID_BAR_VIRTUALIZATION_ACL 0x02 +#define CXL_REGISTER_BLOCK_ID_DEVICE 0x03 + +// +// Component Register Block Register Ranges Offset +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.4 +// +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_IO 0x0 +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_CACHE_MEM0x1000 +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_ARB_MUX 0xE000 + +// +// CXL Cache Memory Capability IDs +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5 +// +#define CXL_CACHE_MEM_CAPABILITY_ID_CXL 0x1 +#define CXL_CACHE_MEM_CAPABILITY_ID_RAS 0x2 +#define CXL_CACHE_MEM_CAPABILITY_ID_SECURITY 0x3 +#define CXL_CACHE_MEM_CAPABILITY_ID_LINK 0x4 +#define CXL_CACHE_MEM_CAPABILITY_ID_HDM_DECODER 0x5 +#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_SECURITY 0x6 +#define CXL_CACHE_MEM_CAPABILITY_ID_IDE 0x7 +#define CXL_CACHE_MEM_CAPABILITY_ID_SNOOP_FILTER 0x8 +#define CXL_CACHE_MEM_CAPABILITY_ID_MASK 0x + +// +// Generic CXL Device Capability IDs 0x ~ 0x3FFF +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1 +// +#define CXL_DEVICE_CAPABILITY_ID_CAPABILITIES_ARRAY_REGISTER0x +#define CXL_DEVICE_CAPABILITY_ID_DEVICE_STATUS 0x0001 +#define CXL_DEVICE_CAPABILITY_ID_PRIMARY_MAILBOX0x0002 +#define CXL_DEVICE_CAPABILITY_ID_SECONDARY_MAILBOX 0x0003 + +// +// Specific CXL Device Capability IDs 0x4000 ~ 0x7FFF +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1 +// +// (ref: CXL 2.0 spec $8.2.8.5) +#define CXL_DEVICE_CAPABILITY_ID_MEMORY_DEVICE_STATUS 0x4000 +#define CXL_DEVICE_CAPABILITY_ID_MASK 0x + +// +// Memory Device Status +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5.1.1 +// +#define CXL_MEM_DEVICE_MEDIA_STATUS_NOT_READY 0b00 +#define CXL_MEM_DEVICE_MEDIA_STATUS_READY 0b01 +#define CXL_MEM_DEVICE_MEDIA_STATUS_ERROR 0b10 +#define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED 0b11 + +// +// PCIe DVS
