Re: [edk2-devel] [PATCH v2 3/4] IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.
Reviewed-by: Nate DeSimone
> -Original Message-
> From: Chiu, Chasel
> Sent: Tuesday, August 9, 2022 5:48 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star
> Subject: [PATCH v2 3/4] IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916
>
> Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM.
> For backward compatibility, new INF are created for new modules.
>
> Cc: Nate DeSimone
> Cc: Star Zeng
> Signed-off-by: Chasel Chiu
> ---
> IntelFsp2Pkg/FspSecCore/SecFsp.c| 4
> IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 9 +
> IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 75
> ++
> +
> IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf | 59
> ++
> +
> IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm| 304
> ++
> ++
> ++
> ++
> ++
> ++
> IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm| 101
> ++
> +++
> IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm | 3 +++
> IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm | 303
> ++
> ++
> ++
> ++
> ++
> +
> IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm | 108
> ++
> ++
> IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 3 +++
> 10 files changed, 969 insertions(+)
>
> diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c
> b/IntelFsp2Pkg/FspSecCore/SecFsp.c
> index d9085ef51f..11be1f97ca 100644
> --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
> +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
> @@ -135,6 +135,10 @@ FspGlobalDataInit (
>PeiFspData->CoreStack = BootLoaderStack;
>
>PeiFspData->PerfIdx = 2;
>
>PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;
>
> + //
>
> + // Cache FspHobList pointer passed by bootloader via ApiParameter2
>
> + //
>
> + PeiFspData->FspHobListPtr = (VOID **)GetFspApiParameter2 ();
>
>
>
>SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY);
>
>
>
> diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> index 35d223a404..a44fbf2a50 100644
> --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> @@ -69,8 +69,17 @@ FspApiCallingCheck (
> Status = EFI_UNSUPPORTED;
>
>} else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex,
> ApiParam))) {
>
> Status = EFI_INVALID_PARAMETER;
>
> + } else if (ApiIdx == FspSiliconInitApiIndex) {
>
> +//
>
> +// Reset MultiPhase NumberOfPhases to zero
>
> +//
>
> +FspData->NumberOfPhases = 0;
>
>}
>
> }
>
> + } else if (ApiIdx == FspMultiPhaseMemInitApiIndex) {
>
> +if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS) ||
> ((UINTN)FspData == MAX_UINT32)) {
>
> + Status = EFI_UNSUPPORTED;
>
> +}
>
>} else if (ApiIdx == FspSmmInitApiIndex) {
>
> //
>
> // FspSmmInitApiIndex check
>
> diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
> b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
> new file mode 100644
> index 00..e93e176f15
> --- /dev/null
> +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
> @@ -0,0 +1,75 @@
> +## @file
>
> +# Sec Core for FSP to support MultiPhase (SeparatePhase)
> MemInitialization.
>
> +#
>
> +# Copyright (c) 2022, Intel Corporation. All rights reserved.
>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +[Defines]
>
> + INF_VERSION= 0x00010005
>
> + BASE_NAME = Fsp24SecCoreM
>
> + FILE_GUID = C5BC0719-4A23-4F6E-94DA-05FB6A0DFA9C
>
> + MODULE_TYPE= SEC
>
> + VERSION_STRING = 1.0
>
> +
>
> +#
>
> +# The following information is for reference only and not required by the
> build tools.
>
> +#
>
> +# VALID_ARCHITECTURES = IA32 X64
>
> +#
>
> +
>
> +[Sources]
>
> + SecMain.c
>
> + SecMain.h
>
> + SecFsp.c
>
> + SecFsp.h
>
> + SecFspApiChk.c
>
> +
>
> +[Sources.IA32]
>
> +
[edk2-devel] [PATCH v2 3/4] IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916
Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM.
For backward compatibility, new INF are created for new modules.
Cc: Nate DeSimone
Cc: Star Zeng
Signed-off-by: Chasel Chiu
---
IntelFsp2Pkg/FspSecCore/SecFsp.c| 4
IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 9 +
IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 75
+++
IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf | 59
+++
IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm| 304
IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm| 101
+
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm | 3 +++
IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm | 303
+++
IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm | 108
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 3 +++
10 files changed, 969 insertions(+)
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index d9085ef51f..11be1f97ca 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -135,6 +135,10 @@ FspGlobalDataInit (
PeiFspData->CoreStack = BootLoaderStack;
PeiFspData->PerfIdx = 2;
PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;
+ //
+ // Cache FspHobList pointer passed by bootloader via ApiParameter2
+ //
+ PeiFspData->FspHobListPtr = (VOID **)GetFspApiParameter2 ();
SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY);
diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
index 35d223a404..a44fbf2a50 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
@@ -69,8 +69,17 @@ FspApiCallingCheck (
Status = EFI_UNSUPPORTED;
} else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex,
ApiParam))) {
Status = EFI_INVALID_PARAMETER;
+ } else if (ApiIdx == FspSiliconInitApiIndex) {
+//
+// Reset MultiPhase NumberOfPhases to zero
+//
+FspData->NumberOfPhases = 0;
}
}
+ } else if (ApiIdx == FspMultiPhaseMemInitApiIndex) {
+if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS) ||
((UINTN)FspData == MAX_UINT32)) {
+ Status = EFI_UNSUPPORTED;
+}
} else if (ApiIdx == FspSmmInitApiIndex) {
//
// FspSmmInitApiIndex check
diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
new file mode 100644
index 00..e93e176f15
--- /dev/null
+++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
@@ -0,0 +1,75 @@
+## @file
+# Sec Core for FSP to support MultiPhase (SeparatePhase) MemInitialization.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 0x00010005
+ BASE_NAME = Fsp24SecCoreM
+ FILE_GUID = C5BC0719-4A23-4F6E-94DA-05FB6A0DFA9C
+ MODULE_TYPE= SEC
+ VERSION_STRING = 1.0
+
+#
+# The following information is for reference only and not required by the
build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[Sources]
+ SecMain.c
+ SecMain.h
+ SecFsp.c
+ SecFsp.h
+ SecFspApiChk.c
+
+[Sources.IA32]
+ Ia32/Stack.nasm
+ Ia32/Fsp24ApiEntryM.nasm
+ Ia32/FspApiEntryCommon.nasm
+ Ia32/FspHelper.nasm
+ Ia32/ReadEsp.nasm
+
+[Sources.X64]
+ X64/Stack.nasm
+ X64/Fsp24ApiEntryM.nasm
+ X64/FspApiEntryCommon.nasm
+ X64/FspHelper.nasm
+ X64/ReadRsp.nasm
+
+[Binaries.Ia32]
+ RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ BaseLib
+ PciCf8Lib
+ SerialPortLib
+ FspSwitchStackLib
+ FspCommonLib
+ FspSecPlatformLib
+ CpuLib
+ UefiCpuLib
+ FspMultiPhaseLib
+
+[Pcd]
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+
