Re: [edk2-devel] [PATCH v6 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op

2023-10-24 Thread Laszlo Ersek 
On 10/21/23 19:33, Dhaval Sharma wrote:
> There are different ways to manage cache on RISC-V Processors.
> One way is to use fence instruction. Another way is to use CPU
> specific cache management operation instructions ratified as
> per RISC-V ISA specifications to be introduced in future
> patches. Current method is fence instruction based, rename the
> function accordingly to add that clarity.
> 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Zhiguang Liu 
> Cc: Sunil V L 
> Cc: Daniel Schaefer 
> Cc: Laszlo Ersek 
> 
> Signed-off-by: Dhaval Sharma 
> ---
> 
> Notes:
> V6:
> - As part of restructuring, adding cache instruction differentiation
>   in function naming
> 
>  MdePkg/Include/Library/BaseLib.h| 4 ++--
>  MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
>  MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 
>  3 files changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h 
> b/MdePkg/Include/Library/BaseLib.h
> index 7142bbfa42f2..d4b56a9601da 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
>  **/
>  VOID
>  EFIAPI
> -RiscVInvalidateInstCacheAsm (
> +RiscVInvalidateInstCacheAsmFence (
>VOID
>);
>  
> @@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
>  **/
>  VOID
>  EFIAPI
> -RiscVInvalidateDataCacheAsm (
> +RiscVInvalidateDataCacheAsmFence (
>VOID
>);
>  
> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
> b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> index d5efcf49a4bf..4eb18edb9aa7 100644
> --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
> @@ -21,7 +21,7 @@ InvalidateInstructionCache (
>VOID
>)
>  {
> -  RiscVInvalidateInstCacheAsm ();
> +  RiscVInvalidateInstCacheAsmFence ();
>  }
>  
>  /**
> @@ -193,7 +193,7 @@ InvalidateDataCache (
>VOID
>)
>  {
> -  RiscVInvalidateDataCacheAsm ();
> +  RiscVInvalidateDataCacheAsmFence ();
>  }
>  
>  /**
> diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
> b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> index 7c10fdd268af..e0eea0b5fb25 100644
> --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
> @@ -9,13 +9,13 @@
>  
> //--
>  
>  .align 3
> -ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
> -ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
> +ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
> +ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsmFence)
>  
> -ASM_PFX(RiscVInvalidateInstCacheAsm):
> +ASM_PFX(RiscVInvalidateInstCacheAsmFence):
>  fence.i
>  ret
>  
> -ASM_PFX(RiscVInvalidateDataCacheAsm):
> +ASM_PFX(RiscVInvalidateDataCacheAsmFence):
>  fence
>  ret

Reviewed-by: Laszlo Ersek 



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[edk2-devel] [PATCH v6 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op

2023-10-21 Thread Dhaval Sharma 
There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.

Cc: Michael D Kinney 
Cc: Liming Gao 
Cc: Zhiguang Liu 
Cc: Sunil V L 
Cc: Daniel Schaefer 
Cc: Laszlo Ersek 

Signed-off-by: Dhaval Sharma 
---

Notes:
V6:
- As part of restructuring, adding cache instruction differentiation
  in function naming

 MdePkg/Include/Library/BaseLib.h| 4 ++--
 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 ++--
 MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 7142bbfa42f2..d4b56a9601da 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt (
 **/
 VOID
 EFIAPI
-RiscVInvalidateInstCacheAsm (
+RiscVInvalidateInstCacheAsmFence (
   VOID
   );
 
@@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm (
 **/
 VOID
 EFIAPI
-RiscVInvalidateDataCacheAsm (
+RiscVInvalidateDataCacheAsmFence (
   VOID
   );
 
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c 
b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
index d5efcf49a4bf..4eb18edb9aa7 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -21,7 +21,7 @@ InvalidateInstructionCache (
   VOID
   )
 {
-  RiscVInvalidateInstCacheAsm ();
+  RiscVInvalidateInstCacheAsmFence ();
 }
 
 /**
@@ -193,7 +193,7 @@ InvalidateDataCache (
   VOID
   )
 {
-  RiscVInvalidateDataCacheAsm ();
+  RiscVInvalidateDataCacheAsmFence ();
 }
 
 /**
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S 
b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
index 7c10fdd268af..e0eea0b5fb25 100644
--- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -9,13 +9,13 @@
 
//--
 
 .align 3
-ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
-ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsmFence)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsmFence)
 
-ASM_PFX(RiscVInvalidateInstCacheAsm):
+ASM_PFX(RiscVInvalidateInstCacheAsmFence):
 fence.i
 ret
 
-ASM_PFX(RiscVInvalidateDataCacheAsm):
+ASM_PFX(RiscVInvalidateDataCacheAsmFence):
 fence
 ret
-- 
2.39.2



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