Re: [edk2-devel] [edk2-platforms][PATCH 1/2] Ampere: PCIe: Add support for Ampere Altra Max
Urgh, I think I forgot to reply to this - apologies.
On Fri, Feb 24, 2023 at 10:26:42 +0700, Nhi Pham wrote:
> Hi Leif,
>
> Thanks for your reviewing. Most of your feedback is valid. I will fix them.
> There is a comment that need your more explanation.
>
> Please see the inline reply for more details.
>
> > > diff --git
> > > a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c
> > > b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c
> > > index aa34a90b44c6..1346fa616ab3 100644
> > > ---
> > > a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c
> > > +++
> > > b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c
> > > @@ -37,7 +37,7 @@
> > > | Y | Y | Y | Y | 3|
> > >
> > > - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights
> > > reserved.
> > > + Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights
> > > reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent
> > > @@ -149,6 +149,10 @@ GetDefaultDevMap (
> > > AC01_ROOT_COMPLEX *RootComplex
> > > )
> > > {
> > > + BOOLEAN IsAc01;
> > > +
> > > + IsAc01 = IsAc01Processor ();
> > > +
> > > if (RootComplex->Pcie[PcieController0].Active
> > > && RootComplex->Pcie[PcieController1].Active
> > > && RootComplex->Pcie[PcieController2].Active
> > > @@ -169,14 +173,20 @@ GetDefaultDevMap (
> > > && RootComplex->Pcie[PcieController5].Active
> > > && RootComplex->Pcie[PcieController6].Active
> > > && RootComplex->Pcie[PcieController7].Active) {
> > > -RootComplex->DefaultDevMapHigh = DevMapMode4;
> > > +if (IsAc01) {
> > > + RootComplex->DefaultDevMapHigh = DevMapMode4;
> > > +}
> >
> > Who sets RootComplex->DefaultDevMapHigh if !IsAc01?
>
> It will be the default value (0) because Ampere Altra Max does not have Root
> Complex Type B.
OK.
So, this just looks a bit like a maintenance nightmare.
There are so many places that individually check for a specific
platform.
And this is not the most readable file to begin with.
So looking at this *existing* function, it seems to be determining how
many PCIe controllers are active. Could we simplify it with some
arithmetic instead of translating truth tables to C conditionals?
If so, it looks like we could have a single IsAc01 check, covering
cases 2-4?
/
Leif
> >
> > > } else if (RootComplex->Pcie[PcieController4].Active
> > >&& RootComplex->Pcie[PcieController6].Active
> > >&& RootComplex->Pcie[PcieController7].Active) {
> > > -RootComplex->DefaultDevMapHigh = DevMapMode3;
> > > +if (IsAc01) {
> > > + RootComplex->DefaultDevMapHigh = DevMapMode3;
> > > +}
> > same
> >
> > > } else if (RootComplex->Pcie[PcieController4].Active
> > >&& RootComplex->Pcie[PcieController6].Active) {
> > > -RootComplex->DefaultDevMapHigh = DevMapMode2;
> > > +if (IsAc01) {
> > > + RootComplex->DefaultDevMapHigh = DevMapMode2;
> > > +}
> > same
> >
> > > } else {
> > > RootComplex->DefaultDevMapHigh = DevMapMode1;
> > > }
> > I feel this function in general could be rewritten more reader-friendly.
> >
> > > @@ -203,12 +213,17 @@ GetLaneAllocation (
> > > EFI_STATUS Status;
> > > INTN RPIndex;
> > > NVPARAMNvParamOffset;
> > > - UINT32 Value, Width;
> > > + UINT32 Value, Width, Controller;
> > > // Retrieve lane allocation and capabilities for each controller
> > > if (RootComplex->Type == RootComplexTypeA) {
> > > -NvParamOffset = (RootComplex->Socket == 0) ?
> > > NV_SI_RO_BOARD_S0_RCA0_CFG : NV_SI_RO_BOARD_S1_RCA0_CFG;
> > > -NvParamOffset += RootComplex->ID * NV_PARAM_ENTRYSIZE;
> > > +if (RootComplex->ID < MaxPcieControllerOfRootComplexA) {
> > > + NvParamOffset = (RootComplex->Socket == 0) ?
> > > NV_SI_RO_BOARD_S0_RCA0_CFG : NV_SI_RO_BOARD_S1_RCA0_CFG;
> > > + NvParamOffset += RootComplex->ID * NV_PARAM_ENTRYSIZE;
> > > +} else {
> > > + NvParamOffset = (RootComplex->Socket == 0) ?
> > > NV_SI_RO_BOARD_S0_RCA4_CFG : NV_SI_RO_BOARD_S1_RCA4_CFG;
> > > + NvParamOffset += (RootComplex->ID -
> > > MaxPcieControllerOfRootComplexA) * NV_PARAM_ENTRYSIZE;
> > > +}
> > Helper function.
> >
> > > } else {
> > > //
> > > // There're two NVParam entries per RootComplexTypeB
> > > @@ -222,7 +237,13 @@ GetLaneAllocation (
> > > Value = 0;
> > > }
> > > - for (RPIndex = 0; RPIndex < MaxPcieControllerOfRootComplexA;
> > > RPIndex++) {
> > > + if (IsAc01Processor ()) {
> > > +Controller = MaxPcieControllerOfRootComplexA;
> > > + } else {
> > > +Controller = RootComplex->MaxPcieController;
> > > + }
> > Straightforward enough, but could still be a helper function.
> >
> > > +
> > > + for (RPIndex = PcieController0; RPIndex < Controller; RPIndex++) {
> > >
Re: [edk2-devel] [edk2-platforms][PATCH 1/2] Ampere: PCIe: Add support for Ampere Altra Max
Hi Leif, Thanks for your reviewing. Most of your feedback is valid. I will fix them. There is a comment that need your more explanation. Please see the inline reply for more details. On 2/15/2023 6:59 PM, Leif Lindholm wrote: On Fri, Jan 13, 2023 at 11:25:16 +0700, Nhi Pham wrote: From: Vu Nguyen This updates the PCIe modules to add support for Ampere Altra Max processor which features 128 PCIe Gen4 lanes (distributed across eight x16 RCAs) using 32 controllers. Signed-off-by: Nhi Pham --- .../AmpereAltraPkg/Include/NVParamDef.h | 64 ++-- .../Library/Ac01PcieLib/PcieCore.h| 8 +- .../Library/BoardPcieLib/BoardPcieLib.c | 63 +++- .../Drivers/PcieInitPei/PcieInitPei.c | 16 +- .../Drivers/PcieInitPei/RootComplexNVParam.c | 101 +--- .../Library/Ac01PcieLib/PcieCore.c| 150 +++--- 6 files changed, 333 insertions(+), 69 deletions(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h index 3259fa1ea45c..4dfc353d2340 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h @@ -29,7 +29,7 @@ As each non-volatile parameter requires 8 bytes, there is a total of 8K parameters. - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent @@ -425,10 +425,10 @@ #define NV_SI_RO_BOARD_S0_RCA5_CFG((107 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */ #define NV_SI_RO_BOARD_S0_RCA6_CFG((108 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */ #define NV_SI_RO_BOARD_S0_RCA7_CFG((109 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020003 */ -#define NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET ((110 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET ((111 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET ((112 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET ((113 * 8) + NV_BOARD_PARAM_START) +#define NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET ((110 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET ((111 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET ((112 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET ((113 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ Could you split the comment additions into a separate patch? I think there are no functional changes to this file, but that is very hard to determine. Thanks, I will split it out. #define NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET ((114 * 8) + NV_BOARD_PARAM_START) #define NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET ((115 * 8) + NV_BOARD_PARAM_START) #define NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET ((116 * 8) + NV_BOARD_PARAM_START) @@ -437,10 +437,10 @@ #define NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET ((119 * 8) + NV_BOARD_PARAM_START) #define NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET ((120 * 8) + NV_BOARD_PARAM_START) #define NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET ((121 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET ((122 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET ((123 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET ((124 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET ((125 * 8) + NV_BOARD_PARAM_START) +#define NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET ((122 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET ((123 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET ((124 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET ((125 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ #define NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET ((126 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */ #define NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET ((127 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */ #define NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET ((128 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */ @@ -462,8 +462,8 @@ #define NV_SI_RO_BOARD_S1_RCA5_CFG((144 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */ #define NV_SI_RO_BOARD_S1_RCA6_CFG((
Re: [edk2-devel] [edk2-platforms][PATCH 1/2] Ampere: PCIe: Add support for Ampere Altra Max
On Fri, Jan 13, 2023 at 11:25:16 +0700, Nhi Pham wrote: > From: Vu Nguyen > > This updates the PCIe modules to add support for > Ampere Altra Max processor which features 128 PCIe > Gen4 lanes (distributed across eight x16 RCAs) using > 32 controllers. > > Signed-off-by: Nhi Pham > --- > .../AmpereAltraPkg/Include/NVParamDef.h | 64 ++-- > .../Library/Ac01PcieLib/PcieCore.h| 8 +- > .../Library/BoardPcieLib/BoardPcieLib.c | 63 +++- > .../Drivers/PcieInitPei/PcieInitPei.c | 16 +- > .../Drivers/PcieInitPei/RootComplexNVParam.c | 101 +--- > .../Library/Ac01PcieLib/PcieCore.c| 150 +++--- > 6 files changed, 333 insertions(+), 69 deletions(-) > > diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h > b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h > index 3259fa1ea45c..4dfc353d2340 100644 > --- a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h > +++ b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h > @@ -29,7 +29,7 @@ >As each non-volatile parameter requires 8 bytes, there is a total of 8K >parameters. > > - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. > + Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved. > >SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -425,10 +425,10 @@ > #define NV_SI_RO_BOARD_S0_RCA5_CFG((107 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x02020202 */ > #define NV_SI_RO_BOARD_S0_RCA6_CFG((108 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x02020202 */ > #define NV_SI_RO_BOARD_S0_RCA7_CFG((109 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x02020003 */ > -#define NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET ((110 * 8) + > NV_BOARD_PARAM_START) > -#define NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET ((111 * 8) + > NV_BOARD_PARAM_START) > -#define NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET ((112 * 8) + > NV_BOARD_PARAM_START) > -#define NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET ((113 * 8) + > NV_BOARD_PARAM_START) > +#define NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET ((110 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x */ > +#define NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET ((111 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x */ > +#define NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET ((112 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x */ > +#define NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET ((113 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x */ Could you split the comment additions into a separate patch? I think there are no functional changes to this file, but that is very hard to determine. > #define NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET ((114 * 8) + > NV_BOARD_PARAM_START) > #define NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET ((115 * 8) + > NV_BOARD_PARAM_START) > #define NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET ((116 * 8) + > NV_BOARD_PARAM_START) > @@ -437,10 +437,10 @@ > #define NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET ((119 * 8) + > NV_BOARD_PARAM_START) > #define NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET ((120 * 8) + > NV_BOARD_PARAM_START) > #define NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET ((121 * 8) + > NV_BOARD_PARAM_START) > -#define NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET ((122 * 8) + > NV_BOARD_PARAM_START) > -#define NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET ((123 * 8) + > NV_BOARD_PARAM_START) > -#define NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET ((124 * 8) + > NV_BOARD_PARAM_START) > -#define NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET ((125 * 8) + > NV_BOARD_PARAM_START) > +#define NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET ((122 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x */ > +#define NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET ((123 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x */ > +#define NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET ((124 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x */ > +#define NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET ((125 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x */ > #define NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET ((126 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x57575757 */ > #define NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET ((127 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x57575757 */ > #define NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET ((128 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x57575757 */ > @@ -462,8 +462,8 @@ > #define NV_SI_RO_BOARD_S1_RCA5_CFG((144 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x02020202 */ > #define NV_SI_RO_BOARD_S1_RCA6_CFG((145 * 8) + > NV_BOARD_PARAM_START) /* Default: 0x02020202 */ > #define NV_SI_RO_BOARD_S1_RCA7_CFG
[edk2-devel] [edk2-platforms][PATCH 1/2] Ampere: PCIe: Add support for Ampere Altra Max
From: Vu Nguyen This updates the PCIe modules to add support for Ampere Altra Max processor which features 128 PCIe Gen4 lanes (distributed across eight x16 RCAs) using 32 controllers. Signed-off-by: Nhi Pham --- .../AmpereAltraPkg/Include/NVParamDef.h | 64 ++-- .../Library/Ac01PcieLib/PcieCore.h| 8 +- .../Library/BoardPcieLib/BoardPcieLib.c | 63 +++- .../Drivers/PcieInitPei/PcieInitPei.c | 16 +- .../Drivers/PcieInitPei/RootComplexNVParam.c | 101 +--- .../Library/Ac01PcieLib/PcieCore.c| 150 +++--- 6 files changed, 333 insertions(+), 69 deletions(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h index 3259fa1ea45c..4dfc353d2340 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h @@ -29,7 +29,7 @@ As each non-volatile parameter requires 8 bytes, there is a total of 8K parameters. - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent @@ -425,10 +425,10 @@ #define NV_SI_RO_BOARD_S0_RCA5_CFG((107 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */ #define NV_SI_RO_BOARD_S0_RCA6_CFG((108 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */ #define NV_SI_RO_BOARD_S0_RCA7_CFG((109 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020003 */ -#define NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET ((110 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET ((111 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET ((112 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET ((113 * 8) + NV_BOARD_PARAM_START) +#define NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET ((110 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET ((111 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET ((112 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET ((113 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ #define NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET ((114 * 8) + NV_BOARD_PARAM_START) #define NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET ((115 * 8) + NV_BOARD_PARAM_START) #define NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET ((116 * 8) + NV_BOARD_PARAM_START) @@ -437,10 +437,10 @@ #define NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET ((119 * 8) + NV_BOARD_PARAM_START) #define NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET ((120 * 8) + NV_BOARD_PARAM_START) #define NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET ((121 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET ((122 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET ((123 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET ((124 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET ((125 * 8) + NV_BOARD_PARAM_START) +#define NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET ((122 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET ((123 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET ((124 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET ((125 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ #define NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET ((126 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */ #define NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET ((127 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */ #define NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET ((128 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */ @@ -462,8 +462,8 @@ #define NV_SI_RO_BOARD_S1_RCA5_CFG((144 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */ #define NV_SI_RO_BOARD_S1_RCA6_CFG((145 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */ #define NV_SI_RO_BOARD_S1_RCA7_CFG((146 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020003 */ -#define NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET ((147 * 8) + NV_BOARD_PARAM_START) -#define NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET ((148 * 8) + NV_BOARD_PARAM_START) +#define NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET ((147 * 8) + NV_BOARD_PARAM_START) /* Default: 0x */ +#define NV_
