They had been implemented in MdePkg/Library/BaseLib
Cc: Daniel Schaefer <g...@danielschaefer.me>
Cc: Sunil V L <suni...@ventanamicro.com>
Cc: Andrei Warkentin <andrei.warken...@intel.com>
Signed-off-by: Evan Chai <evan.c...@intel.com>
---
Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h | 20
+-------------------
Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 41
+----------------------------------------
2 files changed, 2 insertions(+), 59 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index efe85489..f1555843 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -2,6 +2,7 @@
RISC-V CPU library definitions.
Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
+ Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -96,23 +97,4 @@ RiscVReadMachineImplementId (
VOID
);
-VOID
- RiscVSetSupervisorAddressTranslationRegister (UINT64);
-
-VOID
- RiscVSetSupervisorScratch (UINT64);
-
-UINT64
-RiscVGetSupervisorScratch (
- VOID
- );
-
-VOID
- RiscVSetSupervisorStvec (UINT64);
-
-UINT64
-RiscVGetSupervisorStvec (
- VOID
- );
-
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
index e242c9b8..52ef0788 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
@@ -3,6 +3,7 @@
// RISC-V CPU functions.
//
// Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
+// Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -101,43 +102,3 @@ ASM_FUNC (RiscVReadMachineImplementId)
csrr a0, RISCV_CSR_MACHINE_MIMPID
ret
-//
-// Set Supervisor mode scratch.
-// @param a0 : Value set to Supervisor mode scratch
-//
-ASM_FUNC (RiscVSetSupervisorScratch)
- csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0
- ret
-
-//
-// Get Supervisor mode scratch.
-// @retval a0 : Value in Supervisor mode scratch
-//
-ASM_FUNC (RiscVGetSupervisorScratch)
- csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH
- ret
-
-//
-// Set Supervisor mode trap vector.
-// @param a0 : Value set to Supervisor mode trap vector
-//
-ASM_FUNC (RiscVSetSupervisorStvec)
- csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0
- ret
-
-//
-// Get Supervisor mode scratch.
-// @retval a0 : Value in Supervisor mode trap vector
-//
-ASM_FUNC (RiscVGetSupervisorStvec)
- csrr a0, RISCV_CSR_SUPERVISOR_STVEC
- ret
-
-//
-// Set Supervisor Address Translation and
-// Protection Register.
-//
-ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
- csrw RISCV_CSR_SUPERVISOR_SATP, a0
- ret
-
--
2.34.1
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