[edk2-devel] [edk2-platforms][PATCH V3 08/16] Platform/Loongson: Add CPU DXE driver.
The driver produces EFI_CPU_ARCH_PROTOCOL,
Initialize the exception entry address.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054
Signed-off-by: xianglai li
---
.../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c | 382 ++
.../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h | 151 +++
.../Drivers/CpuDxe/CpuDxe.inf | 56 +++
.../Drivers/CpuDxe/LoongArch64/Exception.c| 338
.../Drivers/CpuDxe/LoongArch64/Fpu.S | 67 +++
.../Drivers/CpuDxe/LoongArch64/LoongArch.S| 292 +
6 files changed, 1286 insertions(+)
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.inf
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Exception.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Fpu.S
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/LoongArch.S
diff --git a/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
new file mode 100644
index 00..bff2bd0c0a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
@@ -0,0 +1,382 @@
+/** @file
+ CPU DXE Module to produce CPU ARCH Protocol
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "CpuDxe.h"
+
+BOOLEAN mInterruptState = FALSE;
+
+/*
+ This function flushes the range of addresses from Start to Start+Length
+ from the processor's data cache. If Start is not aligned to a cache line
+ boundary, then the bytes before Start to the preceding cache line boundary
+ are also flushed. If Start+Length is not aligned to a cache line boundary,
+ then the bytes past Start+Length to the end of the next cache line boundary
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+ supported. If the data cache is fully coherent with all DMA operations, then
+ this function can just return EFI_SUCCESS. If the processor does not support
+ flushing a range of the data cache, then the entire data cache can be
flushed.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param StartThe beginning physical address to flush from the
processor's data
+ cache.
+ @param Length The number of bytes to flush from the processor's
data cache. This
+ function may flush more bytes than Length specifies
depending upon
+ the granularity of the flush operation that the
processor supports.
+ @param FlushTypeSpecifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS The address range from Start to Start+Length
was flushed from
+the processor's data cache.
+ @retval EFI_UNSUPPORTEDT The processor does not support the cache flush
type specified
+by FlushType.
+ @retval EFI_DEVICE_ERROR The address range from Start to Start+Length
could not be flushed
+from the processor's data cache.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESSStart,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ )
+{
+
+ switch (FlushType) {
+case EfiCpuFlushTypeWriteBack:
+ WriteBackDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+ break;
+case EfiCpuFlushTypeInvalidate:
+ InvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+ break;
+case EfiCpuFlushTypeWriteBackInvalidate:
+ WriteBackInvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+ break;
+default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function enables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are enabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the
processor.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ EnableInterrupts ();
+
+ mInterruptState = TRUE;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function disables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are disabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be disabled on t
[edk2-devel] [edk2-platforms][PATCH V3 08/16] Platform/Loongson: Add CPU DXE driver.
The driver produces EFI_CPU_ARCH_PROTOCOL,
Initialize the exception entry address.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4054
Signed-off-by: xianglai li
---
.../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c | 382 ++
.../LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h | 151 +++
.../Drivers/CpuDxe/CpuDxe.inf | 56 +++
.../Drivers/CpuDxe/LoongArch64/Exception.c| 338
.../Drivers/CpuDxe/LoongArch64/Fpu.S | 67 +++
.../Drivers/CpuDxe/LoongArch64/LoongArch.S| 292 +
6 files changed, 1286 insertions(+)
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.h
create mode 100644 Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.inf
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Exception.c
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/Fpu.S
create mode 100644
Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/LoongArch64/LoongArch.S
diff --git a/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
new file mode 100644
index 00..bff2bd0c0a
--- /dev/null
+++ b/Platform/Loongson/LoongArchQemuPkg/Drivers/CpuDxe/CpuDxe.c
@@ -0,0 +1,382 @@
+/** @file
+ CPU DXE Module to produce CPU ARCH Protocol
+
+ Copyright (c) 2021 Loongson Technology Corporation Limited. All rights
reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "CpuDxe.h"
+
+BOOLEAN mInterruptState = FALSE;
+
+/*
+ This function flushes the range of addresses from Start to Start+Length
+ from the processor's data cache. If Start is not aligned to a cache line
+ boundary, then the bytes before Start to the preceding cache line boundary
+ are also flushed. If Start+Length is not aligned to a cache line boundary,
+ then the bytes past Start+Length to the end of the next cache line boundary
+ are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+ supported. If the data cache is fully coherent with all DMA operations, then
+ this function can just return EFI_SUCCESS. If the processor does not support
+ flushing a range of the data cache, then the entire data cache can be
flushed.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param StartThe beginning physical address to flush from the
processor's data
+ cache.
+ @param Length The number of bytes to flush from the processor's
data cache. This
+ function may flush more bytes than Length specifies
depending upon
+ the granularity of the flush operation that the
processor supports.
+ @param FlushTypeSpecifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS The address range from Start to Start+Length
was flushed from
+the processor's data cache.
+ @retval EFI_UNSUPPORTEDT The processor does not support the cache flush
type specified
+by FlushType.
+ @retval EFI_DEVICE_ERROR The address range from Start to Start+Length
could not be flushed
+from the processor's data cache.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESSStart,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ )
+{
+
+ switch (FlushType) {
+case EfiCpuFlushTypeWriteBack:
+ WriteBackDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+ break;
+case EfiCpuFlushTypeInvalidate:
+ InvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+ break;
+case EfiCpuFlushTypeWriteBackInvalidate:
+ WriteBackInvalidateDataCacheRange ((VOID *) (UINTN)Start, (UINTN)Length);
+ break;
+default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function enables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are enabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the
processor.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ EnableInterrupts ();
+
+ mInterruptState = TRUE;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function disables interrupt processing by the processor.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS Interrupts are disabled on the processor.
+ @retval EFI_DEVICE_ERROR Interrupts could not be disabled on t
