Reviewed-by: Chasel Chiu
Thanks,
Chasel
> -Original Message-
> From: Desimone, Nathaniel L
> Sent: Tuesday, June 7, 2022 7:17 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Kubacki, Michael
> ; Chaganty, Rangasai V
> ; Kethi Reddy, Deepika
> ; Esakkithevar, Kathappan
>
> Subject: [edk2-platforms] [PATCH V2 3/4] CometlakeOpenBoardPkg: Indicate
> width of CLK duty cycle in FADT
>
> Set the location of the DUTY_CYCLE field in the P_CNT register and indicate
> the
> width of the clock duty cycle to OS power management
>
> Cc: Chasel Chiu
> Cc: Michael Kubacki
> Cc: Rangasai V Chaganty
> Cc: Deepika Kethi Reddy
> Cc: Kathappan Esakkithevar
> Signed-off-by: Nate DeSimone
> ---
> .../CometlakeURvp/OpenBoardPkgPcd.dsc| 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.
> dsc
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.
> dsc
> index 589b002d06..68dd08423b 100644
> ---
> a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.
> dsc
> +++
> b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd
> +++ .dsc
> @@ -1,7 +1,7 @@
> ## @file
> # PCD configuration build description file for the CometlakeURvp board.
> #
> -# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +# Copyright (c) 2020 - 2022, Intel Corporation. All rights
> +reserved.
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -253,6 +253,13 @@
>gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
>gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
>
> + #
> + # Set the location of the DUTY_CYCLE field in the P_CNT register #
> + and indicate the width of the clock duty cycle to OS power management
> + #
> + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
>#
># The PCDs are used to control the Windows SMM Security Mitigations Table -
> Protection Flags
>#
> --
> 2.27.0.windows.1
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