Re: [edk2-devel] Intel® FSP External Architecture Specification v2.2 Has Been Released

2020-09-03 Thread Nate DeSimone
Hi Canh,

We have not released TigerLakeOpenBoardPkg to 
https://github.com/tianocore/edk2-platforms/tree/master/Platform/Intel yet. It 
should be coming soon. In the meantime, we have Comet Lake, Whiskey Lake, and 
Kaby Lake available now.

Building the Tiger Lake variant will be essentially the same as building the 
older variants, please see this file for build instructions: 
https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/Readme.md

Thanks,
Nate

From: Canh Kha 
Sent: Saturday, August 22, 2020 8:12 PM
To: Desimone, Nathaniel L ; devel@edk2.groups.io
Subject: Re: [edk2-devel] Intel® FSP External Architecture Specification v2.2 
Has Been Released

Hi Nate,
Do you have Tiger Lake platform to build bios with the Tiger Lake FSP? Is there 
a guide?
Thanks,
Canh

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Re: [edk2-devel] Intel® FSP External Architecture Specification v2.2 Has Been Released

2020-08-22 Thread Canh Kha
Hi Nate,
Do you have Tiger Lake platform to build bios with the Tiger Lake FSP? Is there 
a guide?
Thanks,
Canh

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[edk2-devel] Intel® FSP External Architecture Specification v2.2 Has Been Released

2020-07-22 Thread Nate DeSimone
Hi Everyone,

We are pleased to announce that the FSP External Architecture Specification 
v2.2 has been posted to https://www.intel.com/fsp! 

Highlights

* Multi-Phase Silicon Initialization – A new optional API has been added to 
FSP-S to address some of the ongoing community feedback surrounding FSP-S. In 
general, the feedback has been that FSP-S is too monolithic. FspSiliconInit() 
does a large amount of initialization in one API call; so much that it has made 
integration difficult in some cases. For example, firmware update/recovery 
flows. To address this, a new FspMultiPhaseSiInit() API has been added which 
splits FSP-S into multiple parts. This allows the bootloader to add board 
specific code throughout the SiliconInit flow as needed. The breakdown of 
silicon initialization steps may vary per product and will be detailed in the 
Integration Guide. FspMultiPhaseSiInit() is only used in API mode. In dispatch 
mode, equivalent functionality can be achieved using PPIs with less complexity.

* FSP Event Handlers – This new feature enables FSP to generate events messages 
to aid in the debugging of firmware issues. This eliminates the need for FSP to 
directly write debug messages to the UART. Instead FSP signals the bootloader 
to inform it of a new debug message. This allows the bootloader to provide 
board specific methods of reporting debug messages beyond the UART. This brings 
feature parity between dispatch mode and API mode as FSP 2.1 defined a similar 
method for dispatch mode.

This change also helps dispatch mode as well. Since it provides a means for 
FSP-T and early PEI to output debug message before the status code services 
PEIMs are initialized.

Roadmap

TigerLakeFspBinPkg provides the first implementation of FSP 2.2. Tiger Lake FSP 
implements 2 phases for FSP-S: FspSiliconInit() will return after TCSS (“Type-C 
Sub System” – Integrated USB-C & Thunderbolt 4) initialization is complete. The 
second phase, invoked by FspMultiPhaseSiInit(), will initialize the graphics 
framebuffer and lock SAI/SPI writes. This allows board specific USB-C 
programming to be done before FSP attempts to start early video, and also 
provides a potentially convenient location for firmware update flows. Looking 
forward, our upcoming Alder Lake platform will also have FSP 2.2 support.

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