https://github.com/tianocore/edk2/pull/828 for this change, be merged.
-Original Message-
From: Gao, Liming
Sent: 2020年7月27日 10:36
To: Javeed, Ashraf ; devel@edk2.groups.io
Cc: Kinney, Michael D
Subject: RE: [PATCH V4 0/2] CXL Specification Registers
This version is good to me. Reviewed-by: Liming Gao
-Original Message-
From: Javeed, Ashraf
Sent: 2020年7月25日 2:26
To: devel@edk2.groups.io
Cc: Kinney, Michael D ; Gao, Liming
Subject: [PATCH V4 0/2] CXL Specification Registers
These 2 patches introduces the Compute Express Link (CXL) Specificition defined
registers.
The Cxl11.h has the actual register definitions of the CXL Specification
Revision 1.1; and the Cxl.h is the main header file to include all versions of
the CXL register definitions.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
--
Ashraf Javeed (2):
MdePkg/Include/IndustryStandard: CXL 1.1 Registers
MdePkg/Include/IndustryStandard: Main CXL header
MdePkg/Include/IndustryStandard/Cxl.h | 22 ++
MdePkg/Include/IndustryStandard/Cxl11.h | 569
+
MdePkg/Include/IndustryStandard/Pci.h | 6 ++
3 files changed, 593 insertions(+), 4 deletions(-) create mode 100644
MdePkg/Include/IndustryStandard/Cxl.h
create mode 100644 MdePkg/Include/IndustryStandard/Cxl11.h
--
2.21.0.windows.1
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