Hi Pranav,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 10/05/2021 09:06 PM, Pranav Madhu wrote:
The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-E1-Edge platform with this information.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 252
2 files changed, 254 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 2dd2275665a2..04ef2bfcaa26 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdE1Edge/Dsdt.asl
RdE1Edge/Madt.aslc
+ RdE1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
new file mode 100644
index ..91baab73d108
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
@@ -0,0 +1,252 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
+* platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
+* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
+* Each cluster includes a 2MB L3 cache. The platform also includes a system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include
+#include
+#include
+#include
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define THREAD_PER_CORE_E1 2
+
+/*!
+ \brief Define helper macro for populating processor thread information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+ \param ThreadId CPU thread number.
+*/
+#define PPTT_THREAD_INIT(PackageId, ClusterId, CpuId, ThreadId)
\
+ {
\
+EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
+ sizeof (RDE1EDGE_PPTT_THREAD),/* Length */
\
+ PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+Package.Cluster[ClusterId].Core[CpuId]), /* Parent */
\
+ ((PackageId << 5) | (ClusterId << 4) | (CpuId << 1) | ThreadId),
\
+/* ACPI Id */
\
+ 0 /* Num of private resource */
\
+)
\
+ }
+
+/*!
+ \brief Define helper macro for populating processor core information.
+ \param PackageId Package instance number.
+ \param ClusterId Cluster instance number.
+ \param CpuId CPU instance number.
+*/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId)
\
+ {
\
+/* Parameters for CPU Core */
\
+EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
+ OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */
\
+ PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+Package.Cluster[ClusterId]),/* Parent */
\
+ 0,/* ACPI Id */
\
+ 2 /* Num of private resource */
\
+),
\
+
\
+/* Offsets of the private resources */
\
+{
