Re: MMU/Cache analysis for OpenRISC
On Tue, Jul 29, 2014 at 3:18 AM, Gedare Bloom ged...@rtems.org wrote: On Mon, Jul 28, 2014 at 1:20 PM, Hesham Moustafa heshamelmat...@gmail.com wrote: Hi, I have read about MMU and Caches in OpenRISC to start implementing related managers in the new or1k port. Before beginning to write the code, I would like to introduce some of the architecture details regarding MMU and Caches. There are both; data and instruction MMU, TLBs, Caches. First, page tables there are divided into two levels; one level can be used with 32 GB or 16 MB pages, and two-levels for 8 KB pages. 32 GB and 16 MB would be too big for RTEMS, and that led us to two-level 8 KB pages. Two-level pages would hurt the performance unless we setup TLBs at startup statically; there are 128 TLB entries. Other than defined run-time sections, the remaining pool of TLB entries can be used for dynamic page-table setup. So you can only have a static setup of at most 1MB (128 entries by 8K)? Yes if we only used 2 level page tables. Is the only use case for the MMU / virtual memory to have memory protection? It provides address translation, memory protection, cahce and some features to implement demand paging. Can the 16MB superpages be mixed with the 8K pages? This can accomodate some user who might have more than 16MB of memory but wants memory protection in a static configuration. I think yes they can be mixed as there is L (Last) flag in rach PTE to decide whether it's in a page directory or it points to actual PTE for translation. This is [1] the related section at the OpenRISC architecture manual. [1] http://openrisc.github.io/or1k.html#__RefHeading__504777_595890882 -Gedare Protection domains are set into a special purpose registers forming 7 groups, and each PTE can associates its protection domain to one of them. Protection provides control over pages for read, write, and execute accesses. Christian, I would like to know more about or1ksim implementation. I guess TLB misses are handled in software and accordingly software look-up operation. Also I would say that PTE reloads are also handled in software. Please correct me if I am wrong. Cache is working with PTEs; each of of which has some control bits to define the Cache attributes for its page. Given the previous little piece of info, I would appreciate your opinion regarding implementation decisions for or1k RTEMS port. Thanks, Hesham ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 1/3] rbtree: Format
On 22/07/2014 11:38 pm, Gedare Bloom wrote: Thanks, I have added a section at http://www.rtems.org/wiki/index.php/Coding_Conventions#Tools and uploaded/linked to your configuration. Why not add to the source tree with a note ? Wiki pages are great if you know they exist !! Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] Fix headers and add RTC to altera-cyclone-v BSP.
Hello, thanks for clarifying the licensing issues with the hwlib Chris. After that problem is resolved, you can find the resubmission of the second patch as an answer to this mail. Please don't hesitate to make any comments to this or one of the other two patches. Kind regards Christian Mauderer ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
RSB 0.4.0
Hi, I have pushed RSB 0.4.0. It contains the following: - GCC 4.8.3 targets are arm, avr, bfin, h8300, i386, m32c, m32r, m68k, microblaze, mips, moxie, powerpc, sh, sparc, sparc64. Newlib is CVS 26-Jul-2014. - GCC 4.9.1 targets are lm32, nios2. Newlib is CVS 26-Jul-201.4 - Show the download status when downloading. - Add checksum support for files. - ARM support for Cortex-M4 and Cortex-R based chips. - Add support for building 3rd Party packages for RTEMS. Add NTP and Net-SNMP as examples. With the checksum support if a file does not have checksum defined a warning message is generated. Please send me patches with the hash to help clean this up. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] Fix headers and add RTC to altera-cyclone-v BSP.
On 29/07/2014 5:37 pm, Christian Mauderer wrote: After that problem is resolved, you can find the resubmission of the second patch as an answer to this mail. The original message has been approved. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Raspberry Pi BSP SPI bus
Hello, The Raspberry Pi SPI bus on the P1 GPIO header is already working, both through polling and interrupts on the bus FIFOS, and has been tested with a microchip 23k256 SRAM device. The bus code can be found in: https://github.com/asuol/rtems/blob/GPIO_API/c/src/lib/libbsp/arm/raspberrypi/i2c/spi.c The 23k256 SRAM minimal device driver (based in the libchip/i2c/spi-memdrv driver) used to test the bus can be found in: https://github.com/asuol/rtems/blob/GPIO_API/c/src/libchip/i2c/23k256.c The application that tests the device can be found in: https://github.com/asuol/rtems/blob/GPIO_API/testsuites/samples/SPI_23k256_TEST/init.c Alan, from what I have seen of your adafruit FRAM device datasheet I recon that it should also work with my 23k256 driver if you comment out lines 65 through 106, as it just sets the device in sequential mode which your device already uses. The current pending issues with the SPI implementation are: - Currently the bus is registered in the system through a function called on an application. Should it stay this way or should the bus be registered in the system in the predriver-hook during the BSP startup? - It can currently work either in polling or interrupt mode, as well as in either 3-wire mode (miso, mosi, and sclk) or in 2-wire mode (bi-directional mode by turning the bus around in the mosi data line, although this stills needs to be tested with another device). These configuration options are currently made staticaly during the SPI bus initialization, but they should be made elsewhere by the user. Should these options be passed to the bus register function or through define constants? Thanks, André Marques. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Fwd: [ANNOUNCEMENT] GDB 7.8 released!
Original Message From: Joel Brobecker brobec...@adacore.com Sent: July 29, 2014 10:59:39 AM EDT To: g...@sourceware.org g...@sourceware.org Subject: [ANNOUNCEMENT] GDB 7.8 released! GDB 7.8 released! Release 7.8 of GDB, the GNU Debugger, is now available via anonymous FTP. GDB is a source-level debugger for Ada, C, C++, Objective-C, Pascal and many other languages. GDB can target (i.e., debug programs running on) more than a dozen different processor architectures, and GDB itself can run on most popular GNU/Linux, Unix and Microsoft Windows variants. You can download GDB from the GNU FTP server in the directory: ftp://ftp.gnu.org/gnu/gdb The vital stats: Size md5sumName 17MiB bd958fe9019d7c7896f29f6724a764ed gdb-7.8.tar.xz 32MiB 38d816d641093db2e13ba284e26090b4 gdb-7.8.tar.gz There is a web page for GDB at: http://www.gnu.org/software/gdb/ That page includes information about GDB mailing lists (an announcement mailing list, developers discussion lists, etc.), details on how to access GDB's source repository, locations for development snapshots, preformatted documentation, and links to related information around the net. We will put errata notes and host-specific tips for this release on-line as any problems come up. All mailing lists archives are also browsable via the web. GDB 7.8 brings new targets, features and improvements, including: * Guile scripting support. * Python scripting enhancements. * New commands: ** guile ** guile-repl ** info auto-load guile-scripts [REGEXP] * New options: ** maint ada set ignore-descriptive-types (on|off) ** maint set target-async (on|off) ** set|show auto-load guile-scripts (on|off) ** set|show auto-connect-native-target ** set|show guile print-stack (none|message|full) ** set|show mi-async (on|off) ** set|show print symbol-loading (off|brief|full) ** set|show record btrace replay-memory-access (read-only|read-write) * Deprecated commands: ** dll-symbols and its two aliases (add-shared-symbol-files and assf). Use the sharedlibrary command instead. ** set|show remotebaud. Use set|show serial baud instead. * Remote Protocol: ** The qXfer:btrace:read packet supports a new annex 'delta'. * GDB/MI: ** A new option -gdb-set mi-async replaces -gdb-set target-async. * New target configurations: ** PowerPC64 GNU/Linux little-endian powerpc64le-*-linux* * btrace enhancements: ** The btrace record target now supports the 'record goto' command. ** The btrace record target supports limited reverse execution and replay. * ISO C99 variable length automatic arrays support. * It is no longer required to set target-async on in order to use background execution commands (e.g., c, s, etc.). * catch syscall now implemented on s390*-linux* targets. * The compare-sections command now works on all targets. * The target native command now connects to the native target, and can be used to launch native programs, even if set auto-connect-native-target is set to off. For a complete list and more details on each item, please see the gdb/NEWS file. -- Joel Brobecker ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
