Re: [PATCH v2 2/2] libbsp/arm: Fix the local interrupt mask disable/enable calls.
On 16/08/16 07:45, Chris Johns wrote: --- c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c b/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c index f650009..cfad45f 100644 --- a/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c +++ b/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c @@ -88,10 +88,10 @@ uint32_t arm_cp15_set_translation_table_entries( rtems_interrupt_level level; uint32_t section_flags_of_first_entry; - rtems_interrupt_disable(level); + rtems_interrupt_local_disable(level); section_flags_of_first_entry = set_translation_table_entries(begin, end, section_flags); - rtems_interrupt_enable(level); + rtems_interrupt_local_enable(level); return section_flags_of_first_entry; } We should only change this if this is known to work on SMP. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] arm/cortex-a: Fix cache flush/invalidate after u-boot.
On 16/08/16 07:40, Chris Johns wrote: On 16/08/2016 15:36, Sebastian Huber wrote: On 16/08/16 07:35, Chris Johns wrote: On 16/08/2016 15:32, Sebastian Huber wrote: https://docs.rtems.org/doc-current/share/rtems/html/c_user/Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor.html#Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor Thank you. I will send a patch in for this. Is a local interrupt disable sufficient on SMP configurations? I do not know. I am only fixing the code because it does not build on SMP. It is intentional that this code doesn't build on SMP. This change to rtems_interrupt_local_disable() flags places which need some attention to correctly work on SMP or need to be disabled. See also: https://lists.rtems.org/pipermail/devel/2015-June/011535.html -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 2/2] libbsp/arm: Fix the local interrupt mask disable/enable calls.
--- c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c b/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c index f650009..cfad45f 100644 --- a/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c +++ b/c/src/lib/libbsp/arm/shared/arm-cp15-set-ttb-entries.c @@ -88,10 +88,10 @@ uint32_t arm_cp15_set_translation_table_entries( rtems_interrupt_level level; uint32_t section_flags_of_first_entry; - rtems_interrupt_disable(level); + rtems_interrupt_local_disable(level); section_flags_of_first_entry = set_translation_table_entries(begin, end, section_flags); - rtems_interrupt_enable(level); + rtems_interrupt_local_enable(level); return section_flags_of_first_entry; } -- 2.4.6 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 1/2] arm/cortex-a: Fix cache flush/invalidate after u-boot.
This is a copy of the patch from Pavel to fix some strange behaviour with
data cache, instruction cache and MMU being enabled by u-boot on the
RaspberryPi.
Closes #2774.
---
.../libbsp/arm/shared/include/arm-a9mpcore-start.h | 38 ++
c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 1 +
c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am | 4 +++
3 files changed, 43 insertions(+)
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
index 7d6185b..2304650 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
@@ -30,8 +30,10 @@
#include
#include
#include
+#include
#include
+
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
@@ -129,8 +131,44 @@ BSP_START_TEXT_SECTION static inline void
arm_a9mpcore_start_hook_0(void)
volatile a9mpcore_scu *scu =
(volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
+ uint32_t sctlr_val;
+
+ sctlr_val = arm_cp15_get_control();
+ /*
+ * Current U-boot loader seems to start kernel image
+ * with I and D caches on and MMU enabled.
+ * If RTEMS application image finds that cache is on
+ * during startup then disable caches.
+ */
+ if (sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
+if (sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
+ /*
+ * If the data cache is on then ensure that it is clean
+ * before switching off to be extra carefull.
+ */
+ if (cpu_id == 0) {
+rtems_cache_flush_entire_data();
+rtems_cache_invalidate_entire_data();
+ }
+}
+arm_cp15_flush_prefetch_buffer();
+sctlr_val &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M |
ARM_CP15_CTRL_A);
+arm_cp15_set_control(sctlr_val);
+ }
+ if (cpu_id == 0) {
+rtems_cache_invalidate_entire_data();
+rtems_cache_invalidate_entire_instruction();
+ } else {
+arm_cache_l1_invalidate_entire_data();
+arm_cache_l1_invalidate_entire_instruction();
+ }
arm_cp15_branch_predictor_invalidate_all();
+ arm_cp15_tlb_invalidate();
+ arm_cp15_flush_prefetch_buffer();
+
+ /* Clear Translation Table Base Control Register */
+ arm_cp15_set_translation_table_base_control_register(0);
if (cpu_id == 0) {
arm_a9mpcore_start_scu_enable(scu);
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
index 8e6f8c3..1ccc33c 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
@@ -43,6 +43,7 @@ include_bsp_HEADERS += ../shared/include/arm-gic-irq.h
include_bsp_HEADERS += ../shared/include/arm-gic-regs.h
include_bsp_HEADERS += ../shared/include/arm-gic-tm27.h
include_bsp_HEADERS += ../shared/include/arm-release-id.h
+include_bsp_HEADERS += ../shared/include/arm-cache-l1.h
include_bsp_HEADERS += include/cadence-i2c.h
include_bsp_HEADERS += include/cadence-i2c-regs.h
include_bsp_HEADERS += include/i2c.h
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am
b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am
index a75c344..f97a453 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am
@@ -126,6 +126,10 @@ $(PROJECT_INCLUDE)/bsp/arm-release-id.h:
../shared/include/arm-release-id.h $(PR
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-release-id.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-release-id.h
+$(PROJECT_INCLUDE)/bsp/arm-cache-l1.h: ../shared/include/arm-cache-l1.h
$(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-cache-l1.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-cache-l1.h
+
$(PROJECT_INCLUDE)/bsp/cadence-i2c.h: include/cadence-i2c.h
$(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/cadence-i2c.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/cadence-i2c.h
--
2.4.6
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Re: [PATCH] arm/cortex-a: Fix cache flush/invalidate after u-boot.
On 16/08/2016 15:36, Sebastian Huber wrote: On 16/08/16 07:35, Chris Johns wrote: On 16/08/2016 15:32, Sebastian Huber wrote: https://docs.rtems.org/doc-current/share/rtems/html/c_user/Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor.html#Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor Thank you. I will send a patch in for this. Is a local interrupt disable sufficient on SMP configurations? I do not know. I am only fixing the code because it does not build on SMP. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] arm/cortex-a: Fix cache flush/invalidate after u-boot.
On 16/08/16 07:35, Chris Johns wrote: On 16/08/2016 15:32, Sebastian Huber wrote: https://docs.rtems.org/doc-current/share/rtems/html/c_user/Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor.html#Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor Thank you. I will send a patch in for this. Is a local interrupt disable sufficient on SMP configurations? -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] arm/cortex-a: Fix cache flush/invalidate after u-boot.
On 16/08/2016 15:32, Sebastian Huber wrote: https://docs.rtems.org/doc-current/share/rtems/html/c_user/Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor.html#Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor Thank you. I will send a patch in for this. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] arm/cortex-a: Fix cache flush/invalidate after u-boot.
On 16/08/16 03:49, Chris Johns wrote: On 15/08/2016 16:54, Pavel Pisa wrote: If you test that chage is OK for Zynq with SMP then I reintroduce change to RPi code (it would worth to have RPi2 SMP working for that testing but that is near to bottom of my own TODO list). My debug server app does not link when SMP is enabled. I am getting: [13/13] Linking build/arm-rtems4.12-xilinx_zynq_zedboard/net-app.exe /opt/work/chris/rtems/kernel/4.12/arm-rtems4.12/xilinx_zynq_zedboard/lib/librtemsbsp.a(libbsp_a-arm-cp15-set-ttb-entries.o): In function `arm_cp15_set_translation_table_entries': /opt/work/chris/rtems/kernel/rtems.master/c/src/lib/libbsp/arm/xilinx-zynq/../shared/arm-cp15-set-ttb-entries.c:91: undefined reference to `rtems_interrupt_disable' /opt/work/chris/rtems/kernel/rtems.master/c/src/lib/libbsp/arm/xilinx-zynq/../shared/arm-cp15-set-ttb-entries.c:94: undefined reference to `rtems_interrupt_enable' It seems these functions are not available for SMP however these calls map to _ISR_level, _ISR_Local_disable and _ISR_Local_enable and these calls are used in the SMP test testsuites/smptests/smpthreadlife01/init.c. I am confused. Sebastian? https://docs.rtems.org/doc-current/share/rtems/html/c_user/Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor.html#Interrupt-Manager-INTERRUPT_005fLOCAL_005fDISABLE-_002d-Disable-Interrupts-on-Current-Processor -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] arm/cortex-a: Fix cache flush/invalidate after u-boot.
On 15/08/2016 16:54, Pavel Pisa wrote: If you test that chage is OK for Zynq with SMP then I reintroduce change to RPi code (it would worth to have RPi2 SMP working for that testing but that is near to bottom of my own TODO list). My debug server app does not link when SMP is enabled. I am getting: [13/13] Linking build/arm-rtems4.12-xilinx_zynq_zedboard/net-app.exe /opt/work/chris/rtems/kernel/4.12/arm-rtems4.12/xilinx_zynq_zedboard/lib/librtemsbsp.a(libbsp_a-arm-cp15-set-ttb-entries.o): In function `arm_cp15_set_translation_table_entries': /opt/work/chris/rtems/kernel/rtems.master/c/src/lib/libbsp/arm/xilinx-zynq/../shared/arm-cp15-set-ttb-entries.c:91: undefined reference to `rtems_interrupt_disable' /opt/work/chris/rtems/kernel/rtems.master/c/src/lib/libbsp/arm/xilinx-zynq/../shared/arm-cp15-set-ttb-entries.c:94: undefined reference to `rtems_interrupt_enable' It seems these functions are not available for SMP however these calls map to _ISR_level, _ISR_Local_disable and _ISR_Local_enable and these calls are used in the SMP test testsuites/smptests/smpthreadlife01/init.c. I am confused. Sebastian? Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] arm/cortex-a: Fix cache flush/invalidate after u-boot.
On 15/08/2016 16:54, Pavel Pisa wrote:
if (cpu_id == 0) {
+rtems_cache_invalidate_entire_data();
+rtems_cache_invalidate_entire_instruction();
} else {
arm_cache_l1_invalidate_entire_data();
arm_cache_l1_invalidate_entire_instruction();
}
The header arm-cache-l1.h is not pre-installed for the zedboard BSP. I
will have to add this.
Chris
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