Re: Error in building application with rpi BSP with waf build system

2020-05-31 Thread Utkarsh Rai 
On Mon, Jun 1, 2020 at 9:32 AM Utkarsh Rai  wrote:

> Hello,
>
> I was unable to build a sample app for raspberrypi, I followed the docs
>  and was able
> to build the app for Xilinx-qemu and beagleboard.
>
> The waf configure command was - ./waf configure
> --rtems=$HOME/sandbox/rtems/5 --rtems-bsp=arm/raspberrypi
>
> The log file shows the following message-
> "
> # project  configured on Mon Jun  1 09:19:15 2020 by
> # waf 2.0.19 (abi 20, python 20711f0 on linux2)
> # using ./waf configure --rtems=/home/utkarsh/sandbox/rtems/5
> --rtems-bsp=arm/raspberrypi
> #
> 
> Setting top to
> /home/utkarsh/Desktop/rtems_test
> 
> Setting out to
> /home/utkarsh/Desktop/rtems_test/build
> from /home/utkarsh/Desktop/rtems_test: No valid arch/bsps found"
>
> A ./rtems-bsps shows that the valid BSP name for RPI is the same as that
> in configure command.
> Is there a typo in my configure command or the waf build does not support
> raspberrypi BSP? Kindly point out my error.
>
> Regards,
> Utkarsh Rai.
>

Sorry, this is resolved, I had deleted my RPI BSP build and was then trying
to build the app.
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Error in building application with rpi BSP with waf build system

2020-05-31 Thread Utkarsh Rai 
Hello,

I was unable to build a sample app for raspberrypi, I followed the docs
 and was able
to build the app for Xilinx-qemu and beagleboard.

The waf configure command was - ./waf configure
--rtems=$HOME/sandbox/rtems/5 --rtems-bsp=arm/raspberrypi

The log file shows the following message-
"
# project  configured on Mon Jun  1 09:19:15 2020 by
# waf 2.0.19 (abi 20, python 20711f0 on linux2)
# using ./waf configure --rtems=/home/utkarsh/sandbox/rtems/5
--rtems-bsp=arm/raspberrypi
#

Setting top to
/home/utkarsh/Desktop/rtems_test

Setting out to
/home/utkarsh/Desktop/rtems_test/build
from /home/utkarsh/Desktop/rtems_test: No valid arch/bsps found"

A ./rtems-bsps shows that the valid BSP name for RPI is the same as that in
configure command.
Is there a typo in my configure command or the waf build does not support
raspberrypi BSP? Kindly point out my error.

Regards,
Utkarsh Rai.
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[PATCH v1 8/9] smpsignal01: Change state before sending the signal

2020-05-31 Thread Jan Sommer 
The signal handler of the consumer might start executing
before rtems_signal_send of the producer returns.
Therefore change the state to SIG_1_SENT before sending the signal.
---
 testsuites/smptests/smpsignal01/init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/testsuites/smptests/smpsignal01/init.c 
b/testsuites/smptests/smpsignal01/init.c
index 36a66bea9b..025e84c6a2 100644
--- a/testsuites/smptests/smpsignal01/init.c
+++ b/testsuites/smptests/smpsignal01/init.c
@@ -81,10 +81,10 @@ static void signal_send(test_context *ctx, test_state 
new_state)
 {
   rtems_status_code sc;
 
+  change_state(ctx, new_state);
   sc = rtems_signal_send(ctx->consumer, TEST_SIGNAL);
   rtems_test_assert(sc == RTEMS_SUCCESSFUL);
 
-  change_state(ctx, new_state);
 }
 
 static void check_consumer_processor(const test_context *ctx)
-- 
2.12.3

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[PATCH v1 3/9] bsp/pc386: Update GDT to work for SMP

2020-05-31 Thread Jan Sommer 
Create a GS segment in the GDT for each processor for storing TLS.
This makes the GDT in startAP.S obsolete as all processors now share the
same GDT, which is passed to each AP at startup.

The correct segment for each processor is calculated in cpu_asm.S.

Update #3335
---
 bsps/i386/pc386/include/bsp/tblsizes.h|  8 ++-
 bsps/i386/pc386/start/getcpuid.c  |  2 +-
 bsps/i386/pc386/start/ldsegs.S|  4 +++-
 bsps/i386/pc386/start/smp-imps.c  | 15 
 bsps/i386/pc386/start/startAP.S   | 39 +--
 cpukit/score/cpu/i386/cpu_asm.S   | 11 +
 cpukit/score/cpu/i386/include/rtems/asm.h | 26 +
 7 files changed, 59 insertions(+), 46 deletions(-)

diff --git a/bsps/i386/pc386/include/bsp/tblsizes.h 
b/bsps/i386/pc386/include/bsp/tblsizes.h
index 13429dc85f..978cde2b3e 100644
--- a/bsps/i386/pc386/include/bsp/tblsizes.h
+++ b/bsps/i386/pc386/include/bsp/tblsizes.h
@@ -20,5 +20,11 @@
 #include 
 
 #define IDT_SIZE (256)
-#define NUM_SYSTEM_GDT_DESCRIPTORS 4
+/* We have 3 fixed segments (NULL, text, data) + a GS segment for TLS */
+#ifdef RTEMS_SMP
+/* Need one GS segment for each processor (x86 can have up to 256 processors) 
*/
+#define NUM_SYSTEM_GDT_DESCRIPTORS 3+256
+#else
+#define NUM_SYSTEM_GDT_DESCRIPTORS 3+1
+#endif
 #define GDT_SIZE (NUM_SYSTEM_GDT_DESCRIPTORS + NUM_APP_DRV_GDT_DESCRIPTORS)
diff --git a/bsps/i386/pc386/start/getcpuid.c b/bsps/i386/pc386/start/getcpuid.c
index c5284d0069..4918a2a970 100644
--- a/bsps/i386/pc386/start/getcpuid.c
+++ b/bsps/i386/pc386/start/getcpuid.c
@@ -17,6 +17,6 @@ unsigned imps_lapic_addr = ((unsigned)(_dummy)) - 
LAPIC_ID;
 
 uint32_t _CPU_SMP_Get_current_processor( void )
 {
-  return APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
+  return imps_apic_cpu_map[APIC_ID(IMPS_LAPIC_READ(LAPIC_ID))];
 }
 
diff --git a/bsps/i386/pc386/start/ldsegs.S b/bsps/i386/pc386/start/ldsegs.S
index b56bf836f0..9ed66ef1a3 100644
--- a/bsps/i386/pc386/start/ldsegs.S
+++ b/bsps/i386/pc386/start/ldsegs.S
@@ -191,9 +191,11 @@ SYM (_Global_descriptor_table):
.word 0x, 0
.byte 0, 0x92, 0xcf, 0
 
-   /* gs segment */
+   /* gs segment(s) */
+   .rept (NUM_SYSTEM_GDT_DESCRIPTORS - 3)
.word 0x, 0
.byte 0, 0x92, 0xcf, 0
+   .endr
 
 /* allocated space for user segments */
 .rept (GDT_SIZE - NUM_SYSTEM_GDT_DESCRIPTORS)
diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c
index 58d9178f90..6480c0d25e 100644
--- a/bsps/i386/pc386/start/smp-imps.c
+++ b/bsps/i386/pc386/start/smp-imps.c
@@ -83,6 +83,7 @@
 #include 
 
 extern void _pc386_delay(void);
+extern uint32_t* gdtdesc;
 
 /* #define KERNEL_PRINT(_format)   printk(_format) */
 
@@ -258,10 +259,10 @@ boot_cpu(imps_processor *proc)
* under the 1MB boundary.
*/
 
-  uint32_t *reset;
+  volatile uint32_t *reset;
 
   bootaddr = (512-64)*1024;
-  reset= (uint32_t *)bootaddr;
+  reset= (volatile uint32_t *)bootaddr;
 
   memcpy(
 (char *) bootaddr,
@@ -269,9 +270,14 @@ boot_cpu(imps_processor *proc)
 (size_t)_binary_appstart_bin_size
   );
 
+  /* Pass start function, stack region and gdtdescr to AP
+   * see startAP.S for location */
   reset[1] = (uint32_t)secondary_cpu_initialize;
   reset[2] = (uint32_t)_Per_CPU_Get_by_index(apicid)->interrupt_stack_high;
-
+  memcpy(
+   (char*) [3],
+   ,
+   6);
   /*
*  Generic CPU startup sequence starts here.
*/
@@ -325,8 +331,6 @@ boot_cpu(imps_processor *proc)
   CMOS_WRITE_BYTE(CMOS_RESET_CODE, 0);
   *((volatile unsigned *) bios_reset_vector) = 0;
 
-  printk("\n");
-
   return success;
 }
 
@@ -359,6 +363,7 @@ add_processor(imps_processor *proc)
 
 /* AP booted successfully, increase number of available cores */
 imps_num_cpus++;
+printk("#%d  Application Processor (AP)\n", imps_apic_cpu_map[apicid]);
   }
 }
 
diff --git a/bsps/i386/pc386/start/startAP.S b/bsps/i386/pc386/start/startAP.S
index 0f81c03144..024c1f70fb 100644
--- a/bsps/i386/pc386/start/startAP.S
+++ b/bsps/i386/pc386/start/startAP.S
@@ -73,9 +73,12 @@ app_processor_start:
  */
 .align 4
 app_cpu_start:
-   .long   0
+.long   0
 app_cpu_stack:
-   .long   0
+.long   0
+app_gdt_descr:
+.word   0   /* GDT size */
+.long   0   /* GDT location */
 
 setup_processor:
 movw%cs, %ax   # Initialize the rest of
@@ -87,7 +90,7 @@ setup_processor:
 | Bare PC machines boot in real mode! We have to turn protected mode 
on.
 
+-*/
 
-lgdtgdtptr - app_processor_start  # load Global Descriptor Table
+lgdtapp_gdt_descr - app_processor_start  # load Global Descriptor 
Table
 
 movl%cr0, %eax
 orl $CR0_PE, %eax
@@ -113,33 +116,3 @@ start_32bit:
 movl$0, app_cpu_stack
 /* Switch to the higher level

[PATCH v1 6/9] bsps/pc386: Fix Clock_isr for SMP

2020-05-31 Thread Jan Sommer 
- Do not forward Clock_isr through Clock_driver_support_at_tick as this
will cause every processor to send IPIs with Clock_isr therby creating
an infinie loop
- Instead the processor handling the clock interrupt causes all other
processors to call rtems_timecounter_tick to update their tick count
---
 bsps/i386/pc386/clock/ckinit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bsps/i386/pc386/clock/ckinit.c b/bsps/i386/pc386/clock/ckinit.c
index d6e4b4..09afe73cde 100644
--- a/bsps/i386/pc386/clock/ckinit.c
+++ b/bsps/i386/pc386/clock/ckinit.c
@@ -73,7 +73,7 @@ extern volatile uint32_t Clock_driver_ticks;
 Processor_mask targets; \
 _Processor_mask_Assign(, _SMP_Get_online_processors()); \
 _Processor_mask_Clear(, _SMP_Get_current_processor());  \
-_SMP_Multicast_action(, Clock_isr, NULL);   \
+_SMP_Multicast_action(, rtems_timecounter_tick, NULL); 
  \
   } while (0)
 #endif
 
-- 
2.12.3

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[PATCH v1 4/9] bsp/pc386: Update context switch and restore

2020-05-31 Thread Jan Sommer 
Uses similar flow in cpu_asm.S for i386 as for arm.
---
 cpukit/score/cpu/i386/cpu_asm.S | 63 +++--
 cpukit/score/cpu/i386/include/rtems/score/cpu.h |  4 +-
 2 files changed, 51 insertions(+), 16 deletions(-)

diff --git a/cpukit/score/cpu/i386/cpu_asm.S b/cpukit/score/cpu/i386/cpu_asm.S
index 9e1e848bbd..6031f6914e 100644
--- a/cpukit/score/cpu/i386/cpu_asm.S
+++ b/cpukit/score/cpu/i386/cpu_asm.S
@@ -51,6 +51,8 @@
 
 SYM (_CPU_Context_switch):
 movl  RUNCONTEXT_ARG(esp),eax  /* eax = running threads context */
+GET_SELF_CPU_CONTROL edx   /* edx has address for per_CPU 
information */
+movl  PER_CPU_ISR_DISPATCH_DISABLE(edx),ecx
 pushf  /* push eflags */
 popl  REG_EFLAGS(eax)  /* save eflags */
 movl  esp,REG_ESP(eax) /* save stack pointer */
@@ -58,26 +60,29 @@ SYM (_CPU_Context_switch):
 movl  ebx,REG_EBX(eax) /* save ebx */
 movl  esi,REG_ESI(eax) /* save source register */
 movl  edi,REG_EDI(eax) /* save destination register */
+movl  ecx, I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE(eax)
 
-#ifdef RTEMS_SMP
-/* The executing context no longer executes on this processor */
-movb  $0, I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(eax)
-#endif
-
+movl  eax,ecx  /* ecx = running threads context */
 movl  HEIRCONTEXT_ARG(esp),eax /* eax = heir threads context */
 
 #ifdef RTEMS_SMP
-/* Wait for heir context to stop execution */
-1:
-movb  I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(eax), bl
-testb bl, bl
-jne   1b
-
-/* The heir context executes now on this processor */
-movb  $1, I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(eax)
+  /*
+   * The executing thread no longer executes on this processor.  Switch
+   * the stack to the temporary interrupt stack of this processor.  Mark
+   * the context of the executing thread as not executing.
+   */
+leal  PER_CPU_INTERRUPT_FRAME_AREA + 
CPU_INTERRUPT_FRAME_SIZE(edx),esp
+movb  $0, I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(ecx)
+
+.L_check_is_executing:
+lock bts  $0,I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET(eax)  /* 
Indicator in carry flag */
+jc.L_get_potential_new_heir
 #endif
 
-restore:
+/* Start restoring context */
+.L_restore:
+movl  I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE(eax),ecx
+movl  ecx,PER_CPU_ISR_DISPATCH_DISABLE(edx)
 pushl REG_EFLAGS(eax)  /* push eflags */
 popf   /* restore eflags */
 movl  REG_ESP(eax),esp /* restore stack pointer */
@@ -110,7 +115,35 @@ restore:
 
 SYM (_CPU_Context_restore):
 movl  NEWCONTEXT_ARG(esp),eax  /* eax = running threads context */
-jmp   restore
+GET_SELF_CPU_CONTROL edx   /* edx has address for per_CPU 
information */
+jmp   .L_restore
+
+#ifdef RTEMS_SMP
+
+.L_get_potential_new_heir:
+
+/* We may have a new heir */
+
+/* Read the executing and heir */
+movlPER_CPU_OFFSET_EXECUTING(edx),ebx
+movlPER_CPU_OFFSET_HEIR(edx),esi
+
+/*
+ * Update the executing only if necessary to avoid cache line
+ * monopolization.
+ */
+cmp esi,ebx
+je  .L_check_is_executing
+
+/* Calculate the heir context pointer */
+addlesi,eax
+sublebx,eax
+
+/* Update the executing */
+movlesi,PER_CPU_OFFSET_EXECUTING(edx)
+
+jmp .L_check_is_executing
+#endif
 
 /*void _CPU_Context_save_fp_context( _context_ptr )
  *  void _CPU_Context_restore_fp_context( _context_ptr )
diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpu.h 
b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
index 5d14455563..7669c4a0cf 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpu.h
@@ -115,9 +115,10 @@ extern "C" {
 #define I386_CONTEXT_CONTROL_EDI_OFFSET 20
 #define I386_CONTEXT_CONTROL_GS_0_OFFSET 24
 #define I386_CONTEXT_CONTROL_GS_1_OFFSET 28
+#define I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 32
 
 #ifdef RTEMS_SMP
-  #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 32
+  #define I386_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 36
 #endif
 
 /* structures */
@@ -136,6 +137,7 @@ typedef struct {
   uint32_tesi;/* extended source index register*/
   uint32_tedi;/* extended destination index flags register */
   segment_descriptors gs; /* gs segment descriptor */
+  uint32_t isr_dispatch_disable;
 #ifdef RTEMS_SMP
   volatile bool is_executing;
 #endif
-- 
2.12.3

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[PATCH v1 9/9] bsp/pc386: Disable interrupt nesting for job handler

2020-05-31 Thread Jan Sommer 
- Fixes timeout for smpipi01 where:
+ Main thread sends perform jobs to worker cpu while it is already
performing jobs
+ Interrupt on worker cpu performs jobs, but with empty job list
+ Worker cpu continues to execut previous job and adds new job list
to itself, which is never performed, since the interrupt has already
been handled
+ Main thread blocks forever on barrier D
---
 bsps/i386/pc386/start/smp-imps.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c
index de593f3c40..0985b8f08f 100644
--- a/bsps/i386/pc386/start/smp-imps.c
+++ b/bsps/i386/pc386/start/smp-imps.c
@@ -768,7 +768,17 @@ static void bsp_inter_processor_interrupt(void *arg)
 
   smp_apic_ack();
 
+  /*
+   * Disallow nesting.
+   */
+   __asm__ __volatile__("cli");
+
   _SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
+
+   /*
+   * Allow nesting.
+   */
+   __asm__ __volatile__("sti");
 }
 
 void
-- 
2.12.3

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[PATCH v1 2/9] bsp/pc386: Turn start16.S into a startAP.S

2020-05-31 Thread Jan Sommer 
start16.S is now only used for SMP configurations to start the
application processors.

This commit removes all unnecessary parts for this job,
i.e. video conssole initalisation, A20 gate activation
and all non-AP related code.

Update #3335
---
 bsps/i386/pc386/start/smp-imps.c|  14 +-
 bsps/i386/pc386/start/start16.S | 254 
 bsps/i386/pc386/start/startAP.S | 145 ++
 c/src/lib/libbsp/i386/pc386/Makefile.am |   4 +-
 4 files changed, 159 insertions(+), 258 deletions(-)
 delete mode 100644 bsps/i386/pc386/start/start16.S
 create mode 100644 bsps/i386/pc386/start/startAP.S

diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c
index 0543b17ec5..58d9178f90 100644
--- a/bsps/i386/pc386/start/smp-imps.c
+++ b/bsps/i386/pc386/start/smp-imps.c
@@ -309,6 +309,11 @@ boot_cpu(imps_processor *proc)
   }
 
   /*
+   *  Wait until AP is in protected mode before starting the next AP
+   */
+  while (reset[2] != 0);
+
+  /*
*  Generic CPU startup sequence ends here, the rest is cleanup.
*/
 
@@ -342,12 +347,17 @@ add_processor(imps_processor *proc)
 printk("#0  BootStrap Processor (BSP)\n");
 return;
   }
+  /* Setup the apic/cpu maps before booting the APs
+   * otherwise calls to _Get_current_processor can deliver
+   * wrong values if the BSP gets interrupted
+   */
+  imps_cpu_apic_map[imps_num_cpus] = apicid;
+  imps_apic_cpu_map[apicid] = imps_num_cpus;
   if (boot_cpu(proc)) {
 
 /*  X  add OS-specific setup for secondary CPUs here */
 
-imps_cpu_apic_map[imps_num_cpus] = apicid;
-imps_apic_cpu_map[apicid] = imps_num_cpus;
+/* AP booted successfully, increase number of available cores */
 imps_num_cpus++;
   }
 }
diff --git a/bsps/i386/pc386/start/start16.S b/bsps/i386/pc386/start/start16.S
deleted file mode 100644
index 3d46f40ed6..00
--- a/bsps/i386/pc386/start/start16.S
+++ /dev/null
@@ -1,254 +0,0 @@
-/*--+
- * start16.s v1.0 - PC386 BSP - 1998/04/13
- *--+
- * This file contains the entry point for the application.
- * The name of this entry point is compiler dependent.
- * It jumps to the BSP which is responsible for performing all initialization.
- *--+
- * (C) Copyright 1997 -
- * - NavIST Group - Real-Time Distributed Systems and Industrial Automation
- *
- * http://pandora.ist.utl.pt
- *
- * Instituto Superior Tecnico * Lisboa * PORTUGAL
- *--+
- * Disclaimer:
- *
- * This file is provided "AS IS" without warranty of any kind, either
- * expressed or implied.
- *--+
- */
-
-/*
- *  COPYRIGHT (c) 2011.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-
-#include 
-
-/*---+
-| Constants
-+*/
-
-#if defined(SMP_SECONDARY_CORE)
-.set PROT_CODE_SEG, 0x08# offset of code segment descriptor into GDT
-#else
-.set PROT_CODE_SEG, 0x0 # offset of code segment descriptor into GDT
-#endif
-
-.set PROT_DATA_SEG, 0x10# offset of code segment descriptor into GDT
-.set CR0_PE,1   # protected mode flag on CR0 register
-.set HDRSTART,  HEADERADDR  # address of start of bin2boot header
-.set HDROFF,0x24# offset into bin2boot header of start32 addr
-.set STACKOFF,  0x200-0x10  # offset to load into %esp, from start of image
-
-/* #define NEW_GAS */
-#ifdef NEW_GAS
-  #define LJMPL ljmpl
-#else
-  #define LJMPL ljmp
-#endif
-
-/*+
-| CODE section
-+*/
-
-.text
-#if defined(SMP_SECONDARY_CORE)
-.globl app_processor_start# entry point
-app_processor_start:
-#else
-.globl _start16 # entry point
-.globl start16
-start16:
-_start16:
-#endif
-
-.code16
-cli # DISABLE INTERRUPTS!!!
-#if defined(SMP_SECONDARY_CORE)
-jmp 1f
-   .align 4
-app_cpu_start:
-   .long   0
-app_cpu_stack:
-   .long   0
-1:
-#endif
-movw%cs, %ax   # Initialize the rest of 
-movw%ax, %ds   #   segment registers
-movw%ax, %es
-movw%ax, %ss
-
-#if !defined(SMP_SECONDARY_CODE) && (RTEMS_VIDEO_80x50 == 1)
-movl$0x0040,%eax# use 32 bit

[PATCH v1 5/9] bsp/pc386: Define interrupt stack frame for smp

2020-05-31 Thread Jan Sommer 
- Defines CPU_Interrupt_frame in cpu_impl.h
- Updates isq_asm.S to save/restore registers in matching order to
interrupt frame
---
 bsps/i386/shared/irq/irq_asm.S | 102 +++--
 cpukit/score/cpu/i386/include/rtems/score/cpu.h|  28 +++---
 .../score/cpu/i386/include/rtems/score/cpuimpl.h   |   2 +
 3 files changed, 73 insertions(+), 59 deletions(-)

diff --git a/bsps/i386/shared/irq/irq_asm.S b/bsps/i386/shared/irq/irq_asm.S
index 2d65a79fe2..6a399f0c15 100644
--- a/bsps/i386/shared/irq/irq_asm.S
+++ b/bsps/i386/shared/irq/irq_asm.S
@@ -25,17 +25,19 @@
 #endif
 
 /* Stack frame we use for intermediate storage   */
-#define ARG_OFF0
-#define MSK_OFF 4/* not used any more*/
-#define EBX_OFF 8/* ebx  */
-#define EBP_OFF 12   /* code restoring ebp/esp relies on */
-#define ESP_OFF 16   /* esp being on top of ebp! */
+#define ARG_OFF  0
+#define EBX_OFF  4/* ebx  */
+#define EBP_OFF  8   /* code restoring ebp/esp relies on */
+#define ESP_OFF 12   /* esp being on top of ebp! */
 #ifdef __SSE__
+#ifdef RTEMS_SMP
+#error SMP with SSE support has not been tested. Use at your own risk.
+#endif
 /* need to be on 16 byte boundary for SSE, add 12 to do that */
 #define FRM_SIZ (20+12+512)
 #define SSE_OFF 32
 #else
-#define FRM_SIZ 20
+#define FRM_SIZ 16
 #endif
 
BEGIN_CODE
@@ -59,7 +61,7 @@ SYM (_ISR_Handler):
 *  NOTE:  If the previous values of the segment registers are
 * pushed, do not forget to adjust SAVED_REGS.
 *
-*  NOTE:  Make sure the exit code which restores these
+*  NOTE:  Make sure the Lthread_dispatch_done code restores these
 * when this type of code is needed.
 */
 
@@ -72,17 +74,15 @@ SYM (_ISR_Handler):
/*
 * Establish an aligned stack frame
 *   original sp
- *   saved ebx
 *   saved ebp
-*   saved irq mask
+*   saved ebx
 *   vector arg to BSP_dispatch_isr   <- aligned SP
 */
movl  esp, eax
subl  $FRM_SIZ, esp
-   andl  $ - CPU_STACK_ALIGNMENT, esp
-   movl  ebx, EBX_OFF(esp)
movl  eax, ESP_OFF(esp)
movl  ebp, EBP_OFF(esp)
+   movl  ebx, EBX_OFF(esp)
 
/*
 * GCC versions starting with 4.3 no longer place the cld
@@ -100,10 +100,10 @@ SYM (_ISR_Handler):
/* We save SSE here (on the task stack) because we possibly
 * call other C-code (besides the ISR, namely _Thread_Dispatch())
 */
-/*  don't wait here; a possible exception condition will eventually be
- *  detected when the task resumes control and executes a FP instruction
+   /*  don't wait here; a possible exception condition will eventually be
+*  detected when the task resumes control and executes a FP instruction
fwait
- */
+*/
fxsave SSE_OFF(esp)
fninit  /* clean-slate FPU*/
movl   $0x1f80, ARG_OFF(esp)/* use ARG_OFF as scratch space   */
@@ -118,15 +118,9 @@ PUBLIC (ISR_STOP)
 ISR_STOP:
 .check_stack_switch:
movl  esp, ebp  /* ebp = previous stack pointer */
+   andl  $ - CPU_STACK_ALIGNMENT, esp  /* Make sure esp is 16 byte 
aligned */
 
-#ifdef RTEMS_SMP
-   call  SYM(_CPU_SMP_Get_current_processor)
-   sall  $PER_CPU_CONTROL_SIZE_LOG2, eax
-   addl  $SYM(_Per_CPU_Information), eax
-   movl  eax, ebx
-#else
-   movl  $SYM(_Per_CPU_Information), ebx
-#endif
+   GET_SELF_CPU_CONTROL ebx
 
/* is this the outermost interrupt? */
cmpl  $0, PER_CPU_ISR_NEST_LEVEL(ebx)
@@ -161,32 +155,48 @@ nested:
 */
movl  ebp, esp
 
-   decl  PER_CPU_ISR_NEST_LEVEL(ebx)  /* one less ISR nest level */
-   /* If interrupts are nested, */
-   /*   then dispatching is disabled */
-
-   decl  PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx)
-   /* unnest multitasking */
-   /* Is dispatch disabled */
-   jne   .exit /* Yes, then exit */
-
-   cmpb  $0, PER_CPU_DISPATCH_NEEDED(ebx)
-   /* Is task switch necessary? */
-   jne   .schedule /* Yes, then call the scheduler */
-   jmp   .exit /* No, exit */
-
-.schedule:
-   /*
-* the scratch registers have already been saved and we are already
-* back on the thread system stack. So we can call _Thread_Dispatch
-* directly
-*/
-   call  _Thread_Dispatch
/*
-* fall through exit to restore complete

[PATCH v1 1/9] bsp/pc386: Fix Makefile for building with SMP

2020-05-31 Thread Jan Sommer 
---
 c/src/lib/libbsp/i386/pc386/Makefile.am | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/c/src/lib/libbsp/i386/pc386/Makefile.am 
b/c/src/lib/libbsp/i386/pc386/Makefile.am
index 354ad0b23e..218e6bc065 100644
--- a/c/src/lib/libbsp/i386/pc386/Makefile.am
+++ b/c/src/lib/libbsp/i386/pc386/Makefile.am
@@ -118,7 +118,7 @@ appcpustart.$(OBJEXT): 
../../../../../../bsps/i386/pc386/start/start16.S
$(CPPASCOMPILE) $(AM_CPPFLAGS) -DSMP_SECONDARY_CORE -o $@ -c $<
 
 appstart.$(OBJEXT): appcpustart.$(OBJEXT)
-   $(LD) -r -N -T 
$(top_srcdir)/../../../../../../bsps/i386/pc386/start/linkcmds \
+   $(LD) -N  \
-Ttext 0x7 -e app_processor_start -nostdlib \
-o appstart_tmp.exe $<
$(OBJCOPY) -O binary appstart_tmp.exe appstart.bin
-- 
2.12.3

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[PATCH v1 0/9] Enable SMP for pc386 based bsps

2020-05-31 Thread Jan Sommer 
Hello,

Here is a patch set which should enable SMP again for the pc386-based BSPs 
(mainly tested with pc686).
So far I only tested it with qemu. Tests on real hardware are pending.
To me it looks like there are no regressions for the standard non-SMP version 
of the BSP, but it is difficult to say for sure.
Subsequent runs of the testsuite with a current master build already produce 
different numbers of failed/timeout/invalid tests.

However, even with the patch set applied the amount of passed tests continues 
to range from 550-557 and the failed/timeout/invalid tests seem to be generally 
the same.
Regarding smptests, the current status with qemu-4.2.0 and 4 cores looks like 
this:

Passed:55
Failed: 1
User Input: 0
Expected Fail:  0
Indeterminate:  0
Benchmark:  0
Timeout:2
Invalid:1
Wrong Version:  0
Wrong Build:0
Wrong Tools:0
-
Total: 59
Failures:
 smpatomic01.exe
Timeouts:
 smpclock01.exe
 smpopenmp01.exe
Invalid:
 smpfatal09.exe
 
Some details on the missing tests:
---
smpfatal09: This test actually does pass, but because the fatal error handler 
is executed before the console is initialized, no output is produced.

smpclock01.exe: Here CPU0 disables its local interrupts and waits for a barrier 
release of CPU1. This means it doesn't handle timer interrupts anymore and 
doesn't send corresponding IPIs to other CPUs.
At the same time CPU1 is waiting for a timer event before releasing the 
barrier. Any hints how to resolve this are very welcome.

smpatomic01: This test seems very large and a bit complicated to me. I will 
have a look at it next, but any suggestions are welcome. It fails with this 
information:
] === atomic or/and test case ===
] worker 0 value: 1
] worker 1 value: 0
] atomic value: expected = 1, actual = 1
] 
../../../../../../smp-refex-rtems/c/src/../../testsuites/smptests/smpatomic01/init.c:
 404 n - s < LONG_MAX
] 
] *** FATAL ***

smpopenmp01: I don't know more about openmp then what is on wikipedia. It has 
currently a low priority for me.

Some details regarding the patch set:
-

- The first 3 commits are basically cleaning the original start16.S to be used 
for starting the application processors only and updating the general bring up 
infrastructure.
- The next 2 commits are updating the low level context switch and isr handling 
in assembly. I used the ARM implementation as a template and tried to stay 
comparably close to it.
- The last 4 commits are smaller changes made after debugging certain test 
cases.


My next step would be to test the SMP functionality on HW. My goal would be to 
get the final revision published as part of the RTEMS5 release.
If you would like to see any logs from a testsuite run with certain parameters, 
just tell me.

Best regards,

Jan



Jan Sommer (9):
  bsp/pc386: Fix Makefile for building with SMP
  bsp/pc386: Turn start16.S into a startAP.S
  bsp/pc386: Update GDT to work for SMP
  bsp/pc386: Update context switch and restore
  bsp/pc386: Define interrupt stack frame for smp
  bsps/pc386: Fix Clock_isr for SMP
  bsps/pc386: Separate smp API functions. Makes smpfatal08 link
  smpsignal01: Change state before sending the signal
  bsp/pc386: Disable interrupt nesting for job handler

 bsps/i386/include/bsp/smp-imps.h   |   3 +
 bsps/i386/pc386/clock/ckinit.c |   2 +-
 bsps/i386/pc386/include/bsp.h  |   7 +
 bsps/i386/pc386/include/bsp/tblsizes.h |   8 +-
 bsps/i386/pc386/start/bspsmp.c |  43 
 bsps/i386/pc386/start/getcpuid.c   |  22 --
 bsps/i386/pc386/start/ldsegs.S |   4 +-
 bsps/i386/pc386/start/smp-imps.c   |  79 ---
 bsps/i386/pc386/start/start16.S| 254 -
 bsps/i386/pc386/start/startAP.S| 118 ++
 bsps/i386/shared/irq/irq_asm.S | 102 +
 c/src/lib/libbsp/i386/pc386/Makefile.am|   8 +-
 cpukit/score/cpu/i386/cpu_asm.S|  74 --
 cpukit/score/cpu/i386/include/rtems/asm.h  |  26 +++
 cpukit/score/cpu/i386/include/rtems/score/cpu.h|  32 +--
 .../score/cpu/i386/include/rtems/score/cpuimpl.h   |   2 +
 testsuites/smptests/smpsignal01/init.c |   2 +-
 17 files changed, 382 insertions(+), 404 deletions(-)
 create mode 100644 bsps/i386/pc386/start/bspsmp.c
 delete mode 100644 bsps/i386/pc386/start/getcpuid.c
 delete mode 100644 bsps/i386/pc386/start/start16.S
 create mode 100644 bsps/i386/pc386/start/startAP.S

-- 
2.12.3

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[PATCH v1 7/9] bsps/pc386: Separate smp API functions. Makes smpfatal08 link

2020-05-31 Thread Jan Sommer 
---
 bsps/i386/include/bsp/smp-imps.h|  3 +++
 bsps/i386/pc386/include/bsp.h   |  7 ++
 bsps/i386/pc386/start/bspsmp.c  | 43 +
 bsps/i386/pc386/start/getcpuid.c| 22 -
 bsps/i386/pc386/start/smp-imps.c| 40 ++
 c/src/lib/libbsp/i386/pc386/Makefile.am |  2 +-
 6 files changed, 61 insertions(+), 56 deletions(-)
 create mode 100644 bsps/i386/pc386/start/bspsmp.c
 delete mode 100644 bsps/i386/pc386/start/getcpuid.c

diff --git a/bsps/i386/include/bsp/smp-imps.h b/bsps/i386/include/bsp/smp-imps.h
index 03434b81ef..7b023ddcfc 100644
--- a/bsps/i386/include/bsp/smp-imps.h
+++ b/bsps/i386/include/bsp/smp-imps.h
@@ -233,6 +233,9 @@ extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
 extern char _binary_appstart_bin_start[];
 extern char _binary_appstart_bin_size[];
 
+/** @brief base address of the local apic. Usually 0xFEE0 */
+extern unsigned imps_lapic_addr;
+
 /*
  *  Defines that use variables
  */
diff --git a/bsps/i386/pc386/include/bsp.h b/bsps/i386/pc386/include/bsp.h
index 7989b880a9..1ed92e469a 100644
--- a/bsps/i386/pc386/include/bsp.h
+++ b/bsps/i386/pc386/include/bsp.h
@@ -252,6 +252,13 @@ uint32_t BSP_irq_count_dump(FILE *f);
 void raw_idt_notify(void);
 void C_dispatch_isr(int vector);
 
+#ifdef RTEMS_SMP
+  /* CPU specific functions used by the SMP API */
+  int imps_probe(void);
+  void ipi_install_irq(void);
+  int send_ipi(unsigned int dst, unsigned int v);
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsps/i386/pc386/start/bspsmp.c b/bsps/i386/pc386/start/bspsmp.c
new file mode 100644
index 00..026f86916f
--- /dev/null
+++ b/bsps/i386/pc386/start/bspsmp.c
@@ -0,0 +1,43 @@
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+void _CPU_SMP_Prepare_start_multitasking( void )
+{
+  /* Do nothing */
+}
+
+bool _CPU_SMP_Start_processor( uint32_t cpu_index )
+{
+  (void) cpu_index;
+
+  return true;
+}
+
+
+uint32_t _CPU_SMP_Get_current_processor( void )
+{
+  return imps_apic_cpu_map[APIC_ID(IMPS_LAPIC_READ(LAPIC_ID))];
+}
+
+uint32_t _CPU_SMP_Initialize( void )
+{
+  /* XXX need to deal with finding too many cores */
+
+  return (uint32_t) imps_probe();
+}
+
+void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
+{
+  if ( cpu_count > 1 )
+ipi_install_irq();
+}
+
+void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
+{
+  send_ipi( target_processor_index, 0x30 );
+}
diff --git a/bsps/i386/pc386/start/getcpuid.c b/bsps/i386/pc386/start/getcpuid.c
deleted file mode 100644
index 4918a2a970..00
--- a/bsps/i386/pc386/start/getcpuid.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  COPYRIGHT (c) 2011.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include 
-
-#include 
-#include 
-
-static int lapic_dummy = 0;
-unsigned imps_lapic_addr = ((unsigned)(_dummy)) - LAPIC_ID;
-
-uint32_t _CPU_SMP_Get_current_processor( void )
-{
-  return imps_apic_cpu_map[APIC_ID(IMPS_LAPIC_READ(LAPIC_ID))];
-}
-
diff --git a/bsps/i386/pc386/start/smp-imps.c b/bsps/i386/pc386/start/smp-imps.c
index 6480c0d25e..de593f3c40 100644
--- a/bsps/i386/pc386/start/smp-imps.c
+++ b/bsps/i386/pc386/start/smp-imps.c
@@ -85,6 +85,9 @@
 extern void _pc386_delay(void);
 extern uint32_t* gdtdesc;
 
+static int lapic_dummy = 0;
+unsigned imps_lapic_addr = ((unsigned)(_dummy)) - LAPIC_ID;
+
 /* #define KERNEL_PRINT(_format)   printk(_format) */
 
 static void CMOS_WRITE_BYTE(
@@ -220,7 +223,7 @@ get_checksum(unsigned start, int length)
 /*
  *  APIC ICR write and status check function.
  */
-static int
+int
 send_ipi(unsigned int dst, unsigned int v)
 {
   int to, send_status;
@@ -698,7 +701,7 @@ imps_force(int ncpus)
  *
  *  Function finished.
  */
-static int
+int
 imps_probe(void)
 {
   /*
@@ -768,7 +771,8 @@ static void bsp_inter_processor_interrupt(void *arg)
   _SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
 }
 
-static void ipi_install_irq(void)
+void
+ipi_install_irq(void)
 {
   rtems_status_code status;
 
@@ -802,33 +806,3 @@ static void secondary_cpu_initialize(void)
 
   _SMP_Start_multitasking_on_secondary_processor( _Per_CPU_Get() );
 }
-
-uint32_t _CPU_SMP_Initialize( void )
-{
-  /* XXX need to deal with finding too many cores */
-
-  return (uint32_t) imps_probe();
-}
-
-void _CPU_SMP_Prepare_start_multitasking( void )
-{
-  /* Do nothing */
-}
-
-bool _CPU_SMP_Start_processor( uint32_t cpu_index )
-{
-  (void) cpu_index;
-
-  return true;
-}
-
-void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
-{
-  if ( cpu_count > 1 )
-ipi_install_irq();
-}
-
-void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
-{
-  send_ipi( target_processor_index, 0x30 );
-}
diff --git a/c/src/lib/libbsp/i386/pc386/Makefile.am 
b/c/src/lib/libbsp/i386/pc386/Makefile.am