Re: rtems-bsps: add ability to print architecture/bsps list

2020-09-28 Thread Chris Johns 
On 29/9/20 8:54 am, Ryan Long wrote:
> The attached patch adds the ability to print the set of bsps in the form of
> architecture/bsp. This is useful for feeding into other programs.

Pushed.

Thanks
Chris
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Re: libbsd master and 6-freebsd-12 branch different

2020-09-28 Thread Chris Johns 
On 29/9/20 2:43 pm, Sebastian Huber wrote:
> On 29/09/2020 04:11, Chris Johns wrote:
> 
>> A few recent patches have been pushed to master but not the 6-freebsd-12 
>> branch.
>> I was wondering if some should be on the 6-freebsd-12 branch as well?
> 
> Some patches are due to FreeBSD API changes.
> 

I did wonder.

> I will do a build run to check if the other patches can be back ported.

The new archs are the ones I spotted but I am not sure the intention is.

Chris

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Re: libbsd master and 6-freebsd-12 branch different

2020-09-28 Thread Sebastian Huber 

On 29/09/2020 04:11, Chris Johns wrote:


A few recent patches have been pushed to master but not the 6-freebsd-12 branch.
I was wondering if some should be on the 6-freebsd-12 branch as well?


Some patches are due to FreeBSD API changes.

I will do a build run to check if the other patches can be back ported.

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Re: [PATCH v2 2/2] Add AArch64 documentation

2020-09-28 Thread Sebastian Huber 

Hello Kinsey,

the patch looks good.

On 28/09/2020 17:25, Kinsey Moore wrote:


---
  cpu-supplement/aarch64.rst | 134 +
  user/bsps/aarch64/a53.rst  |  26 +++
  user/bsps/bsps-aarch64.rst |   2 +-
  3 files changed, 161 insertions(+), 1 deletion(-)
  create mode 100644 cpu-supplement/aarch64.rst
  create mode 100644 user/bsps/aarch64/a53.rst

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
new file mode 100644
index 000..178ea10
--- /dev/null
+++ b/cpu-supplement/aarch64.rst
@@ -0,0 +1,134 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)

I am no sure which part of this patch has a 1988 copyright.
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Re: [PATCH v2 2/2] Add AArch64 documentation

2020-09-28 Thread Sebastian Huber 

On 28/09/2020 17:25, Kinsey Moore wrote:


+Symmetric Multiprocessing
+=
+
+SMP is not currently supported on ARMv8-A.

Is this a limitation of the CPU port or just a missing BSP support?
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Re: [PATCH v2 1/2] cpu-supplement: Fix formatting and missing words

2020-09-28 Thread Sebastian Huber 

On 28/09/2020 17:25, Kinsey Moore wrote:


@@ -196,11 +196,11 @@ Symmetric Multiprocessing
  
  SMP is supported on ARMv7-A.  Available platforms are
  
-- Altera Cyclone V,

+- Altera Cyclone V
  
-- NXP i.MX 7, and

+- NXP i.MX 7
  
-- Xilinx Zynq.

+- Xilinx Zynq


What is the reason for this change?


If you change the formatting like this, then it should be

"Available platforms are:"

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libbsd master and 6-freebsd-12 branch different

2020-09-28 Thread Chris Johns 
Hi,

A few recent patches have been pushed to master but not the 6-freebsd-12 branch.
I was wondering if some should be on the 6-freebsd-12 branch as well?

Thanks
Chris
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Re: On Master All GDB Builds Fail on Cygwin

2020-09-28 Thread Chris Johns 
On 29/9/20 5:35 am, Joel Sherrill wrote:
> Hi
> 
> I left a build going yesterday on Cygwin and GDB failed with this for every
> architecture. I updated my Cygwin install this morning and it still fails 
> with this:
> 
> cp-support.o:/home/jrs007/rtems-cron-6/rtems-source-builder/rtems/build/arm-rtems6-gdb-0295dde-x86_64-pc-cygwin-1/build/gdb/../../sourceware-mirror-binutils-gdb-0295dde/gdb/psymtab.h:32:(.text+0x5291):
> relocation truncated to fit: R_X86_64_PC32 against undefined symbol `TLS init
> function for thread_local_segv_handler'
> cp-support.o:/home/jrs007/rtems-cron-6/rtems-source-builder/rtems/build/arm-rtems6-gdb-0295dde-x86_64-pc-cygwin-1/build/gdb/../../sourceware-mirror-binutils-gdb-0295dde/gdb/psymtab.h:32:(.text+0x529b):
> relocation truncated to fit: R_X86_64_PC32 against undefined symbol `TLS init
> function for thread_local_segv_handler'
> collect2: error: ld returned 1 exit status
> make[2]: *** [Makefile:1867: gdb.exe] Error 1
> make[2]: Leaving directory
> '/home/jrs007/rtems-cron-6/rtems-source-builder/rtems/build/arm-rtems6-gdb-0295dde-x86_64-pc-cygwin-1/build/gdb'
> 
> I found that there are others with the same problem. The only one with a patch
> was this:
> 
> https://stackoverflow.com/questions/61984974/failed-to-build-avr-and-arm-gdb-9-1-under-cygwin-relocation-truncated-to-fit
> 
> I know Cygwin is way down folks' list but any ideas?

It is best to raise this with gdb and/or cygwin.

Chris
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Re: License files missing on 5-freebsd-12 branch

2020-09-28 Thread Chris Johns 
On 28/9/20 9:45 pm, Christian Mauderer wrote:
> Sorry for the delay. I didn't manage to do these before my vacation and
> then I forgot them during vacation. I just pushed them.

No problem and thank you. I hope you had a relaxing vacation?

Chris
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rtems-bsps: add ability to print architecture/bsps list

2020-09-28 Thread Ryan Long 
Hi,

The attached patch adds the ability to print the set of bsps in the form of 
architecture/bsp. This is useful for feeding into other programs.

Thanks,
Ryan


0001-rtems-bsps-add-ability-to-print-architecture-bsp-lis.patch
Description: 0001-rtems-bsps-add-ability-to-print-architecture-bsp-lis.patch
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On Master All GDB Builds Fail on Cygwin

2020-09-28 Thread Joel Sherrill 
Hi

I left a build going yesterday on Cygwin and GDB failed with this for every
architecture. I updated my Cygwin install this morning and it still fails
with this:

cp-support.o:/home/jrs007/rtems-cron-6/rtems-source-builder/rtems/build/arm-rtems6-gdb-0295dde-x86_64-pc-cygwin-1/build/gdb/../../sourceware-mirror-binutils-gdb-0295dde/gdb/psymtab.h:32:(.text+0x5291):
relocation truncated to fit: R_X86_64_PC32 against undefined symbol `TLS
init function for thread_local_segv_handler'
cp-support.o:/home/jrs007/rtems-cron-6/rtems-source-builder/rtems/build/arm-rtems6-gdb-0295dde-x86_64-pc-cygwin-1/build/gdb/../../sourceware-mirror-binutils-gdb-0295dde/gdb/psymtab.h:32:(.text+0x529b):
relocation truncated to fit: R_X86_64_PC32 against undefined symbol `TLS
init function for thread_local_segv_handler'
collect2: error: ld returned 1 exit status
make[2]: *** [Makefile:1867: gdb.exe] Error 1
make[2]: Leaving directory
'/home/jrs007/rtems-cron-6/rtems-source-builder/rtems/build/arm-rtems6-gdb-0295dde-x86_64-pc-cygwin-1/build/gdb'

I found that there are others with the same problem. The only one with a
patch was this:

https://stackoverflow.com/questions/61984974/failed-to-build-avr-and-arm-gdb-9-1-under-cygwin-relocation-truncated-to-fit

I know Cygwin is way down folks' list but any ideas?

Thanks.

--joel
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Error while using the trace linker

2020-09-28 Thread Utkarsh Rai 
Hello,
I am following the tracing example as mentioned in the docs
 for
sparc/erc32 BSP.  When I run the "rtems-tld" command, I get the following
error - "error: /home/utkarsh/sandbox/bsps/sparc: Invalid RTEMS path"

My directory structure is -
|-$HOME- | - sandbox -|- bsps -  |-sparc
 | - rtems
 | - rsb

I have used the exact command as mentioned in the example with changes made
according to my installation from the top of the BSP installation
directory. The rtems-path in the fileio-trace.ini file is set to
"$HOME/sandbox/bsps/sparc".

I know I am making a very simple mistake but  just can't seem to put my
finger on it. Can someone point what is it that I am doing wrong?
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Re: [PATCH v4] Test for clock_nanosleep() with CLOCK_MONOTONIC option

2020-09-28 Thread Utkarsh Rai 
On Mon, Sep 28, 2020 at 9:58 PM Gedare Bloom  wrote:

> Hi Utkarsh,
>
> I was starting to review this, but then I got a little bit confused by
> what you have done.
>
> I think you may have gone down the wrong path to do this work. It
> looks like you copied from libtests/ttest01 to construct this test.
> That is actually a test for the testing infrastructure itself. So its
> format isn't really the proper way to structure a posix clock test. I
> know there aren't a lot of examples of the TTest framework, but this
> should be structured more like one of the existing
> sptests/smptests/psxtests that is using the T_TEST_CASE().
>
> https://docs.rtems.org/branches/master/eng/test-framework.html#the-rtems-test-framework


Oh, Ok I will make the changes.


>
>
> Perhaps, restart with something simpler and send that first. Then you
> should take a look at the existing test we have for the
> clock_nanosleep() that only does CLOCK_REALTIME for some of the logic
> to test as well. It seems like you have done a pretty basic API-level
> test, but it is only checking some return values and not actually
> verifying the implementation did anything.
>

Dr. Joel suggested in the previous review
 that this
test could be the same as clock real-time with the clock type changed but
looking
back I realize that there is much more to that test than what I have
implemented. I will change this.


>
>
> On Mon, Sep 21, 2020 at 9:15 AM Utkarsh Rai 
> wrote:
> >
> > From: Utkarsh 
> Please use full (legal) name for commit metadata
>
> >
> > Closes #3890
> >
> > Signed-off-by: Utkarsh Rai 
> > ---
> >  spec/build/testsuites/psxtests/grp.yml|   2 +
> >  .../psxtests/psxclocknanosleep01.yml  |  20 +++
> >  .../psxtests/psxclocknanosleep01/init.c   |  94 ++
> >  .../psxclocknanosleep01.doc   |  13 ++
> >  .../psxclocknanosleep01.scn   |  41 ++
> >  .../test-clock-nanosleep.c| 120 ++
> >  6 files changed, 290 insertions(+)
> >  create mode 100644
> spec/build/testsuites/psxtests/psxclocknanosleep01.yml
> >  create mode 100644 testsuites/psxtests/psxclocknanosleep01/init.c
> >  create mode 100644
> testsuites/psxtests/psxclocknanosleep01/psxclocknanosleep01.doc
> >  create mode 100644
> testsuites/psxtests/psxclocknanosleep01/psxclocknanosleep01.scn
> >  create mode 100644
> testsuites/psxtests/psxclocknanosleep01/test-clock-nanosleep.c
> >
> > diff --git a/spec/build/testsuites/psxtests/grp.yml
> b/spec/build/testsuites/psxtests/grp.yml
> > index 47dedac275..3342fc6c18 100644
> > --- a/spec/build/testsuites/psxtests/grp.yml
> > +++ b/spec/build/testsuites/psxtests/grp.yml
> > @@ -79,6 +79,8 @@ links:
> >uid: psxclock
> >  - role: build-dependency
> >uid: psxclock01
> > +- role: build-dependency
> > +  uid: psxclocknanosleep01
> >  - role: build-dependency
> >uid: psxclockrealtime01
> >  - role: build-dependency
> > diff --git a/spec/build/testsuites/psxtests/psxclocknanosleep01.yml
> b/spec/build/testsuites/psxtests/psxclocknanosleep01.yml
> > new file mode 100644
> > index 00..39ec1657d2
> > --- /dev/null
> > +++ b/spec/build/testsuites/psxtests/psxclocknanosleep01.yml
> > @@ -0,0 +1,20 @@
> > +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
> > +build-type: test-program
> > +cflags: []
> > +copyrights:
> > +- Copyright (C) 2020 Utkarsh Rai (utkarsh.ra...@mail.com)
> > +cppflags: []
> > +cxxflags: []
> > +enabled-by: true
> > +features: c cprogram
> > +includes: []
> > +ldflags: []
> > +links: []
> > +source:
> > +- testsuites/psxtests/psxclocknanosleep01/init.c
> > +- testsuites/psxtests/psxclocknanosleep01/test-clock-nanosleep.c
> > +stlib: []
> > +target: testsuites/psxtests/psxclocknanosleep01.exe
> > +type: build
> > +use-after: []
> > +use-before: []
> > diff --git a/testsuites/psxtests/psxclocknanosleep01/init.c
> b/testsuites/psxtests/psxclocknanosleep01/init.c
> > new file mode 100644
> > index 00..a5cb4d6054
> > --- /dev/null
> > +++ b/testsuites/psxtests/psxclocknanosleep01/init.c
> > @@ -0,0 +1,94 @@
> > +/* SPDX-License-Identifier: BSD-2-Clause
> > + *
> > + * Copyright (C) 2020 Utkarsh Rai
> > + *
> > + * Redistribution and use in source and binary forms, with or without
> > + * modification, are permitted provided that the following conditions
> > + * are met:
> > + * 1. Redistributions of source code must retain the above copyright
> > + *notice, this list of conditions and the following disclaimer.
> > + * 2. Redistributions in binary form must reproduce the above copyright
> > + *notice, this list of conditions and the following disclaimer in
> the
> > + *documentation and/or other materials provided with the
> distribution.
> > + *
> > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> "AS IS"
> > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
> TO, THE
> > + * IM

Re: [PATCH v4] Test for clock_nanosleep() with CLOCK_MONOTONIC option

2020-09-28 Thread Gedare Bloom 
Hi Utkarsh,

I was starting to review this, but then I got a little bit confused by
what you have done.

I think you may have gone down the wrong path to do this work. It
looks like you copied from libtests/ttest01 to construct this test.
That is actually a test for the testing infrastructure itself. So its
format isn't really the proper way to structure a posix clock test. I
know there aren't a lot of examples of the TTest framework, but this
should be structured more like one of the existing
sptests/smptests/psxtests that is using the T_TEST_CASE().
https://docs.rtems.org/branches/master/eng/test-framework.html#the-rtems-test-framework

Perhaps, restart with something simpler and send that first. Then you
should take a look at the existing test we have for the
clock_nanosleep() that only does CLOCK_REALTIME for some of the logic
to test as well. It seems like you have done a pretty basic API-level
test, but it is only checking some return values and not actually
verifying the implementation did anything.


On Mon, Sep 21, 2020 at 9:15 AM Utkarsh Rai  wrote:
>
> From: Utkarsh 
Please use full (legal) name for commit metadata

>
> Closes #3890
>
> Signed-off-by: Utkarsh Rai 
> ---
>  spec/build/testsuites/psxtests/grp.yml|   2 +
>  .../psxtests/psxclocknanosleep01.yml  |  20 +++
>  .../psxtests/psxclocknanosleep01/init.c   |  94 ++
>  .../psxclocknanosleep01.doc   |  13 ++
>  .../psxclocknanosleep01.scn   |  41 ++
>  .../test-clock-nanosleep.c| 120 ++
>  6 files changed, 290 insertions(+)
>  create mode 100644 spec/build/testsuites/psxtests/psxclocknanosleep01.yml
>  create mode 100644 testsuites/psxtests/psxclocknanosleep01/init.c
>  create mode 100644 
> testsuites/psxtests/psxclocknanosleep01/psxclocknanosleep01.doc
>  create mode 100644 
> testsuites/psxtests/psxclocknanosleep01/psxclocknanosleep01.scn
>  create mode 100644 
> testsuites/psxtests/psxclocknanosleep01/test-clock-nanosleep.c
>
> diff --git a/spec/build/testsuites/psxtests/grp.yml 
> b/spec/build/testsuites/psxtests/grp.yml
> index 47dedac275..3342fc6c18 100644
> --- a/spec/build/testsuites/psxtests/grp.yml
> +++ b/spec/build/testsuites/psxtests/grp.yml
> @@ -79,6 +79,8 @@ links:
>uid: psxclock
>  - role: build-dependency
>uid: psxclock01
> +- role: build-dependency
> +  uid: psxclocknanosleep01
>  - role: build-dependency
>uid: psxclockrealtime01
>  - role: build-dependency
> diff --git a/spec/build/testsuites/psxtests/psxclocknanosleep01.yml 
> b/spec/build/testsuites/psxtests/psxclocknanosleep01.yml
> new file mode 100644
> index 00..39ec1657d2
> --- /dev/null
> +++ b/spec/build/testsuites/psxtests/psxclocknanosleep01.yml
> @@ -0,0 +1,20 @@
> +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
> +build-type: test-program
> +cflags: []
> +copyrights:
> +- Copyright (C) 2020 Utkarsh Rai (utkarsh.ra...@mail.com)
> +cppflags: []
> +cxxflags: []
> +enabled-by: true
> +features: c cprogram
> +includes: []
> +ldflags: []
> +links: []
> +source:
> +- testsuites/psxtests/psxclocknanosleep01/init.c
> +- testsuites/psxtests/psxclocknanosleep01/test-clock-nanosleep.c
> +stlib: []
> +target: testsuites/psxtests/psxclocknanosleep01.exe
> +type: build
> +use-after: []
> +use-before: []
> diff --git a/testsuites/psxtests/psxclocknanosleep01/init.c 
> b/testsuites/psxtests/psxclocknanosleep01/init.c
> new file mode 100644
> index 00..a5cb4d6054
> --- /dev/null
> +++ b/testsuites/psxtests/psxclocknanosleep01/init.c
> @@ -0,0 +1,94 @@
> +/* SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (C) 2020 Utkarsh Rai
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *notice, this list of conditions and the following disclaimer in the
> + *documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
> IS"
> + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
> + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED

[PATCH v2 1/2] cpu-supplement: Fix formatting and missing words

2020-09-28 Thread Kinsey Moore 
---
 cpu-supplement/arm.rst | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/cpu-supplement/arm.rst b/cpu-supplement/arm.rst
index 63aa532..26d88ea 100644
--- a/cpu-supplement/arm.rst
+++ b/cpu-supplement/arm.rst
@@ -34,7 +34,7 @@ for the values.
 Count Leading Zeroes Instruction
 
 
-The ARMv5 and later has the count leading zeroes ``clz`` instruction which
+The ARMv5 and later instruction sets have the count leading zeroes ``clz`` 
instruction which
 could be used to speed up the find first bit operation.  The use of this
 instruction should significantly speed up the scheduling associated with a
 thread blocking.  This is currently not used.
@@ -130,7 +130,7 @@ Memory Model
 
 
 A flat 32-bit memory model is supported.  The board support package must take
-care about the MMU if necessary.
+care of initializing the MMU if necessary.
 
 Interrupt Processing
 
@@ -196,11 +196,11 @@ Symmetric Multiprocessing
 
 SMP is supported on ARMv7-A.  Available platforms are
 
-- Altera Cyclone V,
+- Altera Cyclone V
 
-- NXP i.MX 7, and
+- NXP i.MX 7
 
-- Xilinx Zynq.
+- Xilinx Zynq
 
 Thread-Local Storage
 
-- 
2.20.1

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[PATCH v2 6/8] score: Add AArch64 port

2020-09-28 Thread Kinsey Moore 
This adds a CPU port for AArch64(ARMv8) with support for exceptions and
interrupts.
---
 cpukit/include/rtems/score/tls.h  |   4 +-
 .../cpu/aarch64/aarch64-context-validate.S| 305 ++
 .../aarch64-context-volatile-clobber.S| 100 
 .../cpu/aarch64/aarch64-exception-default.S   | 418 +
 .../cpu/aarch64/aarch64-exception-default.c   |  50 ++
 .../aarch64/aarch64-exception-frame-print.c   | 108 
 .../cpu/aarch64/aarch64-exception-interrupt.S | 317 ++
 .../score/cpu/aarch64/aarch64-thread-idle.c   |  48 ++
 cpukit/score/cpu/aarch64/cpu.c| 196 +++
 cpukit/score/cpu/aarch64/cpu_asm.S| 134 +
 .../cpu/aarch64/include/libcpu/vectors.h  | 100 
 cpukit/score/cpu/aarch64/include/rtems/asm.h  |  89 +++
 .../cpu/aarch64/include/rtems/score/aarch64.h |  83 +++
 .../cpu/aarch64/include/rtems/score/cpu.h | 549 ++
 .../aarch64/include/rtems/score/cpuatomic.h   |  42 ++
 .../cpu/aarch64/include/rtems/score/cpuimpl.h |  83 +++
 spec/build/cpukit/cpuaarch64.yml  |  35 ++
 spec/build/cpukit/librtemscpu.yml |   2 +
 18 files changed, 2662 insertions(+), 1 deletion(-)
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-validate.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-context-volatile-clobber.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-default.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-frame-print.c
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-exception-interrupt.S
 create mode 100644 cpukit/score/cpu/aarch64/aarch64-thread-idle.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu.c
 create mode 100644 cpukit/score/cpu/aarch64/cpu_asm.S
 create mode 100644 cpukit/score/cpu/aarch64/include/libcpu/vectors.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/asm.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/aarch64.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpu.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuatomic.h
 create mode 100644 cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
 create mode 100644 spec/build/cpukit/cpuaarch64.yml

diff --git a/cpukit/include/rtems/score/tls.h b/cpukit/include/rtems/score/tls.h
index 65a49d87be..66961f0083 100644
--- a/cpukit/include/rtems/score/tls.h
+++ b/cpukit/include/rtems/score/tls.h
@@ -85,7 +85,9 @@ typedef struct TLS_Thread_control_block {
   struct TLS_Thread_control_block *tcb;
 #else /* !__i386__ */
   TLS_Dynamic_thread_vector *dtv;
-#if CPU_SIZEOF_POINTER == 4
+/* gcc under AArch64/LP64 expects a 16 byte TCB at the beginning of the TLS
+ * data segment and indexes into it accordingly for TLS variable addresses */
+#if CPU_SIZEOF_POINTER == 4 || defined(AARCH64_MULTILIB_ARCH_V8)
   uintptr_t reserved;
 #endif
 #endif /* __i386__ */
diff --git a/cpukit/score/cpu/aarch64/aarch64-context-validate.S 
b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
new file mode 100644
index 00..31c8d5571c
--- /dev/null
+++ b/cpukit/score/cpu/aarch64/aarch64-context-validate.S
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreCPUAArch64
+ *
+ * @brief Implementation of _CPU_Context_validate
+ *
+ * This file implements _CPU_Context_validate for use in spcontext01.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include 
+#include 
+
+#define FRA

[PATCH v2 5/8] bsps/shared: Add PSCI-based bspreset implementation

2020-09-28 Thread Kinsey Moore 
This adds a bsp_reset implementation based on the ARM PSCI
specification often present in ARMv8 systems.
---
 bsps/shared/start/bspreset-psci.c | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 bsps/shared/start/bspreset-psci.c

diff --git a/bsps/shared/start/bspreset-psci.c 
b/bsps/shared/start/bspreset-psci.c
new file mode 100644
index 00..215be5c9b5
--- /dev/null
+++ b/bsps/shared/start/bspreset-psci.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief PSCI-based BSP reset hook.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+void bsp_reset(void)
+{
+   uint32_t PSCI_FN_SYSTEM_RESET = 0x8409;
+   __asm__ volatile(
+#if defined(AARCH64_MULTILIB_ARCH_V8) || 
defined(AARCH64_MULTILIB_ARCH_V8_ILP32)
+   "mov x0, %0\n"
+#else
+   "mov r0, %0\n"
+#endif
+#ifdef BSP_RESET_SMC
+   "smc #0\n"
+#else
+   "hvc #0\n"
+#endif
+   : : "r" (PSCI_FN_SYSTEM_RESET)
+   );
+}
-- 
2.20.1

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[PATCH v2 8/8] bsps: Add Cortex-A53 ILP32 BSP variant

2020-09-28 Thread Kinsey Moore 
This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
---
 bsps/aarch64/shared/start/linkcmds.base   |  4 -
 bsps/aarch64/shared/start/start.S | 16 
 spec/build/bsps/aarch64/a53/abi.yml   |  7 +-
 .../bsps/aarch64/a53/bspa53ilp32qemu.yml  | 73 +++
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  2 +-
 .../build/bsps/aarch64/a53/linkcmds_ilp32.yml | 71 ++
 .../a53/{linkcmds.yml => linkcmds_lp64.yml}   |  3 +
 7 files changed, 170 insertions(+), 6 deletions(-)
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml
 rename spec/build/bsps/aarch64/a53/{linkcmds.yml => linkcmds_lp64.yml} (97%)

diff --git a/bsps/aarch64/shared/start/linkcmds.base 
b/bsps/aarch64/shared/start/linkcmds.base
index f67404ab62..690ed4b5c9 100644
--- a/bsps/aarch64/shared/start/linkcmds.base
+++ b/bsps/aarch64/shared/start/linkcmds.base
@@ -34,10 +34,6 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-OUTPUT_FORMAT ("elf64-littleaarch64")
-
-OUTPUT_ARCH (aarch64)
-
 ENTRY (_start)
 STARTUP (start.o)
 
diff --git a/bsps/aarch64/shared/start/start.S 
b/bsps/aarch64/shared/start/start.S
index f60e840137..f4c62b2b6c 100644
--- a/bsps/aarch64/shared/start/start.S
+++ b/bsps/aarch64/shared/start/start.S
@@ -101,19 +101,31 @@ _start:
  * Get current per-CPU control and store it in PL1 only Thread ID
  * Register (TPIDRPRW).
  */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_Per_CPU_Information
+#else
ldr x1, =_Per_CPU_Information
+#endif
add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
mcr p15, 0, x1, c13, c0, 4
 
 #endif
 
/* Calculate interrupt stack area end for current processor */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =_ISR_Stack_size
+#else
ldr x1, =_ISR_Stack_size
+#endif
 #ifdef RTEMS_SMP
add x3, x7, #1
mul x1, x1, x3
 #endif
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w2, =_ISR_Stack_area_begin
+#else
ldr x2, =_ISR_Stack_area_begin
+#endif
add x3, x1, x2
 
/* Save original DAIF value */
@@ -135,7 +147,11 @@ _start:
 * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
 * Exception operation (synchronous errors, IRQ, FIQ, System Errors) 
uses SP0
*/
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+   ldr w1, =bsp_stack_exception_size
+#else
ldr x1, =bsp_stack_exception_size
+#endif
/* Switch to SP0 and set exception stack */
msr spsel, #0
mov sp, x3
diff --git a/spec/build/bsps/aarch64/a53/abi.yml 
b/spec/build/bsps/aarch64/a53/abi.yml
index 894839aa24..b65c10981e 100644
--- a/spec/build/bsps/aarch64/a53/abi.yml
+++ b/spec/build/bsps/aarch64/a53/abi.yml
@@ -8,7 +8,12 @@ copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
 default:
 - -mcpu=cortex-a53
-default-by-variant: []
+default-by-variant:
+- value:
+  - -mcpu=cortex-a53
+  - -mabi=ilp32
+  variants:
+  - aarch64/a53_ilp32_qemu
 enabled-by: true
 links: []
 name: ABI_FLAGS
diff --git a/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml 
b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
new file mode 100644
index 00..3e32999860
--- /dev/null
+++ b/spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml
@@ -0,0 +1,73 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: aarch64
+bsp: a53_ilp32_qemu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+cppflags: []
+enabled-by: true
+family: a53
+includes: []
+install:
+- destination: ${BSP_INCLUDEDIR}
+  source:
+  - bsps/aarch64/a53/include/bsp.h
+  - bsps/aarch64/a53/include/tm27.h
+- destination: ${BSP_INCLUDEDIR}/bsp
+  source:
+  - bsps/aarch64/a53/include/bsp/irq.h
+  - bsps/include/bsp/arm-gic-irq.h
+  - bsps/include/bsp/arm-gic-regs.h
+  - bsps/include/bsp/arm-gic-tm27.h
+  - bsps/include/bsp/arm-gic.h
+  - bsps/aarch64/include/bsp/irq-arch.h
+  - bsps/include/bsp/clock-arm-generic-timer.h
+links:
+- role: build-dependency
+  uid: ../start
+- role: build-dependency
+  uid: abi
+- role: build-dependency
+  uid: optloadoff
+- role: build-dependency
+  uid: optnocachelen
+- role: build-dependency
+  uid: optramlen
+- role: build-dependency
+  uid: optramori
+- role: build-dependency
+  uid: tsta53
+- role: build-dependency
+  uid: ../../obj
+- role: build-dependency
+  uid: ../../objirq
+- role: build-dependency
+  uid: ../../optcachedata
+- role: build-dependency
+  uid: ../../optcacheinst
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: linkcmds_ilp32
+- role: build-dependency
+  uid: ../../bspopts
+source:
+- bsps/aarch64/shared/cache/cache.c
+- bsps/aarch64/a53/console/console.c
+- bsps/aarch64/a53/start/bspstart.c
+- bsps/aarch64/a53/s

[PATCH v2 7/8] bsps: Add Cortex-A53 LP64 basic BSP

2020-09-28 Thread Kinsey Moore 
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
---
 bsps/aarch64/a53/console/console.c|  69 ++
 bsps/aarch64/a53/include/bsp.h|  74 +++
 bsps/aarch64/a53/include/bsp/irq.h|  67 ++
 bsps/aarch64/a53/include/tm27.h   |  46 ++
 bsps/aarch64/a53/start/bspstart.c |  49 ++
 bsps/aarch64/a53/start/bspstarthooks.c|  50 ++
 bsps/aarch64/include/bsp/irq-arch.h   |  50 ++
 bsps/aarch64/include/bsp/linker-symbols.h | 161 +
 bsps/aarch64/include/bsp/start.h  | 189 ++
 bsps/aarch64/shared/cache/cache.c | 612 ++
 .../clock/clock-arm-generic-timer-aarch64.c   | 110 
 .../shared/irq/irq-arm-gicv3-aarch64.c|  58 ++
 bsps/aarch64/shared/start/linkcmds.base   | 450 +
 bsps/aarch64/shared/start/start.S | 219 +++
 spec/build/bsps/aarch64/a53/abi.yml   |  17 +
 .../build/bsps/aarch64/a53/bspa53lp64qemu.yml |  73 +++
 spec/build/bsps/aarch64/a53/linkcmds.yml  |  68 ++
 spec/build/bsps/aarch64/a53/optloadoff.yml|  18 +
 spec/build/bsps/aarch64/a53/optnocachelen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramlen.yml |  18 +
 spec/build/bsps/aarch64/a53/optramori.yml |  18 +
 spec/build/bsps/aarch64/a53/tsta53.yml|  56 ++
 spec/build/bsps/aarch64/start.yml |  14 +
 23 files changed, 2504 insertions(+)
 create mode 100644 bsps/aarch64/a53/console/console.c
 create mode 100644 bsps/aarch64/a53/include/bsp.h
 create mode 100644 bsps/aarch64/a53/include/bsp/irq.h
 create mode 100644 bsps/aarch64/a53/include/tm27.h
 create mode 100644 bsps/aarch64/a53/start/bspstart.c
 create mode 100644 bsps/aarch64/a53/start/bspstarthooks.c
 create mode 100644 bsps/aarch64/include/bsp/irq-arch.h
 create mode 100644 bsps/aarch64/include/bsp/linker-symbols.h
 create mode 100644 bsps/aarch64/include/bsp/start.h
 create mode 100644 bsps/aarch64/shared/cache/cache.c
 create mode 100644 bsps/aarch64/shared/clock/clock-arm-generic-timer-aarch64.c
 create mode 100644 bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c
 create mode 100644 bsps/aarch64/shared/start/linkcmds.base
 create mode 100644 bsps/aarch64/shared/start/start.S
 create mode 100644 spec/build/bsps/aarch64/a53/abi.yml
 create mode 100644 spec/build/bsps/aarch64/a53/bspa53lp64qemu.yml
 create mode 100644 spec/build/bsps/aarch64/a53/linkcmds.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optloadoff.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optnocachelen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramlen.yml
 create mode 100644 spec/build/bsps/aarch64/a53/optramori.yml
 create mode 100644 spec/build/bsps/aarch64/a53/tsta53.yml
 create mode 100644 spec/build/bsps/aarch64/start.yml

diff --git a/bsps/aarch64/a53/console/console.c 
b/bsps/aarch64/a53/console/console.c
new file mode 100644
index 00..d9fffb1e0c
--- /dev/null
+++ b/bsps/aarch64/a53/console/console.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64A53
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+arm_pl011_context a53_qemu_vpl011_context = {
+  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
+  .regs = (volatile pl011 *) BSP_A53_QEMU_VPL011_BASE,
+  .initial_baud = 115200
+};
+
+const console_device console_device_table[] = {
+  {
+.device_file = "/dev/tty

[PATCH v2 2/2] Add AArch64 documentation

2020-09-28 Thread Kinsey Moore 
---
 cpu-supplement/aarch64.rst | 134 +
 user/bsps/aarch64/a53.rst  |  26 +++
 user/bsps/bsps-aarch64.rst |   2 +-
 3 files changed, 161 insertions(+), 1 deletion(-)
 create mode 100644 cpu-supplement/aarch64.rst
 create mode 100644 user/bsps/aarch64/a53.rst

diff --git a/cpu-supplement/aarch64.rst b/cpu-supplement/aarch64.rst
new file mode 100644
index 000..178ea10
--- /dev/null
+++ b/cpu-supplement/aarch64.rst
@@ -0,0 +1,134 @@
+.. SPDX-License-Identifier: CC-BY-SA-4.0
+
+.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
+
+AArch64 Specific Information
+
+
+This chapter discusses the dependencies of the
+*ARM AArch64 architecture*
+(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
+of RTEMS.  The ARMv8-A versions are supported by RTEMS.  Processors with a MMU
+use a static configuration which is set up during system start.  SMP is not
+supported.
+
+**Architecture Documents**
+
+For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
+(http://infocenter.arm.com/).
+
+CPU Model Dependent Features
+
+
+This section presents the set of features which vary across ARM AArch64
+implementations and are of importance to RTEMS.  The set of CPU model feature
+macros are defined in the file 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+based upon the particular CPU model flags specified on the compilation command
+line.
+
+CPU Model Name
+--
+
+The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
+level of this CPU model.  See in 
:file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
+for the values.
+
+Floating Point Unit and SIMD
+
+
+The Advanced SIMD (NEON) and Floating-point instruction set extension is
+supported and expected to be present since all ARMv8-A CPUs are expected to
+support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
+(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
+such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
+
+Multilibs
+=
+
+The following multilib variants are available:
+
+#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and 
pointers
+
+#. ``LP64``: AArch64 instruction set and registers using 64bit long int and 
pointers
+
+Use for example the following GCC options:
+
+.. code-block:: shell
+
+-mcpu=cortex-a53 -mabi=ilp32
+
+to build an application or BSP for the ARMv8-A architecture and tune the code
+for a Cortex-A53 processor.  It is important to select the correct ABI.
+
+Calling Conventions
+===
+
+Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
+(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
+
+Memory Model
+
+
+A flat 64-bit or 32-bit memory model is supported depending on the selected 
multilib
+variant.  All AArch64 CPU variants support a built-in MMU for which basic 
initialization
+for a flat memory model is handled.
+
+Interrupt Processing
+
+
+The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
+configuration signals only sampled at reset.  The ARMv8 architecture has four
+exception types: 
+
+- Synchronous Exception
+
+- Interrupt (IRQ)
+
+- Fast Interrupt (FIQ)
+
+- System Error Exception
+
+Of these types only the synchronous and IRQ exceptions have explicit operating
+system support.  It is intentional that the FIQ is not supported by the 
operating
+system.  Without operating system support for the FIQ it is not necessary to
+disable them during critical sections of the system.
+
+Interrupt Levels
+
+
+There are exactly two interrupt levels on ARMv8 with respect to RTEMS.  Level
+zero corresponds to interrupts enabled.  Level one corresponds to interrupts
+disabled.
+
+Interrupt Stack
+---
+
+The board support package must initialize the interrupt stack. The memory for
+the stacks is usually reserved in the linker script.
+
+Default Fatal Error Processing
+==
+
+The default fatal error handler for this architecture performs the following
+actions:
+
+- disables operating system supported interrupts (IRQ),
+
+- places the error code in ``x0``, and
+
+- executes an infinite loop to simulate a halt processor instruction.
+
+Symmetric Multiprocessing
+=
+
+SMP is not currently supported on ARMv8-A.
+
+Thread-Local Storage
+
+
+Thread-local storage (TLS) is supported. AArch64 uses unmodified TLS variant I
+which is not explcitly stated, but can be inferred from the behavior of GCC and
+*Addenda to, and Errata in, the ABI for the Arm® Architecture*
+(https://developer.arm.com/documentation/ihi0045/g). This alters expectations
+for the size of the TLS Thread Control Block (TCB) such that, under the LP64

[PATCH v2 2/8] spec: Add missing spintrcritical24 definition

2020-09-28 Thread Kinsey Moore 
---
 spec/build/bsps/tstnointrcrit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/spec/build/bsps/tstnointrcrit.yml 
b/spec/build/bsps/tstnointrcrit.yml
index 0460aaabb3..46f7d974c8 100644
--- a/spec/build/bsps/tstnointrcrit.yml
+++ b/spec/build/bsps/tstnointrcrit.yml
@@ -24,6 +24,7 @@ actions:
 spintrcritical21: exclude
 spintrcritical22: exclude
 spintrcritical23: exclude
+spintrcritical24: exclude
 build-type: option
 copyrights:
 - Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
-- 
2.20.1

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[PATCH v2 4/8] bsps: Break out AArch32 GICv3 support

2020-09-28 Thread Kinsey Moore 
This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.
---
 bsps/arm/beagle/irq/irq.c |   1 +
 bsps/arm/csb336/irq/irq.c |   1 +
 bsps/arm/csb337/irq/irq.c |   1 +
 bsps/arm/gumstix/irq/irq.c|   1 +
 bsps/arm/headers.am   |   5 +-
 bsps/arm/include/bsp/irq-arch.h   |  51 
 bsps/arm/lpc24xx/irq/irq-dispatch.c   |   1 +
 bsps/arm/lpc32xx/irq/irq.c|   1 +
 bsps/arm/raspberrypi/irq/irq.c|   1 +
 bsps/arm/rtl22xx/irq/irq.c|   1 +
 bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c   |  55 
 bsps/arm/shared/irq/irq-gic.c |   1 +
 bsps/arm/smdk2410/irq/irq.c   |   1 +
 bsps/arm/tms570/irq/irq.c |   1 +
 bsps/headers.am   |   4 +
 bsps/{arm => }/include/bsp/arm-gic-irq.h  |  12 ++
 bsps/{arm => }/include/bsp/arm-gic-regs.h |   0
 bsps/{arm => }/include/bsp/arm-gic-tm27.h |   0
 bsps/{arm => }/include/bsp/arm-gic.h  |   0
 .../irq/irq-arm-gicv3.c}  | 120 +++---
 .../altera-cyclone-v/bspalteracyclonev.yml|   1 +
 spec/build/bsps/arm/atsam/bspatsam.yml|   1 +
 spec/build/bsps/arm/beagle/obj.yml|   1 +
 spec/build/bsps/arm/csb336/bspcsb336.yml  |   1 +
 spec/build/bsps/arm/csb337/obj.yml|   1 +
 spec/build/bsps/arm/edb7312/bspedb7312.yml|   1 +
 spec/build/bsps/arm/grp.yml   |   8 +-
 spec/build/bsps/arm/gumstix/bspgumstix.yml|   1 +
 spec/build/bsps/arm/imx/bspimx.yml|   1 +
 spec/build/bsps/arm/lm3s69xx/obj.yml  |   1 +
 spec/build/bsps/arm/lpc176x/obj.yml   |   1 +
 spec/build/bsps/arm/lpc24xx/obj.yml   |   1 +
 spec/build/bsps/arm/lpc32xx/obj.yml   |   1 +
 spec/build/bsps/arm/raspberrypi/obj.yml   |   1 +
 .../arm/realview-pbx-a9/bsprealviewpbxa9.yml  |   1 +
 spec/build/bsps/arm/rtl22xx/obj.yml   |   1 +
 spec/build/bsps/arm/smdk2410/bspsmdk2410.yml  |   1 +
 spec/build/bsps/arm/stm32f4/obj.yml   |   1 +
 spec/build/bsps/arm/tms570/obj.yml|   1 +
 spec/build/bsps/arm/xen/bspxen.yml|   1 +
 spec/build/bsps/arm/xilinx-zynq/obj.yml   |   1 +
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |   1 +
 42 files changed, 232 insertions(+), 55 deletions(-)
 create mode 100644 bsps/arm/include/bsp/irq-arch.h
 create mode 100644 bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c
 rename bsps/{arm => }/include/bsp/arm-gic-irq.h (88%)
 rename bsps/{arm => }/include/bsp/arm-gic-regs.h (100%)
 rename bsps/{arm => }/include/bsp/arm-gic-tm27.h (100%)
 rename bsps/{arm => }/include/bsp/arm-gic.h (100%)
 rename bsps/{arm/shared/irq/irq-gicv3.c => shared/irq/irq-arm-gicv3.c} (87%)

diff --git a/bsps/arm/beagle/irq/irq.c b/bsps/arm/beagle/irq/irq.c
index 2fa1a5b0f0..202d2d7aa9 100644
--- a/bsps/arm/beagle/irq/irq.c
+++ b/bsps/arm/beagle/irq/irq.c
@@ -16,6 +16,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/csb336/irq/irq.c b/bsps/arm/csb336/irq/irq.c
index e5887b9717..32b3d1734f 100644
--- a/bsps/arm/csb336/irq/irq.c
+++ b/bsps/arm/csb336/irq/irq.c
@@ -14,6 +14,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include 
diff --git a/bsps/arm/csb337/irq/irq.c b/bsps/arm/csb337/irq/irq.c
index 95e93845b9..465e41e91c 100644
--- a/bsps/arm/csb337/irq/irq.c
+++ b/bsps/arm/csb337/irq/irq.c
@@ -14,6 +14,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include 
diff --git a/bsps/arm/gumstix/irq/irq.c b/bsps/arm/gumstix/irq/irq.c
index 425795b165..4168bc2da6 100644
--- a/bsps/arm/gumstix/irq/irq.c
+++ b/bsps/arm/gumstix/irq/irq.c
@@ -13,6 +13,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include 
diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index f0d498c8f4..29f2426a96 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -17,10 +17,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-a9mpcore-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-a9mpcore-start.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-cp15-start.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-errata.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-irq.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
@@ -28,6 +24,7 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-pl111-regs.h
 include_bsp

[PATCH v2 3/8] bsps: Break out AArch32 portions of GPT driver

2020-09-28 Thread Kinsey Moore 
This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
---
 bsps/arm/imx/headers.am   |  1 +
 bsps/arm/imx/include/bsp.h|  2 -
 bsps/arm/imx/start/bspstart.c |  3 +-
 .../clock/clock-arm-generic-timer-aarch32.c   | 76 +++
 bsps/arm/xen/headers.am   |  1 +
 bsps/arm/xen/include/bsp.h|  2 -
 bsps/arm/xen/start/bspstart.c |  3 +-
 bsps/arm/xilinx-zynqmp/headers.am |  1 +
 bsps/arm/xilinx-zynqmp/include/bsp.h  |  2 -
 bsps/arm/xilinx-zynqmp/start/bspstart.c   |  3 +-
 bsps/include/bsp/clock-arm-generic-timer.h| 73 ++
 .../clock/clock-arm-generic-timer.c}  | 65 
 c/src/lib/libbsp/arm/imx/Makefile.am  |  3 +-
 c/src/lib/libbsp/arm/xen/Makefile.am  |  3 +-
 .../lib/libbsp/arm/xilinx-zynqmp/Makefile.am  |  3 +-
 spec/build/bsps/arm/imx/bspimx.yml|  4 +-
 spec/build/bsps/arm/xen/bspxen.yml|  4 +-
 .../arm/xilinx-zynqmp/bspxilinxzynqmp.yml |  4 +-
 18 files changed, 187 insertions(+), 66 deletions(-)
 create mode 100644 bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
 create mode 100644 bsps/include/bsp/clock-arm-generic-timer.h
 rename bsps/{arm/shared/clock/clock-generic-timer.c => 
shared/clock/clock-arm-generic-timer.c} (71%)

diff --git a/bsps/arm/imx/headers.am b/bsps/arm/imx/headers.am
index 3a093b1698..76c1607871 100644
--- a/bsps/arm/imx/headers.am
+++ b/bsps/arm/imx/headers.am
@@ -21,3 +21,4 @@ include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/imx-gpio.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/imx/include/bsp/irq.h
+include_bsp_HEADERS += 
../../../../../../bsps/include/bsp/clock-arm-generic-timer.h
diff --git a/bsps/arm/imx/include/bsp.h b/bsps/arm/imx/include/bsp.h
index 134b3fd858..99b7a0d1d7 100644
--- a/bsps/arm/imx/include/bsp.h
+++ b/bsps/arm/imx/include/bsp.h
@@ -57,8 +57,6 @@ extern uintptr_t imx_gic_dist_base;
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0
 
-void arm_generic_timer_get_config(uint32_t *frequency, uint32_t *irq);
-
 void *imx_get_reg_of_node(const void *fdt, int node);
 
 int imx_iomux_configure_pins(const void *fdt, uint32_t phandle);
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 5fb07bf60a..ff5edaf5a1 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -58,7 +59,7 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return intr[1] + MAGIC_IRQ_OFFSET;
 }
 
-void arm_generic_timer_get_config(
+void aarch_generic_timer_get_config(
   uint32_t *frequency,
   uint32_t *irq
 )
diff --git a/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c 
b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
new file mode 100644
index 00..70509e2a86
--- /dev/null
+++ b/bsps/arm/shared/clock/clock-arm-generic-timer-aarch32.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsARMShared
+ *
+ * @brief ARM-specific clock driver functions.
+ */
+
+/*
+ * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include 
+
+uint64_t aarch_gt_clock_get_compare_value(void)
+{
+#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
+  return arm_cp15_get_counter_pl1_virtual_compare_value();
+#else
+  return arm_cp15_get_counter_pl

[PATCH v2 1/8] Move ARM PL011 UART driver

2020-09-28 Thread Kinsey Moore 
This UART driver is now needed for BSPs other than ARM.
---
 bsps/arm/headers.am| 2 --
 bsps/arm/raspberrypi/console/console-config.c  | 2 +-
 bsps/arm/realview-pbx-a9/include/bsp/console.h | 2 +-
 bsps/arm/xen/console/console.c | 2 +-
 bsps/headers.am| 2 ++
 bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h | 0
 bsps/{arm/include/bsp => include/libchip}/arm-pl011.h  | 2 +-
 bsps/{arm/shared => shared/dev}/serial/arm-pl011.c | 2 +-
 c/src/lib/libbsp/arm/raspberrypi/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am   | 2 +-
 c/src/lib/libbsp/arm/xen/Makefile.am   | 2 +-
 spec/build/bsps/arm/grp.yml| 2 --
 spec/build/bsps/arm/raspberrypi/obj.yml| 1 -
 spec/build/bsps/arm/realview-pbx-a9/bsprealviewpbxa9.yml   | 1 -
 spec/build/bsps/arm/xen/bspxen.yml | 1 -
 spec/build/bsps/obj.yml| 3 +++
 16 files changed, 13 insertions(+), 15 deletions(-)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011-regs.h (100%)
 rename bsps/{arm/include/bsp => include/libchip}/arm-pl011.h (96%)
 rename bsps/{arm/shared => shared/dev}/serial/arm-pl011.c (98%)

diff --git a/bsps/arm/headers.am b/bsps/arm/headers.am
index 3d2b09effa..f0d498c8f4 100644
--- a/bsps/arm/headers.am
+++ b/bsps/arm/headers.am
@@ -21,8 +21,6 @@ include_bsp_HEADERS += 
../../../../../bsps/arm/include/bsp/arm-gic-irq.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic-tm27.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-gic.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011-regs.h
-include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl011.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050-regs.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl050.h
 include_bsp_HEADERS += ../../../../../bsps/arm/include/bsp/arm-pl111-fb.h
diff --git a/bsps/arm/raspberrypi/console/console-config.c 
b/bsps/arm/raspberrypi/console/console-config.c
index bb0b596019..27d02bbe39 100644
--- a/bsps/arm/raspberrypi/console/console-config.c
+++ b/bsps/arm/raspberrypi/console/console-config.c
@@ -25,13 +25,13 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/bsps/arm/realview-pbx-a9/include/bsp/console.h 
b/bsps/arm/realview-pbx-a9/include/bsp/console.h
index da2e4099e2..0ed99ec86e 100644
--- a/bsps/arm/realview-pbx-a9/include/bsp/console.h
+++ b/bsps/arm/realview-pbx-a9/include/bsp/console.h
@@ -15,7 +15,7 @@
 #ifndef LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 #define LIBBSP_ARM_REALVIEW_PBX_A9_BSP_CONSOLE_H
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/xen/console/console.c b/bsps/arm/xen/console/console.c
index 786b98f3ba..446bd2c3b8 100644
--- a/bsps/arm/xen/console/console.c
+++ b/bsps/arm/xen/console/console.c
@@ -29,7 +29,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/bsps/headers.am b/bsps/headers.am
index 5af7e43b4a..825574a5a9 100644
--- a/bsps/headers.am
+++ b/bsps/headers.am
@@ -110,6 +110,8 @@ include_libchip_HEADERS += 
../../bsps/include/libchip/mc68681.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550.h
 include_libchip_HEADERS += ../../bsps/include/libchip/ns16550_p.h
 include_libchip_HEADERS += ../../bsps/include/libchip/open_eth.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011-regs.h
+include_libchip_HEADERS += ../../bsps/include/libchip/arm-pl011.h
 include_libchip_HEADERS += ../../bsps/include/libchip/rtc.h
 include_libchip_HEADERS += ../../bsps/include/libchip/serial.h
 include_libchip_HEADERS += ../../bsps/include/libchip/sersupp.h
diff --git a/bsps/arm/include/bsp/arm-pl011-regs.h 
b/bsps/include/libchip/arm-pl011-regs.h
similarity index 100%
rename from bsps/arm/include/bsp/arm-pl011-regs.h
rename to bsps/include/libchip/arm-pl011-regs.h
diff --git a/bsps/arm/include/bsp/arm-pl011.h b/bsps/include/libchip/arm-pl011.h
similarity index 96%
rename from bsps/arm/include/bsp/arm-pl011.h
rename to bsps/include/libchip/arm-pl011.h
index 49ff413581..947c254bd8 100644
--- a/bsps/arm/include/bsp/arm-pl011.h
+++ b/bsps/include/libchip/arm-pl011.h
@@ -25,7 +25,7 @@
 
 #include 
 
-#include 
+#include 
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsps/arm/shared/serial/arm-pl011.c 
b/bsps/shared/dev/serial/arm-pl011.c
similarity index 98%
rename from bsps/arm/shared/serial/arm-pl011.c
rename to bsps/shared/dev/serial/arm-pl011.c
index 44a409e551..39225e8349 100644
--- a/bsps/arm/shared/serial/arm-pl011.c
+++ b/bsps/shared/dev/serial/arm-pl011.c
@@

Re: [PATCH] shell: Fixing bug in line editing of the shell with CTRL-U.

2020-09-28 Thread Frank Kühndel 
Hello,

we fixed the minor issues in the patch, created two tickets (#4096 for
milestone 5 and #4097 for 6) and Sebastian Huber added the fix to the
git sources.

Many thank to all reviewers for their helpful comments.

Greetings,
Frank

On 9/27/20 9:26 AM, Chris Johns wrote:
> On 26/9/20 2:06 am, Joel Sherrill wrote:
>> On Fri, Sep 25, 2020, 10:06 AM Gedare Bloom > > wrote:
>>
>> On Fri, Sep 25, 2020 at 3:11 AM Frank Kuehndel
>> > > wrote:
>> >
>> > This patch fixes a tiny bug in the command line editing of the RTEMS
>> shell. Typing CTRL-U in the shell should remove all characters left of 
>> the
>> cursor. After pressing CTRL-U, the current implementation does wrongly 
>> place
>> the cursor at the end of the line instead at its beginning.
>> >
>> >
>> > To reproduce the bug, start the shell and type 'abc123' (no ):
>> >
>> > > ~/src/rtems $ qemu-system-arm -net none -nographic -M 
>> realview-pbx-a9 -m
>> 256M -kernel build/arm/realview_pbx_a9_qemu/testsuites/libtests/dl10.exe
>> > >
>> > >
>> > > *** BEGIN OF TEST libdl (RTL) 10 ***
>> > > *** TEST VERSION: 6.0.0.d9bdf166644f612dd628fe4951c12c6f8e94ba5f
>> > > *** TEST STATE: USER_INPUT
>> > > *** TEST BUILD: RTEMS_DEBUG RTEMS_NETWORKING RTEMS_POSIX_API 
>> RTEMS_SMP
>> > > *** TEST TOOLS: 10.2.1 20200904 (RTEMS 6, RSB
>> 31f936a7b74d60bda609a9960c6e1a705ba54974, Newlib a0d7982)
>> > > RTL (libdl) commands: dl, rtl
>> > >
>> > >
>> > > RTEMS Shell on /dev/foobar. Use 'help' to list commands.
>> > > SHLL [/] # abc123
>> >
>> > Then move the cursor onto the '1' by hitting three times the 
>> 
>> key. Next type -U:
>> >
>> > > SHLL [/] # 123
>> >
>> > Note that the cursor is at the end of the line (after '3') instead of
>> correctly at the beginning (on the '1'), now.
>> >
>> > Continuing typing 'echo ' incorrectly results in the output:
>> >
>> > > SHLL [/] # 123echo 123
>> >
>> > The patch changes this behavior so that the cursor in the second last 
>> step
>> will be on the '1' and typing 'echo ' will then correctly reflected as:
>> >
>> > > SHLL [/] # echo 123
>> >
>>
>> Please put the above bug details into a ticket
>> https://devel.rtems.org/wiki/NewTicket with a milestone of 6
>>
>>
>> Why wouldn't this also be appropriate for 5?
>>
> It is fine for 5 with a ticket.
> 
>> And can anyone confirm this happens on real hardware? Sometimes control
>> characters act funny on simulators.
> It is broken on hardware so the simulator and hardware match.
> 
> Chris
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> 

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Not Really Duplicates on build@ Mailing Lists

2020-09-28 Thread Joel Sherrill 
Hi

If you look at the build@ logs, you will see some apparently duplicate test
reports. Well we hope they are duplicates. Otherwise waf and autoconf
builds are not the same. :)

I have updated my script to handle waf and autoconf builds. Based on which
files are present, it builds one way or both. This includes running the
tests. It builds the same BSP in the same configuration with both build
systems back to back.

Once all the bugs are out of this pass, I intend to build every BSP with
both systems and then iterate over a number of configurations for every BSP.

FWIW my build_bsp script takes simple arguments to toggle build settings.
It was easy to use these to drive waf ini settings and --enable/disable. I
still contend it would be easy to provide a script to map a configure
command onto a config.ini file.

--joel
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Re: License files missing on 5-freebsd-12 branch

2020-09-28 Thread Christian Mauderer 
On 17/09/2020 23:37, Chris Johns wrote:
> On 17/9/20 10:57 pm, Joel Sherrill wrote:
>> On Thu, Sep 17, 2020 at 4:33 AM Christian Mauderer
>> > > wrote:
>>
>> Hello,
>>
>> Chris pinged me that I missed to add these patches to the 5-freebsd-12
>> branch. It would be good if we would add the license files to the
>> release branch too. This will allow users to easily find the correct
>> licenses.
>>
>>
>> +1  
> 
> OK to push.
> 
> Thanks
> Chris
> 

Sorry for the delay. I didn't manage to do these before my vacation and
then I forgot them during vacation. I just pushed them.

Best regards

Christian

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