Re: sifive risc-v hifive unleashed bsp (qemu)

2021-02-12 Thread Joel Sherrill 
On Fri, Feb 12, 2021, 8:47 PM Rohan kumar  wrote:

> I will look into this in more detail and get back to you but in mean time
> I want to contribute to any issues so can you suggest any thats need to be
> solved or how do I look for from my own.
>

Projects or just smaller issues?

There is a tag in the ticketing system for small projects but this query
makes me wonder if some should be closed. Deciding a ticket is dead is
good. :)


https://devel.rtems.org/query?status=accepted=assigned=new=reopened=~Small=id=summary=status=owner=type=priority=milestone=priority

Looking at Coverity is a quick way to find a small task. Some tickets
geared to adding a test aren't bad.

--joel

>
> Thanks
> Sanskar
>
>
> On Fri, Feb 12, 2021, 3:01 PM Hesham Almatary <
> hesham.almat...@cl.cam.ac.uk> wrote:
>
>> On Fri, 12 Feb 2021 at 11:24, Sanskar Khandelwal 
>> wrote:
>> >
>> > Hello joel,
>> >
>> > 1. #4162 : sifive risc-v hifive unleashed bsp (qemu)
>> > As you mentioned this a good project i thought to search more about
>> this project I learned a lot while doing so but I still don't understand
>> what is the goal of this project (the description on the ticket is not very
>> detailed ) also I don't have any idea on how to make approach for this
>> project right now so if you can clear both my doubt it will be big help.
>> >
>> You'd need to identify the devices for this platform that QEMU
>> supports (e.g., networking, UART, flash, etc?) and propose some
>> timeline to implement (a subset of) them. That would be part of your
>> proposal evaluation.
>>
>> > Also as you mention that this can be a big task for a gsoc time frame I
>> am thinking that I can do some of it after gsoc too.
>> >
>> > Also I looked for some more open projects and found these interesting
>> so I wanted to know if these are open for participation for gsoc and what's
>> their status and what further enhancement you are looking at each of them.
>> >
>> > 2. #3337 : RISC-V Port in Supervisor Mode
>> > 3. #4182 : Port Rust to RTEMS
>> >
>> > Another thing is that while I am learning more about these projects I
>> want to contribute, so if you can tell me about any issue that I can work
>> on, it will be nice. I think this will help get me more familiar with rtems
>> too.
>> >
>> > Thanks
>> > Sanskar
>> > ___
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>> > devel@rtems.org
>> > http://lists.rtems.org/mailman/listinfo/devel
>> ___
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>> devel@rtems.org
>> http://lists.rtems.org/mailman/listinfo/devel
>>
> ___
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Re: sifive risc-v hifive unleashed bsp (qemu)

2021-02-12 Thread Rohan kumar 
I will look into this in more detail and get back to you but in mean time I
want to contribute to any issues so can you suggest any thats need to be
solved or how do I look for from my own.

Thanks
Sanskar


On Fri, Feb 12, 2021, 3:01 PM Hesham Almatary 
wrote:

> On Fri, 12 Feb 2021 at 11:24, Sanskar Khandelwal 
> wrote:
> >
> > Hello joel,
> >
> > 1. #4162 : sifive risc-v hifive unleashed bsp (qemu)
> > As you mentioned this a good project i thought to search more about this
> project I learned a lot while doing so but I still don't understand what is
> the goal of this project (the description on the ticket is not very
> detailed ) also I don't have any idea on how to make approach for this
> project right now so if you can clear both my doubt it will be big help.
> >
> You'd need to identify the devices for this platform that QEMU
> supports (e.g., networking, UART, flash, etc?) and propose some
> timeline to implement (a subset of) them. That would be part of your
> proposal evaluation.
>
> > Also as you mention that this can be a big task for a gsoc time frame I
> am thinking that I can do some of it after gsoc too.
> >
> > Also I looked for some more open projects and found these interesting so
> I wanted to know if these are open for participation for gsoc and what's
> their status and what further enhancement you are looking at each of them.
> >
> > 2. #3337 : RISC-V Port in Supervisor Mode
> > 3. #4182 : Port Rust to RTEMS
> >
> > Another thing is that while I am learning more about these projects I
> want to contribute, so if you can tell me about any issue that I can work
> on, it will be nice. I think this will help get me more familiar with rtems
> too.
> >
> > Thanks
> > Sanskar
> > ___
> > devel mailing list
> > devel@rtems.org
> > http://lists.rtems.org/mailman/listinfo/devel
> ___
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> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
>
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[PATCH 3/3] powerpc/shared: Fix warnings

2021-02-12 Thread chrisj 
From: Chris Johns 

---
 bsps/powerpc/shared/vme/bspVmeDmaList.c |  3 ++-
 bsps/powerpc/shared/vme/vmeTsi148.c | 15 +--
 bsps/powerpc/shared/vme/vmeUniverse.c   |  8 +---
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/bsps/powerpc/shared/vme/bspVmeDmaList.c 
b/bsps/powerpc/shared/vme/bspVmeDmaList.c
index 73b398dda1..fb552acdab 100644
--- a/bsps/powerpc/shared/vme/bspVmeDmaList.c
+++ b/bsps/powerpc/shared/vme/bspVmeDmaList.c
@@ -47,6 +47,7 @@
  * -- SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -71,7 +72,7 @@ typedef struct VMEDmaListNodeRec_ {
 static void
 lprint(VMEDmaListNode d)
 {
-   printf("n 0x%08lx, p: 0x%08lx, n: 0x%08lx d: 0x%08lx\n",
+   printf("n 0x%08" PRIu32", p: 0x%08" PRIu32 ", n: 0x%08" PRIu32 " d: 
0x%08" PRIu32 "\n",
(uint32_t)d, (uint32_t)d->p, (uint32_t)d->n, (uint32_t)d->d);
 }
 #endif
diff --git a/bsps/powerpc/shared/vme/vmeTsi148.c 
b/bsps/powerpc/shared/vme/vmeTsi148.c
index 4e1893b593..3cb3f94e75 100644
--- a/bsps/powerpc/shared/vme/vmeTsi148.c
+++ b/bsps/powerpc/shared/vme/vmeTsi148.c
@@ -46,6 +46,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -2352,8 +2353,10 @@ static uint32_t
 vme_attr(uint32_t xfer_mode)
 {
 uint32_t vme_mode;
-   if ( am2omode(xfer_mode, _mode) )
+unsigned long ul;
+   if ( am2omode(xfer_mode, ) )
return BSP_VMEDMA_STATUS_UNSUP;
+   vme_mode = (uint32_t) ul;
 
/* am2omode may set prefetch and other bits */
vme_mode &= TSI_DXAT_OTAT_MSK;
@@ -2405,11 +2408,11 @@ static void
 tsi_desc_dump(DmaDescriptor p)
 {
 VmeTsi148DmaListDescriptor d = p;
-   printf("   DSA: 0x%08lx%08lx\n", ld_be32(>dsau),  
ld_be32(>dsal));
-   printf("   DDA: 0x%08lx%08lx\n", ld_be32(>ddau),  
ld_be32(>ddal));
-   printf("   NLA: 0x%08lx%08lx\n", ld_be32(>dnlau), 
ld_be32(>dnlal));
-   printf("   SAT: 0x%08lx  DAT: 0x%08lx\n", 
ld_be32(>dsat), ld_be32(>ddat));
-   printf("   CNT: 0x%08lx\n",  ld_be32(>dcnt));
+   printf("   DSA: 0x%08" PRIx32 "%08" PRIx32 "\n", 
ld_be32(>dsau),  ld_be32(>dsal));
+   printf("   DDA: 0x%08" PRIx32 "%08" PRIx32 "\n", 
ld_be32(>ddau),  ld_be32(>ddal));
+   printf("   NLA: 0x%08" PRIx32 "%08" PRIx32 "\n", 
ld_be32(>dnlau), ld_be32(>dnlal));
+   printf("   SAT: 0x%08" PRIx32 "  DAT: 0x%08" PRIx32 
"\n", ld_be32(>dsat), ld_be32(>ddat));
+   printf("   CNT: 0x%08" PRIx32 "\n",  ld_be32(>dcnt));
 }
 
 
diff --git a/bsps/powerpc/shared/vme/vmeUniverse.c 
b/bsps/powerpc/shared/vme/vmeUniverse.c
index c7373b4e51..18fe61f7c4 100644
--- a/bsps/powerpc/shared/vme/vmeUniverse.c
+++ b/bsps/powerpc/shared/vme/vmeUniverse.c
@@ -1301,6 +1301,7 @@ static uint32_t
 xfer_mode2dctl(uint32_t xfer_mode)
 {
 uint32_t dctl;
+unsigned long ul;
 
/* Check requested bus mode */
 
@@ -1323,8 +1324,9 @@ uint32_t dctl;
return BSP_VMEDMA_STATUS_UNSUP;
 
/* Luckily DCTL bits match MCTL bits so we can use am2mode */
-   if ( am2mode( 1, xfer_mode,  ) )
+   if ( am2mode( 1, xfer_mode,  ) )
return BSP_VMEDMA_STATUS_UNSUP;
+   dctl = (uint32_t) ul;
 
/* However, the book says that for DMA VAS==5 [which would
 * be a CSR access] is reserved. Tests indicate that
@@ -1959,7 +1961,7 @@ unsigned long linten;
 #else
vmeUniverseIntDisable(lvl);
 #endif
-   printk("vmeUniverse ISR: error read from STATID 
register; (level: %i) STATID: 0x%08" PRIx32 " -- DISABLING\n", lvl, status);
+   printk("vmeUniverse ISR: error read from STATID 
register; (level: %i) STATID: 0x%08lx -- DISABLING\n", lvl, status);
} else if (!(ip=universeHdlTbl[status & 
UNIV_VIRQ_STATID_MASK])) {
 #ifdef BSP_PIC_DO_EOI
linten &= ~msk;
@@ -1967,7 +1969,7 @@ unsigned long linten;
vmeUniverseIntDisable(lvl);
 #endif
/* TODO: log error message - RTEMS has no 
logger :-( */
-   printk("vmeUniverse ISR: no handler installed for this 
vector; (level: %i) STATID: 0x%08" PRIx32 " -- DISABLING\n", lvl, status);
+   printk("vmeUniverse ISR: no handler installed for this 
vector; (level: %i) STATID: 0x%08lx -- DISABLING\n", lvl, status);
} else {
/* dispatch handler, it must clear the IRQ at 
the device */
ip->isr(ip->usrData, 
status_VIRQ_STATID_MASK);
-- 
2.24.1

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[PATCH 2/3] powerpc/motorola_powerpc: Fix tm27 warnings

2021-02-12 Thread chrisj 
From: Chris Johns 

---
 bsps/powerpc/motorola_powerpc/include/tm27.h | 24 +---
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/bsps/powerpc/motorola_powerpc/include/tm27.h 
b/bsps/powerpc/motorola_powerpc/include/tm27.h
index 4d616cb3ed..15e66f2a81 100644
--- a/bsps/powerpc/motorola_powerpc/include/tm27.h
+++ b/bsps/powerpc/motorola_powerpc/include/tm27.h
@@ -25,15 +25,23 @@
 
 #define MUST_WAIT_FOR_INTERRUPT 1
 
-void nullFunc(void) {}
-static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
- 0,
- (rtems_irq_enable) nullFunc,
- (rtems_irq_disable) nullFunc,
- (rtems_irq_is_enabled) nullFunc};
-static void Install_tm27_vector(void (*_handler)(void))
+static void null_irq_enable(const rtems_irq_connect_data* a) { (void) a; }
+static void null_irq_disable(const rtems_irq_connect_data* a) { (void) a; }
+static int null_irq_is_enabled(const rtems_irq_connect_data* a) { (void) a; 
return 0; }
+
+static rtems_irq_connect_data clockIrqData =
+{
+ .name = BSP_DECREMENTER,
+ .hdl = 0,
+ .handle = 0,
+ .on = null_irq_enable,
+ .off = null_irq_disable,
+ .isOn = null_irq_is_enabled
+};
+
+static void Install_tm27_vector(rtems_isr (*_handler)(rtems_vector_number))
 {
-  clockIrqData.hdl = _handler;
+  clockIrqData.hdl = (rtems_irq_hdl) _handler;
   if (!BSP_install_rtems_irq_handler ()) {
printk("Error installing clock interrupt handler!\n");
rtems_fatal_error_occurred(1);
-- 
2.24.1

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[PATCH 1/3] score: Fix warning in thread queue ops

2021-02-12 Thread chrisj 
From: Chris Johns 

---
 cpukit/score/src/threadqops.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/cpukit/score/src/threadqops.c b/cpukit/score/src/threadqops.c
index ef20431178..d6ba9dad57 100644
--- a/cpukit/score/src/threadqops.c
+++ b/cpukit/score/src/threadqops.c
@@ -604,9 +604,9 @@ static Thread_Control *_Thread_queue_Priority_first(
   const Thread_queue_Heads *heads
 )
 {
-  Thread_queue_Priority_queue *priority_queue;
-  Priority_Node   *first;
-  Scheduler_Node  *scheduler_node;
+  const Thread_queue_Priority_queue *priority_queue;
+  Priority_Node *first;
+  Scheduler_Node*scheduler_node;
 
 #if defined(RTEMS_SMP)
   _Assert( !_Chain_Is_empty( >Heads.Fifo ) );
-- 
2.24.1

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Re: [PATCH v2] Update motorola_power to irq-generic interrupt management

2021-02-12 Thread Joel Sherrill 
On Fri, Feb 12, 2021 at 7:38 PM  wrote:

> From: Chris Johns 
>
> - Add support to the BSP to enable irq-generic management
>
> - Update the powerpc shared irq code to support irq-generic. This
>   is an option in option for existing powerpc bsps. This change
>

Probably just an option. :)

I'm cool with the patch. This code is all over the place formatting
wise and caution is advised.


>   should be simpler now
>
> - Fix a number of issues in ISA IRQ controller handling by porting
>   fixes from the i386 (PC) BSP
>
> Closes #4238
> Closes #4239
> ---
>  bsps/powerpc/include/bsp/irq_supp.h   |   5 +
>  .../motorola_powerpc/include/bsp/irq.h|  15 +-
>  .../powerpc/motorola_powerpc/start/bspstart.c |   7 +-
>  bsps/powerpc/shared/irq/i8259.c   | 152 ++
>  bsps/powerpc/shared/irq/irq_init.c|  15 +-
>  bsps/powerpc/shared/irq/openpic_i8259_irq.c   |  27 ++--
>  bsps/powerpc/shared/irq/ppc-irq-generic.c | 117 ++
>  .../bsps/powerpc/motorola_powerpc/grp.yml |   2 +-
>  .../bsps/powerpc/motorola_powerpc/obj.yml |   3 +-
>  9 files changed, 286 insertions(+), 57 deletions(-)
>  create mode 100644 bsps/powerpc/shared/irq/ppc-irq-generic.c
>
> diff --git a/bsps/powerpc/include/bsp/irq_supp.h
> b/bsps/powerpc/include/bsp/irq_supp.h
> index 65af48c87f..fbb16d6211 100644
> --- a/bsps/powerpc/include/bsp/irq_supp.h
> +++ b/bsps/powerpc/include/bsp/irq_supp.h
> @@ -50,6 +50,11 @@ extern int  BSP_disable_irq_at_pic(const
> rtems_irq_number irqLine);
>   */
>  extern int  BSP_setup_the_pic(rtems_irq_global_settings* config);
>
> +/*
> + * Set up for the irq-generic.h interface.
> + */
> +int BSP_rtems_irq_generic_set(rtems_irq_global_settings* config);
> +
>  /* IRQ dispatcher to be defined by the PIC driver; note that it MUST
>   * implement shared interrupts.
>   * Note also that the exception frame passed to this handler is not very
> diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> index 3690dbbff7..cbb6ff69cf 100644
> --- a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> +++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> @@ -19,9 +19,17 @@
>  #ifndef BSP_POWERPC_IRQ_H
>  #define BSP_POWERPC_IRQ_H
>
> +#ifndef BSP_SHARED_HANDLER_SUPPORT
>  #define BSP_SHARED_HANDLER_SUPPORT  1
> +#endif
> +
>  #include 
> -#include 
> +
> +/*
> + * Switch to using the generic support. Remove this when all BSPs have
> + * been converted.
> + */
> +#define BSP_POWERPC_IRQ_GENERIC_SUPPORT 1
>
>  /*
>   * 8259 edge/level control definitions at VIA
> @@ -107,6 +115,8 @@ extern "C" {
>  #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
>  #define BSP_LOWEST_OFFSET  (BSP_ISA_IRQ_LOWEST_OFFSET)
>  #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
> +#define BSP_INTERRUPT_VECTOR_MIN   (BSP_LOWEST_OFFSET)
> +#define BSP_INTERRUPT_VECTOR_MAX   (BSP_MAX_OFFSET)
>  /*
>   * Some ISA IRQ symbolic name definition
>   */
> @@ -191,6 +201,9 @@ int BSP_irq_ack_at_i8259s   (const
> rtems_irq_number irqLine);
>   */
>  int BSP_irq_enabled_at_i8259s  (const rtems_irq_number irqLine);
>
> +unsigned short BSP_irq_suspend_i8259s(unsigned short mask);
> +void BSP_irq_resume_i8259s(unsigned short in_progress_save);
> +
>  extern void BSP_rtems_irq_mng_init(unsigned cpuId);
>  extern void BSP_i8259s_init(void);
>
> diff --git a/bsps/powerpc/motorola_powerpc/start/bspstart.c
> b/bsps/powerpc/motorola_powerpc/start/bspstart.c
> index e74b02c446..ef8418e2c6 100644
> --- a/bsps/powerpc/motorola_powerpc/start/bspstart.c
> +++ b/bsps/powerpc/motorola_powerpc/start/bspstart.c
> @@ -27,6 +27,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -334,10 +335,8 @@ static void bsp_early( void )
> */
>bsp_clicks_per_usec   = BSP_bus_frequency/(BSP_time_base_divisor *
> 1000);
>
> -  /*
> -   * Initalize RTEMS IRQ system
> -   */
> -  BSP_rtems_irq_mng_init(0);
> +  /* Initialize interrupt support */
> +  bsp_interrupt_initialize();
>
>/* Activate the page table mappings only after
> * initializing interrupts because the irq_mng_init()
> diff --git a/bsps/powerpc/shared/irq/i8259.c
> b/bsps/powerpc/shared/irq/i8259.c
> index 7363e87ba0..6a80e24946 100644
> --- a/bsps/powerpc/shared/irq/i8259.c
> +++ b/bsps/powerpc/shared/irq/i8259.c
> @@ -12,6 +12,19 @@
>  #include 
>  #include 
>
> +#define PIC_EOSI0x60///< End of Specific Interrupt (EOSI)
> +#define PIC_EOI 0x20///< Generic End of Interrupt (EOI)
> +
> +/* Operation control word type 3.  Bit 3 (0x08) must be set. Even
> address. */
> +#define PIC_OCW3_RIS0x01/* 1 = read IS, 0 = read IR */
> +#define PIC_OCW3_RR 0x02/* register read */
> +#define PIC_OCW3_P  0x04/* poll mode command */
> +/* 0x08 must be 1 to select OCW3 vs OCW2 */
> +#define

[PATCH v2] Update motorola_power to irq-generic interrupt management

2021-02-12 Thread chrisj 
From: Chris Johns 

- Add support to the BSP to enable irq-generic management

- Update the powerpc shared irq code to support irq-generic. This
  is an option in option for existing powerpc bsps. This change
  should be simpler now

- Fix a number of issues in ISA IRQ controller handling by porting
  fixes from the i386 (PC) BSP

Closes #4238
Closes #4239
---
 bsps/powerpc/include/bsp/irq_supp.h   |   5 +
 .../motorola_powerpc/include/bsp/irq.h|  15 +-
 .../powerpc/motorola_powerpc/start/bspstart.c |   7 +-
 bsps/powerpc/shared/irq/i8259.c   | 152 ++
 bsps/powerpc/shared/irq/irq_init.c|  15 +-
 bsps/powerpc/shared/irq/openpic_i8259_irq.c   |  27 ++--
 bsps/powerpc/shared/irq/ppc-irq-generic.c | 117 ++
 .../bsps/powerpc/motorola_powerpc/grp.yml |   2 +-
 .../bsps/powerpc/motorola_powerpc/obj.yml |   3 +-
 9 files changed, 286 insertions(+), 57 deletions(-)
 create mode 100644 bsps/powerpc/shared/irq/ppc-irq-generic.c

diff --git a/bsps/powerpc/include/bsp/irq_supp.h 
b/bsps/powerpc/include/bsp/irq_supp.h
index 65af48c87f..fbb16d6211 100644
--- a/bsps/powerpc/include/bsp/irq_supp.h
+++ b/bsps/powerpc/include/bsp/irq_supp.h
@@ -50,6 +50,11 @@ extern int  BSP_disable_irq_at_pic(const rtems_irq_number 
irqLine);
  */
 extern int  BSP_setup_the_pic(rtems_irq_global_settings* config);
 
+/*
+ * Set up for the irq-generic.h interface.
+ */
+int BSP_rtems_irq_generic_set(rtems_irq_global_settings* config);
+
 /* IRQ dispatcher to be defined by the PIC driver; note that it MUST
  * implement shared interrupts.
  * Note also that the exception frame passed to this handler is not very
diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h 
b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
index 3690dbbff7..cbb6ff69cf 100644
--- a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
+++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
@@ -19,9 +19,17 @@
 #ifndef BSP_POWERPC_IRQ_H
 #define BSP_POWERPC_IRQ_H
 
+#ifndef BSP_SHARED_HANDLER_SUPPORT
 #define BSP_SHARED_HANDLER_SUPPORT  1
+#endif
+
 #include 
-#include 
+
+/*
+ * Switch to using the generic support. Remove this when all BSPs have
+ * been converted.
+ */
+#define BSP_POWERPC_IRQ_GENERIC_SUPPORT 1
 
 /*
  * 8259 edge/level control definitions at VIA
@@ -107,6 +115,8 @@ extern "C" {
 #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
 #define BSP_LOWEST_OFFSET  (BSP_ISA_IRQ_LOWEST_OFFSET)
 #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
+#define BSP_INTERRUPT_VECTOR_MIN   (BSP_LOWEST_OFFSET)
+#define BSP_INTERRUPT_VECTOR_MAX   (BSP_MAX_OFFSET)
 /*
  * Some ISA IRQ symbolic name definition
  */
@@ -191,6 +201,9 @@ int BSP_irq_ack_at_i8259s   (const 
rtems_irq_number irqLine);
  */
 int BSP_irq_enabled_at_i8259s  (const rtems_irq_number irqLine);
 
+unsigned short BSP_irq_suspend_i8259s(unsigned short mask);
+void BSP_irq_resume_i8259s(unsigned short in_progress_save);
+
 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
 extern void BSP_i8259s_init(void);
 
diff --git a/bsps/powerpc/motorola_powerpc/start/bspstart.c 
b/bsps/powerpc/motorola_powerpc/start/bspstart.c
index e74b02c446..ef8418e2c6 100644
--- a/bsps/powerpc/motorola_powerpc/start/bspstart.c
+++ b/bsps/powerpc/motorola_powerpc/start/bspstart.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -334,10 +335,8 @@ static void bsp_early( void )
*/
   bsp_clicks_per_usec   = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
 
-  /*
-   * Initalize RTEMS IRQ system
-   */
-  BSP_rtems_irq_mng_init(0);
+  /* Initialize interrupt support */
+  bsp_interrupt_initialize();
 
   /* Activate the page table mappings only after
* initializing interrupts because the irq_mng_init()
diff --git a/bsps/powerpc/shared/irq/i8259.c b/bsps/powerpc/shared/irq/i8259.c
index 7363e87ba0..6a80e24946 100644
--- a/bsps/powerpc/shared/irq/i8259.c
+++ b/bsps/powerpc/shared/irq/i8259.c
@@ -12,6 +12,19 @@
 #include 
 #include 
 
+#define PIC_EOSI0x60///< End of Specific Interrupt (EOSI)
+#define PIC_EOI 0x20///< Generic End of Interrupt (EOI)
+
+/* Operation control word type 3.  Bit 3 (0x08) must be set. Even address. */
+#define PIC_OCW3_RIS0x01/* 1 = read IS, 0 = read IR */
+#define PIC_OCW3_RR 0x02/* register read */
+#define PIC_OCW3_P  0x04/* poll mode command */
+/* 0x08 must be 1 to select OCW3 vs OCW2 */
+#define PIC_OCW3_SEL0x08/* must be 1 */
+/* 0x10 must be 0 to select OCW3 vs ICW1 */
+#define PIC_OCW3_SMM0x20/* special mode mask */
+#define PIC_OCW3_ESMM   0x40/* enable SMM */
+
 /*-+
 | Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register.

Re: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

2021-02-12 Thread Chris Johns 
On 13/2/21 10:18 am, Kinsey Moore wrote:
> On 12/2/21 5:14 am, Chris Johns wrote:
>> On 13/2/21 10:10 am, Joel Sherrill wrote:
>>> On Fri, Feb 12, 2021 at 5:06 PM Chris Johns >> > wrote:
>>>
>>> On 13/2/21 12:25 am, Jan Sommer wrote:
>>> > This patchset implements a driver for the cadence-spi
>>> > device of the Xilinx Zynq-7000 based SoCs  using the spidev API.s
>>>
>>> Thanks for the driver.
>>>
>>> A quick review of the differences between the Zynq and Ulttrascale in 
>>> this
>>> document from Xilinx:
>>>
>>> 
>>> https://www.xilinx.com/support/documentation/user_guides/ug1213-zynq-migration-guide.pdf
>>> 
>>> 
>>>
>>> shows the SPI hardware is the same. Should this driver be located under
>>> `bsps/shared/dev/spi` and then shared?
>>>
>>> If Kinsey or Jan confirms, then yes it should.
>>
>> Thanks.
>>
>>> Kinsey has had a number 
>>> of drivers work after addressing 64-bit clean issues.
>>
>> Nice. Are these in the tree?
> 
> Looking at the register setup for the two SPI instances in MPSoC, I have 
> verified that these peripherals are identical. It should definitely go in 
> bsps/shared/dev/spi.

Thanks.

> I have already committed some of the driver movement from Zynq or ARM to 
> bsps/shared/dev. There is still quite a bit more to pull out of the Zynq BSP 
> that I haven't quite gotten to.

Awesome and thanks. It is great to see this happening.

Chris
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RE: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

2021-02-12 Thread Kinsey Moore 
On 12/2/21 5:14 am, Chris Johns wrote:
>On 13/2/21 10:10 am, Joel Sherrill wrote:
>> On Fri, Feb 12, 2021 at 5:06 PM Chris Johns > > wrote:
>> 
>> On 13/2/21 12:25 am, Jan Sommer wrote:
>> > This patchset implements a driver for the cadence-spi
>> > device of the Xilinx Zynq-7000 based SoCs  using the spidev API.s
>> 
>> Thanks for the driver.
>> 
>> A quick review of the differences between the Zynq and Ulttrascale in 
>> this
>> document from Xilinx:
>> 
>> 
>> https://www.xilinx.com/support/documentation/user_guides/ug1213-zynq-migration-guide.pdf
>> 
>> 
>> 
>> shows the SPI hardware is the same. Should this driver be located under
>> `bsps/shared/dev/spi` and then shared?
>> 
>> If Kinsey or Jan confirms, then yes it should.
>
> Thanks.
>
>> Kinsey has had a number 
>> of drivers work after addressing 64-bit clean issues.
>
> Nice. Are these in the tree?

Looking at the register setup for the two SPI instances in MPSoC, I have 
verified that these peripherals are identical. It should definitely go in 
bsps/shared/dev/spi.

I have already committed some of the driver movement from Zynq or ARM to 
bsps/shared/dev. There is still quite a bit more to pull out of the Zynq BSP 
that I haven't quite gotten to.

Kinsey
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Re: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

2021-02-12 Thread Chris Johns 
On 13/2/21 10:10 am, Joel Sherrill wrote:
> On Fri, Feb 12, 2021 at 5:06 PM Chris Johns  > wrote:
> 
> On 13/2/21 12:25 am, Jan Sommer wrote:
> > This patchset implements a driver for the cadence-spi
> > device of the Xilinx Zynq-7000 based SoCs  using the spidev API.s
> 
> Thanks for the driver.
> 
> A quick review of the differences between the Zynq and Ulttrascale in this
> document from Xilinx:
> 
> 
> https://www.xilinx.com/support/documentation/user_guides/ug1213-zynq-migration-guide.pdf
> 
> 
> 
> shows the SPI hardware is the same. Should this driver be located under
> `bsps/shared/dev/spi` and then shared?
> 
> If Kinsey or Jan confirms, then yes it should.

Thanks.

> Kinsey has had a number 
> of drivers work after addressing 64-bit clean issues.

Nice. Are these in the tree?

Chris
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Re: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

2021-02-12 Thread Joel Sherrill 
On Fri, Feb 12, 2021 at 5:06 PM Chris Johns  wrote:

> On 13/2/21 12:25 am, Jan Sommer wrote:
> > This patchset implements a driver for the cadence-spi
> > device of the Xilinx Zynq-7000 based SoCs  using the spidev API.s
>
> Thanks for the driver.
>
> A quick review of the differences between the Zynq and Ulttrascale in this
> document from Xilinx:
>
>
> https://www.xilinx.com/support/documentation/user_guides/ug1213-zynq-migration-guide.pdf
>
> shows the SPI hardware is the same. Should this driver be located under
> `bsps/shared/dev/spi` and then shared?
>

If Kinsey or Jan confirms, then yes it should. Kinsey has had a number
of drivers work after addressing 64-bit clean issues.

--joel

>
> Chris
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Re: [PATCH 0/3] bsps/zynq: Add cadence-SPI driver

2021-02-12 Thread Chris Johns 
On 13/2/21 12:25 am, Jan Sommer wrote:
> This patchset implements a driver for the cadence-spi
> device of the Xilinx Zynq-7000 based SoCs  using the spidev API.s

Thanks for the driver.

A quick review of the differences between the Zynq and Ulttrascale in this
document from Xilinx:

https://www.xilinx.com/support/documentation/user_guides/ug1213-zynq-migration-guide.pdf

shows the SPI hardware is the same. Should this driver be located under
`bsps/shared/dev/spi` and then shared?

Chris
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Re: [PATCH] Update motorola_power to irq-generic interrupt management

2021-02-12 Thread Chris Johns 
On 13/2/21 7:35 am, Gedare Bloom wrote:
> On Fri, Feb 12, 2021 at 1:00 PM  wrote:
>>
>> From: Chris Johns 
>>
>> - Add support to the BSP to enable irq-generic management
>>
>> - Update the powerpc shared irq code to support irq-generic. This
>>   is an option in option for existing powerpc bsps. This change
>>   should be simpler now
>>
>> - Fix a number of issues in ISA IRQ controller handling by porting
>>   fixes from the i386 (PC) BSP
>>
>> Closes #4238
>> Closes #4239
>> ---
>>  bsps/powerpc/include/bsp/irq_supp.h   |   5 +
>>  .../motorola_powerpc/include/bsp/irq.h|  15 +-
>>  .../powerpc/motorola_powerpc/start/bspstart.c |   9 +-
>>  bsps/powerpc/shared/irq/i8259.c   | 155 ++
>>  bsps/powerpc/shared/irq/irq_init.c|  15 +-
>>  bsps/powerpc/shared/irq/openpic_i8259_irq.c   |  27 ++-
>>  bsps/powerpc/shared/irq/ppc-irq-generic.c | 118 +
>>  .../bsps/powerpc/motorola_powerpc/grp.yml |   2 +-
>>  .../bsps/powerpc/motorola_powerpc/obj.yml |   3 +-
>>  9 files changed, 291 insertions(+), 58 deletions(-)
>>  create mode 100644 bsps/powerpc/shared/irq/ppc-irq-generic.c
>>
>> diff --git a/bsps/powerpc/include/bsp/irq_supp.h 
>> b/bsps/powerpc/include/bsp/irq_supp.h
>> index 65af48c87f..fbb16d6211 100644
>> --- a/bsps/powerpc/include/bsp/irq_supp.h
>> +++ b/bsps/powerpc/include/bsp/irq_supp.h
>> @@ -50,6 +50,11 @@ extern int  BSP_disable_irq_at_pic(const rtems_irq_number 
>> irqLine);
>>   */
>>  extern int  BSP_setup_the_pic(rtems_irq_global_settings* config);
>>
>> +/*
>> + * Set up for the irq-generic.h interface.
>> + */
>> +int BSP_rtems_irq_generic_set(rtems_irq_global_settings* config);
>> +
>>  /* IRQ dispatcher to be defined by the PIC driver; note that it MUST
>>   * implement shared interrupts.
>>   * Note also that the exception frame passed to this handler is not very
>> diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h 
>> b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
>> index 3690dbbff7..cbb6ff69cf 100644
>> --- a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
>> +++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
>> @@ -19,9 +19,17 @@
>>  #ifndef BSP_POWERPC_IRQ_H
>>  #define BSP_POWERPC_IRQ_H
>>
>> +#ifndef BSP_SHARED_HANDLER_SUPPORT
>>  #define BSP_SHARED_HANDLER_SUPPORT  1
>> +#endif
>> +
>>  #include 
>> -#include 
>> +
>> +/*
>> + * Switch to using the generic support. Remove this when all BSPs have
>> + * been converted.
>> + */
>> +#define BSP_POWERPC_IRQ_GENERIC_SUPPORT 1
>>
>>  /*
>>   * 8259 edge/level control definitions at VIA
>> @@ -107,6 +115,8 @@ extern "C" {
>>  #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
>>  #define BSP_LOWEST_OFFSET  (BSP_ISA_IRQ_LOWEST_OFFSET)
>>  #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
>> +#define BSP_INTERRUPT_VECTOR_MIN   (BSP_LOWEST_OFFSET)
>> +#define BSP_INTERRUPT_VECTOR_MAX   (BSP_MAX_OFFSET)
>>  /*
>>   * Some ISA IRQ symbolic name definition
>>   */
>> @@ -191,6 +201,9 @@ int BSP_irq_ack_at_i8259s   (const 
>> rtems_irq_number irqLine);
>>   */
>>  int BSP_irq_enabled_at_i8259s  (const rtems_irq_number irqLine);
>>
>> +unsigned short BSP_irq_suspend_i8259s(unsigned short mask);
>> +void BSP_irq_resume_i8259s(unsigned short in_progress_save);
>> +
>>  extern void BSP_rtems_irq_mng_init(unsigned cpuId);
>>  extern void BSP_i8259s_init(void);
>>
>> diff --git a/bsps/powerpc/motorola_powerpc/start/bspstart.c 
>> b/bsps/powerpc/motorola_powerpc/start/bspstart.c
>> index e74b02c446..ab48858c46 100644
>> --- a/bsps/powerpc/motorola_powerpc/start/bspstart.c
>> +++ b/bsps/powerpc/motorola_powerpc/start/bspstart.c
>> @@ -27,6 +27,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -334,10 +335,8 @@ static void bsp_early( void )
>> */
>>bsp_clicks_per_usec   = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
>>
>> -  /*
>> -   * Initalize RTEMS IRQ system
>> -   */
>> -  BSP_rtems_irq_mng_init(0);
>> +  /* Initalize interrupt support */
> s/Initalize/Initialize
> 
>> +  bsp_interrupt_initialize();
>>
>>/* Activate the page table mappings only after
>> * initializing interrupts because the irq_mng_init()
>> @@ -360,7 +359,6 @@ static void bsp_early( void )
>>printk("Exit from bspstart\n");
>>  #endif
>>  }
>> -
> This blank line should not be removed

OK

> 
>>  RTEMS_SYSINIT_ITEM(
>>bsp_early,
>>RTEMS_SYSINIT_BSP_EARLY,
>> @@ -370,6 +368,7 @@ RTEMS_SYSINIT_ITEM(
>>  void bsp_start( void )
>>  {
>>/* Initialization was done by bsp_early() */
>> +
> Not needed blank line
>>  }
>>
>>  RTEMS_SYSINIT_ITEM(
>> diff --git a/bsps/powerpc/shared/irq/i8259.c 
>> b/bsps/powerpc/shared/irq/i8259.c
>> index 7363e87ba0..6a0b855981 100644
>> --- a/bsps/powerpc/shared/irq/i8259.c
>> +++ b/bsps/powerpc/shared/irq/i8259.c
>> @@ -12,6 +12,19 @@
>>  #include 
>>  #include 
>>
>> +#define PIC_EOSI

Re: [PATCH] Update motorola_power to irq-generic interrupt management

2021-02-12 Thread Gedare Bloom 
On Fri, Feb 12, 2021 at 1:00 PM  wrote:
>
> From: Chris Johns 
>
> - Add support to the BSP to enable irq-generic management
>
> - Update the powerpc shared irq code to support irq-generic. This
>   is an option in option for existing powerpc bsps. This change
>   should be simpler now
>
> - Fix a number of issues in ISA IRQ controller handling by porting
>   fixes from the i386 (PC) BSP
>
> Closes #4238
> Closes #4239
> ---
>  bsps/powerpc/include/bsp/irq_supp.h   |   5 +
>  .../motorola_powerpc/include/bsp/irq.h|  15 +-
>  .../powerpc/motorola_powerpc/start/bspstart.c |   9 +-
>  bsps/powerpc/shared/irq/i8259.c   | 155 ++
>  bsps/powerpc/shared/irq/irq_init.c|  15 +-
>  bsps/powerpc/shared/irq/openpic_i8259_irq.c   |  27 ++-
>  bsps/powerpc/shared/irq/ppc-irq-generic.c | 118 +
>  .../bsps/powerpc/motorola_powerpc/grp.yml |   2 +-
>  .../bsps/powerpc/motorola_powerpc/obj.yml |   3 +-
>  9 files changed, 291 insertions(+), 58 deletions(-)
>  create mode 100644 bsps/powerpc/shared/irq/ppc-irq-generic.c
>
> diff --git a/bsps/powerpc/include/bsp/irq_supp.h 
> b/bsps/powerpc/include/bsp/irq_supp.h
> index 65af48c87f..fbb16d6211 100644
> --- a/bsps/powerpc/include/bsp/irq_supp.h
> +++ b/bsps/powerpc/include/bsp/irq_supp.h
> @@ -50,6 +50,11 @@ extern int  BSP_disable_irq_at_pic(const rtems_irq_number 
> irqLine);
>   */
>  extern int  BSP_setup_the_pic(rtems_irq_global_settings* config);
>
> +/*
> + * Set up for the irq-generic.h interface.
> + */
> +int BSP_rtems_irq_generic_set(rtems_irq_global_settings* config);
> +
>  /* IRQ dispatcher to be defined by the PIC driver; note that it MUST
>   * implement shared interrupts.
>   * Note also that the exception frame passed to this handler is not very
> diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h 
> b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> index 3690dbbff7..cbb6ff69cf 100644
> --- a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> +++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> @@ -19,9 +19,17 @@
>  #ifndef BSP_POWERPC_IRQ_H
>  #define BSP_POWERPC_IRQ_H
>
> +#ifndef BSP_SHARED_HANDLER_SUPPORT
>  #define BSP_SHARED_HANDLER_SUPPORT  1
> +#endif
> +
>  #include 
> -#include 
> +
> +/*
> + * Switch to using the generic support. Remove this when all BSPs have
> + * been converted.
> + */
> +#define BSP_POWERPC_IRQ_GENERIC_SUPPORT 1
>
>  /*
>   * 8259 edge/level control definitions at VIA
> @@ -107,6 +115,8 @@ extern "C" {
>  #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
>  #define BSP_LOWEST_OFFSET  (BSP_ISA_IRQ_LOWEST_OFFSET)
>  #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
> +#define BSP_INTERRUPT_VECTOR_MIN   (BSP_LOWEST_OFFSET)
> +#define BSP_INTERRUPT_VECTOR_MAX   (BSP_MAX_OFFSET)
>  /*
>   * Some ISA IRQ symbolic name definition
>   */
> @@ -191,6 +201,9 @@ int BSP_irq_ack_at_i8259s   (const 
> rtems_irq_number irqLine);
>   */
>  int BSP_irq_enabled_at_i8259s  (const rtems_irq_number irqLine);
>
> +unsigned short BSP_irq_suspend_i8259s(unsigned short mask);
> +void BSP_irq_resume_i8259s(unsigned short in_progress_save);
> +
>  extern void BSP_rtems_irq_mng_init(unsigned cpuId);
>  extern void BSP_i8259s_init(void);
>
> diff --git a/bsps/powerpc/motorola_powerpc/start/bspstart.c 
> b/bsps/powerpc/motorola_powerpc/start/bspstart.c
> index e74b02c446..ab48858c46 100644
> --- a/bsps/powerpc/motorola_powerpc/start/bspstart.c
> +++ b/bsps/powerpc/motorola_powerpc/start/bspstart.c
> @@ -27,6 +27,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -334,10 +335,8 @@ static void bsp_early( void )
> */
>bsp_clicks_per_usec   = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
>
> -  /*
> -   * Initalize RTEMS IRQ system
> -   */
> -  BSP_rtems_irq_mng_init(0);
> +  /* Initalize interrupt support */
s/Initalize/Initialize

> +  bsp_interrupt_initialize();
>
>/* Activate the page table mappings only after
> * initializing interrupts because the irq_mng_init()
> @@ -360,7 +359,6 @@ static void bsp_early( void )
>printk("Exit from bspstart\n");
>  #endif
>  }
> -
This blank line should not be removed

>  RTEMS_SYSINIT_ITEM(
>bsp_early,
>RTEMS_SYSINIT_BSP_EARLY,
> @@ -370,6 +368,7 @@ RTEMS_SYSINIT_ITEM(
>  void bsp_start( void )
>  {
>/* Initialization was done by bsp_early() */
> +
Not needed blank line
>  }
>
>  RTEMS_SYSINIT_ITEM(
> diff --git a/bsps/powerpc/shared/irq/i8259.c b/bsps/powerpc/shared/irq/i8259.c
> index 7363e87ba0..6a0b855981 100644
> --- a/bsps/powerpc/shared/irq/i8259.c
> +++ b/bsps/powerpc/shared/irq/i8259.c
> @@ -12,6 +12,19 @@
>  #include 
>  #include 
>
> +#define PIC_EOSI0x60///< End of Specific Interrupt (EOSI)
> +#define PIC_EOI 0x20///< Generic End of Interrupt (EOI)
Is there a reason these two have a different comment format as the following?

PowerPC Exception warnings

2021-02-12 Thread Chris Johns 
Hello,

The mvme2703 BSP is producing warnings for these lines of code:

https://git.rtems.org/rtems/tree/bsps/powerpc/shared/exceptions/ppc_exc.S#n132
https://git.rtems.org/rtems/tree/bsps/powerpc/shared/exceptions/ppc_exc.S#n135

The warnings is:

../../../bsps/powerpc/shared/exceptions/ppc_exc.S:132: Warning: invalid register
expression
../../../bsps/powerpc/shared/exceptions/ppc_exc.S:135: Warning: invalid register
expression

The code is:

/* ppc405 has a critical exception using srr2/srr3 */
WRAP_FLVR=p405_crit _PRI=crit _SRR0=srr2 _SRR1=srr3 _RFI=rfci

/* bookE has critical exception using csrr0 cssr1 */
WRAP_FLVR=bookE_crit _PRI=crit _SRR0=csrr0 _SRR1=csrr1 _RFI=rfci

I do not have enough PowerPC foo to fix this.

Chris
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[PATCH] Update motorola_power to irq-generic interrupt management

2021-02-12 Thread chrisj 
From: Chris Johns 

- Add support to the BSP to enable irq-generic management

- Update the powerpc shared irq code to support irq-generic. This
  is an option in option for existing powerpc bsps. This change
  should be simpler now

- Fix a number of issues in ISA IRQ controller handling by porting
  fixes from the i386 (PC) BSP

Closes #4238
Closes #4239
---
 bsps/powerpc/include/bsp/irq_supp.h   |   5 +
 .../motorola_powerpc/include/bsp/irq.h|  15 +-
 .../powerpc/motorola_powerpc/start/bspstart.c |   9 +-
 bsps/powerpc/shared/irq/i8259.c   | 155 ++
 bsps/powerpc/shared/irq/irq_init.c|  15 +-
 bsps/powerpc/shared/irq/openpic_i8259_irq.c   |  27 ++-
 bsps/powerpc/shared/irq/ppc-irq-generic.c | 118 +
 .../bsps/powerpc/motorola_powerpc/grp.yml |   2 +-
 .../bsps/powerpc/motorola_powerpc/obj.yml |   3 +-
 9 files changed, 291 insertions(+), 58 deletions(-)
 create mode 100644 bsps/powerpc/shared/irq/ppc-irq-generic.c

diff --git a/bsps/powerpc/include/bsp/irq_supp.h 
b/bsps/powerpc/include/bsp/irq_supp.h
index 65af48c87f..fbb16d6211 100644
--- a/bsps/powerpc/include/bsp/irq_supp.h
+++ b/bsps/powerpc/include/bsp/irq_supp.h
@@ -50,6 +50,11 @@ extern int  BSP_disable_irq_at_pic(const rtems_irq_number 
irqLine);
  */
 extern int  BSP_setup_the_pic(rtems_irq_global_settings* config);
 
+/*
+ * Set up for the irq-generic.h interface.
+ */
+int BSP_rtems_irq_generic_set(rtems_irq_global_settings* config);
+
 /* IRQ dispatcher to be defined by the PIC driver; note that it MUST
  * implement shared interrupts.
  * Note also that the exception frame passed to this handler is not very
diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h 
b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
index 3690dbbff7..cbb6ff69cf 100644
--- a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
+++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
@@ -19,9 +19,17 @@
 #ifndef BSP_POWERPC_IRQ_H
 #define BSP_POWERPC_IRQ_H
 
+#ifndef BSP_SHARED_HANDLER_SUPPORT
 #define BSP_SHARED_HANDLER_SUPPORT  1
+#endif
+
 #include 
-#include 
+
+/*
+ * Switch to using the generic support. Remove this when all BSPs have
+ * been converted.
+ */
+#define BSP_POWERPC_IRQ_GENERIC_SUPPORT 1
 
 /*
  * 8259 edge/level control definitions at VIA
@@ -107,6 +115,8 @@ extern "C" {
 #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
 #define BSP_LOWEST_OFFSET  (BSP_ISA_IRQ_LOWEST_OFFSET)
 #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
+#define BSP_INTERRUPT_VECTOR_MIN   (BSP_LOWEST_OFFSET)
+#define BSP_INTERRUPT_VECTOR_MAX   (BSP_MAX_OFFSET)
 /*
  * Some ISA IRQ symbolic name definition
  */
@@ -191,6 +201,9 @@ int BSP_irq_ack_at_i8259s   (const 
rtems_irq_number irqLine);
  */
 int BSP_irq_enabled_at_i8259s  (const rtems_irq_number irqLine);
 
+unsigned short BSP_irq_suspend_i8259s(unsigned short mask);
+void BSP_irq_resume_i8259s(unsigned short in_progress_save);
+
 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
 extern void BSP_i8259s_init(void);
 
diff --git a/bsps/powerpc/motorola_powerpc/start/bspstart.c 
b/bsps/powerpc/motorola_powerpc/start/bspstart.c
index e74b02c446..ab48858c46 100644
--- a/bsps/powerpc/motorola_powerpc/start/bspstart.c
+++ b/bsps/powerpc/motorola_powerpc/start/bspstart.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -334,10 +335,8 @@ static void bsp_early( void )
*/
   bsp_clicks_per_usec   = BSP_bus_frequency/(BSP_time_base_divisor * 1000);
 
-  /*
-   * Initalize RTEMS IRQ system
-   */
-  BSP_rtems_irq_mng_init(0);
+  /* Initalize interrupt support */
+  bsp_interrupt_initialize();
 
   /* Activate the page table mappings only after
* initializing interrupts because the irq_mng_init()
@@ -360,7 +359,6 @@ static void bsp_early( void )
   printk("Exit from bspstart\n");
 #endif
 }
-
 RTEMS_SYSINIT_ITEM(
   bsp_early,
   RTEMS_SYSINIT_BSP_EARLY,
@@ -370,6 +368,7 @@ RTEMS_SYSINIT_ITEM(
 void bsp_start( void )
 {
   /* Initialization was done by bsp_early() */
+
 }
 
 RTEMS_SYSINIT_ITEM(
diff --git a/bsps/powerpc/shared/irq/i8259.c b/bsps/powerpc/shared/irq/i8259.c
index 7363e87ba0..6a0b855981 100644
--- a/bsps/powerpc/shared/irq/i8259.c
+++ b/bsps/powerpc/shared/irq/i8259.c
@@ -12,6 +12,19 @@
 #include 
 #include 
 
+#define PIC_EOSI0x60///< End of Specific Interrupt (EOSI)
+#define PIC_EOI 0x20///< Generic End of Interrupt (EOI)
+
+/* Operation control word type 3.  Bit 3 (0x08) must be set. Even address. */
+#define PIC_OCW3_RIS0x01/* 1 = read IS, 0 = read IR */
+#define PIC_OCW3_RR 0x02/* register read */
+#define PIC_OCW3_P  0x04/* poll mode command */
+/* 0x08 must be 1 to select OCW3 vs OCW2 */
+#define PIC_OCW3_SEL0x08/* must be 1 */
+/* 0x10 must be 0 to select OCW3 vs ICW1 */
+#define

Re: [PATCH v2 1/3] assert.h: Add macros to assert status and use it

2021-02-12 Thread Gedare Bloom 
Hi Ryan,

On Fri, Feb 12, 2021 at 8:11 AM Ryan Long  wrote:
>
> These macros are to be used to check the status from calls that are flagged by
> Coverity as 'Unchecked return value'.
>
> Fix file assert.h

Thanks for these updates, it's almost there.  Can you open a ticket
related to this feature improvement, and close that ticket from the
commit message?

> ---
>  cpukit/include/rtems/score/assert.h | 30 ++
>  1 file changed, 30 insertions(+)
>
> diff --git a/cpukit/include/rtems/score/assert.h 
> b/cpukit/include/rtems/score/assert.h
> index cc32448..6bdb01e 100644
> --- a/cpukit/include/rtems/score/assert.h
> +++ b/cpukit/include/rtems/score/assert.h
> @@ -99,6 +99,36 @@ extern "C" {
>  #endif
>
>  /**
> + * @brief Assert if unused return value is equal.
Now that it is more generic, please replaced "return value" with "variable"

> + *
> + * Assert whether @a _var and @a _val are equal and ensure @a _var is
> + * marked as used when not building for debug.
> + *
> + * @param _var The return value to be checked.
ditto

> + * @param _val Indicates what @a _var is supposed to be.
> + */
> +#define _Assert_Unused_variable_equals(_var,_val) \
> +do { \
> +  _Assert((_var) == (_val)); \
> +  (void) (_var); \
> +} while (0)
> +
> +/**
> + * @brief Assert if unused return value is not equal.
ditto

> + *
> + * Assert whether @a _var and @a _val are not equal and ensure @a _var
> + * is marked as used when not building for debug.
> + *
> + * @param _var The return value to be checked.
ditto

> + * @param _val Indicates what @a _var is not supposed to be.
> + */
> +#define _Assert_Unused_variable_unequal(_var,_val) \
> + do { \
> +  _Assert((_var) != (_val)); \
> +   (void) (_var); \
> +} while (0)
> +
> +/**
>   * @brief Returns true if thread dispatching is allowed.
>   *
>   * Thread dispatching can be repressed via _Thread_Disable_dispatch() or
> --
> 1.8.3.1
>
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[PATCH v2 3/3] rtems-debugger-target.c: Fix Coverity Dereference before null check

2021-02-12 Thread Ryan Long 
Fixes CID #1468682 where target is dereferenced before it has been
checked as to whether it is null or not in the
rtems_debugger_target_swbreak_control function.

Fix file rtems-debugger-target.c
---
 cpukit/libdebugger/rtems-debugger-target.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/cpukit/libdebugger/rtems-debugger-target.c 
b/cpukit/libdebugger/rtems-debugger-target.c
index e495170..bf75797 100644
--- a/cpukit/libdebugger/rtems-debugger-target.c
+++ b/cpukit/libdebugger/rtems-debugger-target.c
@@ -171,17 +171,19 @@ int
 rtems_debugger_target_swbreak_control(bool insert, DB_UINT addr, DB_UINT kind)
 {
   rtems_debugger_target* target = rtems_debugger->target;
-  rtems_debugger_target_swbreak* swbreaks = target->swbreaks.block;
+  rtems_debugger_target_swbreak* swbreaks;
   size_t swbreak_size;
   uint8_t*   loc = (void*) addr;
   size_t i;
   intr;
 
-  if (target == NULL || swbreaks == NULL || kind != target->breakpoint_size) {
+  if (target == NULL || target->swbreaks.block == NULL ||
+  kind != target->breakpoint_size) {
 errno = EIO;
 return -1;
   }
 
+  swbreaks = target->swbreaks.block;
   swbreak_size =
 sizeof(rtems_debugger_target_swbreak) + target->breakpoint_size;
 
-- 
1.8.3.1

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[PATCH v2 2/3] consolesimpletask.c: Fix Coverity Unchecked return value

2021-02-12 Thread Ryan Long 
Fixes CID #1437625 and #1472765 where the return value of rtems_task_create and
rtems_task_start is discarded.

Fix file consolesimpletask.c
---
 cpukit/libcsupport/src/consolesimpletask.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/cpukit/libcsupport/src/consolesimpletask.c 
b/cpukit/libcsupport/src/consolesimpletask.c
index 82ea2a5..393de3a 100644
--- a/cpukit/libcsupport/src/consolesimpletask.c
+++ b/cpukit/libcsupport/src/consolesimpletask.c
@@ -217,6 +217,7 @@ static const char _Console_simple_task_Name[] = "console";
 void _Console_simple_task_Initialize( void )
 {
   Console_simple_task_Control *cons;
+  rtems_status_code status;
 
   cons = &_Console_simple_task_Instance;
 
@@ -233,7 +234,7 @@ void _Console_simple_task_Initialize( void )
 
   IMFS_add_node( "/dev", >Node, NULL );
 
-  rtems_task_create(
+  status = rtems_task_create(
 rtems_build_name('C', 'O', 'N', 'S'),
 RTEMS_MAXIMUM_PRIORITY - 1,
 RTEMS_MINIMUM_STACK_SIZE,
@@ -241,10 +242,12 @@ void _Console_simple_task_Initialize( void )
 RTEMS_DEFAULT_MODES,
 >task
   );
+  _Assert_Unused_variable_equals(status, RTEMS_SUCCESSFUL);
 
-  rtems_task_start(
+  status = rtems_task_start(
 cons->task,
 _Console_simple_task_Task,
 (rtems_task_argument) cons
   );
+  _Assert_Unused_variable_equals(status, RTEMS_SUCCESSFUL);
 }
-- 
1.8.3.1

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[PATCH v2 0/3] Fix for Coverity issues

2021-02-12 Thread Ryan Long 
Hi,

Here are the patches with the suggested changes. The macros are now
_Assert_Unused_variable equals and _Assert_Unused_variable_unequal. I
made the corresponding change in consolesimpletask.c. In
rtems-debugger-target.c, I moved the declaration of the swbreaks
variable back to the top of the function and assigned its value where I
had declared and initialized it in the first version of this patch.

Thanks,
Ryan

Ryan Long (3):
  assert.h: Add macros to assert status and use it
  consolesimpletask.c: Fix Coverity Unchecked return value
  rtems-debugger-target.c: Fix Coverity Dereference before null check

 cpukit/include/rtems/score/assert.h| 30 ++
 cpukit/libcsupport/src/consolesimpletask.c |  7 +--
 cpukit/libdebugger/rtems-debugger-target.c |  6 --
 3 files changed, 39 insertions(+), 4 deletions(-)

-- 
1.8.3.1

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[PATCH v2 1/3] assert.h: Add macros to assert status and use it

2021-02-12 Thread Ryan Long 
These macros are to be used to check the status from calls that are flagged by
Coverity as 'Unchecked return value'.

Fix file assert.h
---
 cpukit/include/rtems/score/assert.h | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/cpukit/include/rtems/score/assert.h 
b/cpukit/include/rtems/score/assert.h
index cc32448..6bdb01e 100644
--- a/cpukit/include/rtems/score/assert.h
+++ b/cpukit/include/rtems/score/assert.h
@@ -99,6 +99,36 @@ extern "C" {
 #endif
 
 /**
+ * @brief Assert if unused return value is equal.
+ *
+ * Assert whether @a _var and @a _val are equal and ensure @a _var is
+ * marked as used when not building for debug.
+ *
+ * @param _var The return value to be checked.
+ * @param _val Indicates what @a _var is supposed to be.
+ */
+#define _Assert_Unused_variable_equals(_var,_val) \
+do { \
+  _Assert((_var) == (_val)); \
+  (void) (_var); \
+} while (0)
+
+/**
+ * @brief Assert if unused return value is not equal.
+ *
+ * Assert whether @a _var and @a _val are not equal and ensure @a _var
+ * is marked as used when not building for debug.
+ *
+ * @param _var The return value to be checked.
+ * @param _val Indicates what @a _var is not supposed to be.
+ */
+#define _Assert_Unused_variable_unequal(_var,_val) \
+ do { \
+  _Assert((_var) != (_val)); \
+   (void) (_var); \
+} while (0)
+
+/**
  * @brief Returns true if thread dispatching is allowed.
  *
  * Thread dispatching can be repressed via _Thread_Disable_dispatch() or
-- 
1.8.3.1

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Re: [PATCH 0/4] RISC-V: NOEL-V BSP

2021-02-12 Thread Daniel Hellstrom 

Hi,

Thanks all for your comments. The logs have been attached, I'm a bit 
unsure why the PSXKEY07 was reported as a failure from the log, we 
should probably double check that can get back to you.


/Daniel

  


On 2021-02-09 16:59, Sebastian Huber wrote:

On 08/02/2021 20:44, Daniel Hellstrom wrote:


   # FAIL: ttest01 OK FAIL 0x0005 0x
   # FAIL: ttest02 OK FAIL 0x0005 0x
   # FAIL: psxkey07 OK FAIL 0x0005 0x
These tests should not fail. What are the error messages? It would be 
worth to debug the failures.




*** BEGIN OF TEST TTEST 1 ***
*** TEST VERSION: 6.0.0.b26618919e410d368d59e8fb4f9535cf70107de0
*** TEST STATE: EXPECTED_PASS
*** TEST BUILD: RTEMS_NETWORKING RTEMS_POSIX_API
*** TEST TOOLS: 10.2.1 20210119 (RTEMS 6, RSB 
71178999b6221a97a6d1c4d28f1d437a07d31317, Newlib 62e739b)
A:ttest01
S:Platform:RTEMS
S:Compiler:*
S:Version:*
S:BSP:*
S:RTEMS_DEBUG:*
S:RTEMS_MULTIPROCESSING:*
S:RTEMS_POSIX_API:*
S:RTEMS_PROFILING:*
S:RTEMS_SMP:*
B:zalloc_auto
P:0:0:UI1:test-malloc.c:35
P:1:0:UI1:test-malloc.c:36
P:2:0:UI1:test-malloc.c:26
E:zalloc_auto:N:3:F:0:D:0.001000
B:wrong_step
P:0:0:UI1:test-plan.c:6
F:1:0:UI1:test-plan.c:7:planned step (2)
E:wrong_step:N:2:F:1:D:0.001000
B:verbosity_changes
F:3:0:UI1:test-verbosity.c:12:normal: check fails -> with output
P:4:0:UI1:test-verbosity.c:14
F:5:0:UI1:test-verbosity.c:15:verbose: check fails -> with output
E:verbosity_changes:N:6:F:3:D:0.001000
B:timer
P:0:0:UI1:test-rtems.c:26
P:1:0:UI1:test-rtems.c:29
P:2:0:UI1:test-rtems.c:39
P:3:0:ISR:test-rtems.c:14
P:4:0:ISR:test-rtems.c:15
P:5:0:UI1:test-rtems.c:44
P:6:0:UI1:test-rtems.c:45
P:7:0:UI1:test-rtems.c:48
E:timer:N:8:F:0:D:0.001000
B:time_to_string
P:0:0:UI1:test-time.c:11
P:1:0:UI1:test-time.c:12
P:2:0:UI1:test-time.c:13
P:3:0:UI1:test-time.c:14
P:4:0:UI1:test-time.c:17
P:5:0:UI1:test-time.c:18
E:time_to_string:N:6:F:0:D:0.001000
B:time
P:0:0:UI1:test-time.c:55
P:1:0:UI1:test-time.c:56
P:2:0:UI1:test-time.c:57
P:3:0:UI1:test-time.c:58
P:4:0:UI1:test-time.c:61
P:5:0:UI1:test-time.c:63
P:6:0:UI1:test-time.c:64
P:7:0:UI1:test-time.c:67
P:8:0:UI1:test-time.c:69
P:9:0:UI1:test-time.c:70
P:10:0:UI1:test-time.c:73
P:11:0:UI1:test-time.c:75
P:12:0:UI1:test-time.c:76
P:13:0:UI1:test-time.c:79
P:14:0:UI1:test-time.c:81
P:15:0:UI1:test-time.c:82
P:16:0:UI1:test-time.c:85
P:17:0:UI1:test-time.c:87
P:18:0:UI1:test-time.c:88
P:19:0:UI1:test-time.c:91
P:20:0:UI1:test-time.c:93
P:21:0:UI1:test-time.c:94
P:22:0:UI1:test-time.c:97
P:23:0:UI1:test-time.c:99
P:24:0:UI1:test-time.c:100
P:25:0:UI1:test-time.c:103
P:26:0:UI1:test-time.c:105
P:27:0:UI1:test-time.c:106
P:28:0:UI1:test-time.c:109
P:29:0:UI1:test-time.c:111
P:30:0:UI1:test-time.c:112
P:31:0:UI1:test-time.c:115
P:32:0:UI1:test-time.c:117
P:33:0:UI1:test-time.c:118
P:34:0:UI1:test-time.c:121
P:35:0:UI1:test-time.c:123
P:36:0:UI1:test-time.c:124
P:37:0:UI1:test-time.c:127
P:38:0:UI1:test-time.c:129
P:39:0:UI1:test-time.c:130
E:time:N:40:F:0:D:0.001000
B:ticks
P:0:0:UI1:test-time.c:147
P:1:0:UI1:test-time.c:151
P:2:0:UI1:test-time.c:152
FAILED:80:*ctx->c == c

*** FATAL ***
fatal source: 5 (RTEMS_FATAL_SOURCE_EXIT)
fatal code: 0 (0x)
RTEMS version: 6.0.0.b26618919e410d368d59e8fb4f9535cf70107de0
RTEMS tools: 10.2.1 20210119 (RTEMS 6, RSB 
71178999b6221a97a6d1c4d28f1d437a07d31317, Newlib 62e739b)
executing thread ID: 0x08a010001
executing thread name: UI1 


*** BEGIN OF TEST TTEST 2 ***
*** TEST VERSION: 6.0.0.b26618919e410d368d59e8fb4f9535cf70107de0
*** TEST STATE: EXPECTED_PASS
*** TEST BUILD: RTEMS_NETWORKING RTEMS_POSIX_API
*** TEST TOOLS: 10.2.1 20210119 (RTEMS 6, RSB 
71178999b6221a97a6d1c4d28f1d437a07d31317, Newlib 62e739b)
A:TTEST 2
S:Platform:RTEMS
S:Compiler:10.2.1 20210119 (RTEMS 6, RSB 
71178999b6221a97a6d1c4d28f1d437a07d31317, Newlib 62e739b)
S:Version:6.0.0.b26618919e410d368d59e8fb4f9535cf70107de0
S:BSP:noel64imafd
S:RTEMS_DEBUG:0
S:RTEMS_MULTIPROCESSING:0
S:RTEMS_POSIX_API:1
S:RTEMS_PROFILING:0
S:RTEMS_SMP:0
B:TestThreadSwitch
P:0:0:UI1:init.c:224
P:1:0:UI1:init.c:225
P:2:0:UI1:init.c:226
P:3:0:UI1:init.c:227
P:4:0:UI1:init.c:231
P:5:0:UI1:init.c:232
P:6:0:UI1:init.c:233
P:7:0:UI1:init.c:234
P:8:0:UI1:init.c:238
P:9:0:UI1:init.c:239
P:10:0:UI1:init.c:240
P:11:0:UI1:init.c:241
P:12:0:UI1:init.c:247
P:13:0:UI1:init.c:247
P:14:0:UI1:init.c:247
P:15:0:UI1:init.c:247
P:16:0:UI1:init.c:247
P:17:0:UI1:init.c:247
P:18:0:UI1:init.c:251
P:19:0:UI1:init.c:252
P:20:0:UI1:init.c:253
P:21:0:UI1:init.c:254
P:22:0:UI1:init.c:256
P:23:0:UI1:init.c:257
P:24:0:UI1:init.c:259
P:25:0:UI1:init.c:260
P:26:0:UI1:init.c:269
P:27:0:UI1:init.c:270
P:28:0:UI1:init.c:271
P:29:0:UI1:init.c:272
P:30:0:UI1:init.c:269
P:31:0:UI1:init.c:270
P:32:0:UI1:init.c:271
P:33:0:UI1:init.c:272
P:34:0:UI1:init.c:269
P:35:0:UI1:init.c:270
P:36:0:UI1:init.c:271
P:37:0:UI1:init.c:272
P:38:0:UI1:init.c:269
P:39:0:UI1:init.c:270
P:40:0:UI1:init.c:271
P:41:0:UI1:init.c:272
P:42:0:UI1:init.c:269

[PATCH 1/3] bsps/xilinx_zynq: Add SPI driver for cadence-spi

2021-02-12 Thread Jan Sommer 
---
 .../include/bsp/cadence-spi-regs.h|  84 
 .../arm/xilinx-zynq/include/bsp/cadence-spi.h |  48 ++
 bsps/arm/xilinx-zynq/spi/cadence-spi.c| 437 ++
 3 files changed, 569 insertions(+)
 create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
 create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
 create mode 100644 bsps/arm/xilinx-zynq/spi/cadence-spi.c

diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h 
b/bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
new file mode 100644
index 00..2851c88df1
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 Jan Sommer, Deutsches Zentrum für Luft- und Raumfahrt e. 
V. (DLR)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H
+
+#include 
+
+typedef struct {
+uint32_t config;
+#define CADENCE_SPI_CONFIG_MODEFAIL_EN BSP_BIT32(17)
+#define CADENCE_SPI_CONFIG_MANSTRT BSP_BIT32(16)
+#define CADENCE_SPI_CONFIG_MANSTRT_EN BSP_BIT32(15)
+#define CADENCE_SPI_CONFIG_MANUAL_CS BSP_BIT32(14)
+#define CADENCE_SPI_CONFIG_CS(val) BSP_FLD32(val, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_GET(reg) BSP_FLD32GET(reg, 10, 13)
+#define CADENCE_SPI_CONFIG_CS_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
+#define CADENCE_SPI_CONFIG_PERI_SEL BSP_BIT32(9)
+#define CADENCE_SPI_CONFIG_REF_CLK BSP_BIT32(8)
+#define CADENCE_SPI_CONFIG_BAUD_DIV(val) BSP_FLD32(val, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define CADENCE_SPI_CONFIG_BAUD_DIV_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define CADENCE_SPI_CONFIG_CLK_PH BSP_BIT32(2)
+#define CADENCE_SPI_CONFIG_CLK_POL BSP_BIT32(1)
+#define CADENCE_SPI_CONFIG_MSTREN BSP_BIT32(0)
+   uint32_t irqstatus;
+   uint32_t irqenable;
+   uint32_t irqdisable;
+   uint32_t irqmask;
+#define CADENCE_SPI_IXR_TXUF BSP_BIT32(6)
+#define CADENCE_SPI_IXR_RXFULL BSP_BIT32(5)
+#define CADENCE_SPI_IXR_RXNEMPTY BSP_BIT32(4)
+#define CADENCE_SPI_IXR_TXFULL BSP_BIT32(3)
+#define CADENCE_SPI_IXR_TXOW BSP_BIT32(2)
+#define CADENCE_SPI_IXR_MODF BSP_BIT32(1)
+#define CADENCE_SPI_IXR_RXOVR BSP_BIT32(0)
+uint32_t spienable;
+#define CADENCE_SPI_EN BSP_BIT32(0)
+uint32_t delay;
+#define CADENCE_SPI_DELAY_DNSS(val) BSP_FLD32(val, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_GET(reg) BSP_FLD32GET(reg, 24, 31)
+#define CADENCE_SPI_DELAY_DNSS_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
+#define CADENCE_SPI_DELAY_DBTWN(val) BSP_FLD32(val, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_GET(reg) BSP_FLD32GET(reg, 16, 23)
+#define CADENCE_SPI_DELAY_DBTWN_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
+#define CADENCE_SPI_DELAY_DAFTER(val) BSP_FLD32(val, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define CADENCE_SPI_DELAY_DAFTER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define CADENCE_SPI_DELAY_DINT(val) BSP_FLD32(val, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define CADENCE_SPI_DELAY_DINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+   uint32_t txdata;
+   uint32_t rxdata;
+   uint32_t slave_idle_count;
+   uint32_t txthreshold;
+   uint32_t rxthreshold;
+   uint32_t moduleid;
+} cadence_spi;
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_CADENCE_SPI_REGS_H */
diff --git a/bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h 
b/bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
new file mode 100644
index 00..7d7ecd3885
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
@@ -0,0 +1,48 @@
+/*

[PATCH 3/3] bsps/xilinx_zynq: Add SPI driver to autotools build

2021-02-12 Thread Jan Sommer 
---
 bsps/arm/xilinx-zynq/headers.am  | 2 ++
 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/bsps/arm/xilinx-zynq/headers.am b/bsps/arm/xilinx-zynq/headers.am
index 47738c62be..c70be4 100644
--- a/bsps/arm/xilinx-zynq/headers.am
+++ b/bsps/arm/xilinx-zynq/headers.am
@@ -10,4 +10,6 @@ include_bsp_HEADERS =
 include_bsp_HEADERS += 
../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h
 include_bsp_HEADERS += 
../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/i2c.h
+include_bsp_HEADERS += 
../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
+include_bsp_HEADERS += 
../../../../../../bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
 include_bsp_HEADERS += ../../../../../../bsps/arm/xilinx-zynq/include/bsp/irq.h
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am 
b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
index 8804dc40da..ffde6cd579 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
@@ -71,6 +71,9 @@ librtemsbsp_a_SOURCES += 
../../../../../../bsps/arm/shared/clock/clock-a9mpcore.
 # I2C
 librtemsbsp_a_SOURCES += 
../../../../../../bsps/arm/xilinx-zynq/i2c/cadence-i2c.c
 
+# SPI
+librtemsbsp_a_SOURCES += 
../../../../../../bsps/arm/xilinx-zynq/spi/cadence-spi.c
+
 # Cache
 librtemsbsp_a_SOURCES += 
../../../../../../bsps/arm/shared/cache/cache-l2c-310.c
 
-- 
2.17.1

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[PATCH 2/3] bsps/xilinx_zynq: Add SPI driver to waf

2021-02-12 Thread Jan Sommer 
---
 spec/build/bsps/arm/xilinx-zynq/obj.yml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/spec/build/bsps/arm/xilinx-zynq/obj.yml 
b/spec/build/bsps/arm/xilinx-zynq/obj.yml
index 6602b20a03..c41ba9af98 100644
--- a/spec/build/bsps/arm/xilinx-zynq/obj.yml
+++ b/spec/build/bsps/arm/xilinx-zynq/obj.yml
@@ -17,6 +17,8 @@ install:
   - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h
   - bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h
   - bsps/arm/xilinx-zynq/include/bsp/i2c.h
+  - bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
+  - bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
   - bsps/arm/xilinx-zynq/include/bsp/irq.h
 links: []
 source:
@@ -30,6 +32,7 @@ source:
 - bsps/arm/xilinx-zynq/console/console-init.c
 - bsps/arm/xilinx-zynq/console/debug-console.c
 - bsps/arm/xilinx-zynq/i2c/cadence-i2c.c
+- bsps/arm/xilinx-zynq/spi/cadence-spi.c
 - bsps/arm/xilinx-zynq/start/bspreset.c
 - bsps/arm/xilinx-zynq/start/bspstart.c
 - bsps/arm/xilinx-zynq/start/bspstarthooks.c
-- 
2.17.1

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[PATCH 0/3] bsps/zynq: Add cadence-SPI driver

2021-02-12 Thread Jan Sommer 
This patchset implements a driver for the cadence-spi
device of the Xilinx Zynq-7000 based SoCs  using the spidev API.


Jan Sommer (3):
  bsps/xilinx_zynq: Add SPI driver for cadence-spi
  bsps/xilinx_zynq: Add SPI driver to waf
  bsps/xilinx_zynq: Add SPI driver to autotools build

 bsps/arm/xilinx-zynq/headers.am   |   2 +
 .../include/bsp/cadence-spi-regs.h|  84 
 .../arm/xilinx-zynq/include/bsp/cadence-spi.h |  48 ++
 bsps/arm/xilinx-zynq/spi/cadence-spi.c| 437 ++
 c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am  |   3 +
 spec/build/bsps/arm/xilinx-zynq/obj.yml   |   3 +
 6 files changed, 577 insertions(+)
 create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-spi-regs.h
 create mode 100644 bsps/arm/xilinx-zynq/include/bsp/cadence-spi.h
 create mode 100644 bsps/arm/xilinx-zynq/spi/cadence-spi.c

-- 
2.17.1

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Re: sifive risc-v hifive unleashed bsp (qemu)

2021-02-12 Thread Hesham Almatary 
On Fri, 12 Feb 2021 at 11:24, Sanskar Khandelwal  wrote:
>
> Hello joel,
>
> 1. #4162 : sifive risc-v hifive unleashed bsp (qemu)
> As you mentioned this a good project i thought to search more about this 
> project I learned a lot while doing so but I still don't understand what is 
> the goal of this project (the description on the ticket is not very detailed 
> ) also I don't have any idea on how to make approach for this project right 
> now so if you can clear both my doubt it will be big help.
>
You'd need to identify the devices for this platform that QEMU
supports (e.g., networking, UART, flash, etc?) and propose some
timeline to implement (a subset of) them. That would be part of your
proposal evaluation.

> Also as you mention that this can be a big task for a gsoc time frame I am 
> thinking that I can do some of it after gsoc too.
>
> Also I looked for some more open projects and found these interesting so I 
> wanted to know if these are open for participation for gsoc and what's their 
> status and what further enhancement you are looking at each of them.
>
> 2. #3337 : RISC-V Port in Supervisor Mode
> 3. #4182 : Port Rust to RTEMS
>
> Another thing is that while I am learning more about these projects I want to 
> contribute, so if you can tell me about any issue that I can work on, it will 
> be nice. I think this will help get me more familiar with rtems too.
>
> Thanks
> Sanskar
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sifive risc-v hifive unleashed bsp (qemu)

2021-02-12 Thread Sanskar Khandelwal 
Hello joel,

1. #4162 : sifive risc-v hifive unleashed bsp (qemu)

As you mentioned this a good project i thought to search more about this
project I learned a lot while doing so but I still don't understand what is
the goal of this project (the description on the ticket is not very
detailed ) also I don't have any idea on how to make approach for this
project right now so if you can clear both my doubt it will be big help.

Also as you mention that this can be a big task for a gsoc time frame I am
thinking that I can do some of it after gsoc too.

Also I looked for some more open projects and found these interesting so I
wanted to know if these are open for participation for gsoc and
what's their status and what further enhancement you are looking at each of
them.

2. #3337 : RISC-V Port in Supervisor Mode

3. #4182 : Port Rust to RTEMS 

Another thing is that while I am learning more about these projects I want
to contribute, so if you can tell me about any issue that I can work on, it
will be nice. I think this will help get me more familiar with rtems too.

Thanks
Sanskar
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Re: [PATCH 3/4 v2] bsp/riscv: work area size based on stack pointer

2021-02-12 Thread Hesham Almatary 
On Fri, 12 Feb 2021 at 10:50, Daniel Hellstrom  wrote:
>
> From: Martin Aberg 
>
> Remember the initial stack pointer in start.S. It can later be used to
> determine top of RAM.
> ---
>  bsps/riscv/include/bsp/start.h | 65 
> ++
>  bsps/riscv/shared/start/bspgetworkarea-fromstack.c | 53 ++
>  bsps/riscv/shared/start/start.S| 25 +
>  3 files changed, 143 insertions(+)
>  create mode 100644 bsps/riscv/include/bsp/start.h
>  create mode 100644 bsps/riscv/shared/start/bspgetworkarea-fromstack.c
>
> diff --git a/bsps/riscv/include/bsp/start.h b/bsps/riscv/include/bsp/start.h
> new file mode 100644
> index 000..6c9d57d
> --- /dev/null
> +++ b/bsps/riscv/include/bsp/start.h
> @@ -0,0 +1,65 @@
> +/**
> + * @file
> + *
> + * @ingroup RTEMSBSPsRISCVSharedStart
> + *
> + * @brief RISC-V start definitions.
> + */
> +
> +/*
> + * Copyright (c) 2021 Cobham Gaisler AB.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + *notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + *notice, this list of conditions and the following disclaimer in the
> + *documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + */
> +
> +#ifndef LIBBSP_RISCV_SHARED_START_H
> +#define LIBBSP_RISCV_SHARED_START_H
> +
> +/**
> + * @defgroup RTEMSBSPsRISCVSharedStart Start Support
> + *
> + * @ingroup RTEMSBSPsRISCVShared
> + *
> + * @brief Start support.
> + *
> + * @{
> + */
> +
> +#include 
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> + * This variable is initialized by the first CPU entering the BSP start code.
> + * The value is the stack pointer at entry.
> + */
> +extern uintptr_t riscv_start_stack_pointer;
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +/** @} */
> +
> +#endif /* LIBBSP_RISCV_SHARED_START_H */
> diff --git a/bsps/riscv/shared/start/bspgetworkarea-fromstack.c 
> b/bsps/riscv/shared/start/bspgetworkarea-fromstack.c
> new file mode 100644
> index 000..6885a77
> --- /dev/null
> +++ b/bsps/riscv/shared/start/bspgetworkarea-fromstack.c
> @@ -0,0 +1,53 @@
> +/*
> + *  This set of routines are the BSP specific initialization
> + *  support routines.
> + *
> + *  COPYRIGHT (c) 1989-2020.
> + *  On-Line Applications Research Corporation (OAR),
> + *  Cobham Gaisler AB.
> + *
> + *  The license and distribution terms for this file may be
> + *  found in the file LICENSE in this distribution or at
> + *  http://www.rtems.org/license/LICENSE.
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +/*
> + *  These are provided by the linkcmds for ALL of the BSPs which use this 
> file.
> + */
> +extern char WorkAreaBase[];
> +extern char RamEnd[];
> +
> +static Memory_Area _Memory_Areas[ 1 ];
> +
> +static void bsp_memory_initialize( void )
> +{
> +  char *end;
> +
> +  /* top of RAM inidicated by initial stack pointer */
> +  end = (char *) riscv_start_stack_pointer;
> +  if (end == 0) {
> +/* fall back to linker symbol if not set */
> +end = RamEnd;
> +  }
> +  _Memory_Initialize( &_Memory_Areas[ 0 ], WorkAreaBase, end );
> +}
> +
> +RTEMS_SYSINIT_ITEM(
> +  bsp_memory_initialize,
> +  RTEMS_SYSINIT_MEMORY,
> +  RTEMS_SYSINIT_ORDER_MIDDLE
> +);
> +
> +static const Memory_Information _Memory_Information =
> +  MEMORY_INFORMATION_INITIALIZER( _Memory_Areas );
> +
> +const Memory_Information *_Memory_Get( void )
> +{
> +  return &_Memory_Information;
> +}
> diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S
> index 04a62a2..6f40279 100644
> --- a/bsps/riscv/shared/start/start.S
> +++ b/bsps/riscv/shared/start/start.S
> @@ -35,6 +35,16 @@
>  #include 
>  #include 
>
> +#if __riscv_xlen == 32
> +#define PTR_ALIGN 2
> +#define PTR_SIZE 4
> +#define PTR_VALUE .word
> +#elif __riscv_xlen == 64
> +#define PTR_ALIGN 3
> +#define PTR_SIZE 8
> +#define PTR_VALUE .dword
> +#endif
> +
Since

[PATCH 4/4 v2] bsp/riscv: Add NOEL-V BSP build specification

2021-02-12 Thread Daniel Hellstrom 
From: Martin Aberg 

---
 spec/build/bsps/riscv/noel/abi.yml | 48 +++
 spec/build/bsps/riscv/noel/bspnoel32im.yml | 19 +
 spec/build/bsps/riscv/noel/bspnoel32imafd.yml  | 19 +
 spec/build/bsps/riscv/noel/bspnoel64imac.yml   | 19 +
 spec/build/bsps/riscv/noel/bspnoel64imafd.yml  | 19 +
 spec/build/bsps/riscv/noel/bspnoel64imafdc.yml | 19 +
 spec/build/bsps/riscv/noel/grp.yml | 54 ++
 spec/build/bsps/riscv/noel/obj.yml | 37 ++
 spec/build/bsps/riscv/noel/optconirq.yml   | 16 
 spec/build/bsps/riscv/optrambegin.yml  |  3 ++
 spec/build/cpukit/optarchbits.yml  |  2 +
 spec/build/cpukit/optnet.yml   |  1 +
 spec/build/cpukit/optsmp.yml   |  4 ++
 13 files changed, 260 insertions(+)
 create mode 100644 spec/build/bsps/riscv/noel/abi.yml
 create mode 100644 spec/build/bsps/riscv/noel/bspnoel32im.yml
 create mode 100644 spec/build/bsps/riscv/noel/bspnoel32imafd.yml
 create mode 100644 spec/build/bsps/riscv/noel/bspnoel64imac.yml
 create mode 100644 spec/build/bsps/riscv/noel/bspnoel64imafd.yml
 create mode 100644 spec/build/bsps/riscv/noel/bspnoel64imafdc.yml
 create mode 100644 spec/build/bsps/riscv/noel/grp.yml
 create mode 100644 spec/build/bsps/riscv/noel/obj.yml
 create mode 100644 spec/build/bsps/riscv/noel/optconirq.yml

diff --git a/spec/build/bsps/riscv/noel/abi.yml 
b/spec/build/bsps/riscv/noel/abi.yml
new file mode 100644
index 000..f81e0c1
--- /dev/null
+++ b/spec/build/bsps/riscv/noel/abi.yml
@@ -0,0 +1,48 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- split: null
+- env-append: null
+build-type: option
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+default:
+- -march=rv32ima
+- -mabi=ilp32
+default-by-variant:
+- value:
+  - -march=rv64imafdc
+  - -mabi=lp64d
+  variants:
+  - riscv/noel64imafdc
+- value:
+  - -march=rv64imafd
+  - -mabi=lp64d
+  variants:
+  - riscv/noel64imafd
+- value:
+  - -march=rv64imac
+  - -mabi=lp64
+  variants:
+  - riscv/noel64imac
+- value:
+  - -march=rv64im
+  - -mabi=lp64
+  variants:
+  - riscv/noel64im
+- value:
+  - -march=rv32imafd
+  - -mabi=ilp32d
+  variants:
+  - riscv/noel32imafd
+- value:
+  - -march=rv32im
+  - -mabi=ilp32
+  variants:
+  - riscv/noel32im
+description: |
+  ABI flags
+enabled-by: true
+links: []
+name: ABI_FLAGS
+type: build
diff --git a/spec/build/bsps/riscv/noel/bspnoel32im.yml 
b/spec/build/bsps/riscv/noel/bspnoel32im.yml
new file mode 100644
index 000..bcb27a5
--- /dev/null
+++ b/spec/build/bsps/riscv/noel/bspnoel32im.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: noel32im
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/riscv/noel/bspnoel32imafd.yml 
b/spec/build/bsps/riscv/noel/bspnoel32imafd.yml
new file mode 100644
index 000..e105620
--- /dev/null
+++ b/spec/build/bsps/riscv/noel/bspnoel32imafd.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: noel32imafd
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/riscv/noel/bspnoel64imac.yml 
b/spec/build/bsps/riscv/noel/bspnoel64imac.yml
new file mode 100644
index 000..e32bdb3
--- /dev/null
+++ b/spec/build/bsps/riscv/noel/bspnoel64imac.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: noel64imac
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/riscv/noel/bspnoel64imafd.yml 
b/spec/build/bsps/riscv/noel/bspnoel64imafd.yml
new file mode 100644
index 000..ca9f54d
--- /dev/null
+++ b/spec/build/bsps/riscv/noel/bspnoel64imafd.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: noel64imafd
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp

[PATCH 3/4 v2] bsp/riscv: work area size based on stack pointer

2021-02-12 Thread Daniel Hellstrom 
From: Martin Aberg 

Remember the initial stack pointer in start.S. It can later be used to
determine top of RAM.
---
 bsps/riscv/include/bsp/start.h | 65 ++
 bsps/riscv/shared/start/bspgetworkarea-fromstack.c | 53 ++
 bsps/riscv/shared/start/start.S| 25 +
 3 files changed, 143 insertions(+)
 create mode 100644 bsps/riscv/include/bsp/start.h
 create mode 100644 bsps/riscv/shared/start/bspgetworkarea-fromstack.c

diff --git a/bsps/riscv/include/bsp/start.h b/bsps/riscv/include/bsp/start.h
new file mode 100644
index 000..6c9d57d
--- /dev/null
+++ b/bsps/riscv/include/bsp/start.h
@@ -0,0 +1,65 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsRISCVSharedStart
+ *
+ * @brief RISC-V start definitions.
+ */
+
+/*
+ * Copyright (c) 2021 Cobham Gaisler AB.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_RISCV_SHARED_START_H
+#define LIBBSP_RISCV_SHARED_START_H
+
+/**
+ * @defgroup RTEMSBSPsRISCVSharedStart Start Support
+ *
+ * @ingroup RTEMSBSPsRISCVShared
+ *
+ * @brief Start support.
+ *
+ * @{
+ */
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This variable is initialized by the first CPU entering the BSP start code.
+ * The value is the stack pointer at entry.
+ */
+extern uintptr_t riscv_start_stack_pointer;
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* LIBBSP_RISCV_SHARED_START_H */
diff --git a/bsps/riscv/shared/start/bspgetworkarea-fromstack.c 
b/bsps/riscv/shared/start/bspgetworkarea-fromstack.c
new file mode 100644
index 000..6885a77
--- /dev/null
+++ b/bsps/riscv/shared/start/bspgetworkarea-fromstack.c
@@ -0,0 +1,53 @@
+/*
+ *  This set of routines are the BSP specific initialization
+ *  support routines.
+ *
+ *  COPYRIGHT (c) 1989-2020.
+ *  On-Line Applications Research Corporation (OAR),
+ *  Cobham Gaisler AB.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+/*
+ *  These are provided by the linkcmds for ALL of the BSPs which use this file.
+ */
+extern char WorkAreaBase[];
+extern char RamEnd[];
+
+static Memory_Area _Memory_Areas[ 1 ];
+
+static void bsp_memory_initialize( void )
+{
+  char *end;
+
+  /* top of RAM inidicated by initial stack pointer */
+  end = (char *) riscv_start_stack_pointer;
+  if (end == 0) {
+/* fall back to linker symbol if not set */
+end = RamEnd;
+  }
+  _Memory_Initialize( &_Memory_Areas[ 0 ], WorkAreaBase, end );
+}
+
+RTEMS_SYSINIT_ITEM(
+  bsp_memory_initialize,
+  RTEMS_SYSINIT_MEMORY,
+  RTEMS_SYSINIT_ORDER_MIDDLE
+);
+
+static const Memory_Information _Memory_Information =
+  MEMORY_INFORMATION_INITIALIZER( _Memory_Areas );
+
+const Memory_Information *_Memory_Get( void )
+{
+  return &_Memory_Information;
+}
diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S
index 04a62a2..6f40279 100644
--- a/bsps/riscv/shared/start/start.S
+++ b/bsps/riscv/shared/start/start.S
@@ -35,6 +35,16 @@
 #include 
 #include 
 
+#if __riscv_xlen == 32
+#define PTR_ALIGN 2
+#define PTR_SIZE 4
+#define PTR_VALUE .word
+#elif __riscv_xlen == 64
+#define PTR_ALIGN 3
+#define PTR_SIZE 8
+#define PTR_VALUE .dword
+#endif
+
 PUBLIC(_start)
 
.section.bsp_start_text, "wax", @progbits
@@ -59,6 +69,9 @@ SYM(_start):
LADDR   t0, _RISCV_Exception_handler
csrwmtvec, t0
 
+   /* Save stack pointer so it can mark end of work area later on */
+   mv  t3, sp
+
/* Load stack pointer and branch to secondary processor start if 
necessary */
 #ifdef RTEMS_SMP

[PATCH] bsp/riscv: move riscv/riscv build spec one level up

2021-02-12 Thread Daniel Hellstrom 
From: Martin Aberg 

These build specifications can be useful for other BSPs aswell.
---
 spec/build/bsps/riscv/{riscv => }/objsmp.yml   |  0
 spec/build/bsps/riscv/{riscv => }/optextirqmax.yml |  0
 spec/build/bsps/riscv/{riscv => }/optfdtcpyro.yml  |  0
 spec/build/bsps/riscv/{riscv => }/optfdtmxsz.yml   |  0
 spec/build/bsps/riscv/{riscv => }/optfdtro.yml |  0
 spec/build/bsps/riscv/{riscv => }/optfdtuboot.yml  |  0
 spec/build/bsps/riscv/riscv/grp.yml| 12 ++--
 7 files changed, 6 insertions(+), 6 deletions(-)
 rename spec/build/bsps/riscv/{riscv => }/objsmp.yml (100%)
 rename spec/build/bsps/riscv/{riscv => }/optextirqmax.yml (100%)
 rename spec/build/bsps/riscv/{riscv => }/optfdtcpyro.yml (100%)
 rename spec/build/bsps/riscv/{riscv => }/optfdtmxsz.yml (100%)
 rename spec/build/bsps/riscv/{riscv => }/optfdtro.yml (100%)
 rename spec/build/bsps/riscv/{riscv => }/optfdtuboot.yml (100%)

diff --git a/spec/build/bsps/riscv/riscv/objsmp.yml 
b/spec/build/bsps/riscv/objsmp.yml
similarity index 100%
rename from spec/build/bsps/riscv/riscv/objsmp.yml
rename to spec/build/bsps/riscv/objsmp.yml
diff --git a/spec/build/bsps/riscv/riscv/optextirqmax.yml 
b/spec/build/bsps/riscv/optextirqmax.yml
similarity index 100%
rename from spec/build/bsps/riscv/riscv/optextirqmax.yml
rename to spec/build/bsps/riscv/optextirqmax.yml
diff --git a/spec/build/bsps/riscv/riscv/optfdtcpyro.yml 
b/spec/build/bsps/riscv/optfdtcpyro.yml
similarity index 100%
rename from spec/build/bsps/riscv/riscv/optfdtcpyro.yml
rename to spec/build/bsps/riscv/optfdtcpyro.yml
diff --git a/spec/build/bsps/riscv/riscv/optfdtmxsz.yml 
b/spec/build/bsps/riscv/optfdtmxsz.yml
similarity index 100%
rename from spec/build/bsps/riscv/riscv/optfdtmxsz.yml
rename to spec/build/bsps/riscv/optfdtmxsz.yml
diff --git a/spec/build/bsps/riscv/riscv/optfdtro.yml 
b/spec/build/bsps/riscv/optfdtro.yml
similarity index 100%
rename from spec/build/bsps/riscv/riscv/optfdtro.yml
rename to spec/build/bsps/riscv/optfdtro.yml
diff --git a/spec/build/bsps/riscv/riscv/optfdtuboot.yml 
b/spec/build/bsps/riscv/optfdtuboot.yml
similarity index 100%
rename from spec/build/bsps/riscv/riscv/optfdtuboot.yml
rename to spec/build/bsps/riscv/optfdtuboot.yml
diff --git a/spec/build/bsps/riscv/riscv/grp.yml 
b/spec/build/bsps/riscv/riscv/grp.yml
index 396f898..6af6c88 100644
--- a/spec/build/bsps/riscv/riscv/grp.yml
+++ b/spec/build/bsps/riscv/riscv/grp.yml
@@ -28,17 +28,17 @@ links:
 - role: build-dependency
   uid: obj
 - role: build-dependency
-  uid: objsmp
+  uid: ../objsmp
 - role: build-dependency
-  uid: optextirqmax
+  uid: ../optextirqmax
 - role: build-dependency
-  uid: optfdtcpyro
+  uid: ../optfdtcpyro
 - role: build-dependency
-  uid: optfdtmxsz
+  uid: ../optfdtmxsz
 - role: build-dependency
-  uid: optfdtro
+  uid: ../optfdtro
 - role: build-dependency
-  uid: optfdtuboot
+  uid: ../optfdtuboot
 - role: build-dependency
   uid: optfrdme310arty
 - role: build-dependency
-- 
2.7.4

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