Re: [PATCH v2 5/5] cpukit: Add AArch64 SMP Support
On 21/09/2021 02:15, Gedare Bloom wrote: looks good, thanks. I'll follow-up later as I make progress on the versal smp side too. that's still a bit broken. On Mon, Sep 20, 2021 at 4:56 PM Kinsey Moore wrote: Version 1 of this patch did not update the Versal BSP's usage of the MMU calls. The patch set looks good. The name of the BSP option BSP_CPU_ON_SMC could be a bit more descriptive. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH v1 2/5] testsuites/smpmulticast01: Enforce step ordering
On 20/09/2021 23:38, Kinsey Moore wrote: The order in which step checks for 1 and 2 are not rigidly defined and may actually occur in either order depending on how the threads execute. This waits for the job to complete to enforce the existing ordering. --- testsuites/smptests/smpmulticast01/init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/testsuites/smptests/smpmulticast01/init.c b/testsuites/smptests/smpmulticast01/init.c index 4163dd8370..ec4bab922d 100644 --- a/testsuites/smptests/smpmulticast01/init.c +++ b/testsuites/smptests/smpmulticast01/init.c @@ -506,6 +506,7 @@ T_TEST_CASE(AddJobInJob) _Per_CPU_Add_job(cpu_self, &add_job_in_job_jobs[0]); T_step(0); _SMP_Send_message(cpu_self, SMP_MESSAGE_PERFORM_JOBS); + _Per_CPU_Wait_for_job(cpu_self, &add_job_in_job_jobs[0]); T_step(2); _SMP_Send_message(cpu_self, SMP_MESSAGE_PERFORM_JOBS); _Thread_Dispatch_enable(cpu_self); This patch is fine. It seems that there could be a delay before the interrupt issued by _SMP_Send_message() is actually serviced on this platform. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH rtems 5 1/2] powerpc/io: Make [out/in] le and be calls conditional
From: Chris Johns
- These calls clash with the Linux IO header in LibBSD. Making these
conditional here means BSPs build and the imported Linux header is
untouched.
Updates #4245
---
bsps/powerpc/include/libcpu/io.h | 8
1 file changed, 8 insertions(+)
diff --git a/bsps/powerpc/include/libcpu/io.h b/bsps/powerpc/include/libcpu/io.h
index 521c97801d..c4e529f4d5 100644
--- a/bsps/powerpc/include/libcpu/io.h
+++ b/bsps/powerpc/include/libcpu/io.h
@@ -107,6 +107,7 @@ static inline void out_be16(volatile uint16_t *addr,
uint16_t val)
__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r"
(val));
}
+#ifndef in_le32
static inline uint32_t in_le32(const volatile uint32_t *addr)
{
uint32_t ret;
@@ -115,7 +116,9 @@ static inline uint32_t in_le32(const volatile uint32_t
*addr)
"r" (addr), "m" (*addr));
return ret;
}
+#endif
+#ifndef in_be32
static inline uint32_t in_be32(const volatile uint32_t *addr)
{
uint32_t ret;
@@ -123,17 +126,22 @@ static inline uint32_t in_be32(const volatile uint32_t
*addr)
__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m"
(*addr));
return ret;
}
+#endif
+#ifndef out_le32
static inline void out_le32(volatile uint32_t *addr, uint32_t val)
{
__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
}
+#endif
+#ifndef out_be32
static inline void out_be32(volatile uint32_t *addr, uint32_t val)
{
__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r"
(val));
}
+#endif
#endif /* ASM */
#endif /* _LIBCPU_IO_H */
--
2.24.1
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[PATCH rtems 5 2/2] powerpc/motorola_powerpc: Map LibBSD bus space to the PCI base address
From: Chris Johns
Closes #4516
---
bsps/powerpc/motorola_powerpc/include/bsp.h | 34 +++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/bsps/powerpc/motorola_powerpc/include/bsp.h
b/bsps/powerpc/motorola_powerpc/include/bsp.h
index 62e740272a..7d362bf406 100644
--- a/bsps/powerpc/motorola_powerpc/include/bsp.h
+++ b/bsps/powerpc/motorola_powerpc/include/bsp.h
@@ -31,11 +31,11 @@
#include
#include
#include
-
+
#ifdef qemu
#include
#endif
-
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -115,6 +115,36 @@ extern "C" {
#endif
#endif
+/*
+ * The BSP has PCI devices. Enable support in LibBSD.
+ */
+#define BSP_HAS_PC_PCI
+
+/*
+ * Remap the PCI address space for LibBSD
+ */
+#define RTEMS_BSP_PCI_IO_REGION_BASE 0
+#define RTEMS_BSP_PCI_MEM_REGION_BASE PCI_DRAM_OFFSET
+
+/*
+ * Remap the PCI address space for LibBSD
+ */
+#define RTEMS_BSP_ADDR_PTR(_type) uint ## _type ## _t __volatile*
+#define RTEMS_BSP_ADDR_CPTR(_type) const RTEMS_BSP_ADDR_PTR(_type)
+#define RTEMS_BSP_ADDRESS_READ(_addr, _type) \
+ *((RTEMS_BSP_ADDR_CPTR(_type)) (((RTEMS_BSP_ADDR_CPTR(8)) _addr) +
PCI_DRAM_OFFSET))
+#define RTEMS_BSP_ADDRESS_WRITE(_addr, _val, _type) \
+ *((RTEMS_BSP_ADDR_PTR(_type)) (((RTEMS_BSP_ADDR_PTR(8)) _addr) +
PCI_DRAM_OFFSET)) = (_val)
+
+#define RTEMS_BSP_READ_1(_addr) RTEMS_BSP_ADDRESS_READ(_addr, 8)
+#define RTEMS_BSP_READ_2(_addr) RTEMS_BSP_ADDRESS_READ(_addr, 16)
+#define RTEMS_BSP_READ_4(_addr) RTEMS_BSP_ADDRESS_READ(_addr, 32)
+#define RTEMS_BSP_READ_8(_addr) RTEMS_BSP_ADDRESS_READ(_addr, 64)
+
+#define RTEMS_BSP_WRITE_1(_addr, _val) RTEMS_BSP_ADDRESS_WRITE(_addr, _val, 8)
+#define RTEMS_BSP_WRITE_2(_addr, _val) RTEMS_BSP_ADDRESS_WRITE(_addr, _val, 16)
+#define RTEMS_BSP_WRITE_4(_addr, _val) RTEMS_BSP_ADDRESS_WRITE(_addr, _val, 32)
+#define RTEMS_BSP_WRITE_8(_addr, _val) RTEMS_BSP_ADDRESS_WRITE(_addr, _val, 64)
/*
* Base address definitions for several devices
--
2.24.1
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Re: [PATCH v4] improve the format of error reporting on i386
printk(" EAX = 0%08" PRIx32 "EBX = 0%08" PRIx32 "ECX = 0%08"
PRIx32 "EDX = 0%08" PRIx32 "\n",
should it look like this gedare? will send once you give the ok
On Sun, 19 Sept 2021 at 17:42, zack leung wrote:
> Bumo
>
> Il ven 17 set 2021, 19:57 zack leung ha
> scritto:
>
>> Where am i missing it?
>>
>> Zack
>>
>> On Fri, 17 Sept 2021 at 23:15, Gedare Bloom wrote:
>>
>>> Hi Zack,
>>>
>>> I think you have also missed Joel's request to add an 8-character
>>> width specifier.
>>>
>>> On Thu, Sep 16, 2021 at 6:19 PM zack leung
>>> wrote:
>>> >
>>> > Thread id is now a Hex value. formatting improved for hex values
>>> > Updates #4203
>>> > ---
>>> > cpukit/score/cpu/i386/cpu.c | 6 +++---
>>> > 1 file changed, 3 insertions(+), 3 deletions(-)
>>> >
>>> > diff --git a/cpukit/score/cpu/i386/cpu.c b/cpukit/score/cpu/i386/cpu.c
>>> > index 77b7a7161c..0f17cf0148 100644
>>> > --- a/cpukit/score/cpu/i386/cpu.c
>>> > +++ b/cpukit/score/cpu/i386/cpu.c
>>> > @@ -215,16 +215,16 @@ void _CPU_Exception_frame_print (const
>>> > CPU_Exception_frame *ctx)
>>> > {
>>> >unsigned int faultAddr = 0;
>>> >
>>> printk("--\n");
>>> > - printk("Exception %" PRIu32 " caught at PC %" PRIx32 " by thread %"
>>> > PRId32 "\n",
>>> > + printk("Exception %" PRIu32 " caught at PC 0x%" PRIx32 " by thread
>>> 0x%"
>>> > PRIx32 "\n",
>>> > ctx->idtIndex,
>>> > ctx->eip,
>>> > _Thread_Executing->Object.id);
>>> >
>>> printk("--\n");
>>> >printk("Processor execution context at time of the fault was :\n");
>>> >
>>> printk("--\n");
>>> > - printk(" EAX = %" PRIx32 "EBX = %" PRIx32 "ECX = %" PRIx32 "
>>> > EDX = %" PRIx32 "\n",
>>> > + printk(" EAX = 0x%" PRIx32 "EBX = 0x%" PRIx32 "ECX = 0x%"
>>> PRIx32
>>> > "EDX = 0x%" PRIx32 "\n",
>>> > ctx->eax, ctx->ebx, ctx->ecx, ctx->edx);
>>> > - printk(" ESI = %" PRIx32 "EDI = %" PRIx32 "EBP = %" PRIx32 "
>>> > ESP = %" PRIx32 "\n",
>>> > + printk(" ESI = 0x%" PRIx32 "EDI = 0x%" PRIx32 "EBP = 0x%"
>>> PRIx32
>>> > "ESP = 0x%" PRIx32 "\n",
>>> > ctx->esi, ctx->edi, ctx->ebp, ctx->esp0);
>>> >
>>> printk("--\n");
>>> >printk("Error code pushed by processor itself (if not 0) = %" PRIx32
>>> > "\n",
>>> > --
>>> > 2.33.0
>>> > ___
>>> > devel mailing list
>>> > devel@rtems.org
>>> > http://lists.rtems.org/mailman/listinfo/devel
>>>
>>
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[PATCH rtems-libbsd 5-freebsd-12 2/2] bsp/motorola_powerpc: Add dc, ukphy and legacy PCI support
From: Chris Johns
- Add the dc net dev to the BSP
- Add the ukphy support
- Add PCI Legacy bus support to the PowerPC
Closes #4514
---
freebsd/sys/dev/dc/if_dc.c | 7 +++
freebsd/sys/dev/dc/if_dcreg.h | 7 +++
libbsd.py | 2 +-
rtemsbsd/include/bsp/nexus-devices.h | 8 +++-
rtemsbsd/include/machine/rtems-bsd-nexus-bus.h | 17 +
rtemsbsd/powerpc/include/machine/legacyvar.h | 2 ++
rtemsbsd/powerpc/include/machine/pci_cfgreg.h | 2 ++
7 files changed, 43 insertions(+), 2 deletions(-)
create mode 100644 rtemsbsd/powerpc/include/machine/legacyvar.h
create mode 100644 rtemsbsd/powerpc/include/machine/pci_cfgreg.h
diff --git a/freebsd/sys/dev/dc/if_dc.c b/freebsd/sys/dev/dc/if_dc.c
index 7fc0ef54..b36967da 100644
--- a/freebsd/sys/dev/dc/if_dc.c
+++ b/freebsd/sys/dev/dc/if_dc.c
@@ -156,6 +156,10 @@ MODULE_DEPEND(dc, miibus, 1, 1, 1);
* Various supported device vendors/types and their names.
*/
static const struct dc_type dc_devs[] = {
+#ifdef __rtems__
+ { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21140A), 0,
+ "Intel 21140A 10/100BaseTX" },
+#endif /* __rtems__ */
{ DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
"Intel 21143 10/100BaseTX" },
{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
@@ -2076,6 +2080,9 @@ dc_attach(device_t dev)
dc_eeprom_width(sc);
switch (sc->dc_info->dc_devid) {
+#ifdef __rtems__
+ case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21140A):
+#endif /* __rtems__ */
case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
sc->dc_type = DC_TYPE_21143;
sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
diff --git a/freebsd/sys/dev/dc/if_dcreg.h b/freebsd/sys/dev/dc/if_dcreg.h
index 9ae26cc6..1c5d39a0 100644
--- a/freebsd/sys/dev/dc/if_dcreg.h
+++ b/freebsd/sys/dev/dc/if_dcreg.h
@@ -824,6 +824,13 @@ struct dc_softc {
*/
#defineDC_VENDORID_DEC 0x1011
+#ifdef __rtems__
+/*
+ * DEC/Intel 21140 PCI device ID
+ */
+#defineDC_DEVICEID_21140A 0x0009
+
+#endif /* __rtems__ */
/*
* DEC/Intel 21143 PCI device ID
*/
diff --git a/libbsd.py b/libbsd.py
index ea54d1c2..cab130cf 100644
--- a/libbsd.py
+++ b/libbsd.py
@@ -2639,7 +2639,7 @@ class pci(builder.Module):
]
)
self.addCPUDependentFreeBSDSourceFiles(
-[ 'i386' ],
+[ 'i386', 'powerpc' ],
[
'sys/x86/x86/legacy.c',
'sys/x86/pci/pci_bus.c',
diff --git a/rtemsbsd/include/bsp/nexus-devices.h
b/rtemsbsd/include/bsp/nexus-devices.h
index d2ceab8e..86305e9c 100644
--- a/rtemsbsd/include/bsp/nexus-devices.h
+++ b/rtemsbsd/include/bsp/nexus-devices.h
@@ -197,6 +197,12 @@ SYSINIT_DRIVER_REFERENCE(ukphy, miibus);
RTEMS_BSD_DEFINE_NEXUS_DEVICE(fec, 0, 0, NULL);
SYSINIT_DRIVER_REFERENCE(ukphy, miibus);
-#endif
+#elif defined(LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H)
+
+RTEMS_BSD_DRIVER_PC_LEGACY;
+RTEMS_BSD_DRIVER_PCI_DC;
+RTEMS_BSD_DRIVER_UKPHY;
+
+#endif /* LIBBSP_POWERPC_MOTOROLA_POWERPC_BSP_H */
#endif
diff --git a/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
b/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
index ff545dc0..c2d71eed 100644
--- a/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
+++ b/rtemsbsd/include/machine/rtems-bsd-nexus-bus.h
@@ -77,6 +77,7 @@
* RTEMS_BSD_DRIVER_ICSPHY
* RTEMS_BSD_DRIVER_REPHY
* RTEMS_BSD_DRIVER_PHY_MIC
+ * RTEMS_BSD_DRIVER_UKPHY
*/
#if !defined(RTEMS_BSD_NEXUS_BUS_h)
@@ -441,6 +442,14 @@ extern "C" {
SYSINIT_DRIVER_REFERENCE(re, pci);
#endif /* RTEMS_BSD_DRIVER_PCI_RE */
+/*
+ * DEC Tulip Driver
+ */
+#if !defined(RTEMS_BSD_DRIVER_PCI_DC)
+ #define RTEMS_BSD_DRIVER_PCI_DC \
+SYSINIT_DRIVER_REFERENCE(dc, pci);
+#endif /* RTEMS_BSD_DRIVER_PCI_DC */
+
/**
** MMI Physical Layer Support.
**/
@@ -477,6 +486,14 @@ extern "C" {
SYSINIT_DRIVER_REFERENCE(micphy, miibus);
#endif /* RTEMS_BSD_DRIVER_PHY_MIC */
+/*
+ * UK PHY (for unknown PHY devices)
+ */
+#if !defined(RTEMS_BSD_DRIVER_UKPHY)
+ #define RTEMS_BSD_DRIVER_UKPHY \
+SYSINIT_DRIVER_REFERENCE(ukphy, miibus);
+#endif /* RTEMS_BSD_DRIVER_UKPHY */
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/rtemsbsd/powerpc/include/machine/legacyvar.h
b/rtemsbsd/powerpc/include/machine/legacyvar.h
new file mode 100644
index ..8683a0e5
--- /dev/null
+++ b/rtemsbsd/powerpc/include/machine/legacyvar.h
@@ -0,0 +1,2 @@
+/* See freebsd/sys/x86/include/machine/legacyvar.h */
+#include
diff --git a/rtemsbsd/powerpc/include/machine/pci_cfgreg.h
b/rtemsbsd/powerpc/include/machine/pci_cfgreg.h
new file mode 100644
index ..1bfa468e
--- /dev/null
+++ b/rtemsbsd/powerpc/include/machine/pci_cfgreg.h
@@ -0,0 +1,2 @@
+/* See freebsd/sys/x86/include/machine/pci_cfgreg.h */
+#include
--
2.24.1
[PATCH rtems-libbsd 5-freebsd-12 1/2] rtemsbsd/bus: Add PCI support to the nexus bus
From: Chris Johns
- Add PCI IO region support
- Add support map buffers to PCI address space
- Add BSP conditional IO space support. Some PC implementations
have PCI IO space mapped differently to memory space and this needs
to be reflected in the busspace.
- Include bsp.h to pick per BSP configuration.
Closes #4514
---
rtemsbsd/include/machine/bus.h| 387 ++
rtemsbsd/rtems/rtems-kernel-bus-dma.c | 5 +-
rtemsbsd/rtems/rtems-kernel-nexus.c | 52 +++-
3 files changed, 321 insertions(+), 123 deletions(-)
diff --git a/rtemsbsd/include/machine/bus.h b/rtemsbsd/include/machine/bus.h
index 2f0e7ad6..a0c3d63a 100644
--- a/rtemsbsd/include/machine/bus.h
+++ b/rtemsbsd/include/machine/bus.h
@@ -6,9 +6,13 @@
* @brief TODO.
*
* File origin from FreeBSD 'sys/amd64/include/bus.h'.
+ *
+ * Conditionally supports PCI IO regions (IO Ports).
*/
/*-
+ * Copyright (c) 2021 Chris Johns. All rights reserved.
+ *
* Copyright (c) 2009, 2015 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
@@ -25,7 +29,7 @@
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright
*notice, this list of conditions and the following disclaimer as
*the first lines of this file unmodified.
@@ -34,7 +38,7 @@
*documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
*derived from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
@@ -123,9 +127,46 @@
#endif
#ifdef __i386__
- #error "your include paths are wrong"
+ #error "x86 has its own bus.h; check your include paths are correct"
#endif
+#include
+
+/*
+ * BSP PCI Support
+ *
+ * The RTEMS Nexus bus support can optionaly support PC PCI spaces that
+ * mapped to BSP speciic address spaces. Add the following define to
+ * the BSP header file to enable this support:
+ *
+ * #define BSP_HAS_PC_PCI
+ *
+ * If enabled a BSP must support the following IO region calls:
+ *
+ * inb : read 8 bits
+ * outb : write 8 bits
+ * inw : read 16 bits
+ * outw : write 16 bits
+ * inl : read 32 bits
+ * outl : write 32 bits
+ *
+ * The BSP needs to provide the DRAM address space offset
+ * PCI_DRAM_OFFSET. This is the base address of the DRAM as seen by a
+ * PCI master.
+ *
+ * i386 BSPs have a special bus.h file and do not use this file.
+ */
+
+#ifdef BSP_HAS_PC_PCI
+
+/*
+ * Values for the bus space tag, not to be used directly by MI code.
+ */
+#defineBSP_BUS_SPACE_IO0 /* space is i/o space */
+#defineBSP_BUS_SPACE_MEM 1 /* space is mem space */
+
+#endif /* BSP_HAS_PC_PCI */
+
/*
* Bus address alignment.
*/
@@ -144,6 +185,7 @@
/*
* Bus access.
*/
+#define BUS_SPACE_INVALID_DATA (~0U)
#define BUS_SPACE_UNRESTRICTED (~0U)
/*
@@ -222,37 +264,153 @@ bus_space_barrier(bus_space_tag_t bst __unused,
bus_space_handle_t bsh, bus_size
/* Do nothing */
}
+/*
+ * BSP Bus Space Map Support
+ *
+ * A BSP can provide the following as C macros in the BSP header
+ * (bsp.h) to speicalise for special BSP specific bus operations:
+ *
+ * RTEMS_BSP_READ_1
+ * RTEMS_BSP_READ_2
+ * RTEMS_BSP_READ_4
+ * RTEMS_BSP_READ_8
+ * RTEMS_BSP_WRITE_1
+ * RTEMS_BSP_WRITE_2
+ * RTEMS_BSP_WRITE_4
+ * RTEMS_BSP_WRITE_8
+ */
+
+static __inline uint8_t
+bsp_bus_space_read_1(const uint8_t __volatile *bsp)
+{
+#if defined(RTEMS_BSP_READ_1)
+ return RTEMS_BSP_READ_1(bsp);
+#else
+ return (*bsp);
+#endif
+}
+
+static __inline uint16_t
+bsp_bus_space_read_2(const uint16_t __volatile *bsp)
+{
+#if defined(RTEMS_BSP_READ_2)
+ return RTEMS_BSP_READ_2(bsp);
+#else
+ return (*bsp);
+#endif
+}
+
+static __inline uint32_t
+bsp_bus_space_read_4(const uint32_t __volatile *bsp)
+{
+#if defined(RTEMS_BSP_READ_4)
+ return RTEMS_BSP_READ_4(bsp);
+#else
+ return (*bsp);
+#endif
+}
+
+static __inline uint64_t
+bsp_bus_space_read_8(const uint64_t __volatile *bsp)
+{
+#if defined(RTEMS_BSP_READ_8)
+ return RTEMS_BSP_READ_8(bsp);
+#else
+ return (*bsp);
+#endif
+}
+
+static __inline void
+bsp_bus_space_write_1(uint8_t __volatile *bsp, uint8_t val)
+{
+#if defined(RTEMS_BSP_WRITE_1)
+ RTEMS_BSP_WRITE_1(bsp, val);
+#else
+ *bsp = val;
+#endif
+}
+
+static __inline void
+bsp_bus_space_write_2(uint16_t __volatile *bsp, uint16_t val)
+{
+#if defined(RTEMS_BSP_WRITE_2)
+ RTEMS_BSP_WRITE_2(bsp, val);
+#else
+ *bsp = val;
+#endif
+}
+
+static __inline void
+bsp_bus_space_write_4(uint32_t __volatile *bsp, uint32_t va
Re: [PATCH v2 5/5] cpukit: Add AArch64 SMP Support
looks good, thanks. I'll follow-up later as I make progress on the
versal smp side too. that's still a bit broken.
On Mon, Sep 20, 2021 at 4:56 PM Kinsey Moore wrote:
>
> Version 1 of this patch did not update the Versal BSP's usage of the MMU
> calls.
>
>
> Kinsey
>
> On 9/20/2021 17:43, Kinsey Moore wrote:
> > This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
> > ---
> > bsps/aarch64/include/bsp/aarch64-mmu.h| 13 ++-
> > bsps/aarch64/shared/start/aarch64-smp.c | 85 +++
> > bsps/aarch64/shared/start/start.S | 12 +--
> > .../aarch64/xilinx-versal/start/bspstartmmu.c | 4 +-
> > bsps/aarch64/xilinx-zynqmp/include/bsp.h | 9 ++
> > .../xilinx-zynqmp/start/bspstarthooks.c | 40 -
> > .../aarch64/xilinx-zynqmp/start/bspstartmmu.c | 28 --
> > .../cpu/aarch64/aarch64-exception-interrupt.S | 6 +-
> > cpukit/score/cpu/aarch64/cpu_asm.S| 78 -
> > cpukit/score/cpu/aarch64/include/rtems/asm.h | 5 ++
> > .../cpu/aarch64/include/rtems/score/cpu.h | 13 ++-
> > .../cpu/aarch64/include/rtems/score/cpuimpl.h | 67 ++-
> > spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml | 2 +
> > spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 +
> > .../bsps/aarch64/xilinx-zynqmp/objsmp.yml | 16
> > spec/build/cpukit/optsmp.yml | 4 +
> > testsuites/smptests/smpfatal08/init.c | 2 +-
> > 17 files changed, 350 insertions(+), 36 deletions(-)
> > create mode 100644 bsps/aarch64/shared/start/aarch64-smp.c
> > create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/objsmp.yml
> >
> > diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h
> > b/bsps/aarch64/include/bsp/aarch64-mmu.h
> > index e82012576f..a5f6e846f3 100644
> > --- a/bsps/aarch64/include/bsp/aarch64-mmu.h
> > +++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
> > @@ -385,17 +385,14 @@ BSP_START_TEXT_SECTION static inline void
> > aarch64_mmu_setup_translation_table(
> > }
> >
> > BSP_START_TEXT_SECTION static inline void
> > -aarch64_mmu_setup_translation_table_and_enable(
> > - const aarch64_mmu_config_entry *config_table,
> > - size_t config_count
> > -)
> > +aarch64_mmu_enable( void )
> > {
> > uint64_t sctlr;
> >
> > - aarch64_mmu_setup_translation_table(
> > -config_table,
> > -config_count
> > - );
> > + /* CPUECTLR_EL1.SMPEN is already set on ZynqMP and is not writable */
> > +
> > + /* Invalidate cache */
> > + rtems_cache_invalidate_entire_data();
> >
> > /* Enable MMU and cache */
> > sctlr = _AArch64_Read_sctlr_el1();
> > diff --git a/bsps/aarch64/shared/start/aarch64-smp.c
> > b/bsps/aarch64/shared/start/aarch64-smp.c
> > new file mode 100644
> > index 00..5ec7babce7
> > --- /dev/null
> > +++ b/bsps/aarch64/shared/start/aarch64-smp.c
> > @@ -0,0 +1,85 @@
> > +/* SPDX-License-Identifier: BSD-2-Clause */
> > +
> > +/**
> > + * @file
> > + *
> > + * @ingroup RTEMSBSPsAArch64Shared
> > + *
> > + * @brief SMP startup and interop code.
> > + */
> > +
> > +/*
> > + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
> > + * Written by Kinsey Moore
> > + *
> > + * Redistribution and use in source and binary forms, with or without
> > + * modification, are permitted provided that the following conditions
> > + * are met:
> > + * 1. Redistributions of source code must retain the above copyright
> > + *notice, this list of conditions and the following disclaimer.
> > + * 2. Redistributions in binary form must reproduce the above copyright
> > + *notice, this list of conditions and the following disclaimer in the
> > + *documentation and/or other materials provided with the distribution.
> > + *
> > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
> > IS"
> > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
> > THE
> > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
> > PURPOSE
> > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
> > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
> > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
> > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
> > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
> > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
> > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
> > THE
> > + * POSSIBILITY OF SUCH DAMAGE.
> > + */
> > +
> > +#include
> > +
> > +#include
> > +
> > +static void bsp_inter_processor_interrupt( void *arg )
> > +{
> > + _SMP_Inter_processor_interrupt_handler( _Per_CPU_Get() );
> > +}
> > +
> > +uint32_t _CPU_SMP_Initialize( void )
> > +{
> > + return arm_gic_irq_processor_count();
> > +}
> > +
> > +void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
> > +
Re: [PATCH v2 5/5] cpukit: Add AArch64 SMP Support
Version 1 of this patch did not update the Versal BSP's usage of the MMU
calls.
Kinsey
On 9/20/2021 17:43, Kinsey Moore wrote:
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
---
bsps/aarch64/include/bsp/aarch64-mmu.h| 13 ++-
bsps/aarch64/shared/start/aarch64-smp.c | 85 +++
bsps/aarch64/shared/start/start.S | 12 +--
.../aarch64/xilinx-versal/start/bspstartmmu.c | 4 +-
bsps/aarch64/xilinx-zynqmp/include/bsp.h | 9 ++
.../xilinx-zynqmp/start/bspstarthooks.c | 40 -
.../aarch64/xilinx-zynqmp/start/bspstartmmu.c | 28 --
.../cpu/aarch64/aarch64-exception-interrupt.S | 6 +-
cpukit/score/cpu/aarch64/cpu_asm.S| 78 -
cpukit/score/cpu/aarch64/include/rtems/asm.h | 5 ++
.../cpu/aarch64/include/rtems/score/cpu.h | 13 ++-
.../cpu/aarch64/include/rtems/score/cpuimpl.h | 67 ++-
spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml | 2 +
spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 +
.../bsps/aarch64/xilinx-zynqmp/objsmp.yml | 16
spec/build/cpukit/optsmp.yml | 4 +
testsuites/smptests/smpfatal08/init.c | 2 +-
17 files changed, 350 insertions(+), 36 deletions(-)
create mode 100644 bsps/aarch64/shared/start/aarch64-smp.c
create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/objsmp.yml
diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h
b/bsps/aarch64/include/bsp/aarch64-mmu.h
index e82012576f..a5f6e846f3 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -385,17 +385,14 @@ BSP_START_TEXT_SECTION static inline void
aarch64_mmu_setup_translation_table(
}
BSP_START_TEXT_SECTION static inline void
-aarch64_mmu_setup_translation_table_and_enable(
- const aarch64_mmu_config_entry *config_table,
- size_t config_count
-)
+aarch64_mmu_enable( void )
{
uint64_t sctlr;
- aarch64_mmu_setup_translation_table(
-config_table,
-config_count
- );
+ /* CPUECTLR_EL1.SMPEN is already set on ZynqMP and is not writable */
+
+ /* Invalidate cache */
+ rtems_cache_invalidate_entire_data();
/* Enable MMU and cache */
sctlr = _AArch64_Read_sctlr_el1();
diff --git a/bsps/aarch64/shared/start/aarch64-smp.c
b/bsps/aarch64/shared/start/aarch64-smp.c
new file mode 100644
index 00..5ec7babce7
--- /dev/null
+++ b/bsps/aarch64/shared/start/aarch64-smp.c
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64Shared
+ *
+ * @brief SMP startup and interop code.
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#include
+
+static void bsp_inter_processor_interrupt( void *arg )
+{
+ _SMP_Inter_processor_interrupt_handler( _Per_CPU_Get() );
+}
+
+uint32_t _CPU_SMP_Initialize( void )
+{
+ return arm_gic_irq_processor_count();
+}
+
+void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
+{
+ if ( cpu_count > 0 ) {
+rtems_status_code sc;
+
+sc = rtems_interrupt_handler_install(
+ ARM_GIC_IRQ_SGI_0,
+ "IPI",
+ RTEMS_INTERRUPT_UNIQUE,
+ bsp_inter_processor_interrupt,
+ NULL
+);
+_Assert( sc == RTEMS_SUCCESSFUL );
+(void) sc;
+
+#if defined( BSP_DATA_CACHE_ENABLED ) || \
+defined( BSP_INSTRUCTION_CACHE_ENABLED )
+/* Enable unified L2 cache */
+rtems_cache_enable_data();
+#endif
+ }
+}
+
+void _CPU_SMP_Prepare_start_multitasking( void )
+{
+ /* Do nothing */
+}
+
+void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
+{
+ arm_gic_irq_generat
[PATCH v2 5/5] cpukit: Add AArch64 SMP Support
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
---
bsps/aarch64/include/bsp/aarch64-mmu.h| 13 ++-
bsps/aarch64/shared/start/aarch64-smp.c | 85 +++
bsps/aarch64/shared/start/start.S | 12 +--
.../aarch64/xilinx-versal/start/bspstartmmu.c | 4 +-
bsps/aarch64/xilinx-zynqmp/include/bsp.h | 9 ++
.../xilinx-zynqmp/start/bspstarthooks.c | 40 -
.../aarch64/xilinx-zynqmp/start/bspstartmmu.c | 28 --
.../cpu/aarch64/aarch64-exception-interrupt.S | 6 +-
cpukit/score/cpu/aarch64/cpu_asm.S| 78 -
cpukit/score/cpu/aarch64/include/rtems/asm.h | 5 ++
.../cpu/aarch64/include/rtems/score/cpu.h | 13 ++-
.../cpu/aarch64/include/rtems/score/cpuimpl.h | 67 ++-
spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml | 2 +
spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 +
.../bsps/aarch64/xilinx-zynqmp/objsmp.yml | 16
spec/build/cpukit/optsmp.yml | 4 +
testsuites/smptests/smpfatal08/init.c | 2 +-
17 files changed, 350 insertions(+), 36 deletions(-)
create mode 100644 bsps/aarch64/shared/start/aarch64-smp.c
create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/objsmp.yml
diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h
b/bsps/aarch64/include/bsp/aarch64-mmu.h
index e82012576f..a5f6e846f3 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -385,17 +385,14 @@ BSP_START_TEXT_SECTION static inline void
aarch64_mmu_setup_translation_table(
}
BSP_START_TEXT_SECTION static inline void
-aarch64_mmu_setup_translation_table_and_enable(
- const aarch64_mmu_config_entry *config_table,
- size_t config_count
-)
+aarch64_mmu_enable( void )
{
uint64_t sctlr;
- aarch64_mmu_setup_translation_table(
-config_table,
-config_count
- );
+ /* CPUECTLR_EL1.SMPEN is already set on ZynqMP and is not writable */
+
+ /* Invalidate cache */
+ rtems_cache_invalidate_entire_data();
/* Enable MMU and cache */
sctlr = _AArch64_Read_sctlr_el1();
diff --git a/bsps/aarch64/shared/start/aarch64-smp.c
b/bsps/aarch64/shared/start/aarch64-smp.c
new file mode 100644
index 00..5ec7babce7
--- /dev/null
+++ b/bsps/aarch64/shared/start/aarch64-smp.c
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64Shared
+ *
+ * @brief SMP startup and interop code.
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#include
+
+static void bsp_inter_processor_interrupt( void *arg )
+{
+ _SMP_Inter_processor_interrupt_handler( _Per_CPU_Get() );
+}
+
+uint32_t _CPU_SMP_Initialize( void )
+{
+ return arm_gic_irq_processor_count();
+}
+
+void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
+{
+ if ( cpu_count > 0 ) {
+rtems_status_code sc;
+
+sc = rtems_interrupt_handler_install(
+ ARM_GIC_IRQ_SGI_0,
+ "IPI",
+ RTEMS_INTERRUPT_UNIQUE,
+ bsp_inter_processor_interrupt,
+ NULL
+);
+_Assert( sc == RTEMS_SUCCESSFUL );
+(void) sc;
+
+#if defined( BSP_DATA_CACHE_ENABLED ) || \
+defined( BSP_INSTRUCTION_CACHE_ENABLED )
+/* Enable unified L2 cache */
+rtems_cache_enable_data();
+#endif
+ }
+}
+
+void _CPU_SMP_Prepare_start_multitasking( void )
+{
+ /* Do nothing */
+}
+
+void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
+{
+ arm_gic_irq_generate_software_irq(
+ARM_GIC_IRQ_SGI_0,
+1U << target_processor_index
+ );
+}
diff --git a/bsps/aarch64/shared/start/start.S
b/bsps/aarch64/shared/start/start.
[PATCH v1 5/5] cpukit: Add AArch64 SMP Support
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
---
bsps/aarch64/include/bsp/aarch64-mmu.h| 13 ++-
bsps/aarch64/shared/start/aarch64-smp.c | 85 +++
bsps/aarch64/shared/start/start.S | 12 +--
bsps/aarch64/xilinx-zynqmp/include/bsp.h | 9 ++
.../xilinx-zynqmp/start/bspstarthooks.c | 40 -
.../aarch64/xilinx-zynqmp/start/bspstartmmu.c | 28 --
.../cpu/aarch64/aarch64-exception-interrupt.S | 11 +--
cpukit/score/cpu/aarch64/cpu_asm.S| 79 +++--
cpukit/score/cpu/aarch64/include/rtems/asm.h | 5 ++
.../cpu/aarch64/include/rtems/score/cpu.h | 13 ++-
.../cpu/aarch64/include/rtems/score/cpuimpl.h | 67 ++-
spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml | 2 +
spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml | 2 +
.../bsps/aarch64/xilinx-zynqmp/objsmp.yml | 16
spec/build/cpukit/optsmp.yml | 4 +
testsuites/smptests/smpfatal08/init.c | 2 +-
16 files changed, 342 insertions(+), 46 deletions(-)
create mode 100644 bsps/aarch64/shared/start/aarch64-smp.c
create mode 100644 spec/build/bsps/aarch64/xilinx-zynqmp/objsmp.yml
diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h
b/bsps/aarch64/include/bsp/aarch64-mmu.h
index e82012576f..a5f6e846f3 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -385,17 +385,14 @@ BSP_START_TEXT_SECTION static inline void
aarch64_mmu_setup_translation_table(
}
BSP_START_TEXT_SECTION static inline void
-aarch64_mmu_setup_translation_table_and_enable(
- const aarch64_mmu_config_entry *config_table,
- size_t config_count
-)
+aarch64_mmu_enable( void )
{
uint64_t sctlr;
- aarch64_mmu_setup_translation_table(
-config_table,
-config_count
- );
+ /* CPUECTLR_EL1.SMPEN is already set on ZynqMP and is not writable */
+
+ /* Invalidate cache */
+ rtems_cache_invalidate_entire_data();
/* Enable MMU and cache */
sctlr = _AArch64_Read_sctlr_el1();
diff --git a/bsps/aarch64/shared/start/aarch64-smp.c
b/bsps/aarch64/shared/start/aarch64-smp.c
new file mode 100644
index 00..5ec7babce7
--- /dev/null
+++ b/bsps/aarch64/shared/start/aarch64-smp.c
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64Shared
+ *
+ * @brief SMP startup and interop code.
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#include
+
+static void bsp_inter_processor_interrupt( void *arg )
+{
+ _SMP_Inter_processor_interrupt_handler( _Per_CPU_Get() );
+}
+
+uint32_t _CPU_SMP_Initialize( void )
+{
+ return arm_gic_irq_processor_count();
+}
+
+void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
+{
+ if ( cpu_count > 0 ) {
+rtems_status_code sc;
+
+sc = rtems_interrupt_handler_install(
+ ARM_GIC_IRQ_SGI_0,
+ "IPI",
+ RTEMS_INTERRUPT_UNIQUE,
+ bsp_inter_processor_interrupt,
+ NULL
+);
+_Assert( sc == RTEMS_SUCCESSFUL );
+(void) sc;
+
+#if defined( BSP_DATA_CACHE_ENABLED ) || \
+defined( BSP_INSTRUCTION_CACHE_ENABLED )
+/* Enable unified L2 cache */
+rtems_cache_enable_data();
+#endif
+ }
+}
+
+void _CPU_SMP_Prepare_start_multitasking( void )
+{
+ /* Do nothing */
+}
+
+void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
+{
+ arm_gic_irq_generate_software_irq(
+ARM_GIC_IRQ_SGI_0,
+1U << target_processor_index
+ );
+}
diff --git a/bsps/aarch64/shared/start/start.S
b/bsps/aarch64/shared/start/start.S
index f4c39dacdf..bc6a855217 100644
--- a/bsps/aarch
[PATCH v1 4/5] bsps/gicv2: Allow BSPs to define IRQ attributes
ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
---
.../shared/dev/irq/arm-gicv2-get-attributes.c | 77 +++
bsps/shared/dev/irq/arm-gicv2-zynqmp.c| 76 ++
bsps/shared/dev/irq/arm-gicv2.c | 61 +++
spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml | 1 +
.../altera-cyclone-v/bspalteracyclonev.yml| 1 +
spec/build/bsps/arm/imx/bspimx.yml| 1 +
.../arm/realview-pbx-a9/bsprealviewpbxa9.yml | 1 +
spec/build/bsps/arm/xen/bspxen.yml| 1 +
spec/build/bsps/arm/xilinx-zynq/obj.yml | 1 +
.../arm/xilinx-zynqmp/bspxilinxzynqmp.yml | 1 +
10 files changed, 187 insertions(+), 34 deletions(-)
create mode 100644 bsps/shared/dev/irq/arm-gicv2-get-attributes.c
create mode 100644 bsps/shared/dev/irq/arm-gicv2-zynqmp.c
diff --git a/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
new file mode 100644
index 00..62aa504678
--- /dev/null
+++ b/bsps/shared/dev/irq/arm-gicv2-get-attributes.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief This source file contains the interrupt get attribute implementation.
+ */
+
+/*
+ * Copyright (c) 2013, 2021 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+
+rtems_status_code bsp_interrupt_get_attributes(
+ rtems_vector_number vector,
+ rtems_interrupt_attributes *attributes
+)
+{
+ attributes->is_maskable = true;
+ attributes->maybe_enable = true;
+ attributes->maybe_disable = true;
+ attributes->can_raise = true;
+
+ if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
+/*
+ * It is implementation-defined whether implemented SGIs are permanently
+ * enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and
+ * GICD_ICENABLER0.
+ */
+attributes->can_raise_on = true;
+attributes->cleared_by_acknowledge = true;
+attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
+ } else {
+attributes->can_disable = true;
+attributes->can_clear = true;
+attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
+
+if ( vector > ARM_GIC_IRQ_PPI_LAST ) {
+ /* SPI */
+ attributes->can_get_affinity = true;
+ attributes->can_set_affinity = true;
+}
+ }
+
+ return RTEMS_SUCCESSFUL;
+}
diff --git a/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
new file mode 100644
index 00..ee4479155a
--- /dev/null
+++ b/bsps/shared/dev/irq/arm-gicv2-zynqmp.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief This source file contains the interrupt get attribute implementation.
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ *
[PATCH v1 3/5] bsps/zynqmp: Use correct number of interrupts
GICv2 can support up to 1024 interrupts, but ZynqMP hardware is only
configured for 192 interrupts.
---
bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
index 9af41643bd..3ffb01d1df 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
@@ -48,7 +48,7 @@
extern "C" {
#endif /* __cplusplus */
-#define BSP_INTERRUPT_VECTOR_COUNT 1024
+#define BSP_INTERRUPT_VECTOR_COUNT 192
/* Interrupts vectors */
#define BSP_TIMER_VIRT_PPI 27
--
2.30.2
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[PATCH v1 2/5] testsuites/smpmulticast01: Enforce step ordering
The order in which step checks for 1 and 2 are not rigidly defined and may actually occur in either order depending on how the threads execute. This waits for the job to complete to enforce the existing ordering. --- testsuites/smptests/smpmulticast01/init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/testsuites/smptests/smpmulticast01/init.c b/testsuites/smptests/smpmulticast01/init.c index 4163dd8370..ec4bab922d 100644 --- a/testsuites/smptests/smpmulticast01/init.c +++ b/testsuites/smptests/smpmulticast01/init.c @@ -506,6 +506,7 @@ T_TEST_CASE(AddJobInJob) _Per_CPU_Add_job(cpu_self, &add_job_in_job_jobs[0]); T_step(0); _SMP_Send_message(cpu_self, SMP_MESSAGE_PERFORM_JOBS); + _Per_CPU_Wait_for_job(cpu_self, &add_job_in_job_jobs[0]); T_step(2); _SMP_Send_message(cpu_self, SMP_MESSAGE_PERFORM_JOBS); _Thread_Dispatch_enable(cpu_self); -- 2.30.2 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v1 1/5] bsps/shared: Add PSCI SMP startup support
This adds the SMP function that supports spinup of additional CPU cores
using the ARM standard PSCI inteface. This interface is provided by QEMU
as well as ARM Trusted Firmware running in monitor mode (EL3) on ARMv7 and
AArch64 CPUs. This supports activation va SMC or HVC instructions
depending on BSP configuration.
---
bsps/shared/start/bspsmp-arm-psci.c | 92 +
1 file changed, 92 insertions(+)
create mode 100644 bsps/shared/start/bspsmp-arm-psci.c
diff --git a/bsps/shared/start/bspsmp-arm-psci.c
b/bsps/shared/start/bspsmp-arm-psci.c
new file mode 100644
index 00..879aeb6480
--- /dev/null
+++ b/bsps/shared/start/bspsmp-arm-psci.c
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsShared
+ *
+ * @brief PSCI-based BSP CPU start.
+ */
+
+/*
+ * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+
+#include
+#include
+#if defined( AARCH64_MULTILIB_ARCH_V8 ) || \
+ defined( AARCH64_MULTILIB_ARCH_V8_ILP32 )
+#include
+#else
+#include
+#endif
+
+#if defined( AARCH64_MULTILIB_ARCH_V8 ) || \
+ defined( AARCH64_MULTILIB_ARCH_V8_ILP32 )
+#define REGISTER_PREFIX "x"
+#else
+#define REGISTER_PREFIX "r"
+#endif
+
+bool _CPU_SMP_Start_processor( uint32_t cpu_index )
+{
+#if defined( AARCH64_MULTILIB_ARCH_V8 ) || \
+ defined( AARCH64_MULTILIB_ARCH_V8_ILP32 )
+ uint32_t PSCI_FN_SYSTEM_CPU_ON = 0xC403;
+ uint64_t target_cpu = _AArch64_Read_mpidr_el1();
+ uint64_t ret;
+#else
+ uint32_t PSCI_FN_SYSTEM_CPU_ON = 0x8403;
+ uint32_t target_cpu = _AArch32_Read_mpidr();
+ uint32_t ret;
+#endif
+ target_cpu &= ~( 0xffffUL );
+ target_cpu |= cpu_index;
+
+ __asm__ volatile (
+"mov " REGISTER_PREFIX "0, %1\n"
+"mov " REGISTER_PREFIX "1, %2\n"
+"mov " REGISTER_PREFIX "2, %3\n"
+"mov " REGISTER_PREFIX "3, #0\n"
+#ifdef BSP_CPU_ON_SMC
+"smc #0\n"
+#else
+"hvc #0\n"
+#endif
+"mov %0, " REGISTER_PREFIX "0\n"
+: "=r" ( ret ) : "r" ( PSCI_FN_SYSTEM_CPU_ON ), "r" ( target_cpu ),
+"r" ( _start )
+: REGISTER_PREFIX "0", REGISTER_PREFIX "1", REGISTER_PREFIX "2",
+REGISTER_PREFIX "3"
+ );
+
+ if ( ret != 0 ) {
+return false;
+ }
+
+ return _Per_CPU_State_wait_for_non_initial_state( cpu_index, 0 );
+}
--
2.30.2
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Re: [PATCH] bsp-builder: Fix mailer options exception
Hi Alex,
I prefer Python’s argparse and prefer we move the other way. The options
handling originally came from the RSB and has lots of issues. I regret it.
Sorry about this.
Chris
> On 21 Sep 2021, at 2:08 am, Alex White wrote:
>
> This changes the object holding the command line arguments from an
> argparse.Namespace to an rtemstoolkit.options.command_line. This matches
> the type expected by rtemstoolkit.mailer.mail.__init__ and is the type
> used in tester/rt/test.py and run.py.
> ---
> tester/rt/check.py | 151 +
> 1 file changed, 84 insertions(+), 67 deletions(-)
>
> diff --git a/tester/rt/check.py b/tester/rt/check.py
> index c01c25d..982b65e 100755
> --- a/tester/rt/check.py
> +++ b/tester/rt/check.py
> @@ -54,6 +54,8 @@ from rtemstoolkit import rtems
> from rtemstoolkit import textbox
> from rtemstoolkit import version
>
> +import tester.rt.options
> +
> #
> # Group loggin entries together.
> #
> @@ -1153,55 +1155,40 @@ def run(args):
> description += 'can build based on tier, architecture, or BSP. You
> can control '
> description += 'the profile of build with various build configuration
> settings.'
>
> -argsp = argparse.ArgumentParser(prog = 'rtems-bsp-builder',
> -description = description)
> -argsp.add_argument('--prefix', help = 'Prefix to build the BSP.',
> - type = str)
> -argsp.add_argument('--rtems-tools', help = 'The RTEMS tools
> directory.',
> - type = str)
> -argsp.add_argument('--rtems', help = 'The RTEMS source tree.',
> - type = str)
> -argsp.add_argument('--build-path', help = 'Path to build in.',
> - type = str)
> -argsp.add_argument('--log', help = 'Log file.', type = str)
> -argsp.add_argument('--config-report', help = 'Report the
> configuration.',
> - type = str, default = None,
> - choices = ['all', 'profiles', 'builds', 'archs'])
> -argsp.add_argument('--warnings-report', help = 'Report the warnings
> to a file.',
> - type = str, default = None)
> -argsp.add_argument('--failures-report', help = 'Report the failures
> to a file.',
> - type = str, default = None)
> -argsp.add_argument('--stop-on-error', help = 'Stop on an error.',
> - action = 'store_true')
> -argsp.add_argument('--no-clean', help = 'Do not clean the build
> output.',
> - action = 'store_true')
> -argsp.add_argument('--profiles', help = 'Build the listed profiles
> (profile,profile,..).',
> - type = str, default = 'tier-1')
> -argsp.add_argument('--arch', help = 'Build the architectures
> (arch,arch,..).',
> - type = str)
> -argsp.add_argument('--bsp', help = 'Build the BSPs
> (arch/bsp,arch/bsp,..).',
> - type = str)
> -argsp.add_argument('--build', help = 'Build name to build (see
> --config-report).',
> - type = str, default='all')
> -argsp.add_argument('--jobs', help = 'Number of jobs to run.',
> - type = str, default = '1/%d' % (host.cpus()))
> -argsp.add_argument('--dry-run', help = 'Do not run the actual
> builds.',
> - action = 'store_true')
> -mailer.add_arguments(argsp)
> -
> -opts = argsp.parse_args(args[1:])
> +optargs = {
> +'--prefix': 'Prefix to build the BSP.',
> +'--rtems-tools': 'The RTEMS tools directory.',
> +'--rtems': 'The RTEMS source tree.',
> +'--build-path': 'Path to build in.',
> +'--log': 'Log file.',
> +'--config-report': 'Report the configuration.',
> +'--warnings-report': 'Report the warnings to a file.',
> +'--failures-report': 'Report the failures to a file.',
> +'--stop-on-error': 'Stop on an error.',
> +'--no-clean': 'Do not clean the build output.',
> +'--profiles': 'Build the listed profiles (profile,profile,..).',
> +'--arch': 'Build the architectures (arch,arch,..).',
> +'--bsp': 'Build the BSPs (arch/bsp,arch/bsp,..).',
> +'--build': 'Build name to build (see --config-report).',
> +'--jobs': 'Number of jobs to run.',
> +'--dry-run': 'Do not run the actual builds.'
> +}
> +mailer.append_options(optargs)
> +opts = tester.rt.options.load(args, optargs = optargs)
> +
> mail = None
> -if opts.mail:
> +if opts.find_arg('--mail'):
> mail = mailer.mail(opts)
> # Request these now to generate any errors.
> from_addr = ma
Re: [PATCH v4] improve the format of error reporting on i386
On Mon, Sep 13, 2021 at 5:44 PM Joel Sherrill wrote:
>
> On Sun, Sep 12, 2021 at 7:02 PM zack leung wrote:
> >
> > Thread id is now a Hex value.
> > Updates #4203
> > ---
> > cpukit/score/cpu/i386/cpu.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/cpukit/score/cpu/i386/cpu.c b/cpukit/score/cpu/i386/cpu.c
> > index 77b7a7161c..06af57418d 100644
> > --- a/cpukit/score/cpu/i386/cpu.c
> > +++ b/cpukit/score/cpu/i386/cpu.c
> > @@ -215,7 +215,7 @@ void _CPU_Exception_frame_print (const
> > CPU_Exception_frame *ctx)
> > {
> > unsigned int faultAddr = 0;
> > printk("--\n");
> > - printk("Exception %" PRIu32 " caught at PC %" PRIx32 " by thread %"
> > PRId32 "\n",
> > + printk("Exception %" PRIu32 " caught at PC %" PRIx32 " by thread %"
> > PRIx32 "\n",
>
> PC and ID should use PC 0x%08" PRIx32.
>
> Prefixing with 0x to indicate that the number is hexadecimal. Printing
> it with leading zero's and 8 digits wide helps since the address and
> thread id are 32-bit (8 nibbles). A thread id is usually printed like
> 0x0a010004
>
Zack ^
> Does this patch have all your other changes? I've slept since seeing
> this time and thought there were changes..
>
> --joel
>
> > ctx->idtIndex,
> > ctx->eip,
> > _Thread_Executing->Object.id);
> > --
> > 2.33.0
> > ___
> > devel mailing list
> > devel@rtems.org
> > http://lists.rtems.org/mailman/listinfo/devel
> ___
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
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[PATCH] bsp-builder: Fix mailer options exception
This changes the object holding the command line arguments from an
argparse.Namespace to an rtemstoolkit.options.command_line. This matches
the type expected by rtemstoolkit.mailer.mail.__init__ and is the type
used in tester/rt/test.py and run.py.
---
tester/rt/check.py | 151 +
1 file changed, 84 insertions(+), 67 deletions(-)
diff --git a/tester/rt/check.py b/tester/rt/check.py
index c01c25d..982b65e 100755
--- a/tester/rt/check.py
+++ b/tester/rt/check.py
@@ -54,6 +54,8 @@ from rtemstoolkit import rtems
from rtemstoolkit import textbox
from rtemstoolkit import version
+import tester.rt.options
+
#
# Group loggin entries together.
#
@@ -1153,55 +1155,40 @@ def run(args):
description += 'can build based on tier, architecture, or BSP. You can
control '
description += 'the profile of build with various build configuration
settings.'
-argsp = argparse.ArgumentParser(prog = 'rtems-bsp-builder',
-description = description)
-argsp.add_argument('--prefix', help = 'Prefix to build the BSP.',
- type = str)
-argsp.add_argument('--rtems-tools', help = 'The RTEMS tools
directory.',
- type = str)
-argsp.add_argument('--rtems', help = 'The RTEMS source tree.',
- type = str)
-argsp.add_argument('--build-path', help = 'Path to build in.',
- type = str)
-argsp.add_argument('--log', help = 'Log file.', type = str)
-argsp.add_argument('--config-report', help = 'Report the
configuration.',
- type = str, default = None,
- choices = ['all', 'profiles', 'builds', 'archs'])
-argsp.add_argument('--warnings-report', help = 'Report the warnings to
a file.',
- type = str, default = None)
-argsp.add_argument('--failures-report', help = 'Report the failures to
a file.',
- type = str, default = None)
-argsp.add_argument('--stop-on-error', help = 'Stop on an error.',
- action = 'store_true')
-argsp.add_argument('--no-clean', help = 'Do not clean the build
output.',
- action = 'store_true')
-argsp.add_argument('--profiles', help = 'Build the listed profiles
(profile,profile,..).',
- type = str, default = 'tier-1')
-argsp.add_argument('--arch', help = 'Build the architectures
(arch,arch,..).',
- type = str)
-argsp.add_argument('--bsp', help = 'Build the BSPs
(arch/bsp,arch/bsp,..).',
- type = str)
-argsp.add_argument('--build', help = 'Build name to build (see
--config-report).',
- type = str, default='all')
-argsp.add_argument('--jobs', help = 'Number of jobs to run.',
- type = str, default = '1/%d' % (host.cpus()))
-argsp.add_argument('--dry-run', help = 'Do not run the actual builds.',
- action = 'store_true')
-mailer.add_arguments(argsp)
-
-opts = argsp.parse_args(args[1:])
+optargs = {
+'--prefix': 'Prefix to build the BSP.',
+'--rtems-tools': 'The RTEMS tools directory.',
+'--rtems': 'The RTEMS source tree.',
+'--build-path': 'Path to build in.',
+'--log': 'Log file.',
+'--config-report': 'Report the configuration.',
+'--warnings-report': 'Report the warnings to a file.',
+'--failures-report': 'Report the failures to a file.',
+'--stop-on-error': 'Stop on an error.',
+'--no-clean': 'Do not clean the build output.',
+'--profiles': 'Build the listed profiles (profile,profile,..).',
+'--arch': 'Build the architectures (arch,arch,..).',
+'--bsp': 'Build the BSPs (arch/bsp,arch/bsp,..).',
+'--build': 'Build name to build (see --config-report).',
+'--jobs': 'Number of jobs to run.',
+'--dry-run': 'Do not run the actual builds.'
+}
+mailer.append_options(optargs)
+opts = tester.rt.options.load(args, optargs = optargs)
+
mail = None
-if opts.mail:
+if opts.find_arg('--mail'):
mail = mailer.mail(opts)
# Request these now to generate any errors.
from_addr = mail.from_address()
smtp_host = mail.smtp_host()
-if 'mail_to' in opts and opts.mail_to is not None:
-to_addr = opts.mail_to
+to_addr = opts.find_arg('--mail-to')
+if to_addr:
+to_addr = to_addr[1]
else:
to_addr = 'bu...@rtems.org'
-if opts.log is not None:
-logf = opts.log
+if opts.find_arg
