Re: [PATCH v2 2/3] bsps/riscv: add riscv/kendrytek210 BSP variant source changes
This looks ok, There's a minor problem that this patch might break
existing BSPs due to the change in the option name
(RISCV_ENABLE_FRDME310ARTY_SUPPORT to
RISCV_ENABLE_SIFIVE_UART_SUPPORT) until the spec patch is applied, so
it would be better then to combine the patches together, so that it
commits and builds/works cleanly, but this is a pretty minor issue. I
think these patches can be applied.
On Wed, Mar 15, 2023 at 8:04 PM Alan Cudmore wrote:
>
> This patch adds support for the Kendryte K210 RISC-V BSP variant.
> The SoC uses the existing Interrupt Controller, Timer, and console UART.
> It only needs SoC specific initialization and an embedded device tree binary
> similar to the polarfire SoC BSP.
>
> Updates #4876
> ---
> bsps/riscv/riscv/config/kendrytek210.cfg | 9 ++
> bsps/riscv/riscv/console/console-config.c | 10 +--
> bsps/riscv/riscv/console/fe310-uart.c | 2 +-
> bsps/riscv/riscv/include/bsp.h| 4 +
> bsps/riscv/riscv/include/bsp/k210.h | 105 ++
> bsps/riscv/riscv/include/bsp/riscv.h | 4 +
> bsps/riscv/riscv/start/bspstart.c | 43 +
> 7 files changed, 171 insertions(+), 6 deletions(-)
> create mode 100644 bsps/riscv/riscv/config/kendrytek210.cfg
> create mode 100644 bsps/riscv/riscv/include/bsp/k210.h
>
> diff --git a/bsps/riscv/riscv/config/kendrytek210.cfg
> b/bsps/riscv/riscv/config/kendrytek210.cfg
> new file mode 100644
> index 00..b04e78b0e9
> --- /dev/null
> +++ b/bsps/riscv/riscv/config/kendrytek210.cfg
> @@ -0,0 +1,9 @@
> +include $(RTEMS_ROOT)/make/custom/default.cfg
> +
> +RTEMS_CPU = riscv
> +
> +CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany
> +
> +LDFLAGS = -Wl,--gc-sections
> +
> +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections
> diff --git a/bsps/riscv/riscv/console/console-config.c
> b/bsps/riscv/riscv/console/console-config.c
> index 4916191e0b..72743fe9d5 100644
> --- a/bsps/riscv/riscv/console/console-config.c
> +++ b/bsps/riscv/riscv/console/console-config.c
> @@ -55,7 +55,7 @@
> #include
> #include
>
> -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
> +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
> #include
> static fe310_uart_context fe310_uart_instance;
> #endif
> @@ -239,7 +239,7 @@ static void riscv_console_probe(void)
> }
> #endif
>
> -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
> +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
> if (fdt_stringlist_contains(compat, compat_len, "sifive,uart0")) {
>fe310_uart_context *ctx;
>
> @@ -255,7 +255,7 @@ static void riscv_console_probe(void)
> riscv_console.getchar = fe310_uart_read;
>}
>
> - rtems_termios_device_context_initialize(>base, "FE310UART");
> + rtems_termios_device_context_initialize(>base, "SIFIVEUART");
> }
> #endif
>
> @@ -290,7 +290,7 @@ rtems_status_code console_initialize(
>size_t i;
> #endif
>
> -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
> +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
>fe310_uart_context *ctx;
>char fe310_path[] = "/dev/ttyS0";
> #endif
> @@ -326,7 +326,7 @@ rtems_status_code console_initialize(
>}
> #endif
>
> -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
> +#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
>ctx = _uart_instance;
>rtems_termios_device_install(
> fe310_path,
> diff --git a/bsps/riscv/riscv/console/fe310-uart.c
> b/bsps/riscv/riscv/console/fe310-uart.c
> index 506521add0..ddabcff4c8 100644
> --- a/bsps/riscv/riscv/console/fe310-uart.c
> +++ b/bsps/riscv/riscv/console/fe310-uart.c
> @@ -53,7 +53,7 @@ static void fe310_uart_write (
>fe310_uart_context * ctx = (fe310_uart_context*) base;
>size_t i;
>
> - ctx->regs->div = riscv_get_core_frequency() / 115200 - 1;
> + ctx->regs->div = (riscv_get_core_frequency() / 115200 - 1) & 0x;
>ctx->regs->txctrl |= 1;
>ctx->regs->rxctrl |= 1;
>
> diff --git a/bsps/riscv/riscv/include/bsp.h b/bsps/riscv/riscv/include/bsp.h
> index 911b85f4a3..c33de42aa7 100644
> --- a/bsps/riscv/riscv/include/bsp.h
> +++ b/bsps/riscv/riscv/include/bsp.h
> @@ -60,6 +60,10 @@
>
> #include
>
> +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
> + #include
> +#endif
> +
> #ifdef __cplusplus
> extern "C" {
> #endif
> diff --git a/bsps/riscv/riscv/include/bsp/k210.h
> b/bsps/riscv/riscv/include/bsp/k210.h
> new file mode 100644
> index 00..d5ae062863
> --- /dev/null
> +++ b/bsps/riscv/riscv/include/bsp/k210.h
> @@ -0,0 +1,105 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +
> +/**
> + * @file
> + *
> + * @ingroup k210_regs
> + *
> + * @brief k210 RISC-V CPU defines.
> + */
> +
> +/*
> + * Copyright (c) 2022 Alan Cudmore
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * 2.
[PATCH 2/2] libmisc/shell: Add flashdev command
From: Aaron Nyholm
Closes #4869
---
cpukit/include/rtems/shellconfig.h | 7 +
cpukit/libmisc/shell/main_flashdev.c | 352 +++
spec/build/cpukit/objshell.yml | 1 +
3 files changed, 360 insertions(+)
create mode 100644 cpukit/libmisc/shell/main_flashdev.c
diff --git a/cpukit/include/rtems/shellconfig.h
b/cpukit/include/rtems/shellconfig.h
index a013840ee7..489f281400 100644
--- a/cpukit/include/rtems/shellconfig.h
+++ b/cpukit/include/rtems/shellconfig.h
@@ -98,6 +98,7 @@ extern rtems_shell_cmd_t rtems_shell_MD5_Command;
extern rtems_shell_cmd_t rtems_shell_RTC_Command;
extern rtems_shell_cmd_t rtems_shell_SPI_Command;
+extern rtems_shell_cmd_t rtems_shell_FLASHDEV_Command;
extern rtems_shell_cmd_t rtems_shell_I2CDETECT_Command;
extern rtems_shell_cmd_t rtems_shell_I2CGET_Command;
extern rtems_shell_cmd_t rtems_shell_I2CSET_Command;
@@ -556,6 +557,12 @@ extern rtems_shell_alias_t * const
rtems_shell_Initial_aliases[];
_shell_SPI_Command,
#endif
+#if (defined(CONFIGURE_SHELL_COMMANDS_ALL) \
+ && !defined(CONFIGURE_SHELL_NO_COMMAND_FLASHDEV)) \
+|| defined(CONFIGURE_SHELL_COMMAND_FLASHDEV)
+ _shell_FLASHDEV_Command,
+#endif
+
#if (defined(CONFIGURE_SHELL_COMMANDS_ALL) \
&& !defined(CONFIGURE_SHELL_NO_COMMAND_I2CDETECT)) \
|| defined(CONFIGURE_SHELL_COMMAND_I2CDETECT)
diff --git a/cpukit/libmisc/shell/main_flashdev.c
b/cpukit/libmisc/shell/main_flashdev.c
new file mode 100644
index 00..3c6ca1476c
--- /dev/null
+++ b/cpukit/libmisc/shell/main_flashdev.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (C) 2023, 2023 Aaron Nyholm
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+
+
+int flashdev_shell_read(char *dev_path, uint32_t address, uint32_t bytes);
+int flashdev_shell_write(char *dev_path, uint32_t address, char *file_path);
+int flashdev_shell_readid(char *dev_path);
+int flashdev_shell_type(char *dev_path);
+int flashdev_shell_erase(char *dev_path, uint32_t address, uint32_t bytes);
+
+static const char rtems_flashdev_shell_usage [] =
+ "simple flash read / write / erase\n"
+ "\n"
+ "flashdev [-r ]\n"
+ " [-w ] [-e ]\n"
+ " -rRead at address for bytes\n"
+ " -w Write file to address\n"
+ " -eErase at address for bytes\n"
+ " -tPrint the flash type\n"
+ " -iPrint the READID\n"
+ " -hPrint this help\n";
+
+
+static int rtems_flashdev_shell_main(int argc, char *argv[]) {
+
+ char *dev_path = NULL;
+ int i;
+ uint32_t address;
+ uint32_t bytes;
+ char *file_path;
+
+ for (i = 1; i < argc; ++i) {
+if (argv[i][0] == '-') {
+ switch (argv[i][1]) {
+ case ('r'):
+// Read
+if (argc < 5) {
+ printf("Missing argument\n");
+ return -1;
+}
+if (dev_path == NULL) {
+ printf("Please input FLASH_DEV_PATH before instruction\n");
+ return 1;
+}
+errno = 0;
+address = (uint32_t) strtoul(argv[i+1], NULL, 0);
+if (errno != 0) {
+ printf("Could not read address\n");
+}
+errno = 0;
+bytes = (uint32_t) strtoul(argv[i+2], NULL, 0);
+if (errno != 0) {
+ printf("Could not read address\n");
+}
+return flashdev_shell_read(dev_path, address, bytes);
+break;
+ case ('w'):
+// Write
+if (argc < 5) {
+ printf("Missing argument\n");
+ return -1;
+}
+if (dev_path == NULL) {
+ printf("Please input FLASH_DEV_PATH before instruction\n");
+
[PATCH 1/2] dev/flash: Add API for Flash devices
From: Aaron Nyholm
Updates #4896
---
cpukit/dev/flash/flashdev.c | 353
cpukit/include/dev/flash/flashdev.h | 95
spec/build/cpukit/librtemscpu.yml | 4 +
3 files changed, 452 insertions(+)
create mode 100644 cpukit/dev/flash/flashdev.c
create mode 100644 cpukit/include/dev/flash/flashdev.h
diff --git a/cpukit/dev/flash/flashdev.c b/cpukit/dev/flash/flashdev.c
new file mode 100644
index 00..a37d0e6c3d
--- /dev/null
+++ b/cpukit/dev/flash/flashdev.c
@@ -0,0 +1,353 @@
+/*
+ * Copyright (C) 2023, 2023 Aaron Nyholm
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+int flashdev_do_init(
+ flashdev *flash,
+ void (*destroy)(flashdev *flash)
+);
+
+void flashdev_destroy_and_free(flashdev *flash);
+
+void flashdev_destroy(flashdev *flash);
+
+static void flashdev_obtain(flashdev *flash) {
+ rtems_recursive_mutex_lock(>mutex);
+}
+
+static void flashdev_release(flashdev *flash) {
+ rtems_recursive_mutex_unlock(>mutex);
+}
+
+static ssize_t flashdev_read(
+ rtems_libio_t *iop,
+ void *buffer,
+ size_t count
+ )
+{
+ flashdev *flash = IMFS_generic_get_context_by_iop(iop);
+
+ // Check reading from valid region
+ off_t new_offset = iop->offset + count;
+
+ if (iop->data1 != NULL && new_offset >
((flashdev_region*)iop->data1)->length) {
+rtems_set_errno_and_return_minus_one(EINVAL);
+ }
+
+ // Read flash
+ off_t addr;
+ if (iop->data1 == NULL) {
+addr = iop->offset;
+ } else {
+addr = (iop->offset + ((flashdev_region*)iop->data1)->base);
+ }
+ flashdev_obtain(flash);
+ int status = (*flash->read)(flash->driver, addr, count, buffer);
+ flashdev_release(flash);
+
+ // Update offset and return
+ if (status == 0) {
+iop->offset = new_offset;
+return count;
+ } else {
+rtems_set_errno_and_return_minus_one(-status);
+ }
+}
+
+static ssize_t flashdev_write(
+ rtems_libio_t *iop,
+ const void *buffer,
+ size_t count
+ )
+{
+ flashdev *flash = IMFS_generic_get_context_by_iop(iop);
+
+ // Check writing to valid region
+ off_t new_offset = iop->offset + count;
+
+ if (iop->data1 != NULL && new_offset >
((flashdev_region*)iop->data1)->length) {
+rtems_set_errno_and_return_minus_one(EINVAL);
+ }
+
+ // Write to flash
+ off_t addr;
+ if (iop->data1 == NULL) {
+addr = iop->offset;
+ } else {
+addr = (iop->offset + ((flashdev_region*)iop->data1)->base);
+ }
+ flashdev_obtain(flash);
+ int status = (*flash->write)(flash->driver, addr, count, buffer);
+ flashdev_release(flash);
+
+ // Update offset and return
+ if (status == 0) {
+iop->offset = new_offset;
+return count;
+ } else {
+rtems_set_errno_and_return_minus_one(-status);
+ }
+}
+
+static int flashdev_ioctl(
+ rtems_libio_t *iop,
+ ioctl_command_t command,
+ void *arg
+ )
+{
+ flashdev *flash = IMFS_generic_get_context_by_iop(iop);
+ int err = 0;
+
+ flashdev_obtain(flash);
+
+ switch (command) {
+case FLASHDEV_IOCTL_OBTAIN:
+ flashdev_obtain(flash);
+ err = 0;
+ break;
+case FLASHDEV_IOCTL_RELEASE:
+ flashdev_release(flash);
+ err = 0;
+ break;
+case FLASHDEV_IOCTL_READID:
+ uint32_t *readID_out = arg;
+ *readID_out = (*flash->read_id)(flash);
+ err = 0;
+ break;
+case FLASHDEV_IOCTL_ERASE:
+ erase_args *erase_args_1 = (erase_args*)arg;
+ // Check erasing valid region
+ off_t check_offset = erase_args_1->offset + erase_args_1->count;
+ if ((iop->data1 != NULL) &&
+ (check_offset > ((flashdev_region*)iop->data1)->length ||
+
Flash Device API
This generic flash device API creates a device wrapper for flash drivers. It allows for the flash device to opened as a file descriptor with region limiting. IOCTL calls are present to allow for device idenification. Designed with the goal of creating a generic flash driver that allows different BSPs to create flash devices in a unified manner. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH v2 3/3] spec: add riscv kendrytek210 variant build options
This patch includes the spec/build options for the riscv kendrytek210
BSP variant. It includes options to allow the frdme310arty console
UART to be used on multiple BSPS, device tree options, memory
options, and other required options for the variant.
Updates #4876
---
spec/build/bsps/optdtb.yml| 4 +++-
spec/build/bsps/optdtbheaderpath.yml | 2 ++
spec/build/bsps/optfdtuboot.yml | 3 +++
spec/build/bsps/riscv/optramsize.yml | 2 ++
spec/build/bsps/riscv/riscv/abi.yml | 1 +
.../bsps/riscv/riscv/bspkendrtyek210.yml | 19 ++
spec/build/bsps/riscv/riscv/grp.yml | 4
spec/build/bsps/riscv/riscv/obj.yml | 1 +
.../bsps/riscv/riscv/optkendrytek210.yml | 18 +
spec/build/bsps/riscv/riscv/optns16550max.yml | 4 +++-
spec/build/bsps/riscv/riscv/optsifiveuart.yml | 20 +++
spec/build/cpukit/optsmp.yml | 1 +
12 files changed, 77 insertions(+), 2 deletions(-)
create mode 100644 spec/build/bsps/riscv/riscv/bspkendrtyek210.yml
create mode 100644 spec/build/bsps/riscv/riscv/optkendrytek210.yml
create mode 100644 spec/build/bsps/riscv/riscv/optsifiveuart.yml
diff --git a/spec/build/bsps/optdtb.yml b/spec/build/bsps/optdtb.yml
index 78fed67866..f775dc7750 100644
--- a/spec/build/bsps/optdtb.yml
+++ b/spec/build/bsps/optdtb.yml
@@ -6,7 +6,9 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default:
-- enabled-by: riscv/mpfs64imafdc
+- enabled-by:
+ - riscv/mpfs64imafdc
+ - riscv/kendrytek210
value: true
- enabled-by: true
value: false
diff --git a/spec/build/bsps/optdtbheaderpath.yml
b/spec/build/bsps/optdtbheaderpath.yml
index 65573c4cb8..944c8e830e 100644
--- a/spec/build/bsps/optdtbheaderpath.yml
+++ b/spec/build/bsps/optdtbheaderpath.yml
@@ -8,6 +8,8 @@ copyrights:
default:
- enabled-by: riscv/mpfs64imafdc
value: bsp/mpfs-dtb.h
+- enabled-by: riscv/kendrytek210
+ value: bsp/kendryte-k210-dtb.h
- enabled-by: true
value: false
description: |
diff --git a/spec/build/bsps/optfdtuboot.yml b/spec/build/bsps/optfdtuboot.yml
index 8c53b8b799..9d91639dc6 100644
--- a/spec/build/bsps/optfdtuboot.yml
+++ b/spec/build/bsps/optfdtuboot.yml
@@ -6,6 +6,9 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
default:
+- enabled-by:
+ - riscv/kendrytek210
+ value: false
- enabled-by: true
value: true
description: |
diff --git a/spec/build/bsps/riscv/optramsize.yml
b/spec/build/bsps/riscv/optramsize.yml
index be80c0f462..1fc407d1ea 100644
--- a/spec/build/bsps/riscv/optramsize.yml
+++ b/spec/build/bsps/riscv/optramsize.yml
@@ -15,6 +15,8 @@ default:
value: 0x1000
- enabled-by: riscv/griscv
value: 0x0100
+- enabled-by: riscv/kendrytek210
+ value: 0x0060
- enabled-by: true
value: 0x0400
description: ''
diff --git a/spec/build/bsps/riscv/riscv/abi.yml
b/spec/build/bsps/riscv/riscv/abi.yml
index ab3046ee24..de23bdd795 100644
--- a/spec/build/bsps/riscv/riscv/abi.yml
+++ b/spec/build/bsps/riscv/riscv/abi.yml
@@ -10,6 +10,7 @@ default:
- enabled-by:
- riscv/mpfs64imafdc
- riscv/rv64imafdc
+ - riscv/kendrytek210
value:
- -march=rv64imafdc
- -mabi=lp64d
diff --git a/spec/build/bsps/riscv/riscv/bspkendrtyek210.yml
b/spec/build/bsps/riscv/riscv/bspkendrtyek210.yml
new file mode 100644
index 00..91c601979e
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/bspkendrtyek210.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: kendrytek210
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2022 Alan Cudmore
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+ uid: ../../opto2
+- role: build-dependency
+ uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/riscv/riscv/grp.yml
b/spec/build/bsps/riscv/riscv/grp.yml
index 713c15509a..a2ed4a1052 100644
--- a/spec/build/bsps/riscv/riscv/grp.yml
+++ b/spec/build/bsps/riscv/riscv/grp.yml
@@ -50,10 +50,14 @@ links:
uid: ../../optdtbheaderpath
- role: build-dependency
uid: optfrdme310arty
+- role: build-dependency
+ uid: optkendrytek210
- role: build-dependency
uid: opthtif
- role: build-dependency
uid: optmpfs
+- role: build-dependency
+ uid: optsifiveuart
- role: build-dependency
uid: optns16550max
- role: build-dependency
diff --git a/spec/build/bsps/riscv/riscv/obj.yml
b/spec/build/bsps/riscv/riscv/obj.yml
index 0ddeef828b..d28945fae4 100644
--- a/spec/build/bsps/riscv/riscv/obj.yml
+++ b/spec/build/bsps/riscv/riscv/obj.yml
@@ -16,6 +16,7 @@ install:
- bsps/riscv/riscv/include/bsp/fe310-uart.h
- bsps/riscv/riscv/include/bsp/irq.h
- bsps/riscv/riscv/include/bsp/riscv.h
+ - bsps/riscv/riscv/include/bsp/k210.h
- destination: ${BSP_INCLUDEDIR}/dev/serial
source:
-
[PATCH v2 1/3] bsps/riscv: add device tree source and device tree blob header for k210 bsp variant
This patch adds the k210 device tree source and the corresponding
device tree blob encoded in the header which is used for the
embedded device tree blob for the Kendryte K210 BSP variant.
Updates #4876
---
bsps/riscv/riscv/dts/kendryte-k210.dts| 216
.../riscv/include/bsp/kendryte-k210-dtb.h | 315 ++
2 files changed, 531 insertions(+)
create mode 100644 bsps/riscv/riscv/dts/kendryte-k210.dts
create mode 100644 bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h
diff --git a/bsps/riscv/riscv/dts/kendryte-k210.dts
b/bsps/riscv/riscv/dts/kendryte-k210.dts
new file mode 100644
index 00..cad413dc81
--- /dev/null
+++ b/bsps/riscv/riscv/dts/kendryte-k210.dts
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) Alan Cudmore
+ * Copyright (C) Padmarao Begari
+ * Copyright (C) 2022 Microchip Technology Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /* This is a device tree for the Kendryte K210 SoC. It is a simplified tree
+ * to support the current RTEMS BSP, but it is not sufficient enough for
+ * full linux or u-boot support.
+ * The file structure is based on the device tree source for the
+ * Polarfire SoC created by Padmaro Begari. The K210 device trees from
+ * u-boot were originally used to bring up the RTEMS BSP and were
+ * referenced to develop this file.
+ */
+
+/dts-v1/;
+
+/ {
+/* 32 bit address bus - upper 32 bits are ignored */
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "Kendtryte K210 generic";
+ compatible = "canaan,kendryte-k210";
+
+ aliases {
+ serial0 =
+ serial1 =
+ /* serial2 = */
+ /* serial3 = */
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ timebase-frequency = <780>;
+
+ cpu0: cpu@0 {
+ compatible = "canaan,k210", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa = "rv64imafdc";
+ i-cache-block-size = <64>;
+ i-cache-size = <0x8000>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x8000>;
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "canaan,k210", "riscv";
+ device_type = "cpu";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ i-cache-block-size = <64>;
+ i-cache-size = <0x8000>;
+ d-cache-block-size = <64>;
+ d-cache-size = <0x8000>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+
+ };
+
+ clocks {
+in0: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ };
+ };
+
+ sram: memory@8000 {
+ device_type = "memory";
+
[PATCH v2 2/3] bsps/riscv: add riscv/kendrytek210 BSP variant source changes
This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.
Updates #4876
---
bsps/riscv/riscv/config/kendrytek210.cfg | 9 ++
bsps/riscv/riscv/console/console-config.c | 10 +--
bsps/riscv/riscv/console/fe310-uart.c | 2 +-
bsps/riscv/riscv/include/bsp.h| 4 +
bsps/riscv/riscv/include/bsp/k210.h | 105 ++
bsps/riscv/riscv/include/bsp/riscv.h | 4 +
bsps/riscv/riscv/start/bspstart.c | 43 +
7 files changed, 171 insertions(+), 6 deletions(-)
create mode 100644 bsps/riscv/riscv/config/kendrytek210.cfg
create mode 100644 bsps/riscv/riscv/include/bsp/k210.h
diff --git a/bsps/riscv/riscv/config/kendrytek210.cfg
b/bsps/riscv/riscv/config/kendrytek210.cfg
new file mode 100644
index 00..b04e78b0e9
--- /dev/null
+++ b/bsps/riscv/riscv/config/kendrytek210.cfg
@@ -0,0 +1,9 @@
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU = riscv
+
+CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany
+
+LDFLAGS = -Wl,--gc-sections
+
+CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections
diff --git a/bsps/riscv/riscv/console/console-config.c
b/bsps/riscv/riscv/console/console-config.c
index 4916191e0b..72743fe9d5 100644
--- a/bsps/riscv/riscv/console/console-config.c
+++ b/bsps/riscv/riscv/console/console-config.c
@@ -55,7 +55,7 @@
#include
#include
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
#include
static fe310_uart_context fe310_uart_instance;
#endif
@@ -239,7 +239,7 @@ static void riscv_console_probe(void)
}
#endif
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
if (fdt_stringlist_contains(compat, compat_len, "sifive,uart0")) {
fe310_uart_context *ctx;
@@ -255,7 +255,7 @@ static void riscv_console_probe(void)
riscv_console.getchar = fe310_uart_read;
}
- rtems_termios_device_context_initialize(>base, "FE310UART");
+ rtems_termios_device_context_initialize(>base, "SIFIVEUART");
}
#endif
@@ -290,7 +290,7 @@ rtems_status_code console_initialize(
size_t i;
#endif
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
fe310_uart_context *ctx;
char fe310_path[] = "/dev/ttyS0";
#endif
@@ -326,7 +326,7 @@ rtems_status_code console_initialize(
}
#endif
-#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0
+#if RISCV_ENABLE_SIFIVE_UART_SUPPORT != 0
ctx = _uart_instance;
rtems_termios_device_install(
fe310_path,
diff --git a/bsps/riscv/riscv/console/fe310-uart.c
b/bsps/riscv/riscv/console/fe310-uart.c
index 506521add0..ddabcff4c8 100644
--- a/bsps/riscv/riscv/console/fe310-uart.c
+++ b/bsps/riscv/riscv/console/fe310-uart.c
@@ -53,7 +53,7 @@ static void fe310_uart_write (
fe310_uart_context * ctx = (fe310_uart_context*) base;
size_t i;
- ctx->regs->div = riscv_get_core_frequency() / 115200 - 1;
+ ctx->regs->div = (riscv_get_core_frequency() / 115200 - 1) & 0x;
ctx->regs->txctrl |= 1;
ctx->regs->rxctrl |= 1;
diff --git a/bsps/riscv/riscv/include/bsp.h b/bsps/riscv/riscv/include/bsp.h
index 911b85f4a3..c33de42aa7 100644
--- a/bsps/riscv/riscv/include/bsp.h
+++ b/bsps/riscv/riscv/include/bsp.h
@@ -60,6 +60,10 @@
#include
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+ #include
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/bsps/riscv/riscv/include/bsp/k210.h
b/bsps/riscv/riscv/include/bsp/k210.h
new file mode 100644
index 00..d5ae062863
--- /dev/null
+++ b/bsps/riscv/riscv/include/bsp/k210.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup k210_regs
+ *
+ * @brief k210 RISC-V CPU defines.
+ */
+
+/*
+ * Copyright (c) 2022 Alan Cudmore
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES;
[PATCH v2 0/3] bsps/riscv: Add kendrytek210 riscv BSP variant
Version 2 patch updates: Separated the device tree source and encoded device tree blob into a separate patch, added the license text to k210.h, eliminated whitespace warnings, and eliminated dead code in the conditional compilation structure for the core_get_frequency function in start/bspstart.c. This patch set adds the riscv/kendrytek210 BSP variant to support the Kendryte K210 Dual Core RISC-V SoC. The BSP runs on the renode.io simulator, the Sipeed MAiX BiT and MAiXDuino boards, and would likely run on other boards. RTEMS binaries can be flashed to the boards using the kflash python utility available through the pip command. Currently the BSP supports the console UART which is shared with the frdme310arty, an interrupt controller, and timer. The included device tree source just covers a minimal set of peripherals. The device tree can be expanded as additional device support is addded. Manufacturer, board links, and other information can be found in ticket #4876. Documentation that describes how to build and run the BSP on the boards and simulator has been prepared and will be submitted after the bsp is merged. The full testsuite has not been run on this BSP, but I run a subset of the of testsuite on the renode.io robot test framework. Alan Cudmore (3): bsps/riscv: add device tree source and device tree blob header for k210 bsp variant bsps/riscv: add riscv/kendrytek210 BSP variant source changes spec: add riscv kendrytek210 variant build options bsps/riscv/riscv/config/kendrytek210.cfg | 9 + bsps/riscv/riscv/console/console-config.c | 10 +- bsps/riscv/riscv/console/fe310-uart.c | 2 +- bsps/riscv/riscv/dts/kendryte-k210.dts| 216 bsps/riscv/riscv/include/bsp.h| 4 + bsps/riscv/riscv/include/bsp/k210.h | 105 ++ .../riscv/include/bsp/kendryte-k210-dtb.h | 315 ++ bsps/riscv/riscv/include/bsp/riscv.h | 4 + bsps/riscv/riscv/start/bspstart.c | 43 +++ spec/build/bsps/optdtb.yml| 4 +- spec/build/bsps/optdtbheaderpath.yml | 2 + spec/build/bsps/optfdtuboot.yml | 3 + spec/build/bsps/riscv/optramsize.yml | 2 + spec/build/bsps/riscv/riscv/abi.yml | 1 + .../bsps/riscv/riscv/bspkendrtyek210.yml | 19 ++ spec/build/bsps/riscv/riscv/grp.yml | 4 + spec/build/bsps/riscv/riscv/obj.yml | 1 + .../bsps/riscv/riscv/optkendrytek210.yml | 18 + spec/build/bsps/riscv/riscv/optns16550max.yml | 4 +- spec/build/bsps/riscv/riscv/optsifiveuart.yml | 20 ++ spec/build/cpukit/optsmp.yml | 1 + 21 files changed, 779 insertions(+), 8 deletions(-) create mode 100644 bsps/riscv/riscv/config/kendrytek210.cfg create mode 100644 bsps/riscv/riscv/dts/kendryte-k210.dts create mode 100644 bsps/riscv/riscv/include/bsp/k210.h create mode 100644 bsps/riscv/riscv/include/bsp/kendryte-k210-dtb.h create mode 100644 spec/build/bsps/riscv/riscv/bspkendrtyek210.yml create mode 100644 spec/build/bsps/riscv/riscv/optkendrytek210.yml create mode 100644 spec/build/bsps/riscv/riscv/optsifiveuart.yml -- 2.25.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] bsps/stm32h7: add comments explaining MPU setup
---
bsps/arm/stm32h7/start/mpu-config.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/bsps/arm/stm32h7/start/mpu-config.c
b/bsps/arm/stm32h7/start/mpu-config.c
index ce3c92ccb0..a3ebc065ec 100644
--- a/bsps/arm/stm32h7/start/mpu-config.c
+++ b/bsps/arm/stm32h7/start/mpu-config.c
@@ -31,6 +31,10 @@
const ARMV7M_MPU_Region_config stm32h7_config_mpu_region [] = {
{
+ /*| memory | shareability | privileged | unprivileged | executability |
+ | type | | perms|perms | |
+ +-+---++--+---+
*/
+ /* normal | not shareable | RW | RW | NO */
.begin = stm32h7_memory_sram_axi_begin,
.end = stm32h7_memory_sram_axi_end,
.rasr = ARMV7M_MPU_RASR_XN
@@ -38,6 +42,7 @@ const ARMV7M_MPU_Region_config stm32h7_config_mpu_region [] =
{
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
}, {
+ /* normal | not shareable | RW | RW | NO */
.begin = stm32h7_memory_sdram_1_begin,
.end = stm32h7_memory_sdram_1_end,
.rasr = ARMV7M_MPU_RASR_XN
@@ -45,6 +50,7 @@ const ARMV7M_MPU_Region_config stm32h7_config_mpu_region [] =
{
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
}, {
+ /* normal | not shareable | RW | RW | NO */
.begin = stm32h7_memory_sdram_2_begin,
.end = stm32h7_memory_sdram_2_end,
.rasr = ARMV7M_MPU_RASR_XN
@@ -52,12 +58,14 @@ const ARMV7M_MPU_Region_config stm32h7_config_mpu_region []
= {
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
}, {
+ /* normal | not shareable | RO | no access| YES */
.begin = bsp_section_start_begin,
.end = bsp_section_text_end,
.rasr = ARMV7M_MPU_RASR_AP(0x5)
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
}, {
+ /* normal | not shareable | RO | no access| NO */
.begin = bsp_section_rodata_begin,
.end = bsp_section_rodata_end,
.rasr = ARMV7M_MPU_RASR_XN
@@ -65,6 +73,7 @@ const ARMV7M_MPU_Region_config stm32h7_config_mpu_region [] =
{
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
}, {
+ /* device | not shareable | RW | RW | NO */
.begin = bsp_section_nocache_begin,
.end = bsp_section_nocachenoload_end,
.rasr = ARMV7M_MPU_RASR_XN
@@ -72,6 +81,7 @@ const ARMV7M_MPU_Region_config stm32h7_config_mpu_region [] =
{
| ARMV7M_MPU_RASR_TEX(0x2)
| ARMV7M_MPU_RASR_ENABLE,
}, {
+ /* n/a | n/a | n/a| n/a | NO */
.begin = stm32h7_memory_null_begin,
.end = stm32h7_memory_null_end,
.rasr = ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_ENABLE,
--
2.25.1
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[PATCH] bsps/zynqmp: Use correct include path
The existing include path only works from inside the RTEMS build. This
fixes the include path to work both in the RTEMS build and with builds
of external apps since this file gets installed with the BSP.
---
bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h
b/bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h
index ac957bb686..5f05308a1f 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/jffs2_xqspipsu.h
@@ -36,7 +36,7 @@
#ifndef LIBBSP_XILINX_ZYNQMP_JFFS2_XQSPIPSU_H
#define LIBBSP_XILINX_ZYNQMP_JFFS2_XQSPIPSU_H
-#include "xqspipsu.h"
+#include
#ifdef __cplusplus
extern "C" {
--
2.30.2
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[PATCH] score/arm: improve printed exception information for Cortex-Mx CPUs
Sponsored-By: Precidata
---
.../score/cpu/arm/arm-exception-frame-print.c | 101 ++
.../cpu/arm/include/rtems/score/armv7m.h | 11 ++
2 files changed, 112 insertions(+)
diff --git a/cpukit/score/cpu/arm/arm-exception-frame-print.c
b/cpukit/score/cpu/arm/arm-exception-frame-print.c
index 4bb1efedec..6a773d9e2d 100644
--- a/cpukit/score/cpu/arm/arm-exception-frame-print.c
+++ b/cpukit/score/cpu/arm/arm-exception-frame-print.c
@@ -32,6 +32,9 @@
#include
#include
+#if defined(ARM_MULTILIB_ARCH_V7M)
+#include
+#endif
#include
static void _ARM_VFP_context_print( const ARM_VFP_context *vfp_context )
@@ -57,6 +60,103 @@ static void _ARM_VFP_context_print( const ARM_VFP_context
*vfp_context )
#endif
}
+static void _ARM_Cortex_M_fault_info_print(void)
+{
+#if defined(ARM_MULTILIB_ARCH_V7M)
+/* prints content of additional debugging registers
+ * available on Cortex-Mx where x > 0 cores.
+ */
+uint32_t cfsr = _ARMV7M_SCB->cfsr;
+uint8_t mmfsr = ARMV7M_SCB_CFSR_MMFSR_GET(cfsr);
+uint8_t bfsr = (ARMV7M_SCB_CFSR_BFSR_GET(cfsr) >> 8);
+uint16_t ufsr = (ARMV7M_SCB_CFSR_UFSR_GET(cfsr) >> 16);
+uint32_t hfsr = _ARMV7M_SCB->hfsr;
+if (mmfsr > 0) {
+printk("MMFSR= 0x%08" PRIx32 " (memory fault)\n", mmfsr);
+if ((mmfsr & 0x1) != 0) {
+printk(" IACCVIOL : 1 (instruction access violation)\n");
+}
+if ((mmfsr & 0x2) != 0) {
+printk(" DACCVIOL : 1 (data access violation)\n");
+}
+if ((mmfsr & 0x8) != 0) {
+printk(" MUNSTKERR : 1 (fault on unstacking on exception
return)\n");
+}
+if ((mmfsr & 0x10) != 0) {
+printk(" MSTKERR: 1 (fault on stacking on exception
entry)\n");
+}
+if ((mmfsr & 0x20) != 0) {
+printk(" MLSPERR: 1 (fault during lazy FP stack
preservation)\n");
+}
+if ((mmfsr & 0x80) != 0) {
+printk(" MMFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n",
_ARMV7M_SCB->mmfar);
+}
+else {
+printk(" MMFARVALID : 0 (undetermined error address)\n");
+}
+}
+if (bfsr > 0) {
+printk("BFSR = 0x%08" PRIx32 " (bus fault)\n", bfsr);
+if ((bfsr & 0x1) != 0) {
+printk(" IBUSERR: 1 (instruction fetch error)\n");
+}
+if ((bfsr & 0x2) != 0) {
+printk(" PRECISERR : 1 (data bus error with known exact
location)\n");
+}
+if ((bfsr & 0x4) != 0) {
+printk(" IMPRECISERR: 1 (data bus error without known exact
location)\n");
+}
+if ((bfsr & 0x8) != 0) {
+printk(" UNSTKERR : 1 (fault on unstacking on exception
return)\n");
+}
+if ((bfsr & 0x10) != 0) {
+printk(" STKERR : 1 (fault on stacking on exception
entry)\n");
+}
+if ((bfsr & 0x20) != 0) {
+printk(" LSPERR : 1 (fault during lazy FP stack
preservation)\n");
+}
+if ((bfsr & 0x80) != 0) {
+printk(" BFARVALID : 1 -> 0x%08" PRIx32 " (error address)\n",
_ARMV7M_SCB->bfar);
+}
+else {
+printk(" BFARVALID : 0 (undetermined error address)\n");
+}
+}
+if (ufsr > 0) {
+printk("UFSR = 0x%08" PRIx32 " (usage fault)\n", ufsr);
+if ((ufsr & 0x1) != 0) {
+printk(" UNDEFINSTR : 1 (undefined instruction issued)\n");
+}
+if ((ufsr & 0x2) != 0) {
+printk(" INVSTATE : 1 (invalid instruction state (Thumb not
set in EPSR or invalid IT state in EPSR))\n");
+}
+if ((ufsr & 0x4) != 0) {
+printk(" INVPC : 1 (integrity check failure on
EXC_RETURN)\n");
+}
+if ((ufsr & 0x8) != 0) {
+printk(" NOCP : 1 (coprocessor instruction issued but
coprocessor disabled or non existent)\n");
+}
+if ((ufsr & 0x100) != 0) {
+printk(" UNALIGNED : 1 (unaligned access operation
occurred)\n");
+}
+if ((ufsr & 0x200) != 0) {
+printk(" DIVBYZERO : 1 (division by zero)");
+}
+}
+if ((hfsr & (ARMV7M_SCB_HFSR_VECTTBL_MASK | ARMV7M_SCB_HFSR_DEBUGEVT_MASK
| ARMV7M_SCB_HFSR_FORCED_MASK)) != 0) {
+printk("HFSR = 0x%08" PRIx32 " (hard fault)\n", hfsr);
+if ((hfsr & ARMV7M_SCB_HFSR_VECTTBL_MASK) != 0) {
+printk(" VECTTBL: 1 (error in address located in vector
table)\n");
+}
+if ((hfsr & ARMV7M_SCB_HFSR_FORCED_MASK) != 0) {
+printk(" FORCED : 1 (configurable fault escalated to hard
fault)\n");
+}
+if ((hfsr & ARMV7M_SCB_HFSR_DEBUGEVT_MASK) != 0) {
+printk(" DEBUGEVT : 1 (debug event occurred with debug system
disabled)\n");
+}
+}
+#endif
+}
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
{
printk(
@@ -100,4 +200,5 @@
Re: rtems gtest
On 15.03.23 14:58, Sam Price wrote: I was looking at rtems-gtest from 4 years ago. https://git.rtems.org/sebh/rtems-gtest.git/ Is this currently in use anywhere for the testing side? I used the latest version recently. I was easy to port to RTEMS. If not I plan on forking the main line google test and writing a toolchain file. The rtems gtest doesn't seem to share the same history as the official google test repo. Yes, this repository used the released versions. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
rtems gtest
I was looking at rtems-gtest from 4 years ago. https://git.rtems.org/sebh/rtems-gtest.git/ Is this currently in use anywhere for the testing side? If not I plan on forking the main line google test and writing a toolchain file. The rtems gtest doesn't seem to share the same history as the official google test repo. -- Thanks, Sam Price ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 0/1] Fix a typo in the stm32h7 BSP Documentation
Thank you On Wed, Mar 15, 2023, 5:21 AM Karel Gardas wrote: > > Thanks! Applied with a slightly modified commit message. > > Karel > > On 3/15/23 05:38, Ruturaj Nanoti wrote: > > Hi, > > > > I found a small typo while going through the BSP documentation for > > stm32h7 and fixed it in this commit. > > > > Thank You > > > > Ruturaj Nanoti (1): > >Fixed a typo in the /user/bsps/arm/stm32h7.rst file. > > > > user/bsps/arm/stm32h7.rst | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 2/2] bsps/riscv: add riscv/kendrytek210 BSP variant
On Tue, Mar 14, 2023 at 11:35 PM Gedare Bloom wrote:
> >> >> > diff --git a/bsps/riscv/riscv/start/bspstart.c
> b/bsps/riscv/riscv/start/bspstart.c
> >> >> > index 30d479ce88..a0b6e683f6 100644
> >> >> > --- a/bsps/riscv/riscv/start/bspstart.c
> >> >> > +++ b/bsps/riscv/riscv/start/bspstart.c
> >> >> > @@ -201,6 +201,14 @@ static uint32_t get_core_frequency(void)
> >> >> > return fdt32_to_cpu(*val);
> >> >> >}
> >> >> > #endif
> >> >> > +
> >> >> > +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
> >> >> > + uint32_t cpu_clock;
> >> >> > +
> >> >> > + cpu_clock = k210_get_frequency();
> >> >> > + return cpu_clock;
> >> >> > +#endif
> >> >> > +
> >> >> >return 0;
> >> >
> >> >
> >> > When you choose the kendrtyek210 BSP variant, the
> RISCV_ENABLE_KENDRYTE_K210_SUPPORT is set to true enabling the code that is
> needed for frequency calculation in this file. I tried to follow the same
> pattern for the MPFS and FRDME310ARTY variants here.
> >> > The K210, FRME310ARTY, and MPFS options could probably use
> refactoring, but I was reluctant to change existing code for the MPFS and
> 310ARTY since I do not have a way of testing them.
> >> >
> >> I would at a minimum make it #else return 0
> >> to avoid having unreachable code in your build.
> >>
> >
> > The "return 0" is right after my ifdef block. If I put #else return 0,
> then there will be two "return 0" statements.
> > If none of the variant options are defined, then the entire routine
> defaults to "return 0" at the bottom.
> > Should I eliminate that and put the else clauses for the FRDME310ARTY
> and MPFS variants too?
>
> I meant to put the 'return 0;' in an #else
> That will leave the tail of the function with just one return
> statement, dependent on the CPP macro conditional.
> #if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
> uint32_t cpu_clock;
>
> cpu_clock = k210_get_frequency();
> return cpu_clock;
> #else
> return 0;
> #endif
>
> This will avoid having a dead code issue. The other blocks above don't
> need to be modified.
>
> I understand now. The 310ARTY or MPFS could fall through to the 'return
0', but the k210 code will always return leaving the extra 'return 0' as
dead code.
I'll send a v2 patch set. I also removed some whitespace warnings that
occur when you apply the patches.
In addition to a few whitespace warnings in the code I added, the
rtems-bin2c tool leaves a space at the end of each line in the array,
causing git to complain about the extra whitespace. If you think that
should be fixed we could put in a ticket for the tool. That could be an
easy contribution for a student.
Thanks,
Alan
> > Thanks,
> > Alan
> >
> >>
> >>
> >> >
> >> >> This code is unreachable if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0.
> >> >>
> >> >> > }
> >> >> >
> >> >> > @@ -215,6 +223,40 @@ uint32_t bsp_fdt_map_intr(const uint32_t
> *intr, size_t icells)
> >> >> >return RISCV_INTERRUPT_VECTOR_EXTERNAL(intr[0]);
> >> >> > }
> >> >> >
> >> >> > +#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
> >> >> > +uint32_t k210_get_frequency(void)
> >> >> > +{
> >> >> > + k210_sysctl_t *sysctl = (k210_sysctl_t *)K210_SYSCTL_BASE;
> >> >> > + uint32_t cpu_clock = 0;
> >> >> > + uint32_t clk_freq;
> >> >> > + uint32_t pll0, nr, nf, od;
> >> >> > + uint32_t node;
> >> >> > + const char *fdt;
> >> >> > + const fdt32_t *val;
> >> >> > + int len;
> >> >> > +
> >> >> > + fdt = bsp_fdt_get();
> >> >> > + node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
> >> >> > + val = fdt_getprop(fdt, node, "clock-frequency", );
> >> >> > + if (val != NULL && len == 4) {
> >> >> > +clk_freq = fdt32_to_cpu(*val);
> >> >> > +
> >> >> > +if (CLKSEL0_ACLK_SEL(sysctl->clk_sel0) == 1) {
> >> >> > + /* PLL0 selected */
> >> >> > + pll0 = sysctl->pll0;
> >> >> > + nr = PLL_CLK_R(pll0) + 1;
> >> >> > + nf = PLL_CLK_F(pll0) + 1;
> >> >> > + od = PLL_CLK_OD(pll0) + 1;
> >> >> > + cpu_clock = (clk_freq / nr * nf / od)/2;
> >> >> > +} else {
> >> >> > + /* OSC selected */
> >> >> > + cpu_clock = clk_freq;
> >> >> > +}
> >> >> > + }
> >> >> > + return cpu_clock;
> >> >> > +}
> >> >> > +#endif
> >> >> > +
> >> >> > void bsp_start(void)
> >> >> > {
> >> >> >riscv_find_harts();
> >> >> > --
> >> >> > 2.25.1
> >> >> >
> >> >> > ___
> >> >> > devel mailing list
> >> >> > devel@rtems.org
> >> >> > http://lists.rtems.org/mailman/listinfo/devel
>
___
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http://lists.rtems.org/mailman/listinfo/devel
[PATCH] doxygen: Document hash algorithm files
--- cpukit/doxygen/hash-algorithms.h | 149 +++ 1 file changed, 149 insertions(+) create mode 100644 cpukit/doxygen/hash-algorithms.h diff --git a/cpukit/doxygen/hash-algorithms.h b/cpukit/doxygen/hash-algorithms.h new file mode 100644 index 00..c920d7685e --- /dev/null +++ b/cpukit/doxygen/hash-algorithms.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSImplDoxygen + * + * @brief This header file contains Doxygen items related to hash algorithms. + */ + +/* + * Copyright (C) 2023 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup RTEMSAPIHashAlgorithms Hash Algorithms + * + * @ingroup RTEMSAPI + * + * @brief This group contains interfaces to hash algorithms. + */ + +/** + * @file cpukit/include/md4.h + * + * @ingroup RTEMSAPIHashAlgorithms + * + * @brief This header file contains interfaces of the HD4 hash algorithm + * support. + */ + +/** + * @file cpukit/include/md5.h + * + * @ingroup RTEMSAPIHashAlgorithms + * + * @brief This header file contains interfaces of the HD5 hash algorithm + * support. + */ + +/** + * @file cpukit/include/sha224.h + * + * @ingroup RTEMSAPIHashAlgorithms + * + * @brief This header file contains interfaces of the SHA224 hash algorithm + * support. + */ + +/** + * @file cpukit/include/sha256.h + * + * @ingroup RTEMSAPIHashAlgorithms + * + * @brief This header file contains interfaces of the SHA256 hash algorithm + * support. + */ + +/** + * @file cpukit/include/sha384.h + * + * @ingroup RTEMSAPIHashAlgorithms + * + * @brief This header file contains interfaces of the SHA384 hash algorithm + * support. + */ + +/** + * @file cpukit/include/sha512.h + * + * @ingroup RTEMSAPIHashAlgorithms + * + * @brief This header file contains interfaces of the SHA512 hash algorithm + * support. + */ + +/** + * @file cpukit/include/sha512t.h + * + * @ingroup RTEMSAPIHashAlgorithms + * + * @brief This header file contains interfaces of the trucated SHA512 hash + * algorithm support. + */ + + +/** + * @defgroup RTEMSImplHashAlgorithms Hash Algorithms + * + * @ingroup RTEMSImpl + * + * @brief This group contains items related to the implementation of hash + * algorithms. + */ + +/** + * @file cpukit/libmd/md4.c + * + * @ingroup RTEMSImplHashAlgorithms + * + * @brief This source file contains the implemention of the MD4 hash algorithm. + */ + +/** + * @file cpukit/libmd/md5.c + * + * @ingroup RTEMSImplHashAlgorithms + * + * @brief This source file contains the implemention of the MD5 hash algorithm. + */ + +/** + * @file cpukit/libmd/sha256c.c + * + * @ingroup RTEMSImplHashAlgorithms + * + * @brief This source file contains the implemention of the SHA256 hash + * algorithm and variants. + */ + +/** + * @file cpukit/libmd/sha512c.c + * + * @ingroup RTEMSImplHashAlgorithms + * + * @brief This source file contains the implemention of the SHA512 hash + * algorithm and variants. + */ -- 2.35.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 0/1] Fix a typo in the stm32h7 BSP Documentation
Thanks! Applied with a slightly modified commit message. Karel On 3/15/23 05:38, Ruturaj Nanoti wrote: Hi, I found a small typo while going through the BSP documentation for stm32h7 and fixed it in this commit. Thank You Ruturaj Nanoti (1): Fixed a typo in the /user/bsps/arm/stm32h7.rst file. user/bsps/arm/stm32h7.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] cpuuse: Add implementation Doxygen group
---
cpukit/libmisc/cpuuse/cpuusagedata.c | 2 +-
cpukit/libmisc/cpuuse/cpuusagereport.c | 2 +-
cpukit/libmisc/cpuuse/cpuusagereset.c | 2 +-
cpukit/libmisc/cpuuse/cpuusagetop.c| 2 +-
cpukit/libmisc/cpuuse/cpuuseimpl.h | 26 ++
5 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/cpukit/libmisc/cpuuse/cpuusagedata.c
b/cpukit/libmisc/cpuuse/cpuusagedata.c
index b28ba5c3ad..fa39a6d754 100644
--- a/cpukit/libmisc/cpuuse/cpuusagedata.c
+++ b/cpukit/libmisc/cpuuse/cpuusagedata.c
@@ -3,7 +3,7 @@
/**
* @file
*
- * @ingroup RTEMSAPICPUUsageReporting
+ * @ingroup RTEMSImplCPUUsageReporting
*
* @brief This source file contains the definition of
* ::CPU_usage_Uptime_at_last_reset.
diff --git a/cpukit/libmisc/cpuuse/cpuusagereport.c
b/cpukit/libmisc/cpuuse/cpuusagereport.c
index 69e9c78518..bdeee375e3 100644
--- a/cpukit/libmisc/cpuuse/cpuusagereport.c
+++ b/cpukit/libmisc/cpuuse/cpuusagereport.c
@@ -3,7 +3,7 @@
/**
* @file
*
- * @ingroup RTEMSAPICPUUsageReporting
+ * @ingroup RTEMSImplCPUUsageReporting
*
* @brief This source file contains the definition of
* rtems_cpu_usage_report() and rtems_cpu_usage_report_with_plugin().
diff --git a/cpukit/libmisc/cpuuse/cpuusagereset.c
b/cpukit/libmisc/cpuuse/cpuusagereset.c
index e8b76cd189..e56ab3cded 100644
--- a/cpukit/libmisc/cpuuse/cpuusagereset.c
+++ b/cpukit/libmisc/cpuuse/cpuusagereset.c
@@ -3,7 +3,7 @@
/**
* @file
*
- * @ingroup RTEMSAPICPUUsageReporting
+ * @ingroup RTEMSImplCPUUsageReporting
*
* @brief This source file contains the definition of
* rtems_cpu_usage_reset().
diff --git a/cpukit/libmisc/cpuuse/cpuusagetop.c
b/cpukit/libmisc/cpuuse/cpuusagetop.c
index 1ee3a5571c..eed89ad211 100644
--- a/cpukit/libmisc/cpuuse/cpuusagetop.c
+++ b/cpukit/libmisc/cpuuse/cpuusagetop.c
@@ -3,7 +3,7 @@
/**
* @file
*
- * @ingroup RTEMSAPICPUUsageReporting
+ * @ingroup RTEMSImplCPUUsageReporting
*
* @brief This source file contains the definition of
* rtems_cpu_usage_top() and rtems_cpu_usage_top_with_plugin().
diff --git a/cpukit/libmisc/cpuuse/cpuuseimpl.h
b/cpukit/libmisc/cpuuse/cpuuseimpl.h
index 1162d1e892..8c6c407b4b 100644
--- a/cpukit/libmisc/cpuuse/cpuuseimpl.h
+++ b/cpukit/libmisc/cpuuse/cpuuseimpl.h
@@ -1,5 +1,14 @@
/* SPDX-License-Identifier: BSD-2-Clause */
+/**
+ * @file
+ *
+ * @ingroup RTEMSImplCPUUsageReporting
+ *
+ * @brief This header file provides interfaces of the
+ * @ref RTEMSImplCPUUsageReporting implementation.
+ */
+
/*
* COPYRIGHT (c) 1989-2011.
* On-Line Applications Research Corporation (OAR).
@@ -35,8 +44,25 @@
extern "C" {
#endif
+/**
+ * @defgroup RTEMSImplCPUUsageReporting CPU Usage Reporting
+ *
+ * @ingroup RTEMSImpl
+ *
+ * @brief This group contains the implementation of
+ * @ref RTEMSAPICPUUsageReporting.
+ *
+ * @{
+ */
+
+/**
+ * @brief This object provides the uptime timestamp at the last CPU usage
+ * reset.
+ */
extern Timestamp_Control CPU_usage_Uptime_at_last_reset;
+/** @} */
+
#ifdef __cplusplus
}
#endif
--
2.35.3
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