[libbsd 6-freebsd-12] rtemsbsd/rc_conf: Fixed non-nullterminated string causing crashes
From: Aaron Nyholm
---
rtemsbsd/rtems/rtems-bsd-rc-conf.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/rtemsbsd/rtems/rtems-bsd-rc-conf.c
b/rtemsbsd/rtems/rtems-bsd-rc-conf.c
index d559c256..f4cc987b 100644
--- a/rtemsbsd/rtems/rtems-bsd-rc-conf.c
+++ b/rtemsbsd/rtems/rtems-bsd-rc-conf.c
@@ -869,7 +869,7 @@ rtems_bsd_run_rc_conf(const char* name, int timeout, bool
verbose)
if (r < 0)
return r;
- rc_conf = malloc(sb.st_size);
+ rc_conf = malloc(sb.st_size + 1);
if (rc_conf == NULL) {
errno = ENOMEM;
return -1;
@@ -892,6 +892,8 @@ rtems_bsd_run_rc_conf(const char* name, int timeout, bool
verbose)
fclose(file);
+ rc_conf[sb.st_size] = '\0';
+
r = rtems_bsd_run_rc_conf_script(name, rc_conf, timeout, verbose);
free(rc_conf);
--
2.25.1
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[libbsd master] rtemsbsd/rc_conf: Fixed non-nullterminated string causing crashes
From: Aaron Nyholm
---
rtemsbsd/rtems/rtems-bsd-rc-conf.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/rtemsbsd/rtems/rtems-bsd-rc-conf.c
b/rtemsbsd/rtems/rtems-bsd-rc-conf.c
index d559c256..f4cc987b 100644
--- a/rtemsbsd/rtems/rtems-bsd-rc-conf.c
+++ b/rtemsbsd/rtems/rtems-bsd-rc-conf.c
@@ -869,7 +869,7 @@ rtems_bsd_run_rc_conf(const char* name, int timeout, bool
verbose)
if (r < 0)
return r;
- rc_conf = malloc(sb.st_size);
+ rc_conf = malloc(sb.st_size + 1);
if (rc_conf == NULL) {
errno = ENOMEM;
return -1;
@@ -892,6 +892,8 @@ rtems_bsd_run_rc_conf(const char* name, int timeout, bool
verbose)
fclose(file);
+ rc_conf[sb.st_size] = '\0';
+
r = rtems_bsd_run_rc_conf_script(name, rc_conf, timeout, verbose);
free(rc_conf);
--
2.25.1
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Re: [PATCH 1/3] bsps/riscv: Make SMP start more robust
On 16/3/2023 5:59 pm, Sebastian Huber wrote:
> In SMP configurations, check that we run on a configured processor. If not,
> then there is not much what can be done since we do not have a stack available
not much that can be done ?
No comment on the actual patch as I do not know RISCV :)
Chris
> for this processor. Just loop forever in this case. Do this in assemlby to
> ensure that no stack memory is used.
> ---
> bsps/riscv/riscv/start/bspsmp.c | 5 +
> bsps/riscv/shared/start/start.S | 16 ++--
> 2 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/bsps/riscv/riscv/start/bspsmp.c b/bsps/riscv/riscv/start/bspsmp.c
> index 91f4f7b96a..ce5792f5b8 100644
> --- a/bsps/riscv/riscv/start/bspsmp.c
> +++ b/bsps/riscv/riscv/start/bspsmp.c
> @@ -36,10 +36,7 @@ void bsp_start_on_secondary_processor(Per_CPU_Control
> *cpu_self)
>
>cpu_index_self = _Per_CPU_Get_index(cpu_self);
>
> - if (
> -cpu_index_self < rtems_configuration_get_maximum_processors()
> - && _SMP_Should_start_processor(cpu_index_self)
> - ) {
> + if (_SMP_Should_start_processor(cpu_index_self)) {
> set_csr(mie, MIP_MSIP | MIP_MEIP);
> _SMP_Start_multitasking_on_secondary_processor(cpu_self);
>} else {
> diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S
> index 34e1839ca1..42e4348cd0 100644
> --- a/bsps/riscv/shared/start/start.S
> +++ b/bsps/riscv/shared/start/start.S
> @@ -66,8 +66,17 @@ SYM(_start):
> LADDR sp, _ISR_Stack_area_begin
> LADDR t2, _ISR_Stack_size
> csrrs0, mhartid
> - li t3, RISCV_BOOT_HARTID
> - sub s0, s0, t3
> + li t3, RISCV_BOOT_HARTID
> + sub s0, s0, t3
> +
> + /*
> + * Check that this is a configured processor. If not, then there is
> + * not much what can be done since we do not have a stack available for
> + * this processor. Just loop forever in this case.
> + */
> + LREGt3, _SMP_Processor_configured_maximum
> + bgeus0, t3, .Lwfi
> +
> LADDR t0, _Per_CPU_Information
> sllit1, s0, PER_CPU_CONTROL_SIZE_LOG2
> add s1, t0, t1
> @@ -100,6 +109,9 @@ SYM(_start):
> tailboot_card
>
> #ifdef RTEMS_SMP
> +.Lwfi:
> + wfi
> + j .Lwfi
>
> .Lstart_on_secondary_processor:
>
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Re: Flash Device API
On 16/3/2023 6:13 pm, Sebastian Huber wrote: > Hello Aaron, > > this API seems to be RTEMS-specific. Maybe we should simply pick up an > existing > solution which is in more wide spread use, for example: > > https://docs.zephyrproject.org/latest/hardware/peripherals/flash.html That interface seems Zepher specific and looks to me like a series of calls that appear reasonable as a list to cover. The patch Aaron has posted is a driver. I prefer a driver like we have for I2C, SPI etc because the of support it brings. The initial set of ioctl commands is small to start with. If you feel we should offer more I suggest they get added once this is merged. Is the change OK? Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 1/3] bsps/riscv: Make SMP start more robust
Hi Sebastian,
I applied these three patches after my patches and ran them on my K210
board and simulator. I have a set of 12 tests including benchmarks, SMP01,
SMP08, ticker, etc. Everything ran OK.
Is there anything in particular I can try to test them like setting the
maximum CPUs to 1? (K210 is a dual core)
Alan
On Thu, Mar 16, 2023 at 4:59 AM Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> In SMP configurations, check that we run on a configured processor. If
> not,
> then there is not much what can be done since we do not have a stack
> available
> for this processor. Just loop forever in this case. Do this in assemlby
> to
> ensure that no stack memory is used.
> ---
> bsps/riscv/riscv/start/bspsmp.c | 5 +
> bsps/riscv/shared/start/start.S | 16 ++--
> 2 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/bsps/riscv/riscv/start/bspsmp.c
> b/bsps/riscv/riscv/start/bspsmp.c
> index 91f4f7b96a..ce5792f5b8 100644
> --- a/bsps/riscv/riscv/start/bspsmp.c
> +++ b/bsps/riscv/riscv/start/bspsmp.c
> @@ -36,10 +36,7 @@ void bsp_start_on_secondary_processor(Per_CPU_Control
> *cpu_self)
>
>cpu_index_self = _Per_CPU_Get_index(cpu_self);
>
> - if (
> -cpu_index_self < rtems_configuration_get_maximum_processors()
> - && _SMP_Should_start_processor(cpu_index_self)
> - ) {
> + if (_SMP_Should_start_processor(cpu_index_self)) {
> set_csr(mie, MIP_MSIP | MIP_MEIP);
> _SMP_Start_multitasking_on_secondary_processor(cpu_self);
>} else {
> diff --git a/bsps/riscv/shared/start/start.S
> b/bsps/riscv/shared/start/start.S
> index 34e1839ca1..42e4348cd0 100644
> --- a/bsps/riscv/shared/start/start.S
> +++ b/bsps/riscv/shared/start/start.S
> @@ -66,8 +66,17 @@ SYM(_start):
> LADDR sp, _ISR_Stack_area_begin
> LADDR t2, _ISR_Stack_size
> csrrs0, mhartid
> - li t3, RISCV_BOOT_HARTID
> - sub s0, s0, t3
> + li t3, RISCV_BOOT_HARTID
> + sub s0, s0, t3
> +
> + /*
> +* Check that this is a configured processor. If not, then there
> is
> +* not much what can be done since we do not have a stack
> available for
> +* this processor. Just loop forever in this case.
> +*/
> + LREGt3, _SMP_Processor_configured_maximum
> + bgeus0, t3, .Lwfi
> +
> LADDR t0, _Per_CPU_Information
> sllit1, s0, PER_CPU_CONTROL_SIZE_LOG2
> add s1, t0, t1
> @@ -100,6 +109,9 @@ SYM(_start):
> tailboot_card
>
> #ifdef RTEMS_SMP
> +.Lwfi:
> + wfi
> + j .Lwfi
>
> .Lstart_on_secondary_processor:
>
> --
> 2.35.3
>
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[PATCH] bsps/xqspipsu: Add support for reading ECC
This adds a helper function to read the ECC status for an ECC unit in
SPI-attached NOR memory.
---
bsps/include/dev/spi/xqspipsu-flash-helper.h | 29 +++
bsps/include/dev/spi/xqspipsu_flash_config.h | 1 +
bsps/shared/dev/spi/xqspipsu-flash-helper.c | 223 +++
3 files changed, 253 insertions(+)
diff --git a/bsps/include/dev/spi/xqspipsu-flash-helper.h
b/bsps/include/dev/spi/xqspipsu-flash-helper.h
index 075f7f826d..22f85f156c 100644
--- a/bsps/include/dev/spi/xqspipsu-flash-helper.h
+++ b/bsps/include/dev/spi/xqspipsu-flash-helper.h
@@ -79,3 +79,32 @@ int QspiPsu_NOR_Read(
u32 ByteCount,
u8 **ReadBfrPtr
);
+
+/*/
+/**
+ *
+ * This function performs a read of the ECC Status Register for a given
address.
+ *
+ * @param QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
+ * @param Address contains the address of the ECC unit for which the ECCSR
+ * needs to be read. The ECC unit contains 16 bytes of user data
+ * and all bytes in an ECC unit will return the same ECCSR.
+ * @param ReadBfrPtr is a pointer to a single byte to which the ECCSR will
+ * be written.
+ *
+ * @return XST_SUCCESS if successful, else XST_FAILURE.
+ *
+ * @note Only the three least significant bits of the returned byte are
+ * meaningful. If all bits are 0, ECC is enabled for this unit and
+ * no errors have been encountered.
+ * Bit 0 is 1: ECC is disabled for the requested unit.
+ * Bit 1 is 1: A single bit error has been corrected in user data.
+ * Bit 2 is 1: A single bit error has been found in the ECC data
+ * and may indicate user data corruption.
+ *
+
**/
+int QspiPsu_NOR_Read_Ecc(
+ XQspiPsu *QspiPsuPtr,
+ u32 Address,
+ u8 *ReadBfrPtr
+);
diff --git a/bsps/include/dev/spi/xqspipsu_flash_config.h
b/bsps/include/dev/spi/xqspipsu_flash_config.h
index 323b223ee3..8ef89f85ff 100644
--- a/bsps/include/dev/spi/xqspipsu_flash_config.h
+++ b/bsps/include/dev/spi/xqspipsu_flash_config.h
@@ -79,6 +79,7 @@ extern "C" {
#define BANK_REG_RD0x16
#define BANK_REG_WR0x17
+#define READ_ECCSR 0x18
/* Bank register is called Extended Address Register in Micron */
#define EXTADD_REG_RD 0xC8
#define EXTADD_REG_WR 0xC5
diff --git a/bsps/shared/dev/spi/xqspipsu-flash-helper.c
b/bsps/shared/dev/spi/xqspipsu-flash-helper.c
index 7fa04efdde..43dc700507 100644
--- a/bsps/shared/dev/spi/xqspipsu-flash-helper.c
+++ b/bsps/shared/dev/spi/xqspipsu-flash-helper.c
@@ -2003,3 +2003,226 @@ static int FlashEnableQuadMode(XQspiPsu *QspiPsuPtr)
return Status;
}
+
+static int MultiDieReadEcc(
+ XQspiPsu *QspiPsuPtr,
+ u32 Address,
+ u32 ByteCount,
+ u8 *WriteBfrPtr,
+ u8 *ReadBfrPtr
+);
+
+int QspiPsu_NOR_Read_Ecc(
+ XQspiPsu *QspiPsuPtr,
+ u32 Address,
+ u8 *ReadBfrPtr
+)
+{
+ u32 RealAddr;
+ u32 DiscardByteCnt;
+ u32 FlashMsgCnt;
+ u8 EccBuffer[16];
+ int ByteCount = sizeof(EccBuffer);
+ int Status;
+
+ /* Check die boundary conditions if required for any flash */
+ if (Flash_Config_Table[FCTIndex].NumDie > 1) {
+
+Status = MultiDieReadEcc(QspiPsuPtr, Address, ByteCount,
+ CmdBfr, EccBuffer);
+if (Status == XST_SUCCESS) {
+ /* All bytes are the same, so copy one return byte into the output
buffer */
+ *ReadBfrPtr = EccBuffer[0];
+}
+return Status;
+ }
+
+ /* For Dual Stacked, split and read for boundary crossing */
+ /*
+ * Translate address based on type of connection
+ * If stacked assert the slave select based on address
+ */
+ RealAddr = GetRealAddr(QspiPsuPtr, Address);
+
+ CmdBfr[COMMAND_OFFSET] = READ_ECCSR;
+ CmdBfr[ADDRESS_1_OFFSET] =
+ (u8)((RealAddr & 0xFF00) >> 24);
+ CmdBfr[ADDRESS_2_OFFSET] =
+ (u8)((RealAddr & 0xFF) >> 16);
+ CmdBfr[ADDRESS_3_OFFSET] =
+ (u8)((RealAddr & 0xFF00) >> 8);
+ CmdBfr[ADDRESS_4_OFFSET] =
+ (u8)(RealAddr & 0xF0);
+ DiscardByteCnt = 5;
+
+ FlashMsgCnt = 0;
+
+ FlashMsg[FlashMsgCnt].TxBfrPtr = CmdBfr;
+ FlashMsg[FlashMsgCnt].RxBfrPtr = NULL;
+ FlashMsg[FlashMsgCnt].ByteCount = DiscardByteCnt;
+ FlashMsg[FlashMsgCnt].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
+ FlashMsg[FlashMsgCnt].Flags = XQSPIPSU_MSG_FLAG_TX;
+
+ FlashMsgCnt++;
+
+ FlashMsg[FlashMsgCnt].TxBfrPtr = NULL;
+ FlashMsg[FlashMsgCnt].RxBfrPtr = NULL;
+ FlashMsg[FlashMsgCnt].ByteCount = DUMMY_CLOCKS;
+ FlashMsg[FlashMsgCnt].Flags = 0;
+
+ FlashMsgCnt++;
+
+ FlashMsg[FlashMsgCnt].TxBfrPtr = NULL;
+ FlashMsg[FlashMsgCnt].RxBfrPtr = EccBuffer;
+ FlashMsg[FlashMsgCnt].ByteCount = ByteCount;
+ FlashMsg[FlashMsgCnt].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
+ FlashMsg[FlashMsgCnt].Flags = XQSPIPSU_MSG_FLAG_RX;
+
+ if (QspiPsuPtr->Config.ConnectionMode ==
+
Re: [PATCH 1/2] spec: add MPU CTRL option to be usable on ARMV7M based BSPs
On 3/16/23 14:34, Sebastian Huber wrote: On 16.03.23 14:28, Karel Gardas wrote: +description: | + Default value of the ARM MPU CTRL register +default: +- enabled-by: + - arm/imxrt1052 + - arm/stm32h7 + - arm/nucleo-h743zi + - arm/stm32h7b3i-dk + - arm/stm32h747i-disco + - arm/stm32h757i-eval + value: (ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA) +- enabled-by: true + value: ARMV7M_MPU_CTRL_ENABLE The patch set looks good, but please make the current value (ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA) the default value. Done. I also fixed imxrt by moving mpu opt before bspopts in order to get define generated into the bspopts.h. Thanks for the review and suggestion on this! Karel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 1/2] spec: add MPU CTRL option to be usable on ARMV7M based BSPs
On 16.03.23 14:28, Karel Gardas wrote: +description: | + Default value of the ARM MPU CTRL register +default: +- enabled-by: + - arm/imxrt1052 + - arm/stm32h7 + - arm/nucleo-h743zi + - arm/stm32h7b3i-dk + - arm/stm32h747i-disco + - arm/stm32h757i-eval + value: (ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA) +- enabled-by: true + value: ARMV7M_MPU_CTRL_ENABLE The patch set looks good, but please make the current value (ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA) the default value. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 2/2] score/arm: enhance ARMV7M MPU setup with capability to set control register
Due to API change, the patch also fixes affected BSPs and uses value provided by MPU CTRL spec option there. Sponsored-By: Precidata --- bsps/arm/imxrt/start/bspstarthooks.c | 2 +- .../stm32h7/boards/stm/nucleo-h743zi/stm32h7-bspstarthooks.c | 2 +- .../stm32h7/boards/stm/stm32h743i-eval/stm32h7-bspstarthooks.c | 2 +- .../boards/stm/stm32h747i-disco/stm32h7-bspstarthooks.c| 2 +- .../stm32h7/boards/stm/stm32h757i-eval/stm32h7-bspstarthooks.c | 2 +- .../stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-bspstarthooks.c | 2 +- cpukit/score/cpu/arm/include/rtems/score/armv7m.h | 3 ++- 7 files changed, 8 insertions(+), 7 deletions(-) diff --git a/bsps/arm/imxrt/start/bspstarthooks.c b/bsps/arm/imxrt/start/bspstarthooks.c index 684c263152..482300a1bc 100644 --- a/bsps/arm/imxrt/start/bspstarthooks.c +++ b/bsps/arm/imxrt/start/bspstarthooks.c @@ -46,7 +46,7 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void) SCB_EnableDCache(); } - _ARMV7M_MPU_Setup(imxrt_config_mpu_region, imxrt_config_mpu_region_count); + _ARMV7M_MPU_Setup(ARMV7M_MPU_CTRL_DEFAULT, imxrt_config_mpu_region, imxrt_config_mpu_region_count); } BSP_START_TEXT_SECTION void bsp_start_hook_1(void) diff --git a/bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-bspstarthooks.c b/bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-bspstarthooks.c index eda503925f..636a124d64 100644 --- a/bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-bspstarthooks.c +++ b/bsps/arm/stm32h7/boards/stm/nucleo-h743zi/stm32h7-bspstarthooks.c @@ -62,7 +62,7 @@ void bsp_start_hook_0(void) SCB_EnableDCache(); } - _ARMV7M_MPU_Setup(stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); + _ARMV7M_MPU_Setup(ARMV7M_MPU_CTRL_DEFAULT, stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); #endif } diff --git a/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-bspstarthooks.c b/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-bspstarthooks.c index 8d34e357ee..0a25253215 100644 --- a/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-bspstarthooks.c +++ b/bsps/arm/stm32h7/boards/stm/stm32h743i-eval/stm32h7-bspstarthooks.c @@ -63,7 +63,7 @@ void bsp_start_hook_0(void) SCB_EnableDCache(); } - _ARMV7M_MPU_Setup(stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); + _ARMV7M_MPU_Setup(ARMV7M_MPU_CTRL_DEFAULT, stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); #endif } diff --git a/bsps/arm/stm32h7/boards/stm/stm32h747i-disco/stm32h7-bspstarthooks.c b/bsps/arm/stm32h7/boards/stm/stm32h747i-disco/stm32h7-bspstarthooks.c index 8d34e357ee..0a25253215 100644 --- a/bsps/arm/stm32h7/boards/stm/stm32h747i-disco/stm32h7-bspstarthooks.c +++ b/bsps/arm/stm32h7/boards/stm/stm32h747i-disco/stm32h7-bspstarthooks.c @@ -63,7 +63,7 @@ void bsp_start_hook_0(void) SCB_EnableDCache(); } - _ARMV7M_MPU_Setup(stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); + _ARMV7M_MPU_Setup(ARMV7M_MPU_CTRL_DEFAULT, stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); #endif } diff --git a/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-bspstarthooks.c b/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-bspstarthooks.c index 1bb81e3b60..1fa8563477 100644 --- a/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-bspstarthooks.c +++ b/bsps/arm/stm32h7/boards/stm/stm32h757i-eval/stm32h7-bspstarthooks.c @@ -79,7 +79,7 @@ void bsp_start_hook_0(void) SCB_EnableDCache(); } - _ARMV7M_MPU_Setup(stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); + _ARMV7M_MPU_Setup(ARMV7M_MPU_CTRL_DEFAULT, stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); #endif } diff --git a/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-bspstarthooks.c b/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-bspstarthooks.c index 8d34e357ee..0a25253215 100644 --- a/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-bspstarthooks.c +++ b/bsps/arm/stm32h7/boards/stm/stm32h7b3i-dk/stm32h7-bspstarthooks.c @@ -63,7 +63,7 @@ void bsp_start_hook_0(void) SCB_EnableDCache(); } - _ARMV7M_MPU_Setup(stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); + _ARMV7M_MPU_Setup(ARMV7M_MPU_CTRL_DEFAULT, stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); #endif } diff --git a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h index 10b3955671..2b1e785cf7 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h +++ b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h @@ -691,6 +691,7 @@ static inline void _ARMV7M_MPU_Disable_region( } static inline void _ARMV7M_MPU_Setup( + uint32_t ctrl, const ARMV7M_MPU_Region_config *cfg, size_t cfg_count ) @@ -726,7 +727,7 @@ static inline void _ARMV7M_MPU_Setup( _ARMV7M_MPU_Disable_region(mpu, region); } - mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA; + mpu->ctrl = ctrl; scb->shcsr |= ARMV
[PATCH 1/2] spec: add MPU CTRL option to be usable on ARMV7M based BSPs
The patch also enables usage of the option on imxrt and stm32h7 based BSPs.
Sponsored-By: Precidata
---
spec/build/bsps/arm/imxrt/bspimxrt.yml | 2 ++
spec/build/bsps/arm/optmpuctrl.yml | 25 +
spec/build/bsps/arm/stm32h7/grp.yml| 2 ++
3 files changed, 29 insertions(+)
create mode 100644 spec/build/bsps/arm/optmpuctrl.yml
diff --git a/spec/build/bsps/arm/imxrt/bspimxrt.yml
b/spec/build/bsps/arm/imxrt/bspimxrt.yml
index b666be5241..e05ceeccd9 100644
--- a/spec/build/bsps/arm/imxrt/bspimxrt.yml
+++ b/spec/build/bsps/arm/imxrt/bspimxrt.yml
@@ -165,6 +165,8 @@ links:
uid: linkcmdsmemory
- role: build-dependency
uid: ../../bspopts
+- role: build-dependency
+ uid: ../optmpuctrl
source:
- bsps/arm/imxrt/console/console.c
- bsps/arm/imxrt/dts/imxrt1050-evkb.c
diff --git a/spec/build/bsps/arm/optmpuctrl.yml
b/spec/build/bsps/arm/optmpuctrl.yml
new file mode 100644
index 00..96f68968a6
--- /dev/null
+++ b/spec/build/bsps/arm/optmpuctrl.yml
@@ -0,0 +1,25 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-string: null
+- define-unquoted: null
+build-type: option
+copyrights:
+- Copyright (C) 2023 Karel Gardas
+description: |
+ Default value of the ARM MPU CTRL register
+default:
+- enabled-by:
+ - arm/imxrt1052
+ - arm/stm32h7
+ - arm/nucleo-h743zi
+ - arm/stm32h7b3i-dk
+ - arm/stm32h747i-disco
+ - arm/stm32h757i-eval
+ value: (ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA)
+- enabled-by: true
+ value: ARMV7M_MPU_CTRL_ENABLE
+enabled-by: true
+format: '{}'
+links: []
+name: ARMV7M_MPU_CTRL_DEFAULT
+type: build
diff --git a/spec/build/bsps/arm/stm32h7/grp.yml
b/spec/build/bsps/arm/stm32h7/grp.yml
index 9735b6734c..c415a7a71d 100644
--- a/spec/build/bsps/arm/stm32h7/grp.yml
+++ b/spec/build/bsps/arm/stm32h7/grp.yml
@@ -24,6 +24,8 @@ links:
uid: ../../objmem
- role: build-dependency
uid: optenmpualign
+- role: build-dependency
+ uid: ../optmpuctrl
- role: build-dependency
uid: optenuart4
- role: build-dependency
--
2.25.1
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[PATCH] doxygen: Add group for FreeBSD kernel header files
--- cpukit/doxygen/top-level-groups.h | 9 + cpukit/include/machine/_kernel_cpuset.h | 2 ++ cpukit/include/machine/_kernel_in.h | 2 ++ cpukit/include/machine/_kernel_in6.h| 2 ++ cpukit/include/machine/_kernel_mman.h | 2 ++ cpukit/include/machine/_kernel_param.h | 2 ++ cpukit/include/machine/_kernel_time.h | 2 ++ cpukit/include/machine/_kernel_types.h | 2 ++ cpukit/include/machine/_kernel_uio.h| 2 ++ 9 files changed, 25 insertions(+) diff --git a/cpukit/doxygen/top-level-groups.h b/cpukit/doxygen/top-level-groups.h index 77463f2466..095d9aaf34 100644 --- a/cpukit/doxygen/top-level-groups.h +++ b/cpukit/doxygen/top-level-groups.h @@ -58,6 +58,15 @@ * @ingroup RTEMSImpl */ +/** + * @defgroup RTEMSImplFreeBSDKernel FreeBSD Kernel Space Support + * + * @ingroup RTEMSImpl + * + * @brief This group contains the interfaces used by FreeBSD kernel space + * components ported to RTEMS. + */ + /** * @defgroup RTEMSTestSuites Test Suites * diff --git a/cpukit/include/machine/_kernel_cpuset.h b/cpukit/include/machine/_kernel_cpuset.h index 19c1a3e504..e005792b81 100644 --- a/cpukit/include/machine/_kernel_cpuset.h +++ b/cpukit/include/machine/_kernel_cpuset.h @@ -3,6 +3,8 @@ /** * @file * + * @ingroup RTEMSImplFreeBSDKernel + * * @brief This header file provides CPU set definitions for the kernel space * (_KERNEL is defined before including ). */ diff --git a/cpukit/include/machine/_kernel_in.h b/cpukit/include/machine/_kernel_in.h index 78492453cd..1c7ad25565 100644 --- a/cpukit/include/machine/_kernel_in.h +++ b/cpukit/include/machine/_kernel_in.h @@ -35,6 +35,8 @@ /** * @file * + * @ingroup RTEMSImplFreeBSDKernel + * * @brief This header file provides IPv4 definitions for the kernel space * (_KERNEL is defined before including ). */ diff --git a/cpukit/include/machine/_kernel_in6.h b/cpukit/include/machine/_kernel_in6.h index 857b51548d..e198e5d37a 100644 --- a/cpukit/include/machine/_kernel_in6.h +++ b/cpukit/include/machine/_kernel_in6.h @@ -34,6 +34,8 @@ /** * @file * + * @ingroup RTEMSImplFreeBSDKernel + * * @brief This header file provides IPv6 definitions for the kernel space * (_KERNEL is defined before including ). */ diff --git a/cpukit/include/machine/_kernel_mman.h b/cpukit/include/machine/_kernel_mman.h index fa2677a122..57a0482d65 100644 --- a/cpukit/include/machine/_kernel_mman.h +++ b/cpukit/include/machine/_kernel_mman.h @@ -3,6 +3,8 @@ /** * @file * + * @ingroup RTEMSImplFreeBSDKernel + * * @brief This header file provides memory map definitions for the kernel space * (_KERNEL is defined before including ). */ diff --git a/cpukit/include/machine/_kernel_param.h b/cpukit/include/machine/_kernel_param.h index 1235d7b324..5100382ef5 100644 --- a/cpukit/include/machine/_kernel_param.h +++ b/cpukit/include/machine/_kernel_param.h @@ -3,6 +3,8 @@ /** * @file * + * @ingroup RTEMSImplFreeBSDKernel + * * @brief This header file provides parameter definitions for the kernel space * (_KERNEL is defined before including ). */ diff --git a/cpukit/include/machine/_kernel_time.h b/cpukit/include/machine/_kernel_time.h index c65355d006..91df51b69a 100644 --- a/cpukit/include/machine/_kernel_time.h +++ b/cpukit/include/machine/_kernel_time.h @@ -37,6 +37,8 @@ /** * @file * + * @ingroup RTEMSImplFreeBSDKernel + * * @brief This header file provides time definitions for the kernel space * (_KERNEL is defined before including ). */ diff --git a/cpukit/include/machine/_kernel_types.h b/cpukit/include/machine/_kernel_types.h index 7f70964e2d..b9f576255c 100644 --- a/cpukit/include/machine/_kernel_types.h +++ b/cpukit/include/machine/_kernel_types.h @@ -3,6 +3,8 @@ /** * @file * + * @ingroup RTEMSImplFreeBSDKernel + * * @brief This header file provides type definitions for the kernel space * (_KERNEL is defined before including ). */ diff --git a/cpukit/include/machine/_kernel_uio.h b/cpukit/include/machine/_kernel_uio.h index c9454e97ca..8e368770f1 100644 --- a/cpukit/include/machine/_kernel_uio.h +++ b/cpukit/include/machine/_kernel_uio.h @@ -35,6 +35,8 @@ /** * @file * + * @ingroup RTEMSImplFreeBSDKernel + * * @brief This header file provides device driver I/O definitions for the * kernel space (_KERNEL is defined before including ). */ -- 2.35.3 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] score/arm: make MPU setup more generic
On 16.03.23 10:37, Karel Gardas wrote: On 3/16/23 10:19, Sebastian Huber wrote: On 16.03.23 10:14, Karel Gardas wrote: This patch makes MPU setup more generic by adding capability to set also control register. This way BSPs are allowed to enable MPU also for hard faults by simply not setting PRIVDEFENA attribute to control register. Compatibility with previous behavior and API is preserved. Is this really a BSP-specific choice or more a user option which should be controlled by a BSP option (through config.ini)? config.ini would be even more generic and probably more elegant too. However for upstreaming I took a more conservative approach to have a chance. Let me ask what do you prefer and what will you support? I'm happy to write that as long as it is reasonable simple and makes chance to upstream higher. My goal is simple: I'm working on BSP for Precidata SL-3011 board. The board is using STM32H747. Board firmware responsible for hardware management runs on CM4 while RTEMS and app code will run on CM7 and will be using firmware services by calling some API. For communication between both domains we use SRAM4. To be able to print hard fault from RTEMS on CM7 I need either: - keep cache disabled for SRAM4 region even for hard fault (hence MPU change proposed) or - disable cache in print exception frame directly which involves quite a bit of hacking around and looks to be more source code invasive than MPU change. I would add the ctrl parameter to _ARMV7M_MPU_Setup() and add a ARMV7M_MPU_CTRL_DEFAULT (default value ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA) BSP option for all Cortex-M BSPs. -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] score/arm: make MPU setup more generic
On 3/16/23 10:19, Sebastian Huber wrote: On 16.03.23 10:14, Karel Gardas wrote: This patch makes MPU setup more generic by adding capability to set also control register. This way BSPs are allowed to enable MPU also for hard faults by simply not setting PRIVDEFENA attribute to control register. Compatibility with previous behavior and API is preserved. Is this really a BSP-specific choice or more a user option which should be controlled by a BSP option (through config.ini)? config.ini would be even more generic and probably more elegant too. However for upstreaming I took a more conservative approach to have a chance. Let me ask what do you prefer and what will you support? I'm happy to write that as long as it is reasonable simple and makes chance to upstream higher. My goal is simple: I'm working on BSP for Precidata SL-3011 board. The board is using STM32H747. Board firmware responsible for hardware management runs on CM4 while RTEMS and app code will run on CM7 and will be using firmware services by calling some API. For communication between both domains we use SRAM4. To be able to print hard fault from RTEMS on CM7 I need either: - keep cache disabled for SRAM4 region even for hard fault (hence MPU change proposed) or - disable cache in print exception frame directly which involves quite a bit of hacking around and looks to be more source code invasive than MPU change. Thanks! Karel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH] score/arm: make MPU setup more generic
On 16.03.23 10:14, Karel Gardas wrote: This patch makes MPU setup more generic by adding capability to set also control register. This way BSPs are allowed to enable MPU also for hard faults by simply not setting PRIVDEFENA attribute to control register. Compatibility with previous behavior and API is preserved. Is this really a BSP-specific choice or more a user option which should be controlled by a BSP option (through config.ini)? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] score/arm: make MPU setup more generic
This patch makes MPU setup more generic by adding capability to set
also control register. This way BSPs are allowed to enable MPU
also for hard faults by simply not setting PRIVDEFENA attribute
to control register. Compatibility with previous behavior and API
is preserved.
Sponsored-By: Precidata
---
cpukit/score/cpu/arm/include/rtems/score/armv7m.h | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
index 744dca26d3..cfd676cce7 100644
--- a/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
+++ b/cpukit/score/cpu/arm/include/rtems/score/armv7m.h
@@ -701,7 +701,8 @@ static inline void _ARMV7M_MPU_Disable_region(
mpu->rasr = 0;
}
-static inline void _ARMV7M_MPU_Setup(
+static inline void _ARMV7M_MPU_Setup_with_ctrl(
+ uint32_t ctrl,
const ARMV7M_MPU_Region_config *cfg,
size_t cfg_count
)
@@ -737,13 +738,21 @@ static inline void _ARMV7M_MPU_Setup(
_ARMV7M_MPU_Disable_region(mpu, region);
}
- mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE | ARMV7M_MPU_CTRL_PRIVDEFENA;
+ mpu->ctrl = ctrl;
scb->shcsr |= ARMV7M_SCB_SHCSR_MEMFAULTENA;
_ARM_Data_synchronization_barrier();
_ARM_Instruction_synchronization_barrier();
}
+static inline void _ARMV7M_MPU_Setup(
+ const ARMV7M_MPU_Region_config *cfg,
+ size_t cfg_count
+)
+{
+ _ARMV7M_MPU_Setup_with_ctrl(ARMV7M_MPU_CTRL_ENABLE |
ARMV7M_MPU_CTRL_PRIVDEFENA, cfg, cfg_count);
+}
+
#endif /* ASM */
#endif /* ARM_MULTILIB_ARCH_V7M */
--
2.25.1
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Re: Flash Device API
Hello Aaron, this API seems to be RTEMS-specific. Maybe we should simply pick up an existing solution which is in more wide spread use, for example: https://docs.zephyrproject.org/latest/hardware/peripherals/flash.html -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/ ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 1/3] bsps/riscv: Make SMP start more robust
In SMP configurations, check that we run on a configured processor. If not,
then there is not much what can be done since we do not have a stack available
for this processor. Just loop forever in this case. Do this in assemlby to
ensure that no stack memory is used.
---
bsps/riscv/riscv/start/bspsmp.c | 5 +
bsps/riscv/shared/start/start.S | 16 ++--
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/bsps/riscv/riscv/start/bspsmp.c b/bsps/riscv/riscv/start/bspsmp.c
index 91f4f7b96a..ce5792f5b8 100644
--- a/bsps/riscv/riscv/start/bspsmp.c
+++ b/bsps/riscv/riscv/start/bspsmp.c
@@ -36,10 +36,7 @@ void bsp_start_on_secondary_processor(Per_CPU_Control
*cpu_self)
cpu_index_self = _Per_CPU_Get_index(cpu_self);
- if (
-cpu_index_self < rtems_configuration_get_maximum_processors()
- && _SMP_Should_start_processor(cpu_index_self)
- ) {
+ if (_SMP_Should_start_processor(cpu_index_self)) {
set_csr(mie, MIP_MSIP | MIP_MEIP);
_SMP_Start_multitasking_on_secondary_processor(cpu_self);
} else {
diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S
index 34e1839ca1..42e4348cd0 100644
--- a/bsps/riscv/shared/start/start.S
+++ b/bsps/riscv/shared/start/start.S
@@ -66,8 +66,17 @@ SYM(_start):
LADDR sp, _ISR_Stack_area_begin
LADDR t2, _ISR_Stack_size
csrrs0, mhartid
- li t3, RISCV_BOOT_HARTID
- sub s0, s0, t3
+ li t3, RISCV_BOOT_HARTID
+ sub s0, s0, t3
+
+ /*
+* Check that this is a configured processor. If not, then there is
+* not much what can be done since we do not have a stack available for
+* this processor. Just loop forever in this case.
+*/
+ LREGt3, _SMP_Processor_configured_maximum
+ bgeus0, t3, .Lwfi
+
LADDR t0, _Per_CPU_Information
sllit1, s0, PER_CPU_CONTROL_SIZE_LOG2
add s1, t0, t1
@@ -100,6 +109,9 @@ SYM(_start):
tailboot_card
#ifdef RTEMS_SMP
+.Lwfi:
+ wfi
+ j .Lwfi
.Lstart_on_secondary_processor:
--
2.35.3
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[PATCH 3/3] bsps/riscv: Use per-CPU mtimecmp in clock driver
Use the mtimecmp from the PLIC/CLINT initialization in the clock driver. This
register is defined by the device tree and does not assume a fixed mapping.
---
bsps/riscv/riscv/clock/clockdrv.c | 41 +++
1 file changed, 15 insertions(+), 26 deletions(-)
diff --git a/bsps/riscv/riscv/clock/clockdrv.c
b/bsps/riscv/riscv/clock/clockdrv.c
index 28222c69db..6d70419a5c 100644
--- a/bsps/riscv/riscv/clock/clockdrv.c
+++ b/bsps/riscv/riscv/clock/clockdrv.c
@@ -8,7 +8,7 @@
*/
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018, 2023 embedded brains GmbH
* COPYRIGHT (c) 2015 Hesham Alatary
*
* Redistribution and use in source and binary forms, with or without
@@ -41,6 +41,7 @@
#include
#include
#include
+#include
#include
#include
@@ -92,18 +93,16 @@ static uint64_t riscv_clock_read_mtime(volatile
RISCV_CLINT_timer_reg *mtime)
static void riscv_clock_at_tick(riscv_timecounter *tc)
{
- volatile RISCV_CLINT_regs *clint;
+ Per_CPU_Control *cpu_self;
+ volatile RISCV_CLINT_timer_reg *mtimecmp;
uint64_t value;
- uint32_t cpu = rtems_scheduler_get_processor();
-
- cpu = _RISCV_Map_cpu_index_to_hardid(cpu);
-
- clint = tc->clint;
- value = clint->mtimecmp[cpu].val_64;
+ cpu_self = _Per_CPU_Get();
+ mtimecmp = cpu_self->cpu_per_cpu.clint_mtimecmp;
+ value = mtimecmp->val_64;
value += tc->interval;
- riscv_clock_write_mtimecmp(&clint->mtimecmp[cpu], value);
+ riscv_clock_write_mtimecmp(mtimecmp, value);
}
static void riscv_clock_handler_install(void)
@@ -153,16 +152,12 @@ static uint32_t riscv_clock_get_timebase_frequency(const
void *fdt)
return fdt32_to_cpu(*val);
}
-static void riscv_clock_clint_init(
- volatile RISCV_CLINT_regs *clint,
- uint64_t cmpval,
- uint32_t cpu
-)
+static void riscv_clock_clint_init(uint64_t cmpval)
{
- riscv_clock_write_mtimecmp(
-&clint->mtimecmp[cpu],
- cmpval
- );
+ Per_CPU_Control *cpu_self;
+
+ cpu_self = _Per_CPU_Get();
+ riscv_clock_write_mtimecmp(cpu_self->cpu_per_cpu.clint_mtimecmp, cmpval);
/* Enable mtimer interrupts */
set_csr(mie, MIP_MTIP);
@@ -171,13 +166,7 @@ static void riscv_clock_clint_init(
#if defined(RTEMS_SMP) && !defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR)
static void riscv_clock_secondary_action(void *arg)
{
- volatile RISCV_CLINT_regs *clint = riscv_clint;
- uint64_t *cmpval = arg;
- uint32_t cpu = _CPU_SMP_Get_current_processor();
-
- cpu = _RISCV_Map_cpu_index_to_hardid(cpu);
-
- riscv_clock_clint_init(clint, *cmpval, cpu);
+ riscv_clock_clint_init(*(uint64_t *) arg);
}
#endif
@@ -219,7 +208,7 @@ static void riscv_clock_initialize(void)
cmpval = riscv_clock_read_mtime(&clint->mtime);
cmpval += interval;
- riscv_clock_clint_init(clint, cmpval, RISCV_BOOT_HARTID);
+ riscv_clock_clint_init(cmpval);
riscv_clock_secondary_initialization(clint, cmpval, interval);
/* Initialize timecounter */
--
2.35.3
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[PATCH 2/3] bsps/riscv: Fix riscv_get_hart_index_by_phandle()
Take a non-zero RISCV_BOOT_HARTID into account.
---
bsps/riscv/riscv/start/bspsmp.c | 2 +-
bsps/riscv/riscv/start/bspstart.c | 10 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/bsps/riscv/riscv/start/bspsmp.c b/bsps/riscv/riscv/start/bspsmp.c
index ce5792f5b8..34796a5120 100644
--- a/bsps/riscv/riscv/start/bspsmp.c
+++ b/bsps/riscv/riscv/start/bspsmp.c
@@ -46,7 +46,7 @@ void bsp_start_on_secondary_processor(Per_CPU_Control
*cpu_self)
uint32_t _CPU_SMP_Initialize(void)
{
- return riscv_hart_count - RISCV_BOOT_HARTID;
+ return riscv_hart_count;
}
bool _CPU_SMP_Start_processor(uint32_t cpu_index)
diff --git a/bsps/riscv/riscv/start/bspstart.c
b/bsps/riscv/riscv/start/bspstart.c
index 30d479ce88..f27713b5bf 100644
--- a/bsps/riscv/riscv/start/bspstart.c
+++ b/bsps/riscv/riscv/start/bspstart.c
@@ -111,6 +111,14 @@ static void riscv_find_harts(void)
hart_index = fdt32_to_cpu(val[0]);
+#if RISCV_BOOT_HARTID != 0
+if (hart_index < RISCV_BOOT_HARTID) {
+ continue;
+}
+
+hart_index -= RISCV_BOOT_HARTID;
+#endif
+
if (hart_index >= RTEMS_ARRAY_SIZE(riscv_hart_phandles)) {
continue;
}
@@ -166,7 +174,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle)
for (hart_index = 0; hart_index < riscv_hart_count; ++hart_index) {
if (riscv_hart_phandles[hart_index] == phandle) {
- return hart_index;
+ return hart_index + RISCV_BOOT_HARTID;
}
}
--
2.35.3
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