Re: [PATCH v3 1/3] bsps/microblaze: Allow copying FDT from U-Boot
On Mon, Apr 10, 2023 at 9:25 PM Chris Johns wrote: > > On 10/4/2023 1:47 pm, Alex White wrote: > > .../microblaze_invalidate_dcache_range.S | 104 ++ > > Why not provide the RTEMS cache API and use that? Hi Chris, Good catch. It would be ideal to provide the existing RTEMS cache API. I have created ticket #4895 to track that. Thanks, Alex ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH] print/texinfo: Add texinfo package
From: Chris Johns
- MacOS systems do not come with makeinfo
- Fix the internal build logic. There was config logic in a
bset file that does not support logic operators. Use a
special tmp internal path to isolate the internal tools.
---
bare/config/print/texinfo-7.0.3.cfg | 12 +++
bare/config/print/texinfo-internal.bset | 11 ++
bare/config/print/texinfo.bset | 4 +
bare/config/print/texinfo.cfg | 8 ++
bare/config/textproc/gsed-internal.bset | 4 -
rtems/config/tools/rtems-default-tools.bset | 13 ++-
source-builder/config/gsed-1.cfg| 6 +-
source-builder/config/texinfo-1.cfg | 107
source-builder/defaults.mc | 5 +-
9 files changed, 158 insertions(+), 12 deletions(-)
create mode 100644 bare/config/print/texinfo-7.0.3.cfg
create mode 100644 bare/config/print/texinfo-internal.bset
create mode 100644 bare/config/print/texinfo.bset
create mode 100644 bare/config/print/texinfo.cfg
create mode 100644 source-builder/config/texinfo-1.cfg
diff --git a/bare/config/print/texinfo-7.0.3.cfg
b/bare/config/print/texinfo-7.0.3.cfg
new file mode 100644
index 000..f8e67be
--- /dev/null
+++ b/bare/config/print/texinfo-7.0.3.cfg
@@ -0,0 +1,12 @@
+#
+# GNU texinfo 7.0.3
+#
+
+%include %{_configdir}/base.cfg
+
+%define texinfo_version 7.0.3
+
+%hash sha512 texinfo-%{texinfo_version}.tar.gz \
+
uJXP+WVCInQgPxcWNogeOx5VfrmruXIwd6OnnpTgrcXW12Icuqe+R9PF1l/8k/uybwfb+0MMdFoYbq7iiIQGSA==
+
+%include %{_configdir}/texinfo-1.cfg
diff --git a/bare/config/print/texinfo-internal.bset
b/bare/config/print/texinfo-internal.bset
new file mode 100644
index 000..8fa5544
--- /dev/null
+++ b/bare/config/print/texinfo-internal.bset
@@ -0,0 +1,11 @@
+#
+# Internal GNU texinfo
+#
+
+%define _internal_texinfo yes
+%define _disable_collecting yes
+%define _disable_packaging yes
+%define _disable_reporting yes
+%define _disable_installing yes
+
+%include print/texinfo.bset
diff --git a/bare/config/print/texinfo.bset b/bare/config/print/texinfo.bset
new file mode 100644
index 000..347c48d
--- /dev/null
+++ b/bare/config/print/texinfo.bset
@@ -0,0 +1,4 @@
+#
+# GNU texinfo
+#
+print/texinfo.cfg
diff --git a/bare/config/print/texinfo.cfg b/bare/config/print/texinfo.cfg
new file mode 100644
index 000..5fa0cba
--- /dev/null
+++ b/bare/config/print/texinfo.cfg
@@ -0,0 +1,8 @@
+#
+# GNU makeinfo has a version option, check for it.
+# If not found build it.
+#
+%define has_makeinfo %(makeinfo --version > /dev/null 2>&1; echo $?)
+%if %{has_makeinfo} != 0
+ %include %{_configdir}/print/texinfo-7.0.3.cfg
+%endif
diff --git a/bare/config/textproc/gsed-internal.bset
b/bare/config/textproc/gsed-internal.bset
index c45e498..7b2c3b8 100644
--- a/bare/config/textproc/gsed-internal.bset
+++ b/bare/config/textproc/gsed-internal.bset
@@ -2,10 +2,6 @@
# Internal GNU sed
#
-%if !{defined _internal_gsed_path}
- %error no gsed internal install path defined
-%endif
-
%define _internal_gsed yes
%define _disable_collecting yes
%define _disable_packaging yes
diff --git a/rtems/config/tools/rtems-default-tools.bset
b/rtems/config/tools/rtems-default-tools.bset
index b81f1e8..0291786 100644
--- a/rtems/config/tools/rtems-default-tools.bset
+++ b/rtems/config/tools/rtems-default-tools.bset
@@ -5,16 +5,23 @@
# GCC requires a GNU sed so build an internal version if one is not
# available
#
-%define _internal_gsed_path %{_tmppath}/sb-%{_uid}/${SB_PREFIX_CLEAN}
-textproc/gsed-internal
+%define _internal_gsed_path %{_tmpinternal}
+%defineifnot with_rtems_gmp textproc/gsed-internal
+
+# GNU tools need texinfo for makeinfo to build documentation
+%define _internal_texinfo_path %{_tmpinternal}
+%defineifnot with_rtems_texinfo print/texinfo-internal
#
# Build gdb first to raise the Python install error as early as
-# possible. GDB needs expat so it needs to be built before gdb.
+# possible.
+#
+# GCC and GDB need GMP.
#
%{with_rtems_dtc}
%{with_rtems_expat}
%{with_rtems_gmp}
+%{with_rtems_texinfo}
%{with_rtems_gdb}
%{with_rtems_binutils}
%{with_rtems_gcc}
diff --git a/source-builder/config/gsed-1.cfg b/source-builder/config/gsed-1.cfg
index 87eb0fb..9135414 100644
--- a/source-builder/config/gsed-1.cfg
+++ b/source-builder/config/gsed-1.cfg
@@ -11,9 +11,6 @@
%ifn %{defined _internal_gsed}
%define _internal_gsed no
%endif
-%ifn %{defined _internal_gsed_path}
- %define _internal_gsed_path %{_prefix}
-%endif
Name: gsed-%{gsed_version}-%{_host}-%{release}
Summary: GNU sed v%{gsed_version} for host %{_host}
@@ -30,6 +27,9 @@ URL: https://www.gnu.org/software/sed/
# Remap the install paths if it is an internal build
#
%if %{_internal_gsed} == yes
+ %if !%{defined _internal_gsed_path}
+%error no gsed internal install path defined
+ %endif
%define gsed_prefix %{_internal_gsed_path}
%else
%define gsed_prefix %{_prefix}
diff --git a/source-builder/config/texinfo-1.cfg
[PATCH v2 2/2] bsps/powerpc: Fix warnings with PPC_SPECIAL_PURPOSE_REGISTER
From: Chris Johns
- This change avoids the GCC extension of blocks in expressions that
ISO forbids and is warned about with the pedantic warnings option.
---
bsps/powerpc/include/libcpu/powerpc-utility.h | 42 ++-
.../powerpc/shared/exceptions/ppc_exc_print.c | 25 ++-
2 files changed, 38 insertions(+), 29 deletions(-)
diff --git a/bsps/powerpc/include/libcpu/powerpc-utility.h
b/bsps/powerpc/include/libcpu/powerpc-utility.h
index 922e5d2407..0f916ae9fa 100644
--- a/bsps/powerpc/include/libcpu/powerpc-utility.h
+++ b/bsps/powerpc/include/libcpu/powerpc-utility.h
@@ -574,18 +574,12 @@ static inline void ppc_set_decrementer_register(uint32_t
dec)
/**
* @brief Returns the value of the Special Purpose Register with number @a spr.
- *
- * @note This macro uses a GNU C extension.
*/
-#define PPC_SPECIAL_PURPOSE_REGISTER(spr) \
- ({ \
-uint32_t val; \
-__asm__ volatile (\
- "mfspr %0, " PPC_STRINGOF(spr) \
- : "=r" (val) \
-); \
-val;\
- } )
+#define PPC_SPECIAL_PURPOSE_REGISTER(spr, val) \
+ __asm__ volatile (\
+"mfspr %0, " PPC_STRINGOF(spr) \
+: "=r" (val) \
+ )
/**
* @brief Sets the Special Purpose Register with number @a spr to the value in
@@ -612,7 +606,7 @@ static inline void ppc_set_decrementer_register(uint32_t
dec)
uint32_t val; \
uint32_t mybits = bits; \
_ISR_Local_disable(level); \
-val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
+PPC_SPECIAL_PURPOSE_REGISTER(spr, val); \
val |= mybits; \
PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
_ISR_Local_enable(level); \
@@ -632,7 +626,7 @@ static inline void ppc_set_decrementer_register(uint32_t
dec)
uint32_t mybits = bits; \
uint32_t mymask = mask; \
_ISR_Local_disable(level); \
-val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
+PPC_SPECIAL_PURPOSE_REGISTER(spr, val); \
val &= ~mymask; \
val |= mybits; \
PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
@@ -651,7 +645,7 @@ static inline void ppc_set_decrementer_register(uint32_t
dec)
uint32_t val; \
uint32_t mybits = bits; \
_ISR_Local_disable(level); \
-val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
+PPC_SPECIAL_PURPOSE_REGISTER(spr, val); \
val &= ~mybits; \
PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
_ISR_Local_enable(level); \
@@ -790,7 +784,9 @@ static inline void ppc_set_time_base(uint32_t val)
static inline uint32_t ppc_time_base_upper(void)
{
- return PPC_SPECIAL_PURPOSE_REGISTER(TBRU);
+ uint32_t val;
+ PPC_SPECIAL_PURPOSE_REGISTER(TBRU, val);
+ return val;
}
static inline void ppc_set_time_base_upper(uint32_t val)
@@ -810,12 +806,16 @@ static inline void ppc_set_time_base_64(uint64_t val)
static inline uint32_t ppc_alternate_time_base(void)
{
- return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL);
+ uint32_t val;
+ PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL, val);
+ return val;
}
static inline uint32_t ppc_alternate_time_base_upper(void)
{
- return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU);
+ uint32_t val;
+ PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU, val);
+ return val;
}
static inline uint64_t ppc_alternate_time_base_64(void)
@@ -835,7 +835,9 @@ static inline uint64_t ppc_alternate_time_base_64(void)
static inline uint32_t ppc_processor_id(void)
{
- return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR);
+ uint32_t val;
+ PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR, val);
+ return val;
}
static inline void ppc_set_processor_id(uint32_t val)
@@ -845,7 +847,9 @@ static inline void ppc_set_processor_id(uint32_t val)
static inline uint32_t ppc_fsl_system_version(void)
{
- return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR);
+ uint32_t val;
+ PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR, val);
+ return val;
}
static inline uint32_t ppc_fsl_system_version_cid(uint32_t svr)
diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_print.c
b/bsps/powerpc/shared/exceptions/ppc_exc_print.c
index e4fcc73cb1..ff231beff9 100644
--- a/bsps/powerpc/shared/exceptions/ppc_exc_print.c
+++ b/bsps/powerpc/shared/exceptions/ppc_exc_print.c
@@ -42,18 +42,23 @@ typedef struct LRFrameRec_ {
static uint32_t ppc_exc_get_DAR_dflt(void)
{
- if (ppc_cpu_is_60x())
-return PPC_SPECIAL_PURPOSE_REGISTER(PPC_DAR);
- else
+ uint32_t val;
+ if (ppc_cpu_is_60x()) {
+PPC_SPECIAL_PURPOSE_REGISTER(PPC_DAR, val);
+return val;
+ } else {
switch (ppc_cpu_is_bookE()) {
default:
break;
case PPC_BOOKE_STD:
case PPC_BOOKE_E500:
-return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_DEAR);
+PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_DEAR, val);
+return val;
case PPC_BOOKE_405:
-return PPC_SPECIAL_PURPOSE_REGISTER(PPC405_DEAR);
+PPC_SPECIAL_PURPOSE_REGISTER(PPC405_DEAR, val);
+return val;
}
+ }
return 0xdeadbeef;
}
@@ -170,13 +175,13 @@ void _CPU_Exception_frame_print(const CPU_Exception_frame
*excPtr)
printk(" %s = 0x%08" PRIx32
[PATCH v2 1/2] bsps/motorola_powerpc: Change defines from BSP names to avoid clash
From: Chris Johns
- Change mvme2100 to mot_pcc_mvme2100 to avoid clashing with the
RTEMS_BSP value for the BSP. You cannot have a define that is the
BSP name or the RTEMS_BSP name will be the define.
---
bsps/mips/include/bsp/i8259.h | 2 +-
bsps/powerpc/motorola_powerpc/include/bsp.h| 6 +++---
bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h | 2 +-
bsps/powerpc/motorola_powerpc/include/bsp/irq.h| 2 +-
bsps/powerpc/motorola_powerpc/start/bspreset.c | 2 +-
bsps/powerpc/motorola_powerpc/start/bspstart.c | 10 +-
bsps/powerpc/motorola_powerpc/start/motorola.c | 2 +-
bsps/powerpc/shared/irq/irq_init.c | 6 +++---
bsps/powerpc/shared/pci/detect_raven_bridge.c | 2 +-
bsps/powerpc/shared/rtc/todcfg.c | 6 +++---
.../bsps/powerpc/motorola_powerpc/optmvme2100.yml | 2 +-
.../bsps/powerpc/motorola_powerpc/optmvme2307.yml | 2 +-
.../bsps/powerpc/motorola_powerpc/optmvme2700.yml | 2 +-
13 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/bsps/mips/include/bsp/i8259.h b/bsps/mips/include/bsp/i8259.h
index 1a947829b0..e833fd2d36 100644
--- a/bsps/mips/include/bsp/i8259.h
+++ b/bsps/mips/include/bsp/i8259.h
@@ -169,7 +169,7 @@ extern "C" {
/** @} */
-#if defined(mvme2100)
+#if defined(mot_ppc_mvme2100)
#define BSP_DEC21143_IRQ(BSP_PCI_IRQ_LOWEST_OFFSET + 1)
#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
#define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
diff --git a/bsps/powerpc/motorola_powerpc/include/bsp.h
b/bsps/powerpc/motorola_powerpc/include/bsp.h
index db0995fa5c..d44bcd5cff 100644
--- a/bsps/powerpc/motorola_powerpc/include/bsp.h
+++ b/bsps/powerpc/motorola_powerpc/include/bsp.h
@@ -89,7 +89,7 @@ extern "C" {
*/
/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
-#if defined(mvme2100)
+#if defined(mot_ppc_mvme2100)
#define_IO_BASECHRP_ISA_IO_BASE
#define_ISA_MEM_BASE CHRP_ISA_MEM_BASE
/* address of our ram on the PCI bus */
@@ -154,7 +154,7 @@ extern "C" {
* find out what it is which is VERY different from other Motorola boards.
*/
-#if defined(mvme2100)
+#if defined(mot_ppc_mvme2100)
#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e1)
/* #define BSP_UART_IOBASE_COM1 (0xffe1) */
#define BSP_OPEN_PIC_BASE_OFFSET 0x4
@@ -169,7 +169,7 @@ extern "C" {
#define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0)
#endif
-#if defined(mvme2300) || defined(mvme2307) || defined(mvme2700)
+#if defined(mvme2300) || defined(mot_ppc_mvme2307) || defined(mot_ppc_mvme2700)
#define MVME_HAS_DEC21140
#endif
#endif
diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
index 9b355819f1..9e57730d60 100644
--- a/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
+++ b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
@@ -66,7 +66,7 @@
* available and unused!
*/
-#if defined(mvme2100)
+#if defined(mot_ppc_mvme2100)
#define _VME_A32_WIN0_ON_PCI 0x9000
#define _VME_A24_ON_PCI 0x9f00
#define _VME_A16_ON_PCI 0x9fff
diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
index fea2859c3e..74bda323eb 100644
--- a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
+++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
@@ -133,7 +133,7 @@ extern "C" {
#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0)
#endif
-#if defined(mvme2100)
+#if defined(mot_ppc_mvme2100)
#define BSP_DEC21143_IRQ(BSP_PCI_IRQ_LOWEST_OFFSET + 1)
#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
#define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
diff --git a/bsps/powerpc/motorola_powerpc/start/bspreset.c
b/bsps/powerpc/motorola_powerpc/start/bspreset.c
index 0931badae4..d0af42284f 100644
--- a/bsps/powerpc/motorola_powerpc/start/bspreset.c
+++ b/bsps/powerpc/motorola_powerpc/start/bspreset.c
@@ -16,7 +16,7 @@ void bsp_reset(void)
CPU_print_stack();
/* shutdown and reboot */
-#if defined(mvme2100)
+#if defined(mot_ppc_mvme2100)
*(unsigned char*)0xffe0 |= 0x80;
#else
/* Memory-mapped Port 92 PIB device access
diff --git a/bsps/powerpc/motorola_powerpc/start/bspstart.c
b/bsps/powerpc/motorola_powerpc/start/bspstart.c
index a781297565..894cf9d73d 100644
--- a/bsps/powerpc/motorola_powerpc/start/bspstart.c
+++ b/bsps/powerpc/motorola_powerpc/start/bspstart.c
@@ -109,7 +109,7 @@ char *save_boot_params(
return loaderParam;
}
-#if defined(mvme2100)
+#if defined(mot_ppc_mvme2100)
unsigned int EUMBBAR;
/*
@@ -130,7 +130,7 @@ uint32_t _CPU_Counter_frequency(void)
static void bsp_early( void )
{
-#if !defined(mvme2100)
+#if !defined(mot_ppc_mvme2100)
unsigned l2cr;
Re: [PATCH 2/2] bsps/powerpc: Fix warnings with PPC_SPECIAL_PURPOSE_REGISTER
On 11/4/2023 10:29 pm, Joel Sherrill wrote:
> Anything to add to the message beyond "fix" to explain this patch? :)
>
> I think the software engineering guide uses a comment similar to this as an
> anti-pattern. Lol
How about:
- This change avoids the GCC extension of blocks in expressions that
ISO forbids and is warned about with the pedantic warnings option.
?
Chris
>
> On Tue, Apr 11, 2023, 12:00 AM mailto:chr...@rtems.org>>
> wrote:
>
> From: Chris Johns mailto:chr...@rtems.org>>
>
> ---
> bsps/powerpc/include/libcpu/powerpc-utility.h | 40 +++
> .../powerpc/shared/exceptions/ppc_exc_print.c | 25 +++-
> 2 files changed, 38 insertions(+), 27 deletions(-)
>
> diff --git a/bsps/powerpc/include/libcpu/powerpc-utility.h
> b/bsps/powerpc/include/libcpu/powerpc-utility.h
> index 922e5d2407..fb831c9fa8 100644
> --- a/bsps/powerpc/include/libcpu/powerpc-utility.h
> +++ b/bsps/powerpc/include/libcpu/powerpc-utility.h
> @@ -577,15 +577,11 @@ static inline void
> ppc_set_decrementer_register(uint32_t dec)
> *
> * @note This macro uses a GNU C extension.
> */
> -#define PPC_SPECIAL_PURPOSE_REGISTER(spr) \
> - ({ \
> - uint32_t val; \
> - __asm__ volatile (\
> - "mfspr %0, " PPC_STRINGOF(spr) \
> - : "=r" (val) \
> - ); \
> - val;\
> - } )
> +#define PPC_SPECIAL_PURPOSE_REGISTER(spr, val) \
> + __asm__ volatile (\
> + "mfspr %0, " PPC_STRINGOF(spr) \
> + : "=r" (val) \
> + )
>
> /**
> * @brief Sets the Special Purpose Register with number @a spr to the
> value in
> @@ -612,7 +608,7 @@ static inline void
> ppc_set_decrementer_register(uint32_t
> dec)
> uint32_t val; \
> uint32_t mybits = bits; \
> _ISR_Local_disable(level); \
> - val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
> + PPC_SPECIAL_PURPOSE_REGISTER(spr, val); \
> val |= mybits; \
> PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
> _ISR_Local_enable(level); \
> @@ -632,7 +628,7 @@ static inline void
> ppc_set_decrementer_register(uint32_t
> dec)
> uint32_t mybits = bits; \
> uint32_t mymask = mask; \
> _ISR_Local_disable(level); \
> - val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
> + PPC_SPECIAL_PURPOSE_REGISTER(spr, val); \
> val &= ~mymask; \
> val |= mybits; \
> PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
> @@ -651,7 +647,7 @@ static inline void
> ppc_set_decrementer_register(uint32_t
> dec)
> uint32_t val; \
> uint32_t mybits = bits; \
> _ISR_Local_disable(level); \
> - val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
> + PPC_SPECIAL_PURPOSE_REGISTER(spr, val); \
> val &= ~mybits; \
> PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
> _ISR_Local_enable(level); \
> @@ -790,7 +786,9 @@ static inline void ppc_set_time_base(uint32_t val)
>
> static inline uint32_t ppc_time_base_upper(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(TBRU);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(TBRU, val);
> + return val;
> }
>
> static inline void ppc_set_time_base_upper(uint32_t val)
> @@ -810,12 +808,16 @@ static inline void ppc_set_time_base_64(uint64_t
> val)
>
> static inline uint32_t ppc_alternate_time_base(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL, val);
> + return val;
> }
>
> static inline uint32_t ppc_alternate_time_base_upper(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU, val);
> + return val;
> }
>
> static inline uint64_t ppc_alternate_time_base_64(void)
> @@ -835,7 +837,9 @@ static inline uint64_t
> ppc_alternate_time_base_64(void)
>
> static inline uint32_t ppc_processor_id(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR, val);
> + return val;
> }
>
> static inline void ppc_set_processor_id(uint32_t val)
> @@ -845,7 +849,9 @@ static inline void ppc_set_processor_id(uint32_t val)
>
> static inline uint32_t ppc_fsl_system_version(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR, val);
> + return val;
> }
>
> static inline uint32_t ppc_fsl_system_version_cid(uint32_t svr)
> diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_print.c
> b/bsps/powerpc/shared/exceptions/ppc_exc_print.c
> index e4fcc73cb1..ff231beff9 100644
> --- a/bsps/powerpc/shared/exceptions/ppc_exc_print.c
> +++
Re: [PATCH 1/2] bsps/motorola_powerpc: Change defines from BSP names to avoid clash
On 11/4/2023 10:44 pm, Joel Sherrill wrote:
> On Tue, Apr 11, 2023, 12:00 AM mailto:chr...@rtems.org>>
> wrote:
>
> From: Chris Johns mailto:chr...@rtems.org>>
>
> - Change mvme2100 to mot_pcc_mvme2100 to avoid clashing with the
> RTEMS_BSP value for the BSP. You cannot have a define that is the
> BSP name.
> ---
> bsps/mips/include/bsp/i8259.h | 4 ++--
> bsps/powerpc/motorola_powerpc/include/bsp.h | 6 +++---
> bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h | 2 +-
> bsps/powerpc/motorola_powerpc/include/bsp/irq.h | 2 +-
> bsps/powerpc/motorola_powerpc/start/bspreset.c | 2 +-
> bsps/powerpc/motorola_powerpc/start/bspstart.c | 10 +-
> bsps/powerpc/motorola_powerpc/start/motorola.c | 2 +-
> bsps/powerpc/shared/irq/irq_init.c | 6 +++---
> bsps/powerpc/shared/pci/detect_raven_bridge.c | 2 +-
> bsps/powerpc/shared/rtc/todcfg.c | 6 +++---
> .../bsps/powerpc/motorola_powerpc/optmvme2100.yml | 2 +-
> .../bsps/powerpc/motorola_powerpc/optmvme2307.yml | 2 +-
> .../bsps/powerpc/motorola_powerpc/optmvme2700.yml | 2 +-
> 13 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/bsps/mips/include/bsp/i8259.h b/bsps/mips/include/bsp/i8259.h
> index 1a947829b0..29e3853874 100644
> --- a/bsps/mips/include/bsp/i8259.h
> +++ b/bsps/mips/include/bsp/i8259.h
> @@ -37,7 +37,7 @@
> * @{
> */
>
>
> This patch looks ok except for this if 1. It appears it was already there but
> you touched it. Any explanation? Can the if 1 be removed?
>
It is a whitespace change and I decided to leave this in to clean it up. The
MIPS BSP as copied a header and I fixed the define to make sure all places have
been updated however any MIPS user should consider this common header being
shared but that is outside the scope of this change.
Is this OK?
Chris
> -#if 1
> +#if 1
> #define ISA8259_M_ELCR 0x4d0
> #define ISA8259_S_ELCR 0x4d1
> #endif
> @@ -169,7 +169,7 @@ extern "C" {
>
> /** @} */
>
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
> #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
> #define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
> diff --git a/bsps/powerpc/motorola_powerpc/include/bsp.h
> b/bsps/powerpc/motorola_powerpc/include/bsp.h
> index db0995fa5c..d44bcd5cff 100644
> --- a/bsps/powerpc/motorola_powerpc/include/bsp.h
> +++ b/bsps/powerpc/motorola_powerpc/include/bsp.h
> @@ -89,7 +89,7 @@ extern "C" {
> */
>
> /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from
> libcpu/io.h) */
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define _IO_BASE CHRP_ISA_IO_BASE
> #define _ISA_MEM_BASE CHRP_ISA_MEM_BASE
> /* address of our ram on the PCI bus */
> @@ -154,7 +154,7 @@ extern "C" {
> * find out what it is which is VERY different from other Motorola
> boards.
> */
>
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e1)
> /* #define BSP_UART_IOBASE_COM1 (0xffe1) */
> #define BSP_OPEN_PIC_BASE_OFFSET 0x4
> @@ -169,7 +169,7 @@ extern "C" {
> #define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0)
> #endif
>
> -#if defined(mvme2300) || defined(mvme2307) || defined(mvme2700)
> +#if defined(mvme2300) || defined(mot_ppc_mvme2307) ||
> defined(mot_ppc_mvme2700)
> #define MVME_HAS_DEC21140
> #endif
> #endif
> diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
> b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
> index 9b355819f1..9e57730d60 100644
> --- a/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
> +++ b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
> @@ -66,7 +66,7 @@
> * available and unused!
> */
>
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define _VME_A32_WIN0_ON_PCI 0x9000
> #define _VME_A24_ON_PCI 0x9f00
> #define _VME_A16_ON_PCI 0x9fff
> diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> index fea2859c3e..74bda323eb 100644
> --- a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> +++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> @@ -133,7 +133,7 @@ extern "C" {
> #define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0)
> #endif
>
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define
Re: [PATCH v2] docs/user: add docs for riscv/kendrytek210 BSP variant
Looks good - I generated the HTML and PDF versions. Thanks, Alan On Tue, Apr 11, 2023 at 5:05 PM Joel Sherrill wrote: > Sorry. I didn't realise there were that many revisions and when I searched > my inbox I missed it > > I reverted V2 and applied V6. Hopefully ok now > > On Tue, Apr 11, 2023, 2:54 PM Alan Cudmore wrote: > >> Sorry, meant to reply to the list too.. I think you pushed v2 of my >> patch. I was up to v6 that fixed a bunch of issues. >> What is the best way to fix this? Rewind, or I can submit a new patch >> based on this. >> Thanks, Alan >> >> On Tue, Apr 11, 2023, 2:29 PM Joel Sherrill wrote: >> >>> Pushed. Thanks. >>> >>> Please check that it looks good to you. >>> >>> --joel >>> >>> On Fri, Mar 31, 2023 at 11:15 AM Alan Cudmore >>> wrote: >>> This patch adds the documentation for building and running RTEMS on the Kendryte K210 RISC-V SoC. The generic riscv introducion was re-arranged to list the multilib variants then the specific hardware targets. In addition a couple of errors were fixed for the generic QEMU commands. V2 corrected a typo, expanded K210 Console UART parameters, and addded a hyperlink to renode.io install instructions. Closes #4876 --- user/bsps/bsps-riscv.rst | 116 ++- 1 file changed, 103 insertions(+), 13 deletions(-) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 41f369f..af79e6e 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-riscv.rst @@ -8,7 +8,7 @@ riscv (RISC-V) riscv = -This BSP offers 12 variants: +**This BSP offers 10 variants, each corresponding to a GCC multilib:** * rv32i @@ -30,23 +30,22 @@ This BSP offers 12 variants: * rv64imafdc -* frdme310arty - -* mpfs64imafdc - -Each rv* variant corresponds to a GCC multilib. A particular variant reflects an -ISA with ABI and code model choice. All rv64 BSPs have medany code model by +Each variant reflects an ISA with ABI and code model choice. All rv64 BSPs have medany code model by default, while rv32 BSPs are medlow. The reason is that RV32 medlow can access the entire 32-bit address space, while RV64 medlow can only access addresses below 0x8000. With RV64 medany, it's possible to perform accesses above -0x8000. +0x8000. The BSP must be started in machine mode. + +The reference platform for the rv* variants is the QEMU `virt` machine. + +**The BSP also provides the following 3 variants for specific hardware targets:** -The BSP must be started im machine mode. +* frdme310arty - The reference platform for this variant is the Arty FPGA board with the Sifive Freedom E310 reference design. -The reference platform for this BSP is the QEMU `virt` machine. +* mpfs64imafdc - The reference platform for this variant is the Microchip PolarFire SoC Icicle Kit. + +* kendrytek210 - The reference platform for this variant is the Kendryte K210 SoC on the Sipeed MAiX Bit or MAiXDuino board. -The reference platform for the mpfs64imafdc BSP variant is the Microchip -PolarFire SoC Icicle Kit. Build Configuration Options --- @@ -90,6 +89,9 @@ configuration INI file. The ``waf`` defaults can be used to inspect the values. The maximum number of NS16550 devices supported by the console driver (2 by default). +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` + Enable the Sifive console UART (disabled by default) + ``RISCV_RAM_REGION_BEGIN`` The begin of the RAM region for linker command file (default is 0x8000). @@ -104,6 +106,10 @@ configuration INI file. The ``waf`` defaults can be used to inspect the values. Enables support Microchip PolarFire SoC if defined to a non-zero value, otherwise it is disabled (disabled by default). +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` + Enables support for the Kendtryte K210 SoC if defined to a non-zero + value, otherwise it is disabled (disabled by default). + ``RISCV_BOOT_HARTID`` The boot hartid (processor number) of risc-v cpu by default 0. @@ -131,7 +137,7 @@ The console driver supports devices compatible to * "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option). -* "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option). +* "sifive,uart0" (see ``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` BSP option). This console driver is used by the frdme310arty and kendrytek210 BSP variants. They are initialized according to the device tree. The console driver does not
Re: [PATCH v2] docs/user: add docs for riscv/kendrytek210 BSP variant
Sorry. I didn't realise there were that many revisions and when I searched my inbox I missed it I reverted V2 and applied V6. Hopefully ok now On Tue, Apr 11, 2023, 2:54 PM Alan Cudmore wrote: > Sorry, meant to reply to the list too.. I think you pushed v2 of my patch. > I was up to v6 that fixed a bunch of issues. > What is the best way to fix this? Rewind, or I can submit a new patch > based on this. > Thanks, Alan > > On Tue, Apr 11, 2023, 2:29 PM Joel Sherrill wrote: > >> Pushed. Thanks. >> >> Please check that it looks good to you. >> >> --joel >> >> On Fri, Mar 31, 2023 at 11:15 AM Alan Cudmore >> wrote: >> >>> This patch adds the documentation for building and running RTEMS on the >>> Kendryte K210 >>> RISC-V SoC. The generic riscv introducion was re-arranged to list the >>> multilib variants >>> then the specific hardware targets. In addition a couple of errors were >>> fixed for the >>> generic QEMU commands. >>> >>> V2 corrected a typo, expanded K210 Console UART parameters, and addded a >>> hyperlink >>> to renode.io install instructions. >>> >>> Closes #4876 >>> --- >>> user/bsps/bsps-riscv.rst | 116 ++- >>> 1 file changed, 103 insertions(+), 13 deletions(-) >>> >>> diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst >>> index 41f369f..af79e6e 100644 >>> --- a/user/bsps/bsps-riscv.rst >>> +++ b/user/bsps/bsps-riscv.rst >>> @@ -8,7 +8,7 @@ riscv (RISC-V) >>> riscv >>> = >>> >>> -This BSP offers 12 variants: >>> +**This BSP offers 10 variants, each corresponding to a GCC multilib:** >>> >>> * rv32i >>> >>> @@ -30,23 +30,22 @@ This BSP offers 12 variants: >>> >>> * rv64imafdc >>> >>> -* frdme310arty >>> - >>> -* mpfs64imafdc >>> - >>> -Each rv* variant corresponds to a GCC multilib. A particular variant >>> reflects an >>> -ISA with ABI and code model choice. All rv64 BSPs have medany code >>> model by >>> +Each variant reflects an ISA with ABI and code model choice. All rv64 >>> BSPs have medany code model by >>> default, while rv32 BSPs are medlow. The reason is that RV32 medlow can >>> access >>> the entire 32-bit address space, while RV64 medlow can only access >>> addresses >>> below 0x8000. With RV64 medany, it's possible to perform accesses >>> above >>> -0x8000. >>> +0x8000. The BSP must be started in machine mode. >>> + >>> +The reference platform for the rv* variants is the QEMU `virt` machine. >>> + >>> +**The BSP also provides the following 3 variants for specific hardware >>> targets:** >>> >>> -The BSP must be started im machine mode. >>> +* frdme310arty - The reference platform for this variant is the Arty >>> FPGA board with the Sifive Freedom E310 reference design. >>> >>> -The reference platform for this BSP is the QEMU `virt` machine. >>> +* mpfs64imafdc - The reference platform for this variant is the >>> Microchip PolarFire SoC Icicle Kit. >>> + >>> +* kendrytek210 - The reference platform for this variant is the >>> Kendryte K210 SoC on the Sipeed MAiX Bit or MAiXDuino board. >>> >>> -The reference platform for the mpfs64imafdc BSP variant is the Microchip >>> -PolarFire SoC Icicle Kit. >>> >>> Build Configuration Options >>> --- >>> @@ -90,6 +89,9 @@ configuration INI file. The ``waf`` defaults can be >>> used to inspect the values. >>> The maximum number of NS16550 devices supported by the console >>> driver (2 >>> by default). >>> >>> +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` >>> + Enable the Sifive console UART (disabled by default) >>> + >>> ``RISCV_RAM_REGION_BEGIN`` >>> The begin of the RAM region for linker command file (default is >>> 0x8000). >>> >>> @@ -104,6 +106,10 @@ configuration INI file. The ``waf`` defaults can be >>> used to inspect the values. >>> Enables support Microchip PolarFire SoC if defined to a non-zero >>> value, otherwise it is disabled (disabled by default). >>> >>> +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` >>> + Enables support for the Kendtryte K210 SoC if defined to a non-zero >>> + value, otherwise it is disabled (disabled by default). >>> + >>> ``RISCV_BOOT_HARTID`` >>> The boot hartid (processor number) of risc-v cpu by default 0. >>> >>> @@ -131,7 +137,7 @@ The console driver supports devices compatible to >>> >>> * "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option). >>> >>> -* "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option). >>> +* "sifive,uart0" (see ``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` BSP option). >>> This console driver is used by the frdme310arty and kendrytek210 BSP >>> variants. >>> >>> They are initialized according to the device tree. The console driver >>> does not >>> configure the pins or peripheral clocks. The console device is selected >>> @@ -145,11 +151,13 @@ and spike machines. For instance, to run the >>> ``rv64imafdc`` BSP with the >>> following "config.ini" file. >>> >>> .. code-block:: none >>> + >>>
Re: [PATCH v2] docs/user: add docs for riscv/kendrytek210 BSP variant
Sorry, meant to reply to the list too.. I think you pushed v2 of my patch. I was up to v6 that fixed a bunch of issues. What is the best way to fix this? Rewind, or I can submit a new patch based on this. Thanks, Alan On Tue, Apr 11, 2023, 2:29 PM Joel Sherrill wrote: > Pushed. Thanks. > > Please check that it looks good to you. > > --joel > > On Fri, Mar 31, 2023 at 11:15 AM Alan Cudmore > wrote: > >> This patch adds the documentation for building and running RTEMS on the >> Kendryte K210 >> RISC-V SoC. The generic riscv introducion was re-arranged to list the >> multilib variants >> then the specific hardware targets. In addition a couple of errors were >> fixed for the >> generic QEMU commands. >> >> V2 corrected a typo, expanded K210 Console UART parameters, and addded a >> hyperlink >> to renode.io install instructions. >> >> Closes #4876 >> --- >> user/bsps/bsps-riscv.rst | 116 ++- >> 1 file changed, 103 insertions(+), 13 deletions(-) >> >> diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst >> index 41f369f..af79e6e 100644 >> --- a/user/bsps/bsps-riscv.rst >> +++ b/user/bsps/bsps-riscv.rst >> @@ -8,7 +8,7 @@ riscv (RISC-V) >> riscv >> = >> >> -This BSP offers 12 variants: >> +**This BSP offers 10 variants, each corresponding to a GCC multilib:** >> >> * rv32i >> >> @@ -30,23 +30,22 @@ This BSP offers 12 variants: >> >> * rv64imafdc >> >> -* frdme310arty >> - >> -* mpfs64imafdc >> - >> -Each rv* variant corresponds to a GCC multilib. A particular variant >> reflects an >> -ISA with ABI and code model choice. All rv64 BSPs have medany code model >> by >> +Each variant reflects an ISA with ABI and code model choice. All rv64 >> BSPs have medany code model by >> default, while rv32 BSPs are medlow. The reason is that RV32 medlow can >> access >> the entire 32-bit address space, while RV64 medlow can only access >> addresses >> below 0x8000. With RV64 medany, it's possible to perform accesses >> above >> -0x8000. >> +0x8000. The BSP must be started in machine mode. >> + >> +The reference platform for the rv* variants is the QEMU `virt` machine. >> + >> +**The BSP also provides the following 3 variants for specific hardware >> targets:** >> >> -The BSP must be started im machine mode. >> +* frdme310arty - The reference platform for this variant is the Arty >> FPGA board with the Sifive Freedom E310 reference design. >> >> -The reference platform for this BSP is the QEMU `virt` machine. >> +* mpfs64imafdc - The reference platform for this variant is the >> Microchip PolarFire SoC Icicle Kit. >> + >> +* kendrytek210 - The reference platform for this variant is the Kendryte >> K210 SoC on the Sipeed MAiX Bit or MAiXDuino board. >> >> -The reference platform for the mpfs64imafdc BSP variant is the Microchip >> -PolarFire SoC Icicle Kit. >> >> Build Configuration Options >> --- >> @@ -90,6 +89,9 @@ configuration INI file. The ``waf`` defaults can be >> used to inspect the values. >> The maximum number of NS16550 devices supported by the console >> driver (2 >> by default). >> >> +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` >> + Enable the Sifive console UART (disabled by default) >> + >> ``RISCV_RAM_REGION_BEGIN`` >> The begin of the RAM region for linker command file (default is >> 0x8000). >> >> @@ -104,6 +106,10 @@ configuration INI file. The ``waf`` defaults can be >> used to inspect the values. >> Enables support Microchip PolarFire SoC if defined to a non-zero >> value, otherwise it is disabled (disabled by default). >> >> +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` >> + Enables support for the Kendtryte K210 SoC if defined to a non-zero >> + value, otherwise it is disabled (disabled by default). >> + >> ``RISCV_BOOT_HARTID`` >> The boot hartid (processor number) of risc-v cpu by default 0. >> >> @@ -131,7 +137,7 @@ The console driver supports devices compatible to >> >> * "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option). >> >> -* "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option). >> +* "sifive,uart0" (see ``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` BSP option). >> This console driver is used by the frdme310arty and kendrytek210 BSP >> variants. >> >> They are initialized according to the device tree. The console driver >> does not >> configure the pins or peripheral clocks. The console device is selected >> @@ -145,11 +151,13 @@ and spike machines. For instance, to run the >> ``rv64imafdc`` BSP with the >> following "config.ini" file. >> >> .. code-block:: none >> + >> [riscv/rv64imafdc] >> >> Run the following QEMU command. >> >> .. code-block:: shell >> + >> $ qemu-system-riscv64 -M virt -nographic -bios $RTEMS_EXE >> $ qemu-system-riscv64 -M spike -nographic -bios $RTEMS_EXE >> >> @@ -160,11 +168,13 @@ For instance, to run the ``rv64imafdc`` BSP with >> the following >> "config.ini" file. >> >> ..
Re: [PATCH v2] docs/user: add docs for riscv/kendrytek210 BSP variant
Pushed. Thanks. Please check that it looks good to you. --joel On Fri, Mar 31, 2023 at 11:15 AM Alan Cudmore wrote: > This patch adds the documentation for building and running RTEMS on the > Kendryte K210 > RISC-V SoC. The generic riscv introducion was re-arranged to list the > multilib variants > then the specific hardware targets. In addition a couple of errors were > fixed for the > generic QEMU commands. > > V2 corrected a typo, expanded K210 Console UART parameters, and addded a > hyperlink > to renode.io install instructions. > > Closes #4876 > --- > user/bsps/bsps-riscv.rst | 116 ++- > 1 file changed, 103 insertions(+), 13 deletions(-) > > diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst > index 41f369f..af79e6e 100644 > --- a/user/bsps/bsps-riscv.rst > +++ b/user/bsps/bsps-riscv.rst > @@ -8,7 +8,7 @@ riscv (RISC-V) > riscv > = > > -This BSP offers 12 variants: > +**This BSP offers 10 variants, each corresponding to a GCC multilib:** > > * rv32i > > @@ -30,23 +30,22 @@ This BSP offers 12 variants: > > * rv64imafdc > > -* frdme310arty > - > -* mpfs64imafdc > - > -Each rv* variant corresponds to a GCC multilib. A particular variant > reflects an > -ISA with ABI and code model choice. All rv64 BSPs have medany code model > by > +Each variant reflects an ISA with ABI and code model choice. All rv64 > BSPs have medany code model by > default, while rv32 BSPs are medlow. The reason is that RV32 medlow can > access > the entire 32-bit address space, while RV64 medlow can only access > addresses > below 0x8000. With RV64 medany, it's possible to perform accesses > above > -0x8000. > +0x8000. The BSP must be started in machine mode. > + > +The reference platform for the rv* variants is the QEMU `virt` machine. > + > +**The BSP also provides the following 3 variants for specific hardware > targets:** > > -The BSP must be started im machine mode. > +* frdme310arty - The reference platform for this variant is the Arty FPGA > board with the Sifive Freedom E310 reference design. > > -The reference platform for this BSP is the QEMU `virt` machine. > +* mpfs64imafdc - The reference platform for this variant is the Microchip > PolarFire SoC Icicle Kit. > + > +* kendrytek210 - The reference platform for this variant is the Kendryte > K210 SoC on the Sipeed MAiX Bit or MAiXDuino board. > > -The reference platform for the mpfs64imafdc BSP variant is the Microchip > -PolarFire SoC Icicle Kit. > > Build Configuration Options > --- > @@ -90,6 +89,9 @@ configuration INI file. The ``waf`` defaults can be used > to inspect the values. > The maximum number of NS16550 devices supported by the console > driver (2 > by default). > > +``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` > + Enable the Sifive console UART (disabled by default) > + > ``RISCV_RAM_REGION_BEGIN`` > The begin of the RAM region for linker command file (default is > 0x8000). > > @@ -104,6 +106,10 @@ configuration INI file. The ``waf`` defaults can be > used to inspect the values. > Enables support Microchip PolarFire SoC if defined to a non-zero > value, otherwise it is disabled (disabled by default). > > +``RISCV_ENABLE_KENDRYTE_K210_SUPPORT`` > + Enables support for the Kendtryte K210 SoC if defined to a non-zero > + value, otherwise it is disabled (disabled by default). > + > ``RISCV_BOOT_HARTID`` > The boot hartid (processor number) of risc-v cpu by default 0. > > @@ -131,7 +137,7 @@ The console driver supports devices compatible to > > * "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option). > > -* "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option). > +* "sifive,uart0" (see ``RISCV_ENABLE_SIFIVE_UART_SUPPORT`` BSP option). > This console driver is used by the frdme310arty and kendrytek210 BSP > variants. > > They are initialized according to the device tree. The console driver > does not > configure the pins or peripheral clocks. The console device is selected > @@ -145,11 +151,13 @@ and spike machines. For instance, to run the > ``rv64imafdc`` BSP with the > following "config.ini" file. > > .. code-block:: none > + > [riscv/rv64imafdc] > > Run the following QEMU command. > > .. code-block:: shell > + > $ qemu-system-riscv64 -M virt -nographic -bios $RTEMS_EXE > $ qemu-system-riscv64 -M spike -nographic -bios $RTEMS_EXE > > @@ -160,11 +168,13 @@ For instance, to run the ``rv64imafdc`` BSP with the > following > "config.ini" file. > > .. code-block:: none > + > [riscv/rv64imafdc] > > Run the following Spike command. > > .. code-block:: shell > + > $ spike --isa=rv64imafdc $RTEMS_EXE > > Unlike QEMU, Spike supports enabling/disabling a subset of the imafdc > extensions > @@ -277,6 +287,86 @@ Serial terminal UART1 displays the SMP example > messages > > *** END OF TEST SMP 1 *** > > +Kendryte K210 > +- > + > +The Kendryte
Re: Ping for docs/user risc-v doc update
I'm running errands but will push this for you when I get home. On Tue, Apr 11, 2023, 9:28 AM Alan Cudmore wrote: > I think it's in pretty good shape: > https://lists.rtems.org/pipermail/devel/2023-April/074845.html > I did not wrap the existing console sections, but I used line wrap to > format the other paragraphs to be 80 chars or less. I also updated the > hardcoded RTEMS versions to use macros. > Thanks, > Alan > > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Ping for docs/user risc-v doc update
I think it's in pretty good shape: https://lists.rtems.org/pipermail/devel/2023-April/074845.html I did not wrap the existing console sections, but I used line wrap to format the other paragraphs to be 80 chars or less. I also updated the hardcoded RTEMS versions to use macros. Thanks, Alan ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 1/2] bsps/motorola_powerpc: Change defines from BSP names to avoid clash
On Tue, Apr 11, 2023, 12:00 AM wrote:
> From: Chris Johns
>
> - Change mvme2100 to mot_pcc_mvme2100 to avoid clashing with the
> RTEMS_BSP value for the BSP. You cannot have a define that is the
> BSP name.
> ---
> bsps/mips/include/bsp/i8259.h | 4 ++--
> bsps/powerpc/motorola_powerpc/include/bsp.h| 6 +++---
> bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h | 2 +-
> bsps/powerpc/motorola_powerpc/include/bsp/irq.h| 2 +-
> bsps/powerpc/motorola_powerpc/start/bspreset.c | 2 +-
> bsps/powerpc/motorola_powerpc/start/bspstart.c | 10 +-
> bsps/powerpc/motorola_powerpc/start/motorola.c | 2 +-
> bsps/powerpc/shared/irq/irq_init.c | 6 +++---
> bsps/powerpc/shared/pci/detect_raven_bridge.c | 2 +-
> bsps/powerpc/shared/rtc/todcfg.c | 6 +++---
> .../bsps/powerpc/motorola_powerpc/optmvme2100.yml | 2 +-
> .../bsps/powerpc/motorola_powerpc/optmvme2307.yml | 2 +-
> .../bsps/powerpc/motorola_powerpc/optmvme2700.yml | 2 +-
> 13 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/bsps/mips/include/bsp/i8259.h b/bsps/mips/include/bsp/i8259.h
> index 1a947829b0..29e3853874 100644
> --- a/bsps/mips/include/bsp/i8259.h
> +++ b/bsps/mips/include/bsp/i8259.h
> @@ -37,7 +37,7 @@
> * @{
> */
>
This patch looks ok except for this if 1. It appears it was already there
but you touched it. Any explanation? Can the if 1 be removed?
>
> -#if 1
> +#if 1
> #define ISA8259_M_ELCR 0x4d0
> #define ISA8259_S_ELCR 0x4d1
> #endif
> @@ -169,7 +169,7 @@ extern "C" {
>
> /** @} */
>
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define BSP_DEC21143_IRQ(BSP_PCI_IRQ_LOWEST_OFFSET + 1)
> #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
> #define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
> diff --git a/bsps/powerpc/motorola_powerpc/include/bsp.h
> b/bsps/powerpc/motorola_powerpc/include/bsp.h
> index db0995fa5c..d44bcd5cff 100644
> --- a/bsps/powerpc/motorola_powerpc/include/bsp.h
> +++ b/bsps/powerpc/motorola_powerpc/include/bsp.h
> @@ -89,7 +89,7 @@ extern "C" {
> */
>
> /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from
> libcpu/io.h) */
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define_IO_BASECHRP_ISA_IO_BASE
> #define_ISA_MEM_BASE CHRP_ISA_MEM_BASE
> /* address of our ram on the PCI bus */
> @@ -154,7 +154,7 @@ extern "C" {
> * find out what it is which is VERY different from other Motorola
> boards.
> */
>
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e1)
> /* #define BSP_UART_IOBASE_COM1 (0xffe1) */
> #define BSP_OPEN_PIC_BASE_OFFSET 0x4
> @@ -169,7 +169,7 @@ extern "C" {
> #define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0)
> #endif
>
> -#if defined(mvme2300) || defined(mvme2307) || defined(mvme2700)
> +#if defined(mvme2300) || defined(mot_ppc_mvme2307) ||
> defined(mot_ppc_mvme2700)
> #define MVME_HAS_DEC21140
> #endif
> #endif
> diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
> b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
> index 9b355819f1..9e57730d60 100644
> --- a/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
> +++ b/bsps/powerpc/motorola_powerpc/include/bsp/VMEConfig.h
> @@ -66,7 +66,7 @@
> * available and unused!
> */
>
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define _VME_A32_WIN0_ON_PCI 0x9000
> #define _VME_A24_ON_PCI 0x9f00
> #define _VME_A16_ON_PCI 0x9fff
> diff --git a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> index fea2859c3e..74bda323eb 100644
> --- a/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> +++ b/bsps/powerpc/motorola_powerpc/include/bsp/irq.h
> @@ -133,7 +133,7 @@ extern "C" {
> #define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0)
> #endif
>
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
> #define BSP_DEC21143_IRQ(BSP_PCI_IRQ_LOWEST_OFFSET + 1)
> #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
> #define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
> diff --git a/bsps/powerpc/motorola_powerpc/start/bspreset.c
> b/bsps/powerpc/motorola_powerpc/start/bspreset.c
> index 0931badae4..d0af42284f 100644
> --- a/bsps/powerpc/motorola_powerpc/start/bspreset.c
> +++ b/bsps/powerpc/motorola_powerpc/start/bspreset.c
> @@ -16,7 +16,7 @@ void bsp_reset(void)
>CPU_print_stack();
>/* shutdown and reboot */
>
> -#if defined(mvme2100)
> +#if defined(mot_ppc_mvme2100)
>*(unsigned char*)0xffe0 |= 0x80;
> #else
> /* Memory-mapped Port 92 PIB device access
> diff --git a/bsps/powerpc/motorola_powerpc/start/bspstart.c
>
Re: [PATCH 2/2] bsps/powerpc: Fix warnings with PPC_SPECIAL_PURPOSE_REGISTER
Anything to add to the message beyond "fix" to explain this patch? :)
I think the software engineering guide uses a comment similar to this as an
anti-pattern. Lol
On Tue, Apr 11, 2023, 12:00 AM wrote:
> From: Chris Johns
>
> ---
> bsps/powerpc/include/libcpu/powerpc-utility.h | 40 +++
> .../powerpc/shared/exceptions/ppc_exc_print.c | 25 +++-
> 2 files changed, 38 insertions(+), 27 deletions(-)
>
> diff --git a/bsps/powerpc/include/libcpu/powerpc-utility.h
> b/bsps/powerpc/include/libcpu/powerpc-utility.h
> index 922e5d2407..fb831c9fa8 100644
> --- a/bsps/powerpc/include/libcpu/powerpc-utility.h
> +++ b/bsps/powerpc/include/libcpu/powerpc-utility.h
> @@ -577,15 +577,11 @@ static inline void
> ppc_set_decrementer_register(uint32_t dec)
> *
> * @note This macro uses a GNU C extension.
> */
> -#define PPC_SPECIAL_PURPOSE_REGISTER(spr) \
> - ({ \
> -uint32_t val; \
> -__asm__ volatile (\
> - "mfspr %0, " PPC_STRINGOF(spr) \
> - : "=r" (val) \
> -); \
> -val;\
> - } )
> +#define PPC_SPECIAL_PURPOSE_REGISTER(spr, val) \
> + __asm__ volatile (\
> +"mfspr %0, " PPC_STRINGOF(spr) \
> +: "=r" (val) \
> + )
>
> /**
> * @brief Sets the Special Purpose Register with number @a spr to the
> value in
> @@ -612,7 +608,7 @@ static inline void
> ppc_set_decrementer_register(uint32_t dec)
> uint32_t val; \
> uint32_t mybits = bits; \
> _ISR_Local_disable(level); \
> -val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
> +PPC_SPECIAL_PURPOSE_REGISTER(spr, val); \
> val |= mybits; \
> PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
> _ISR_Local_enable(level); \
> @@ -632,7 +628,7 @@ static inline void
> ppc_set_decrementer_register(uint32_t dec)
> uint32_t mybits = bits; \
> uint32_t mymask = mask; \
> _ISR_Local_disable(level); \
> -val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
> +PPC_SPECIAL_PURPOSE_REGISTER(spr, val); \
> val &= ~mymask; \
> val |= mybits; \
> PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
> @@ -651,7 +647,7 @@ static inline void
> ppc_set_decrementer_register(uint32_t dec)
> uint32_t val; \
> uint32_t mybits = bits; \
> _ISR_Local_disable(level); \
> -val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
> +PPC_SPECIAL_PURPOSE_REGISTER(spr, val); \
> val &= ~mybits; \
> PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
> _ISR_Local_enable(level); \
> @@ -790,7 +786,9 @@ static inline void ppc_set_time_base(uint32_t val)
>
> static inline uint32_t ppc_time_base_upper(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(TBRU);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(TBRU, val);
> + return val;
> }
>
> static inline void ppc_set_time_base_upper(uint32_t val)
> @@ -810,12 +808,16 @@ static inline void ppc_set_time_base_64(uint64_t val)
>
> static inline uint32_t ppc_alternate_time_base(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL, val);
> + return val;
> }
>
> static inline uint32_t ppc_alternate_time_base_upper(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU, val);
> + return val;
> }
>
> static inline uint64_t ppc_alternate_time_base_64(void)
> @@ -835,7 +837,9 @@ static inline uint64_t ppc_alternate_time_base_64(void)
>
> static inline uint32_t ppc_processor_id(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR, val);
> + return val;
> }
>
> static inline void ppc_set_processor_id(uint32_t val)
> @@ -845,7 +849,9 @@ static inline void ppc_set_processor_id(uint32_t val)
>
> static inline uint32_t ppc_fsl_system_version(void)
> {
> - return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR);
> + uint32_t val;
> + PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR, val);
> + return val;
> }
>
> static inline uint32_t ppc_fsl_system_version_cid(uint32_t svr)
> diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_print.c
> b/bsps/powerpc/shared/exceptions/ppc_exc_print.c
> index e4fcc73cb1..ff231beff9 100644
> --- a/bsps/powerpc/shared/exceptions/ppc_exc_print.c
> +++ b/bsps/powerpc/shared/exceptions/ppc_exc_print.c
> @@ -42,18 +42,23 @@ typedef struct LRFrameRec_ {
>
> static uint32_t ppc_exc_get_DAR_dflt(void)
> {
> - if (ppc_cpu_is_60x())
> -return PPC_SPECIAL_PURPOSE_REGISTER(PPC_DAR);
> - else
> + uint32_t val;
> + if (ppc_cpu_is_60x()) {
> +PPC_SPECIAL_PURPOSE_REGISTER(PPC_DAR, val);
> +return val;
> + } else {
> switch (ppc_cpu_is_bookE()) {
>default:
> break;
>case PPC_BOOKE_STD:
>case PPC_BOOKE_E500:
> -return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_DEAR);
> +PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_DEAR, val);
> +return val;
>case PPC_BOOKE_405:
> -return PPC_SPECIAL_PURPOSE_REGISTER(PPC405_DEAR);
>
Re: [PATCH] gdb-common: Fix the python-config library parsing
Thanks for the quick fix. I tested here and indeed this fixes the
reported issue.
Karel
On 4/11/23 08:03, chr...@rtems.org wrote:
From: Chris Johns
Closes #4894
---
source-builder/config/gdb-common-1.cfg | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/source-builder/config/gdb-common-1.cfg
b/source-builder/config/gdb-common-1.cfg
index a52e64d..0fea334 100644
--- a/source-builder/config/gdb-common-1.cfg
+++ b/source-builder/config/gdb-common-1.cfg
@@ -109,8 +109,8 @@
%define gdb-host-libs -L '%{host_ldflags}'
%endif
%if %{gdb-python-config} != %{nil}
- %define gdb-python-lib-filter awk 'BEGIN{FS="
"}/python/{for(i=1;i
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
[PATCH] gdb-common: Fix the python-config library parsing
From: Chris Johns
Closes #4894
---
source-builder/config/gdb-common-1.cfg | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/source-builder/config/gdb-common-1.cfg
b/source-builder/config/gdb-common-1.cfg
index a52e64d..0fea334 100644
--- a/source-builder/config/gdb-common-1.cfg
+++ b/source-builder/config/gdb-common-1.cfg
@@ -109,8 +109,8 @@
%define gdb-host-libs -L '%{host_ldflags}'
%endif
%if %{gdb-python-config} != %{nil}
- %define gdb-python-lib-filter awk 'BEGIN{FS="
"}/python/{for(i=1;ihttp://lists.rtems.org/mailman/listinfo/devel
