Re: (libdl) Fwd: New Defects reported by Coverity Scan for RTEMS

2023-08-21 Thread Chris Johns 
On 22/8/2023 10:02 am, Gedare Bloom wrote:
> flag it as a false positive.

I agree.

> g7 is a global register that is reserved for system / compiler use in
> the sparc ABI

The reigster is set up by the operating system out of the view of Coverity. I
took the code from:

https://git.rtems.org/rtems/tree/cpukit/score/cpu/sparc/include/rtems/score/cpuimpl.h#n242

Chris


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Re: (libdl) Fwd: New Defects reported by Coverity Scan for RTEMS

2023-08-21 Thread Gedare Bloom 
flag it as a false positive.

g7 is a global register that is reserved for system / compiler use in
the sparc ABI

On Mon, Aug 21, 2023 at 2:17 PM Joel Sherrill  wrote:
>
> Moving it back to devel@.
>
> It appears to be from this bit of magic in the same file which implements it 
> using a direct reference to register g7.
>
> #elif defined(__sparc__)
> #include 
> # define __get_tls() ({ void** __val; register uintptr_t g7 __asm__( "g7" ); 
> __val = (void**) g7; __val; })
>
> I honestly don't know how to tell Coverity or GCC that this is reading a 
> register we trust.
>
>
> On Mon, Aug 21, 2023 at 2:58 PM Chris Johns  wrote:
>>
>> Hi
>>
>> It is code from somewhere else so sorry I have no idea.
>>
>> Chris
>>
>> On 21 Aug 2023, at 11:33 pm, Joel Sherrill  wrote:
>>
>> 
>> Unitialized variable issue from Coverity in libdl
>>
>> -- Forwarded message -
>> From: 
>> Date: Mon, Aug 21, 2023 at 12:33 AM
>> Subject: New Defects reported by Coverity Scan for RTEMS
>> To: 
>>
>>
>> Hi,
>>
>> Please find the latest report on new defect(s) introduced to RTEMS found 
>> with Coverity Scan.
>>
>> 1 new defect(s) introduced to RTEMS found with Coverity Scan.
>>
>>
>> New defect(s) Reported-by: Coverity Scan
>> Showing 1 of 1 defect(s)
>>
>>
>> ** CID 1541150:  Memory - illegal accesses  (UNINIT)
>> /cpukit/libdl/rtl-tls.c: 111 in rtems_rtl_tls_get_base()
>>
>>
>> 
>> *** CID 1541150:  Memory - illegal accesses  (UNINIT)
>> /cpukit/libdl/rtl-tls.c: 111 in rtems_rtl_tls_get_base()
>> 105 #endif
>> 106
>> 107 #if defined(__get_tls)
>> 108
>> 109 void* rtems_rtl_tls_get_base (void)
>> 110 {
>> >>> CID 1541150:  Memory - illegal accesses  (UNINIT)
>> >>> Using uninitialized value "g7".
>> 111   return (void*) __get_tls();
>> 112 }
>> 113
>>
>>
>> 
>> To view the defects in Coverity Scan visit, 
>> https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P0qcxCbhZ31OYv50ypUUzi-2FdSNmuyRB7BEFT8xQ4-2B8hpujh0hTgQljRGId4Dg-3D-3Deeiw_EU3W9teASMK00lBXX9WT4lsogDrkCcNZLvg-2FVxwAXMqJ0gdhGGumG7Gy0Tn5Dw3PQUbh2-2BNMdpxfdtJmNYuHO3QG97iSLio7uY7m4yyhwWxZmfc2p4Yk5m-2B2JQ7-2FNr1n2P8EvOyfDnsHe5-2FCDlZpmVnHhGqVY9mLjZbQG-2FJIE3w3MlGbiKwQw8j63a169WP32Wpts1j8m1uekKxkyIv1KA-3D-3D
>>
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Re: (libdl) Fwd: New Defects reported by Coverity Scan for RTEMS

2023-08-21 Thread Joel Sherrill 
Moving it back to devel@.

It appears to be from this bit of magic in the same file which implements
it using a direct reference to register g7.

#elif defined(__sparc__)
#include 
# define __get_tls() ({ void** __val; register uintptr_t g7 __asm__( "g7"
); __val = (void**) g7; __val; })

I honestly don't know how to tell Coverity or GCC that this is reading a
register we trust.


On Mon, Aug 21, 2023 at 2:58 PM Chris Johns  wrote:

> Hi
>
> It is code from somewhere else so sorry I have no idea.
>
> Chris
>
> On 21 Aug 2023, at 11:33 pm, Joel Sherrill  wrote:
>
> 
> Unitialized variable issue from Coverity in libdl
>
> -- Forwarded message -
> From: 
> Date: Mon, Aug 21, 2023 at 12:33 AM
> Subject: New Defects reported by Coverity Scan for RTEMS
> To: 
>
>
> Hi,
>
> Please find the latest report on new defect(s) introduced to RTEMS found
> with Coverity Scan.
>
> 1 new defect(s) introduced to RTEMS found with Coverity Scan.
>
>
> New defect(s) Reported-by: Coverity Scan
> Showing 1 of 1 defect(s)
>
>
> ** CID 1541150:  Memory - illegal accesses  (UNINIT)
> /cpukit/libdl/rtl-tls.c: 111 in rtems_rtl_tls_get_base()
>
>
>
> 
> *** CID 1541150:  Memory - illegal accesses  (UNINIT)
> /cpukit/libdl/rtl-tls.c: 111 in rtems_rtl_tls_get_base()
> 105 #endif
> 106
> 107 #if defined(__get_tls)
> 108
> 109 void* rtems_rtl_tls_get_base (void)
> 110 {
> >>> CID 1541150:  Memory - illegal accesses  (UNINIT)
> >>> Using uninitialized value "g7".
> 111   return (void*) __get_tls();
> 112 }
> 113
>
>
>
> 
> To view the defects in Coverity Scan visit,
> https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P0qcxCbhZ31OYv50ypUUzi-2FdSNmuyRB7BEFT8xQ4-2B8hpujh0hTgQljRGId4Dg-3D-3Deeiw_EU3W9teASMK00lBXX9WT4lsogDrkCcNZLvg-2FVxwAXMqJ0gdhGGumG7Gy0Tn5Dw3PQUbh2-2BNMdpxfdtJmNYuHO3QG97iSLio7uY7m4yyhwWxZmfc2p4Yk5m-2B2JQ7-2FNr1n2P8EvOyfDnsHe5-2FCDlZpmVnHhGqVY9mLjZbQG-2FJIE3w3MlGbiKwQw8j63a169WP32Wpts1j8m1uekKxkyIv1KA-3D-3D
>
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[PATCH rtems-docs] user/riscv/sifive_u: Added Documentation for the new SiFive Unleashed BSP

2023-08-21 Thread Amna 
This commit contains all the required information to build and run the
new BSP.
---
 user/bsps/bsps-riscv.rst | 52 
 1 file changed, 52 insertions(+)

diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst
index 263796e..76b70ce 100644
--- a/user/bsps/bsps-riscv.rst
+++ b/user/bsps/bsps-riscv.rst
@@ -475,3 +475,55 @@ griscv
 
 This RISC-V BSP supports chips using the
 `GRLIB `_.
+
+SiFive Unleashed
+
+
+SiFive HiFive Unleashed is a development board featuring the Freedom U540
+SoC, A Linux-capable, multi-core, RISC-V processor. The 1.5+ GHz FU540 SoC 
features
+a 4-core U54 CPU + 1-core U51 CPU. 
+
+It can be run on QEMU provided by the RTEMS source builder's
+devel/qemu bset. This BSP requires a minimum of 128MB (Default) of RAM size
+which can be changed using the RISCV_RAM_REGION_SIZE configuration option. 
+RAM start region is the default 0x8000. It uses the sifive UART for 
+console. Maximum 5 cores are present in the BSP. sifive_u BSP uses rv64imac 
+architecture.
+
+
+**Building the sifive_u BSP**
+
+Configuration file ``config.ini``:
+
+.. code-block:: none
+
+[riscv/sifive_u]
+RTEMS_SMP = True
+
+Build RTEMS:
+
+.. code-block:: shell
+
+$ ./waf configure --prefix=$HOME/rtems-start/rtems/@rtems-ver-major@
+$ ./waf
+
+**Running the sifive_u BSP**
+
+.. code-block:: shell
+
+$ qemu-system-riscv64 -nographic -m 256M -smp 2 -machine sifive_u -bios 
none -kernel hello.exe
+
+Build Configuration Options
+---
+
+The following options can be used in the BSP section of the ``waf``
+configuration INI file. The ``waf`` defaults can be used to inspect the values.
+
+
+``RISCV_MAXIMUM_EXTERNAL_INTERRUPTS``
+ The maximum number of external interrupts supported by the BSP (default
+ is 53).
+
+``RISCV_RAM_REGION_SIZE``
+ The size of the RAM region for linker command file (default 128MiB).
+
-- 
2.25.1

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[PATCH] bsp/riscv: Add a new SiFive Unleashed QEMU bsp

2023-08-21 Thread Amna 
This commits add a new SiFive Unleashed bsp which follows the RV64IMAC RISC-V
Architecture. It can be run on QEMU provided by the RTEMS source builder's
devel/qemu bset. This BSP requires a minimum of 128MB (Default) of RAM size
which can be changed using the RISCV_RAM_REGION_SIZE configuration option. RAM
start region is the default 0x8000. It uses the sifive UART for console.
Maximum 5 cores are present in the BSP.

NOTE: RTEMS_SMP flags needs to be set true in the config.ini when building the
BSP as QEMU requires at least 2 cores for running the Sifive_u machine. When
built with no SMP flag, QEMU would throw random text to the terminal when
running the executable. Same behavior  can be seen when other RV* bsp are built
without SMP flag and machine are having more than 1 core.
---
 spec/build/bsps/riscv/optextirqmax.yml|  2 ++
 spec/build/bsps/riscv/optramsize.yml  |  2 ++
 spec/build/bsps/riscv/riscv/abi.yml   |  4 +++-
 spec/build/bsps/riscv/riscv/bspsifive_u.yml   | 19 +++
 spec/build/bsps/riscv/riscv/optsifiveuart.yml |  1 +
 spec/build/cpukit/optsmp.yml  |  1 +
 6 files changed, 28 insertions(+), 1 deletion(-)
 create mode 100644 spec/build/bsps/riscv/riscv/bspsifive_u.yml

diff --git a/spec/build/bsps/riscv/optextirqmax.yml 
b/spec/build/bsps/riscv/optextirqmax.yml
index 5a0fc9a766..7071abda35 100644
--- a/spec/build/bsps/riscv/optextirqmax.yml
+++ b/spec/build/bsps/riscv/optextirqmax.yml
@@ -8,6 +8,8 @@ copyrights:
 default:
 - enabled-by: riscv/mpfs64imafdc
   value: 187
+- enabled-by: riscv/sifive_u
+  value: 53
 - enabled-by: true
   value: 128
 description: |
diff --git a/spec/build/bsps/riscv/optramsize.yml 
b/spec/build/bsps/riscv/optramsize.yml
index 876a447087..43436adde7 100644
--- a/spec/build/bsps/riscv/optramsize.yml
+++ b/spec/build/bsps/riscv/optramsize.yml
@@ -17,6 +17,8 @@ default:
   value: 0x0100
 - enabled-by: riscv/kendrytek210
   value: 0x0060
+- enabled-by: riscv/sifive_u
+  value: 0x800
 - enabled-by: true
   value: 0x0400
 description: ''
diff --git a/spec/build/bsps/riscv/riscv/abi.yml 
b/spec/build/bsps/riscv/riscv/abi.yml
index bca6512f20..4f55997216 100644
--- a/spec/build/bsps/riscv/riscv/abi.yml
+++ b/spec/build/bsps/riscv/riscv/abi.yml
@@ -22,7 +22,9 @@ default:
   - -march=rv64imafd
   - -mabi=lp64d
   - -mcmodel=medany
-- enabled-by: riscv/rv64imac
+- enabled-by: 
+  - riscv/rv64imac
+  - riscv/sifive_u
   value:
   - -march=rv64imac
   - -mabi=lp64
diff --git a/spec/build/bsps/riscv/riscv/bspsifive_u.yml 
b/spec/build/bsps/riscv/riscv/bspsifive_u.yml
new file mode 100644
index 00..b732932eaa
--- /dev/null
+++ b/spec/build/bsps/riscv/riscv/bspsifive_u.yml
@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: riscv
+bsp: sifive_u
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2023 Amna Mannan
+cppflags: []
+enabled-by: true
+family: riscv
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: ../../opto2
+- role: build-dependency
+  uid: grp
+source: []
+type: build
diff --git a/spec/build/bsps/riscv/riscv/optsifiveuart.yml 
b/spec/build/bsps/riscv/riscv/optsifiveuart.yml
index 8ff27d0275..ec1fd761e5 100644
--- a/spec/build/bsps/riscv/riscv/optsifiveuart.yml
+++ b/spec/build/bsps/riscv/riscv/optsifiveuart.yml
@@ -9,6 +9,7 @@ default:
 - enabled-by:
   - riscv/kendrytek210
   - riscv/frdme310arty
+  - riscv/sifive_u
   value: true
 - enabled-by: true
   value: false
diff --git a/spec/build/cpukit/optsmp.yml b/spec/build/cpukit/optsmp.yml
index 28b9bd4cd8..0936a42412 100644
--- a/spec/build/cpukit/optsmp.yml
+++ b/spec/build/cpukit/optsmp.yml
@@ -50,6 +50,7 @@ enabled-by:
 - riscv/rv64imafdc_medany
 - riscv/rv64imafd_medany
 - riscv/kendrytek210
+- riscv/sifive_u
 - sparc/erc32
 - sparc/gr712rc
 - sparc/gr740
-- 
2.25.1

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[PATCH rtems v1 10/10] x86_64/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 .../score/cpu/x86_64/include/rtems/score/cpuimpl.h | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
index e0e301b6bc..726a515d4e 100644
--- a/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpuimpl.h
@@ -44,21 +44,25 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
-  /* TODO */
-}
+  (void) pattern;
 
-static inline void _CPU_Instruction_illegal( void )
-{
-  __asm__ volatile ( ".word 0" );
+  /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
 }
 
+static inline void _CPU_Instruction_illegal( void )
+{
+  __asm__ volatile ( ".word 0" );
+}
+
 static inline void _CPU_Instruction_no_operation( void )
 {
   __asm__ volatile ( "nop" );
-- 
2.31.1

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[PATCH rtems v1 08/10] sparc64/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
index c49c637805..a29a519644 100644
--- a/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc64/include/rtems/score/cpuimpl.h
@@ -60,11 +60,15 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
+  (void) pattern;
+
   /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
-- 
2.31.1

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[PATCH rtems v1 07/10] sh/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
index 3e37c8f57d..ca87c61c2b 100644
--- a/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h
@@ -41,11 +41,15 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
+  (void) pattern;
+
   /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
-- 
2.31.1

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[PATCH rtems v1 09/10] v850/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
index 5ec528961c..3985c3cdb9 100644
--- a/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/v850/include/rtems/score/cpuimpl.h
@@ -60,11 +60,15 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
+  (void) pattern;
+
   /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
-- 
2.31.1

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[PATCH rtems v1 05/10] mips/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
index ad6b7ae615..d619eb6213 100644
--- a/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/mips/include/rtems/score/cpuimpl.h
@@ -60,11 +60,15 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
+  (void) pattern;
+
   /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
-- 
2.31.1

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[PATCH rtems v1 04/10] m68k/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
index ec90a41ae2..4bee157215 100644
--- a/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/m68k/include/rtems/score/cpuimpl.h
@@ -60,11 +60,15 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
+  (void) pattern;
+
   /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
-- 
2.31.1

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[PATCH rtems v1 06/10] moxie/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
index 8ded8c34e9..30c2c75f2b 100644
--- a/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/moxie/include/rtems/score/cpuimpl.h
@@ -60,11 +60,15 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
+  (void) pattern;
+
   /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
-- 
2.31.1

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[PATCH rtems v1 03/10] lm32/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
index 679ef452f4..870640864c 100644
--- a/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/lm32/include/rtems/score/cpuimpl.h
@@ -40,11 +40,15 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
+  (void) pattern;
+
   /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
-- 
2.31.1

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[PATCH rtems v1 01/10] bfin/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
index 05628a2c0b..aaf34a3ce0 100644
--- a/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/bfin/include/rtems/score/cpuimpl.h
@@ -41,11 +41,15 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
+  (void) pattern;
+
   /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
-- 
2.31.1

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[PATCH rtems v1 02/10] i386/include/rtems/score/cpuimpl.h: Address unused parameter warning

2023-08-21 Thread Joel Sherrill 
---
 cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h 
b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
index f0e4088218..ba5d820016 100644
--- a/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/i386/include/rtems/score/cpuimpl.h
@@ -62,11 +62,15 @@ RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, 
CPU_Uint32ptr error );
 
 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
 {
+  (void) pattern;
+
   /* TODO */
 }
 
 static inline void _CPU_Context_validate( uintptr_t pattern )
 {
+  (void) pattern;
+
   while (1) {
 /* TODO */
   }
-- 
2.31.1

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[PATCH rtems v1 00/10] Address unused parameter warnings

2023-08-21 Thread Joel Sherrill 
Some of the architecture ports do not have implementations of
the context validation methods. The stubs do not reference the
parameter. This series of patches addresses that.

I separated them so each port is distinct.

--joel

Joel Sherrill (10):
  bfin/include/rtems/score/cpuimpl.h: Address unused parameter warning
  i386/include/rtems/score/cpuimpl.h: Address unused parameter warning
  lm32/include/rtems/score/cpuimpl.h: Address unused parameter warning
  m68k/include/rtems/score/cpuimpl.h: Address unused parameter warning
  mips/include/rtems/score/cpuimpl.h: Address unused parameter warning
  moxie/include/rtems/score/cpuimpl.h: Address unused parameter warning
  sh/include/rtems/score/cpuimpl.h: Address unused parameter warning
  sparc64/include/rtems/score/cpuimpl.h: Address unused parameter
warning
  v850/include/rtems/score/cpuimpl.h: Address unused parameter warning
  x86_64/include/rtems/score/cpuimpl.h: Address unused parameter warning

 .../score/cpu/bfin/include/rtems/score/cpuimpl.h   |  4 
 .../score/cpu/i386/include/rtems/score/cpuimpl.h   |  4 
 .../score/cpu/lm32/include/rtems/score/cpuimpl.h   |  4 
 .../score/cpu/m68k/include/rtems/score/cpuimpl.h   |  4 
 .../score/cpu/mips/include/rtems/score/cpuimpl.h   |  4 
 .../score/cpu/moxie/include/rtems/score/cpuimpl.h  |  4 
 cpukit/score/cpu/sh/include/rtems/score/cpuimpl.h  |  4 
 .../cpu/sparc64/include/rtems/score/cpuimpl.h  |  4 
 .../score/cpu/v850/include/rtems/score/cpuimpl.h   |  4 
 .../score/cpu/x86_64/include/rtems/score/cpuimpl.h | 14 +-
 10 files changed, 45 insertions(+), 5 deletions(-)

-- 
2.31.1

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